code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module timing_gen_xy #(
parameter DATA_WIDTH = 16 // Video data one clock data width
) (
input rst_n,
input clk,
input i_hs,
input i_vs,
input i_de,
input [DATA_WIDTH - 1:0] i_data,
outp... | 8.049548 |
module timing_io (
input wire sysclk,
input wire clk1_pad,
input wire clk2_pad,
input wire poc_pad,
input wire ior,
// Timing and I/O Board Outputs
output wire clk1,
output wire clk2,
output wire a12,
output wire a22,
output wire a32,
output wire m12,
output wire m22... | 7.629368 |
module timing_management_unit #(
parameter HIGH_COUNT = 1,
parameter LOW_COUNT = 12
) (
input rst,
input clk_in,
output reg clk_out
);
parameter COUNTER_LAST_BIT_INDEX = HIGH_COUNT + LOW_COUNT - 1;
reg [COUNTER_LAST_BIT_INDEX : 0] reg_counter;
wire [COUNTER_LAST_BIT_INDEX : 0] counter_in ... | 7.513826 |
module timing_state (
input en,
input clk,
input [1:0] KEY,
input [9:0] SW,
output reg [9:0] LEDR,
output wire [7:0] HEX0,
output wire [7:0] HEX1,
output wire [7:0] HEX2,
output wire [7:0] HEX3,
output reg [3:0] score_a,
output reg [3:0] score_b,
output reg [3:0] scor... | 8.697175 |
module timing_strobe_generator #(
parameter CLOCKS_PER_TICK = 415_667 // 25MHz / 60Hz
) (
input wire i_clk,
output wire o_tick_stb,
output wire o_beat_stb
);
localparam TICK_WIDTH = $clog2(CLOCKS_PER_TICK);
reg [TICK_WIDTH-1:0] r_tick_counter = 0;
always @(posedge i_clk) begin
if (r_tick_co... | 6.522316 |
module timing_subsystem #(
parameter C_USE_HARDWARE_CLOCKS = 0
) (
input wire rst_n,
input wire CLK_48M,
// generated clocks
output wire CLK_24M,
output wire CLK_12M,
output wire CLK_6M,
output wire CLK_6MD,
// video synchronisation
output wire nVSYNC,
output wire nHSYNC,
... | 7.424261 |
module: TILEGEN
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// License: https://www.apache.org/licenses/LICENSE-2.0
//
////////////////////////////////////////////////////////////////////////////////
module timing_subsystem_tb;
reg clk_in;
reg rst_n;
// == ... | 7.238032 |
module timing_top (
// 12MHz clock input
input clk,
input [8:0] a,
input [8:0] b,
output [35:0] c
);
wire rst = 1'b0;
timing pipeline (
.clk(clk),
.rst(rst),
.a (a),
.b (b),
.c (c)
);
endmodule
| 7.744135 |
module tiny (
clk,
reset,
sel,
addr,
w,
data,
out,
done
);
input clk, reset;
input sel;
input [5:0] addr;
input w;
input [`WIDTH_D0:0] data;
output [`WIDTH_D0:0] out;
output done;
/* for FSM */
wire [5:0] fsm_addr;
/* for RAM */
wire [5:0] ram_a_addr, ram_b_addr;
... | 6.906849 |
module f3m_add (
A,
B,
C
);
input [`WIDTH : 0] A, B;
output [`WIDTH : 0] C;
genvar i;
generate
for (i = 0; i < `M; i = i + 1) begin : aa
f3_add aa (
A[(2*i+1) : 2*i],
B[(2*i+1) : 2*i],
C[(2*i+1) : 2*i]
);
end
endgenerate
endmodule
| 7.024046 |
module PPG (
d,
A,
C
);
input [1:0] d;
input [`WIDTH:0] A;
output [`WIDTH:0] C;
genvar i;
generate
for (i = 0; i < `M; i = i + 1) begin : ppg0
f3_mult f3_mult_0 (
d,
A[2*i+1:2*i],
C[2*i+1:2*i]
);
end
endgenerate
endmodule
| 7.164526 |
module muxer (
from_ram,
from_const,
const_effective,
out
);
input [`WIDTH_D0:0] from_ram, from_const;
input const_effective;
output [`WIDTH_D0:0] out;
assign out = const_effective ? from_const : from_ram;
endmodule
| 6.618212 |
module ram #(
parameter DATA = 1188,
parameter ADDR = 6
) (
input clk,
// Port A
input wire a_wr,
input wire [ADDR-1:0] a_addr,
input wire [DATA-1:0] a_din,
output reg [DATA-1:0] a_dout,
// Port B
input wire b_wr,
input wire [ADDR-1:0] b_addr,
... | 7.30525 |
module const_ (
clk,
addr,
out,
effective
);
input clk;
input [5:0] addr;
output reg [`WIDTH_D0:0] out;
output reg effective; // active high if out is effective
always @(posedge clk) begin
effective <= 1;
case (addr)
1: out <= 0;
2: out <= 1;
4: out <= {6'b000101... | 7.25663 |
module FSM (
clk,
reset,
rom_addr,
rom_q,
ram_a_addr,
ram_b_addr,
ram_b_w,
pe,
done
);
input clk;
input reset;
output reg [8:0] rom_addr; /* command id. extra bits? */
input [28:0] rom_q; /* command value */
output reg [5:0] ram_a_addr;
output reg [5:0] ram_b_addr;
ou... | 6.752458 |
module select (
sel,
addr_in,
addr_fsm_in,
w_in,
addr_out,
w_out
);
input sel;
input [5:0] addr_in;
input [5:0] addr_fsm_in;
input w_in;
output [5:0] addr_out;
output w_out;
assign addr_out = sel ? addr_in : addr_fsm_in;
assign w_out = sel & w_in;
endmodule
| 7.910302 |
module TinyAESTopTestbench;
localparam RESET_PERIOD = 200000; //in pSec
parameter CLKIN_PERIOD = 5000;
//**************************************************************************//
// Wire Declarations
//**************************************************************************//
reg sys_rst_n;
wi... | 6.753723 |
module top (
input clk,
output D1,
output D2,
output D3,
output D4,
output D5,
output D6,
output D7,
output D8,
output uart_txd,
input uart_rxd,
output i2c_scl,
inout i2c_sda,
output spi_sclk,
output spi_mosi,
input spi_miso,
output spi_cs,
output ... | 7.233807 |
module tinycpu(clk,reset,run,in,cs,pcout,irout,qtop,abus,dbus,out);
input [0:0] clk,reset,run;
input [15:0] in;
output [2:0] cs;
output [15:0] irout,qtop,dbus,out;
output [11:0] pcout,abus;
wire [15] qnext,ramout,aluout;
reg [11:0] abus;
reg halt,cont,pcinc,push,pop,abus2pc,dbus2ir,dbus2qtop,dbus2ram,dbus... | 6.540244 |
module tinyEVR #(
parameter EVSTROBE_COUNT = 126,
parameter DEBUG = "false",
parameter TIMESTAMP_WIDTH = 64
) (
input wire evrRxClk,
(*mark_debug=DEBUG*) input [15:0] evrRxWord,
(*mark_debug=DEBUG*) input [ 1:0] evrCharIsK,
(*mark_debug=DEBUG*) output wire ... | 7.146152 |
module smallEVR #(
parameter ACTION_WIDTH = 1,
parameter DEBUG = "false",
parameter TIMESTAMP_WIDTH = 64
) (
input wire evrRxClk,
(*mark_debug=DEBUG*) input [15:0] evrRxWord,
(*mark_debug=DEBUG*) input [ 1:0] evrCharIsK,
(*mark_debug=DEBUG*) output wire p... | 7.50974 |
module tinyEVRcommon #(
parameter ACTION_RAM_WIDTH = 0,
parameter EVSTROBE_COUNT = 126,
parameter DEBUG = "false",
parameter TIMESTAMP_WIDTH = 64,
parameter ACT_MSB = ACTION_RAM_WIDTH ? ACTION_RAM_WIDTH - 1 : EVSTROBE_COUNT,
parameter ACT_LSB = ACTION_RAM_WIDTH ? ... | 7.47872 |
module tinyEVR_tb;
parameter TIMESTAMP_WIDTH = 64;
parameter ACTION_WIDTH = 4;
parameter EVSTROBE_COUNT = 126;
parameter EVCODE_SHIFT_ZERO = 8'h70;
parameter EVCODE_SHIFT_ONE = 8'h71;
parameter EVCODE_SECONDS_MARKER = 8'h7D;
reg sysClk = 1;
reg sysActionWriteEnab... | 6.738797 |
module TinyFPGA_B (
//output pin1_usb_dp,
//inout pin2_usb_dn,
input pin3_clk_16mhz, // 16MHz clock
//output pin4,
//output pin5,
output pin6, // Seven unused LEDs: 6 to 12
output pin7,
output pin8,
output pin9,
output pin10,
output pin11,
output pin12,
output pin13... | 6.592493 |
module TinyFPGA_B (
input CLK, // 16MHz clock
output LED, // User/boot LED next to power LED
output USBPU // USB pull-up resistor
);
reg [23:0] counter;
always @(posedge CLK) counter <= counter + 1;
// drive USB pull-up resistor to '0' to disable USB
assign USBPU = 0;
assign LED = counte... | 6.592493 |
module TinyMIPS_tb ();
// Regfile Data
reg clk;
reg regwrite;
reg [2:0] ra1;
reg [2:0] ra2;
reg [2:0] wa;
reg [7:0] wd;
wire [7:0] rd1, rd2;
// ALU Control Data
reg [5:0] funct;
reg [1:0] aluop;
wire [2:0] alucont;
// ALU Data
wire [7:0] result;
regfile reg1 (
.rd1(... | 6.629121 |
module rv2isa_InstUnpack (
// Packed message
input [`RV2ISA_INST_NBITS-1:0] inst,
// Packed fields
output [`RV2ISA_INST_OPCODE_NBITS-1:0] opcode,
output [ `RV2ISA_INST_RD_NBITS-1:0] rd,
output [ `RV2ISA_INST_RS1_NBITS-1:0] rs1,
output [ `RV2ISA_INST_RS2_NBITS-1:0] rs2,
output [... | 8.211707 |
module tinytot (
input clk,
input reset
);
wire xpc10;
always @(posedge clk) begin
//Start HPR tinytot.exe
if ((xpc10 == 0 /*0:US*/)) $finish(0);
//End HPR tinytot.exe
end
//Total area 0
// Total state bits in module = 0 bits.
// Total number of leaf cells = 0
endmodule
| 7.306575 |
module aes_128 (
clk,
state,
key,
out
);
input clk;
input [127:0] state, key;
output [127:0] out;
reg [127:0] s0, k0;
wire [127:0] s1, s2, s3, s4, s5, s6, s7, s8, s9,
k1, k2, k3, k4, k5, k6, k7, k8, k9,
k0b, k1b, k2b, k3b, k4b, k5b, k6b, k7b, k8b, k9b;
... | 6.624619 |
module one_round (
clk,
state_in,
key,
state_out
);
input clk;
input [127:0] state_in, key;
output reg [127:0] state_out;
wire [31:0] s0, s1, s2, s3,
z0, z1, z2, z3,
p00, p01, p02, p03,
p10, p11, p12, p13,
... | 7.018166 |
module final_round (
clk,
state_in,
key_in,
state_out
);
input clk;
input [127:0] state_in;
input [127:0] key_in;
output reg [127:0] state_out;
wire [31:0] s0, s1, s2, s3, z0, z1, z2, z3, k0, k1, k2, k3;
wire [7:0] p00, p01, p02, p03, p10, p11, p12, p13, p20, p21, p22, p23, p30, p31, p32, p3... | 7.609225 |
module S4 (
clk,
in,
out
);
input clk;
input [31:0] in;
output [31:0] out;
S
S_0 (
clk,
in[31:24],
out[31:24]
),
S_1 (
clk,
in[23:16],
out[23:16]
),
S_2 (
clk,
in[15:8],
out[15:8]... | 6.592394 |
module T (
clk,
in,
out
);
input clk;
input [7:0] in;
output [31:0] out;
S s0 (
clk,
in,
out[31:24]
);
assign out[23:16] = out[31:24];
xS s4 (
clk,
in,
out[7:0]
);
assign out[15:8] = out[23:16] ^ out[7:0];
endmodule
| 6.667023 |
module up_counter #(
parameter END_VALUE = 30,
NB_BITS = 5
) (
input clk,
input reset,
input trigger,
output done
);
// on the falling edge of the trigger signal we start counting
// until a reset or a new falling edge trigger occurs
reg [NB_BITS:0] counter;
reg triggered;
assign ... | 6.602909 |
module for the Ascend chip.
//==============================================================================
module tiny_aes_vc707(
input sys_clk_p,
input sys_clk_n,
input sys_rst, // SW8
output uart_txd,
input uart_rxd
);
//-----------------------------------------------------------------... | 6.949754 |
module td_fused_top_ap_hmul_3_max_dsp_16 (
input wire aclk,
input wire aclken,
input wire s_axis_a_tvalid,
input wire [15:0] s_axis_a_tdata,
input wire s_axis_b_tvalid,
input wire [15:0] s_axis_b_tdata,
output wire m_axis_result_tvalid,
output wir... | 6.827284 |
module td_fused_top_ap_hadd_6_full_dsp_16 (
input wire aclk,
input wire aclken,
input wire s_axis_a_tvalid,
input wire [15:0] s_axis_a_tdata,
input wire s_axis_b_tvalid,
input wire [15:0] s_axis_b_tdata,
output wire m_axis_result_tvalid,
output wi... | 6.827284 |
module td_fused_top_ap_hcmp_0_no_dsp_16 (
input wire s_axis_a_tvalid,
input wire [15:0] s_axis_a_tdata,
input wire s_axis_b_tvalid,
input wire [15:0] s_axis_b_tdata,
input wire s_axis_operation_tvalid,
input wire [ 7:0] s_axis_operation_tdata,
output wire m_... | 6.827284 |
module td_fused_top_Block_entry_proc_proc491 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp_434,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
... | 6.827284 |
module td_fused_top_Block_entry_proc_proc492 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp_435,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
... | 6.827284 |
module td_fused_top_Block_entry_proc_proc493 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp_436,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
... | 6.827284 |
module td_fused_top_Block_entry_proc_proc498 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
outp... | 6.827284 |
module td_fused_top_Block_entry_proc_proc499 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp_251,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
... | 6.827284 |
module td_fused_top_Block_entry_proc_proc500 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp_252,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
... | 6.827284 |
module td_fused_top_Block_entry_proc_proc501 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp_253,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
... | 6.827284 |
module td_fused_top_Block_entry_proc_proc506 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
outp... | 6.827284 |
module td_fused_top_Block_entry_proc_proc512 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
outp... | 6.827284 |
module td_fused_top_Block_entry_proc_proc513 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp_218,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
... | 6.827284 |
module td_fused_top_Block_entry_proc_proc514 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp_219,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
... | 6.827284 |
module td_fused_top_Block_entry_proc_proc515 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp_220,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
... | 6.827284 |
module td_fused_top_Block_entry_proc_proc520 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
outp... | 6.827284 |
module td_fused_top_Block_entry_proc_proc521 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp_141,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
... | 6.827284 |
module td_fused_top_Block_entry_proc_proc522 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp_142,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
... | 6.827284 |
module td_fused_top_Block_entry_proc_proc523 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp_143,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
... | 6.827284 |
module td_fused_top_Block_entry_proc_proc528 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
outp... | 6.827284 |
module td_fused_top_Block_entry_proc_proc534 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
outp... | 6.827284 |
module td_fused_top_Block_entry_proc_proc535 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp_108,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
... | 6.827284 |
module td_fused_top_Block_entry_proc_proc536 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp_109,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
... | 6.827284 |
module td_fused_top_Block_entry_proc_proc537 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp_110,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
... | 6.827284 |
module td_fused_top_Block_entry_proc_proc542 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
outp... | 6.827284 |
module td_fused_top_Block_entry_proc_proc543 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp_31,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
o... | 6.827284 |
module td_fused_top_Block_entry_proc_proc544 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp_32,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
o... | 6.827284 |
module td_fused_top_Block_entry_proc_proc545 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp_33,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
o... | 6.827284 |
module td_fused_top_Block_entry_proc_proc550 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
outp... | 6.827284 |
module td_fused_top_Block_entry_proc_proc556 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
outp... | 6.827284 |
module td_fused_top_Block_entry_proc_proc557 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp_431,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
... | 6.827284 |
module td_fused_top_Block_entry_proc_proc558 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp_432,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
... | 6.827284 |
module td_fused_top_Block_entry_proc_proc559 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp_433,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
... | 6.827284 |
module td_fused_top_Block_entry_proc_proc565 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
outp... | 6.827284 |
module td_fused_top_Block_entry_proc_proc566 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp_354,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
... | 6.827284 |
module td_fused_top_Block_entry_proc_proc567 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp_355,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
... | 6.827284 |
module td_fused_top_Block_entry_proc_proc568 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp_356,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
... | 6.827284 |
module td_fused_top_Block_entry_proc_proc573 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
outp... | 6.827284 |
module td_fused_top_Block_entry_proc_proc574 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp_272,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
... | 6.827284 |
module td_fused_top_Block_entry_proc_proc (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP16_accum1_out_0_memcore_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 4;
parameter MEM_SIZE = 14;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
ou... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP16_accum1_out_0_memcore (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
q1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd14;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [AddressWi... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP16_accum2_out_0_memcore_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 3;
parameter MEM_SIZE = 7;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
out... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP16_accum2_out_0_memcore (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
q1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd7;
parameter AddressWidth = 32'd3;
input reset;
input clk;
input [AddressWid... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP16_ifmap_vec_memcore_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
d1,
we1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 6;
parameter MEM_SIZE = 54;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
i... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP16_ifmap_vec_memcore (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1,
q1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd54;
parameter AddressWidth = 32'd6;
input reset;
input clk;
in... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP16_ifmap_vec #(
parameter
DataWidth = 16,
AddressRange = 32,
AddressWidth = 5,
BufferCount = 2,
IndexWidth = 1
) (
// system signals
input wire clk,
input wire reset,
// initiator
input... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP16_products_0_memcore_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 5;
parameter MEM_SIZE = 27;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
outp... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP16_products_0_memcore (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
q1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd27;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidt... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP47680_accum1_out_0_memcore_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
d1,
we1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 4;
parameter MEM_SIZE = 16;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP47680_accum1_out_0_memcore (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1,
q1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd16;
parameter AddressWidth = 32'd4;
input reset;
input clk... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP47680_accum2_out_0_memcore_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
d1,
we1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 4;
parameter MEM_SIZE = 16;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP47680_accum2_out_0_memcore (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1,
q1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd16;
parameter AddressWidth = 32'd4;
input reset;
input clk... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP47680_accum2_out_0 #(
parameter
DataWidth = 16,
AddressRange = 32,
AddressWidth = 3,
BufferCount = 2,
IndexWidth = 1
) (
// system signals
input wire clk,
input wire reset,
// initiator
... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP47680_ifmap_vec_0_0_0_memcore_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
d1,
we1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 7;
parameter MEM_SIZE = 128;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP47680_ifmap_vec_0_0_0_memcore (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1,
q1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd128;
parameter AddressWidth = 32'd7;
input reset;
input... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP47680_products_0_0_memcore_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 6;
parameter MEM_SIZE = 64;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP47680_products_0_0_memcore (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
q1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd64;
parameter AddressWidth = 32'd6;
input reset;
input clk;
input [Addres... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP47773_accum1_out_0_memcore_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
d1,
we1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP47773_accum1_out_0_memcore (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1,
q1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP47773_accum2_out_0_memcore_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 3;
parameter MEM_SIZE = 8;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
inpu... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP47773_accum2_out_0_memcore (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd8;
parameter AddressWidth = 32'd3;
input reset;
input clk;
input... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP47773_ifmap_vec_0_memcore_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
d1,
we1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 9;
parameter MEM_SIZE = 288;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP47773_ifmap_vec_0_memcore (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1,
q1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd288;
parameter AddressWidth = 32'd9;
input reset;
input clk... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP47773_ifmap_vec_0 #(
parameter
DataWidth = 16,
AddressRange = 32,
AddressWidth = 8,
BufferCount = 2,
IndexWidth = 1
) (
// system signals
input wire clk,
input wire reset,
// initiator
... | 6.827284 |
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