code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module timer_ssp (
input clock,
input rst_n,
input [31:0] apb_addr,
input apb_sel,
input apb_write,
input apb_ena,
input [31:0] apb_wdata,
output reg [31:0] apb_rdata,
input [ 3:0] apb_pstb,
output ... | 7.371588 |
module timer_stepper_test;
reg clk = 0;
reg [31:0] prescaler = 5;
reg run = 0;
wire [23:0] data;
time_stepper #(
.TIME_LENGTH(24)
) test (
clk,
prescaler,
run,
data
);
initial begin
$dumpfile("timer_stepper_test.v");
$dumpvars(0, timer_stepper_test);
#10 run... | 7.661777 |
module timer_stream_adapter (
asyncTime_V,
synchTime_1_V_V_din,
synchTime_1_V_V_full_n,
synchTime_1_V_V_write,
synchTime_2_V_V_din,
synchTime_2_V_V_full_n,
synchTime_2_V_V_write,
ap_clk,
ap_rst
);
parameter ap_const_lv64_0 = 64'b0000000000000000000000000000000000000000000000000000... | 7.147767 |
module timer_stream_adapter_ap_rst_if #(
parameter RESET_ACTIVE_LOW = 0
) (
input wire din,
output wire dout
);
assign dout = (RESET_ACTIVE_LOW == 1) ? ~din : din;
endmodule
| 7.147767 |
module timer_stream_adapter_synchTime_1_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
output wire TVALID,
input wire TREADY,
output wire [63:0] TDATA,
// User signals
input wire [63:0] synchTime_1_V_V_din,
output wire synchTim... | 7.147767 |
module timer_stream_adapter_synchTime_1_fifo #(
parameter DATA_BITS = 8,
DEPTH_BITS = 4
) (
input wire clk,
input wire aclr,
output wire empty_n,
output wire full_n,
input wire read,
input wire ... | 7.147767 |
module timer_stream_adapter_synchTime_1_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output ... | 7.147767 |
module timer_stream_adapter_synchTime_2_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
output wire TVALID,
input wire TREADY,
output wire [63:0] TDATA,
// User signals
input wire [63:0] synchTime_2_V_V_din,
output wire synchTim... | 7.147767 |
module timer_stream_adapter_synchTime_2_fifo #(
parameter DATA_BITS = 8,
DEPTH_BITS = 4
) (
input wire clk,
input wire aclr,
output wire empty_n,
output wire full_n,
input wire read,
input wire ... | 7.147767 |
module timer_stream_adapter_synchTime_2_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output ... | 7.147767 |
module timer_stream_adapter_top (
synchTime_1_TVALID,
synchTime_1_TREADY,
synchTime_1_TDATA,
synchTime_2_TVALID,
synchTime_2_TREADY,
synchTime_2_TDATA,
aresetn,
aclk,
asyncTime_V
);
parameter RESET_ACTIVE_LOW = 1;
output synchTime_1_TVALID;
input synchTime_1_TREADY;
output ... | 7.147767 |
module timer_sync (
input wire sys_rst,
input wire sys_clk,
input wire t, // external input clock
output wire t_rise,
output wire t_fall
);
// Latch
`ifdef TIME_SYNC_LATCH
reg t_latch;
always @(sys_clk, t) begin
if (sys_clk) t_latch <= t;
end
`endif
reg t_reg;
always @(posedge sy... | 7.224187 |
module: timer
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module timer_t;
// Inputs
reg clk;
reg rst;
reg [23:0] tmr_period;
reg [23:0] tmr_compare;
// Outputs
wire [23... | 7.287821 |
module timer_tb;
reg RSTB;
reg clock;
reg power1, power2;
always #10 clock <= (clock === 1'b0);
initial begin
clock <= 0;
end
initial begin
$dumpfile("timer.vcd");
$dumpvars(0, timer_tb);
// Repeat cycles of 1000 clock edges as needed to complete testbench
repeat (50) begin
... | 6.888373 |
module: timer
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module timer_test;
// Inputs
reg clk;
reg rst;
reg start;
reg endn;
// Outputs
wire [9:0] sec;
wire [2:0] remainder;
... | 7.287821 |
module Timer_testbench;
/* Inicialização das variáveis de input */
reg count_tb, reset_tb, clk_tb;
reg signed [8:0] adder_tb;
/* Inicialização da variáveis de output */
wire [3:0] seconds0_tb, seconds1_tb, minutes0_tb;
wire [6:0] s0_7seg, s1_7seg, m0_7seg;
/* Inicialização do módulo a ser testado */... | 6.631631 |
module Timer_v #(
parameter DATA_WIDTH = 4
) (
i_clk,
rst_n,
data_in,
cnt_out,
enable,
cnt_one
);
input i_clk;
input rst_n;
input [DATA_WIDTH-1:0] data_in;
input enable;
output [DATA_WIDTH-1:0] cnt_out;
output cnt_one;
wire [DATA_WIDTH-1:0] count_next;
reg [DATA_WIDTH-1:0... | 7.103779 |
module timer_ver (
clk,
rst_n,
en_out
);
input clk, rst_n;
output en_out;
reg en_out;
reg [31:0] counter;
reg [31:0] trig_time;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
en_out <= 1'b0;
counter <= 32'd0;
trig_time <= 32'd100000; //2ms
end else begi... | 6.676996 |
module timer_ver_db (
clk,
rst_n,
en_out
);
input clk, rst_n;
output en_out;
reg en_out;
reg [31:0] counter;
reg [31:0] trig_time;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
en_out <= 1'b0;
counter <= 32'd0;
trig_time <= 32'd1000000; //20ms
end else... | 6.794421 |
module//////////
module Timer_v_tb ();
parameter WIDTH = 4 ;
reg i_clk ;
reg rst_n ;
reg enable ;
reg [WIDTH-1:0] data_in ;
wire [WIDTH-1:0] cnt_out ;
wire cnt_one ;
///instantiation ///
Timer_v DUT (i_clk , rst_n , data_in , cnt_out , enable , cnt_one) ;
initial
begin
i_clk = 1'b0 ;
rst_n = 1'b0 ;
end
a... | 7.045634 |
module timer_wb (
// RCC
input wire i_clk,
input wire i_reset,
// Trigger out signal
output wire o_timer_trigger,
// Wishbone
input wire [31:0] i_wb_adr,
input wire [31:0] i_wb_dat,
input wire [ 3:0] i_wb_sel,
input wire i_wb_we,
input wire ... | 8.7028 |
module timer_wrapper ( /*AUTOARG*/
// Outputs
timer_apb_prdata,
timer_apb_pready,
timer_apb_pslverr,
timer_hires_irq,
timer_systick_irq,
// Inputs
apb_timer_psel,
apb_timer_paddr,
apb_timer_penable,
apb_timer_pwrite,
apb_timer_pwdata,
clk,
rst_n
);
input apb_... | 7.23652 |
module xyz (
input clk,
output reg p
);
always @(clk) begin
p <= clk;
end
endmodule
| 7.433964 |
module tb ();
reg clk;
wire p;
xyz x (
clk,
p
);
initial clk = 1'b0;
always @(*) #5 clk = ~clk;
initial begin
$dumpfile("tb.vcd");
$dumpvars(0, tb);
// clk = 1'b0;
#1000 $finish;
end
endmodule
| 7.002324 |
module example (
input logic a,
b,
c,
output y
);
logic ab, bb, cb, n1, n2, n3;
assign #1{ab, bb, cb} = -{a, b, c};
assign #2 n1 = ab & bb & cb;
assign #2 n2 = a & bb & cb;
assign #2 n3 = a & bb & c;
assign #4 y = n1 | n2 | n3;
endmodule
| 6.978445 |
module top;
logic a, b, c, y;
example U0 (
a,
b,
c,
y
);
initial begin
$dumpfile("outputs/simple.vcd");
$dumpvars(0, top);
$display("\t\ttime\ta\tb\tc\t\y");
$monitor("%d\t%b\t%b\t%b\t%b", $time, a, b, c, y);
#1 a = 1;
b = 0;
c = 0;
#1 a = 1;
b = 0... | 7.3094 |
module timescale_syntax (
a,
b,
c
);
input a;
input b;
output c;
assign c = a ^ b;
endmodule
| 6.834049 |
module TimeSelector (
input [2:0] c_type,
input [2:0] ing_type,
output reg [1:0] t_value
);
always @(*) begin
if (c_type == 3'b001)
case (ing_type)
3'b001: t_value = 2;
3'b010: t_value = 3;
3'b011: t_value = 0;
3'b100: t_value = 0;
3'b101: t_value = 1... | 6.525033 |
module ubbDemodulator #(
parameter S_AXIS_CONFIG_TDATA_WIDTH = 32,
parameter S_AXIS_RCVR_TDATA_WIDTH = 16,
parameter S_AXIS_RCVR_TUSER_WIDTH = 2,
parameter S_AXIS_NCO_TDATA_WIDTH = 32,
parameter S_AXIS_NCO_TUSER_WIDTH = 2,
parameter M_AXIS_TIME_TDATA_WIDTH = 64,
parameter M_AXIS_... | 7.335111 |
module TimeShow (
input [5:0] hour__,
input [5:0] minute__,
input [5:0] second__,
input [5:0] hour_,
input [5:0] minute_,
input [5:0] second_,
input set_en,
input alarm_en,
output [41:0] all_hex
);
reg [5:0] second;
reg [5:0] minute;
reg [5:0] hour;
initial begin
se... | 7.003601 |
module timeslot (
clk_6M,
rstz,
p_1us,
p_05us,
regi_time_base_offset,
corre_sync_p,
pssyncCLK_p,
//
BTCLK,
tslot_p,
half_tslot_p,
offcounter_1us,
regi_slot_offset
);
input clk_6M, rstz, p_1us, p_05us;
input [27:0] regi_time_base_offset;
input corre_sync_p, pss... | 6.520066 |
module TimesN_comb1 (
output [7:0] Times_x,
input [7:0] X
);
wire [7:0] Times_x1, Times_x2;
assign Times_x1 = X;
assign Times_x2 = Times_x1 + X;
assign Times_x = Times_x2 + X;
endmodule
| 6.666919 |
module TimesN_pipe (
output reg [7:0] Times_x,
input clk,
input [7:0] X
);
reg [7:0] Times_x1, Times_x2;
reg [7:0] X1, X2;
always @(posedge clk) begin
// Pipeline stage 1
X1 <= X;
Times_x1 <= X;
// Pipeline stage 2
X2 <= X1;
Times_x2 <= Times_x1 + X1;
// Pipeline stage 3
... | 6.534716 |
module Timestamp_Counter (
input i_sys_clk,
input i_enable,
input i_incr,
input i_event,
output o_rollover,
output reg [7:0] o_time
);
assign o_rollover = (&o_time) & i_incr;
always @(posedge i_sys_clk) begin
if (!i_enable) begin
o_time <= 1;
end else if (i_event) begin
... | 7.552579 |
module Timestamp_Counter_tb;
reg clk, incr, _event, enable;
wire w_rollover;
wire [7:0] w_time;
Timestamp_Counter tsc (
.i_sys_clk(clk),
.i_enable(enable),
.i_event(_event),
.i_incr(incr),
.o_rollover(w_rollover),
.o_time(w_time)
);
always #2 clk = ~clk;
initial beg... | 7.552579 |
modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to dis... | 8.081644 |
module timestamp_forward (
clk_in,
timestamp_in,
clk_out,
timestamp_out
);
parameter TIMESTAMP_WIDTH = 64;
input clk_in;
input [TIMESTAMP_WIDTH-1:0] timestamp_in;
input clk_out;
output [TIMESTAMP_WIDTH-1:0] timestamp_out;
// clk_in domain
reg req_in = 0;
reg ack_in = 0;
reg [TIMESTA... | 7.231397 |
module timestamp_gen #(
parameter TIMESTAMP_WIDTH = 5,
parameter TIMESTAMP_UNIT_WIDTH = 32,
parameter TIMESTAMP_UNIT = 1 << TIMESTAMP_UNIT_WIDTH
) (
input clk,
input reset,
output reg [TIMESTAMP_WIDTH-1:0] timestamp
);
reg [TIMESTAMP_UNIT_WIDTH-1:0] counter;
always @(posedge clk) begin
... | 7.279181 |
module timestamp_insertion #(
parameter TIMESTAMP_WIDTH = 64,
parameter C_M_AXIS_DATA_WIDTH = 256,
parameter C_M_AXIS_TUSER_WIDTH = 128
) (
output reg [ C_M_AXIS_DATA_WIDTH-1:0] m_axis_tdata,
output reg [ C_M_AXIS_TUSER_WIDTH-1:0] m_axis_tuser,
output reg [C_M_AXIS_DATA_WIDTH/8-1:0] m_axis_tst... | 7.796676 |
module timestamp_pad_proc #(
parameter TS_POSITION_WIDTH = 8,
parameter C_M_AXIS_TDATA_WIDTH = 256,
parameter C_S_AXIS_TDATA_WIDTH = 256
) (
input axi_aclk,
input axi_resetn,
input [ 63:0] ref_counter,
input ts_valid,
input [ TS_POSI... | 8.520097 |
modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to dis... | 8.081644 |
module TimeStamp_stimulus;
reg clk, reset;
initial begin
clk = 1'b1;
reset = 1'b1;
#20 reset = 1'b0;
end
always #2 clk = ~clk;
wire [3:0] oldest;
reg en;
reg [3:0] access;
TimeStamp time_stamp (
.clk(clk),
.reset(reset),
.en(en),
.access(access),
.oldest_sta... | 6.883594 |
modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to dis... | 8.081644 |
modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to dis... | 8.081644 |
module Times_to_Seg (
input clk,
input reset,
input [3:0] Second_First,
input [3:0] Second_Second,
input [3:0] Minute_First,
input [3:0] Minute_Second,
input [3:0] Hour_First,
input [3:0] Hour_Second,
output reg [7:0] seg_out,
output reg [7:0] seg_en
);
reg [2:0] count;
wire... | 6.715929 |
module timetag_bench ();
reg clk;
reg fx2_clk;
reg cmd_wr;
reg [7:0] cmd_in;
wire [15:0] length;
reg request_length;
wire [7:0] data;
wire data_rdy;
reg data_ack;
reg [3:0] detectors;
wire [3:0] laser_en;
wire running;
// Bidirs
// Instantiate the UUT
timetag uut (
.fx2_clk(f... | 6.650135 |
module TimeTrans (
output flicker,
output reg [7:0] oSeg,
output [3:0] oAn,
input [4:0] lightTime,
input Cm,
Cc,
input clk
);
wire [7:0] oSeg1, oSeg2, oSeg3, oSeg4;
wire [7:0] sec;
reg [3:0] CmBuf = 4'd15;
reg [3:0] CcBuf = 4'd15;
DigitTrans dt (
flicker,
sec,
... | 6.531705 |
module TimeUnitEnable (
input clk,
input reset,
output pulse
);
function integer Size(input integer in);
for (Size = 0; in > 0; Size = Size + 1) in = in >> 1;
endfunction
parameter FREQ_CLK = 50000000;
parameter FREQ_WANTED = 20000;
localparam NB_TIC = FREQ_CLK / FREQ_WANTED; // Divisio... | 6.700418 |
module TimeZoneHours (
TZHours,
clk,
KeyPlus,
KeyMinus,
reset,
EditPos,
EditMode,
screen,
TZPlusMinus
);
output reg [6:0] TZHours;
input [2:0] EditPos;
input EditMode, clk, KeyPlus, KeyMinus, reset, TZPlusMinus;
input [1:0] screen;
reg [2:0] mode;
always @(posedge clk, ... | 6.749354 |
module TimeZoneMinutes (
TZMinutes,
clk,
KeyPlus,
KeyMinus,
reset,
EditPos,
EditMode,
screen
);
output reg [6:0] TZMinutes;
input [2:0] EditPos;
input EditMode, clk, KeyPlus, KeyMinus, reset;
input [1:0] screen;
reg [2:0] mode;
always @(posedge clk, negedge reset) begin
... | 8.196704 |
module TimeZonePlusMinus (
TZPlusMinus,
clk,
KeyPlus,
KeyMinus,
reset,
EditPos,
EditMode,
screen,
TZHours
);
output reg TZPlusMinus;
input [2:0] EditPos;
input EditMode, clk, KeyPlus, KeyMinus, reset;
input [6:0] TZHours;
input [1:0] screen;
reg mode;
always @(posedge... | 7.827526 |
module implements the product between an input Galois
Finite {2^8} element and a fixed element {03} of the same field.
-------------------------------------------------------------------------------
-- Copyright (C) 2016 ClariPhy Argentina S.A. All rights reserved
----------------------------------------------... | 7.842559 |
module implements the product between an input Galois
Finite {2^8} element and a fixed element {02} of the same field.
-------------------------------------------------------------------------------
-- Copyright (C) 2016 ClariPhy Argentina S.A. All rights reserved
----------------------------------------------... | 7.842559 |
module timer_ns (
input wire clk,
output reg clk_1ms,
input [1:0] spe
);
reg [31:0] cnt;
reg [31:0] rep;
initial begin
cnt[31:0] <= 0;
clk_1ms <= 0;
end
always @(posedge clk) begin
case (spe) //ٶȿص״̬ȷʱӵƵ
2'b00: begin
rep <= 25000000; //1HZ
end
2'b01: b... | 6.698628 |
module time_alignment (
input clk,
input rst_n,
//ǰ
input pre_src_frame_vsync,
input pre_src_frame_href,
input pre_src_frame_clken,
input [23 : 0] pre_img,
input pre_tx_frame_vsync,
input pre_tx_frame_href,
input ... | 6.913041 |
module TIME_CAL (
RESETN,
CLK,
IN_TIME,
IN_DATE,
IN_ALARM_TIME,
MODE,
MODE_STATE,
SETTING,
ALARM_SETTING,
SETTING_OK,
OUT_TIME,
OUT_DATE,
OUT_ALARM_TIME
);
input RESETN, CLK;
input [16:0] IN_ALARM_TIME;
input [16:0] IN_TIME;
input [15:0] IN_DATE;
input MODE... | 6.923508 |
module time_change (
clk_1hz,
count,
mode,
led1,
hour_change,
minute_change,
alarm_en,
count_alarm
);
input clk_1hz, mode, hour_change, minute_change, alarm_en;
output led1;
output [20:0] count;
output [20:0] count_alarm;
reg led1;
reg [20:0] count;
reg [20:0] count_alarm;
... | 6.894827 |
module time_cnt (
input wire aclk,
input wire ap_start,
output wire time_out
);
localparam [32-1:0] LP_TIME_VALUE = 32'h7735_9400; // around 8s for 250MHz
reg [32-1:0] time_cnt = 32'd0;
assign time_out = (time_cnt == 32'd1);
always @(posedge aclk) begin
if (ap_start) begin
time_cnt ... | 6.837235 |
module time_comparator #(
parameter BITS = 32
) (
input [BITS-1:0] clock,
input [BITS-1:0] timestamp,
output reg match,
output reg valid
);
reg [BITS-1:0] half_range;
reg [BITS-1:0] delta;
always @* begin
//FIXME: this should be based on BITS
half_range = 32'h7fffffff;
delta = ... | 6.694844 |
module time_comparator_tb;
reg [31:0] clock;
reg [31:0] timestamp;
wire match;
wire valid;
`define JITTER 4
time_comparator time_check (
.clock(clock),
.timestamp(timestamp),
.match(match),
.valid(valid)
);
integer i;
initial begin
$display("timestamp,clock,match,vali... | 6.694844 |
module time_compare (
input [63:0] time_now,
input [63:0] trigger_time,
output now,
output early,
output late,
output too_early
);
wire sec_match = (time_now[63:32] == trigger_time[63:32]);
wire sec_late = (time_now[63:32] > trigger_time[63:32]);
wire tick_match = (time_no... | 7.402805 |
module TIME_CONT (
RESETN,
CLK,
IN_TIME,
IN_DATE,
FLAG,
UP,
DOWN,
OUT_TIME,
OUT_DATE
);
input RESETN, CLK;
input [16:0] IN_TIME, IN_DATE;
input [2:0] FLAG;
input [2:0] UP, DOWN;
output wire [16:0] OUT_TIME, OUT_DATE;
/* FLAG BUFF */
parameter FLAG_CONTROL_STATE = 3'b0... | 6.7723 |
module divider1 (
input clk,
output reg clk_1
);
parameter NUM_DIV = 100000000;
reg [31:0] cnt;
always @(posedge clk) begin
if (cnt < NUM_DIV / 2 - 1) begin
cnt <= cnt + 1'b1;
clk_1 <= clk_1;
end else begin
cnt <= 32'b0;
clk_1 <= ~clk_1;
end
end
endmodule
| 7.259919 |
module TimeDeal (
input clk, //1s
input rst_n,
output [3:0] min_l,
output [3:0] min_h,
output [3:0] sec_l,
output [3:0] sec_h
);
reg [3:0] dout1;
reg [3:0] dout2;
reg [3:0] dout3;
reg [3:0] dout4;
//秒的高、低位，分钟的高、低位
reg carry1, carry2, carry3;
//进位
//先处理秒的低位
always @(posedge c... | 7.760355 |
module time_design (
input clk,
input rst,
input [15:0] data,
output reg [7:0] seg_data,
output reg [3:0] seg_cs
);
reg clk_500HZ;
integer clk_cnt;
always @(posedge clk or posedge rst) begin
if (rst) begin
clk_500HZ <= 0;
clk_cnt <= 0;
end else begin
if (clk_cnt >=... | 8.093298 |
module time_display (
// input
CLK,
RSTN,
SEG_A_VAL,
SEG_B_VAL,
SEG_C_VAL,
SEG_D_VAL,
// output
SEG_A,
SEG_B,
SEG_C,
SEG_D
);
// ------ input --------------------------------------------
input CLK, RSTN;
input [3:0] SEG_A_VAL, SEG_B_VAL, SEG_C_VAL, SEG_D_VAL;
// ... | 6.981525 |
module time_divider #( //分频器
parameter N = 2,
WIDTH = 8
) (
input clk,
input rst,
output reg clk_out
); //N是分频比，WIDTH计数器位宽
reg [WIDTH-1:0] cnt;
always @(posedge clk or posedge rst) begin
if (rst) begin
cnt <= 0;
clk_out <= 0;
end
else if(cnt==(N>>1)-1) //偶分频，计数器计到N/2-1... | 6.589183 |
module time_exceed (
input wire clk,
input wire rst,
input wire [7:0] ms,
input wire [7:0] sec,
input wire [7:0] min,
output reg legal
);
always @(posedge clk or posedge rst) begin
if (rst) legal <= 'b1;
else begin
if (min == 8'b0000_0001 || min == 8'b0000_0000) legal <= 'b1;
... | 8.210795 |
module time_fifo #(
parameter NAME = "SETME"
) (
input clk,
input rst,
input [1:0] state,
input print
);
real idle, calc, done, sum;
always @(posedge clk) begin
if (rst) begin
idle = 0;
calc = 0;
done = 0;
end else begin
case (state)
0: idle = idle + 1;
... | 6.872364 |
module time_fsm (
input wire enable,
input wire reset,
input wire CLK, //10kHz
input wire [15:0] secondsToCount,
output reg finished
);
reg [15:0] count;
reg [15:0] seconds;
reg [ 7:0] countSeconds;
parameter MAX = 10000;
/*Contador de tiempo: habilita y deshabilita el paso al siguie... | 7.742458 |
module time_manager (
//input
CLK,
RSTN,
//output
SEC_SIG
);
//--- input --------------------------------------------------------------
input CLK;
input RSTN;
//--- output -------------------------------------------------------------
output SEC_SIG;
//--- reg -------------------------... | 6.602098 |
module time_parameters (
input reset,
input clock,
input [1:0] parameter_selector, //from switch
input [3:0] time_value, //from switch
input reprogram,
input [1:0] interval,
output [3:0] value
);
parameter T_ARM_DELAY = 2'b00;
parameter T_DRIVER_DELAY = 2'b01;
parameter T_PASSENGE... | 7.050443 |
module time_posedge #(
parameter NAME = "SETME"
) (
input signal
);
integer old_time;
always @(posedge signal) begin
$display("%s: %d ns", NAME, $stime - old_time);
old_time <= $stime;
end
endmodule
| 6.533868 |
module time_sel_sync (
input wire areset,
input wire clk,
input wire sel,
input wire [63:0] ntp_time_a,
input wire ntp_time_upd_a,
input wire [63:0] ntp_time_b,
input wire ntp_time_upd_b,
output wire [63:0] ntp_time
);
(* ASYNC_REG = "TRUE", S... | 7.451523 |
module time_signature_clock (
input clk,
input [31:0] beat_cycles,
output [1:0] pulse
);
parameter BEATS_PER_MEASURE = 4;
parameter NOTE_BEAT = 4;
parameter PULSE_LENGTH = 10000000;
reg [31:0] period_count = 0;
reg [ 7:0] beat_count = 0;
reg [ 1:0] tick = 2'b10;
always @(posedge clk)
i... | 7.642278 |
module time_simulation ();
reg clk;
initial begin
clk = 1'b0;
repeat (10) begin
#50 clk = ~clk;
end
#50 $finish;
end
Top test (.clkin(clk));
endmodule
| 6.544532 |
module time_slice_gen #(
) ( // generate time slice for tx_control.v
input wire clk,
input wire rstn,
input wire tsf_pulse_1M,
input wire slv_reg_wren_signal,
input wire [1:0] count_total_slice_idx,
input wire [19:0] count_total,
input wire [1:0] count_start_slice_idx,
input wire [19:... | 7.715108 |
module TIME_STATE_MACHINE (
input wire reset_n,
clk,
set_time,
// alarm,
//Toggle_switch,
hours_set,
mins_set,
//output reg [4 : 0] hour,
// reg [5 : 0] mins,
output reg hours,
mins,
secs
);
parameter first = 2'b00, second = 2'b01, third = 2'b10, four = 2'b1... | 6.747396 |
module time_stepper #(
parameter TIME_LENGTH = 24
) (
input i_clk,
input [31:0] prescaler,
input i_run,
output reg [TIME_LENGTH - 1 : 0] o_time
);
reg [31:0] counter = 0;
always @(posedge i_clk) begin
if (i_run) begin
counter <= counter + 1;
if (counter >= prescaler) begin
... | 7.849752 |
module time_suit (
clk,
rst_n,
clk_suit
);
input clk;
input rst_n;
output clk_suit;
reg [27:0] count;
reg clk_suit;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
count <= 0;
clk_suit <= 0;
end else if (count < 20000) count <= count + 1;
else begin
... | 6.856237 |
module time_sync (
input wb_clk_i,
input rst_i,
input cyc_i,
input stb_i,
input [2:0] adr_i,
input we_i,
input [31:0] dat_i,
output [31:0] dat_o,
output ack_o,
input sys_clk_i,
output [31:0] master_time_o,
input pps_posedge,
input pps_negedge,
input exp_pps_in,
... | 7.746656 |
module Time_Synch (
input clk,
rst,
syn_run,
input metric_val,
input [21:0] P_Metric_Re,
P_Metric_Im,
input [21:0] R_Metric,
input [3:0] SNR,
output syn_done,
output reg [31:0] FRE_O
);
parameter SYN_VAL = 6'd56;
reg [16:0] Synch_thres_coeff[15:0]; // ... | 8.369612 |
module time_text (
input wire clk,
reset,
pause,
input wire refresh_tick,
input wire [20:0] pix_x,
pix_y,
output wire time_on,
output wire [2:0] bit_addr,
output wire [10:0] rom_addr
);
//variables
wire [ 3:0] row_addr;
reg [12:0] char_addr;
reg [23:0] time_tick;
reg [... | 6.997507 |
module time_transfer_tb ();
reg clk = 0, rst = 1;
always #5 clk = ~clk;
initial begin
@(negedge clk);
@(negedge clk);
rst <= 0;
end
initial $dumpfile("time_transfer_tb.vcd");
initial $dumpvars(0, time_transfer_tb);
initial #100000000 $finish;
wire exp_time, pps, pps_rcv;
wire [63:0] v... | 7.489384 |
module time_updater (
input wire clk,
output wire timer
);
reg [11:0] cnt;
assign timer = cnt[11];
always @(posedge clk) begin
cnt <= (cnt === {12{1'b1}}) ? 12'h0 : cnt + 12'h1;
end
endmodule
| 6.912329 |
module time_val_rdy #(
parameter NAME = "SETME"
) (
input clk,
input rst,
input val,
input rdy
input print
);
real idle, calc, done, sum;
always @ (posedge clk) begin
if (rst) begin
idle = 0;
calc = 0;
done = 0;
end
else begi... | 6.908664 |
module top;
reg ck;
specify
$width(posedge ck, 30);
$width(negedge ck, 25);
endspecify
initial $monitor("%4d: ck=%b", $time, ck);
initial begin
ck = 1'b1;
#50;
ck = 1'b0;
$display("No violation expected at %d", $time);
#50;
ck = 1'b1;
$display("No violation expected at ... | 6.559821 |
module TimingControl #(
parameter SYM_WIDTH = 1,
parameter INT_WIDTH = 1,
parameter DEC_WIDTH = 14,
parameter signed [`DATA_WIDTH-1 : 0] ONE_DIV_FS_DIV_BAND = 'sh03E3,
parameter signed [`DATA_WIDTH-1 : 0] ONE = 'sh4000
) (
input wire clk,
input wire rstn,
input wire signed [`DATA_WIDTH-1... | 7.634528 |
module timingsgen (
input clock,
input VideoMode videoMode,
output reg [11:0] counterX,
output reg [11:0] counterY,
output reg [11:0] visible_counterX,
output reg [11:0] visible_counterY,
output reg hsync,
output reg vsync,
output reg de,
output reg state
);
/*
H_SYNC ... | 7.07401 |
module timing_adapter_0001 (
// Interface: clk
input clk,
// Interface: reset
input reset_n,
// Interface: in
input in_valid,
input [7:0] in_data,
// Interface: out
output reg out_valid,
output reg [7:0] out_data,
input ... | 7.827601 |
module timing_adapter_32 (
// Interface: clk
input clk,
input reset,
// Interface: in
output reg in_ready,
input in_valid,
input [31:0] in_data,
input in_startofpacket,
input in_endofpacket,
input [ 1:0... | 7.827601 |
module timing_adapter_8 (
// Interface: clk
input clk, //INPUT : CLK
input reset, //INPUT : Asynchronous ACTIVE LOW Reset
// Interface: in
output reg in_ready, //OUTPUT : 'TIMING ADAPTER' READYNESS TO ACCEPT DATA FROM 'MAC'
input in_valid, //INPUT : 'MAC TO TIMING AD... | 7.827601 |
module timing_adapter_fifo_32 (
output reg [3:0] fill_level,
// Interface: clock
input clk,
input reset,
// Interface: data_in
output reg in_ready,
input in_valid,
input [36:0] in_data,
// Interface: data_out
input out_... | 7.827601 |
module timing_adapter_fifo_8 (
output reg [6:0] fill_level, //OUTPUT : 'TIMING ADAPTER' FIFO FILL LEVEL
// Interface: clock
input clk, //INPUT : CLK
input reset, //INPUT : Asynchronous ACTIVE LOW Reset
// Interface: data_in
output reg in_ready, //OUTPUT : 'TIMING ADAPTER' READYNESS TO ACC... | 7.827601 |
module timingcontrol (
wrflag,
MEMWR,
cs,
clk,
HLDA,
AEN,
reset,
IReady,
TReady,
IOR,
IOW,
IOflag,
mem2mem,
Data_flag,
flag_data_ready,
address_ready,
processor_write_done,
myBus,
command_writed,
request_writed,
address_bus,
TC
); ... | 7.163447 |
module timing_counter #(
parameter nCK_PER_CLK = 4,
parameter DDR_PRD = 2.5,
parameter TP = 35
) (
input clk,
input rst,
input start,
input [(`CLOG2(nCK_PER_CLK))-1:0] slot,
output [(`CLOG2(nCK_PER_CLK))-1:0] offset,
output done
);
localparam integer CTR_VAL = $ceil(... | 7.572248 |
module timing (
input clk,
input rst,
input valid,
input [3:0] strb,
input [2:0] addr,
input [31:0] data_i,
output reg ready,
output reg irq
);
reg timer_en;
reg [31:0] TIMER_CNT_MAX;
reg [31:0] timer_cnt;
always @(posedge clk)
if (rst) ready <= 1'b0;
else if (valid & ... | 6.81778 |
module timing_ctrl_shift (
output wire seventy_d35,
output wire da, // Sign test pulse for Multiplicand (via CCU 2).
output wire dx, // Digit test pulse for Multiplier.
output wire dy, // Resetting pulse after addition of partial product.
output wire g2_pos, // Multiplicand and shifting gate.
... | 7.166194 |
module timing_gen #(
parameter DELAY = 10,
parameter WIDTH = 20
) (
input wire clk,
input wire reset,
output reg tgen
);
initial begin
tgen = 1'b0;
end
always @(posedge clk) tgen = #DELAY 1'b1;
always @(posedge tgen) tgen = #WIDTH 1'b0;
endmodule
| 6.905555 |
module timing_generator_VGA (
input wire clk,
reset,
output wire hsync,
vsync,
video_on,
p_tick,
output wire [9:0] pixel_x,
pixel_y
);
//Declaracin de constantes
//Parmetros para VGA 640x480
localparam HD = 640; //rea de despliegue horizontal
localparam HF = 48; // borde izq... | 7.784965 |
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