code stringlengths 35 6.69k | score float64 6.5 11.5 |
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module tileSelect (
clk,
resetn,
enable,
pause,
location_out
);
input clk, resetn, enable, pause;
output reg [3:0] location_out;
reg [4:0] current_state, next_state;
wire rate_out;
rateDivider r0 (
clk,
resetn,
rate_out
);
localparam TILE_0 = 4'd0,
TILE_1 = 4'd1,... | 7.330474 |
module rateDivider (
clock_in,
resetn,
clock_out
);
input clock_in, resetn;
output clock_out;
reg [6:0] count;
always @(posedge clock_in) begin
if (resetn == 1'b0) count <= 0;
else if (count == 0) count <= 7'd100;
else count <= count - 1'b1;
end
assign clock_out = ~|count[7:0];
en... | 7.564049 |
module test_tilerender_top (
input wire [0 : 0] clk,
input wire [0 : 0] reset,
output wire [0 : 0] hsync,
output wire [0 : 0] vsync,
output wire [2 : 0] rgb
);
/*******************************************************
* WIRE AND REG DECLARATION *
**************... | 7.649092 |
module Crossbar__98fa4340c7cb5a19 (
input logic [0:0] clk,
input logic [0:0] reset,
input logic [0:0] recv_data__en[0:4],
input CGRAData_32_1 recv_data__msg[0:4],
output logic [0:0] recv_data__rdy[0:4],
input logic [0:0] recv_opt__en,
input CGRAConfig_5_5_6 recv_opt__msg,
output logic [0... | 8.331541 |
module CtrlMem__CtrlType_CGRAConfig_5_5_6__ctrl_mem_size_3__num_ctrl_3 (
input logic [0:0] clk,
input logic [0:0] reset,
input logic [0:0] recv_ctrl__en,
input CGRAConfig_5_5_6 recv_ctrl__msg,
output logic [0:0] recv_ctrl__rdy,
input logic [0:0] recv_waddr__en,
input logic [1:0] recv_waddr__... | 6.639327 |
module Crossbar__85a8b278d9b91463 (
input logic [0:0] clk,
input logic [0:0] reset,
input logic [0:0] recv_data__en[0:5],
input CGRAData_32_1 recv_data__msg[0:5],
output logic [0:0] recv_data__rdy[0:5],
input logic [0:0] recv_opt__en,
input CGRAConfig_5_6_6 recv_opt__msg,
output logic [0... | 8.268085 |
module CtrlMem__CtrlType_CGRAConfig_5_6_6__ctrl_mem_size_3__num_ctrl_3 (
input logic [0:0] clk,
input logic [0:0] reset,
input logic [0:0] recv_ctrl__en,
input CGRAConfig_5_6_6 recv_ctrl__msg,
output logic [0:0] recv_ctrl__rdy,
input logic [0:0] recv_waddr__en,
input logic [1:0] recv_waddr__... | 6.639327 |
module Crossbar__85a8b278d9b91463 (
input logic [0:0] clk,
input logic [0:0] reset,
input logic [0:0] recv_data__en[0:5],
input CGRAData_32_1 recv_data__msg[0:5],
output logic [0:0] recv_data__rdy[0:5],
input logic [0:0] recv_opt__en,
input CGRAConfig_5_6_6 recv_opt__msg,
output logic [0... | 8.268085 |
module CtrlMem__CtrlType_CGRAConfig_5_6_6__ctrl_mem_size_3__num_ctrl_3 (
input logic [0:0] clk,
input logic [0:0] reset,
input logic [0:0] recv_ctrl__en,
input CGRAConfig_5_6_6 recv_ctrl__msg,
output logic [0:0] recv_ctrl__rdy,
input logic [0:0] recv_waddr__en,
input logic [1:0] recv_waddr__... | 6.639327 |
module Crossbar__9de0b627a60fd452 (
input logic [0:0] clk,
input logic [0:0] reset,
input logic [0:0] recv_data__en[0:5],
input CGRAData_32_1 recv_data__msg[0:5],
output logic [0:0] recv_data__rdy[0:5],
input logic [0:0] recv_opt__en,
input CGRAConfig_5_6_8 recv_opt__msg,
output logic [0... | 8.434496 |
module CtrlMem__CtrlType_CGRAConfig_5_6_8__ctrl_mem_size_3__num_ctrl_3 (
input logic [0:0] clk,
input logic [0:0] reset,
input logic [0:0] recv_ctrl__en,
input CGRAConfig_5_6_8 recv_ctrl__msg,
output logic [0:0] recv_ctrl__rdy,
input logic [0:0] recv_waddr__en,
input logic [1:0] recv_waddr__... | 6.639327 |
module Crossbar__9de0b627a60fd452 (
input logic [0:0] clk,
input logic [0:0] reset,
input logic [0:0] recv_data__en[0:5],
input CGRAData_32_1 recv_data__msg[0:5],
output logic [0:0] recv_data__rdy[0:5],
input logic [0:0] recv_opt__en,
input CGRAConfig_5_6_8 recv_opt__msg,
output logic [0... | 8.434496 |
module CtrlMem__CtrlType_CGRAConfig_5_6_8__ctrl_mem_size_3__num_ctrl_3 (
input logic [0:0] clk,
input logic [0:0] reset,
input logic [0:0] recv_ctrl__en,
input CGRAConfig_5_6_8 recv_ctrl__msg,
output logic [0:0] recv_ctrl__rdy,
input logic [0:0] recv_waddr__en,
input logic [1:0] recv_waddr__... | 6.639327 |
module Crossbar__9de0b627a60fd452 (
input logic [0:0] clk,
input logic [0:0] reset,
input logic [0:0] recv_data__en[0:5],
input CGRAData_32_1 recv_data__msg[0:5],
output logic [0:0] recv_data__rdy[0:5],
input logic [0:0] recv_opt__en,
input CGRAConfig_5_6_8 recv_opt__msg,
output logic [0... | 8.434496 |
module CtrlMem__CtrlType_CGRAConfig_5_6_8__ctrl_mem_size_3__num_ctrl_3 (
input logic [0:0] clk,
input logic [0:0] reset,
input logic [0:0] recv_ctrl__en,
input CGRAConfig_5_6_8 recv_ctrl__msg,
output logic [0:0] recv_ctrl__rdy,
input logic [0:0] recv_waddr__en,
input logic [1:0] recv_waddr__... | 6.639327 |
module Crossbar__9de0b627a60fd452 (
input logic [0:0] clk,
input logic [0:0] reset,
input logic [0:0] recv_data__en[0:5],
input CGRAData_32_1 recv_data__msg[0:5],
output logic [0:0] recv_data__rdy[0:5],
input logic [0:0] recv_opt__en,
input CGRAConfig_5_6_8 recv_opt__msg,
output logic [0... | 8.434496 |
module CtrlMem__CtrlType_CGRAConfig_5_6_8__ctrl_mem_size_3__num_ctrl_3 (
input logic [0:0] clk,
input logic [0:0] reset,
input logic [0:0] recv_ctrl__en,
input CGRAConfig_5_6_8 recv_ctrl__msg,
output logic [0:0] recv_ctrl__rdy,
input logic [0:0] recv_waddr__en,
input logic [1:0] recv_waddr__... | 6.639327 |
module ChannelRTL__DataType_CGRAData_32_1_1__latency_1 (
input logic [0:0] clk,
output logic [1:0] count,
input logic [0:0] reset,
input logic [0:0] recv__en,
input CGRAData_32_1_1 recv__msg,
output logic [0:0] recv__rdy,
output logic [0:0] send__en,
output CGRAData_32_1_1 send__msg,
... | 6.712902 |
module CtrlMemRTL__8f238acfb01302b1 (
input logic [0:0] clk,
input logic [0:0] reset,
input logic [0:0] recv_ctrl__en,
input CGRAConfig_6_4_6_8 recv_ctrl__msg,
output logic [0:0] recv_ctrl__rdy,
input logic [0:0] recv_waddr__en,
input logic [1:0] recv_waddr__msg,
output logic [0:0] recv_... | 6.696227 |
module RegisterRTL__DataType_CGRAData_1_1__latency_1 (
input logic [0:0] clk,
input logic [0:0] reset,
input logic [0:0] recv__en,
input CGRAData_1_1 recv__msg,
output logic [0:0] recv__rdy,
output logic [0:0] send__en,
output CGRAData_1_1 send__msg,
input logic [0:0] send__rdy
);
loca... | 6.84815 |
module tile_8x1 (
clk,
scan_clk,
clb_scan_in,
clb_scan_out,
clb_scan_en,
conn_scan_in,
conn_scan_out,
conn_scan_en,
reset,
left_in,
right_in,
top_in,
bottom_in,
left_out,
right_out,
top_out,
bottom_out,
left_clb_out,
left_clb_in,
bottom_clb... | 6.756362 |
module tile_4x1 (
clk,
scan_clk,
clb_scan_in,
clb_scan_out,
clb_scan_en,
conn_scan_in,
conn_scan_out,
conn_scan_en,
reset,
left_in,
right_in,
top_in,
bottom_in,
left_out,
right_out,
top_out,
bottom_out,
left_clb_out,
left_clb_in,
bottom_clb... | 6.814472 |
module tile_2x1 (
clk,
scan_clk,
clb_scan_in,
clb_scan_out,
clb_scan_en,
conn_scan_in,
conn_scan_out,
conn_scan_en,
reset,
left_in,
right_in,
top_in,
bottom_in,
left_out,
right_out,
top_out,
bottom_out,
left_clb_out,
left_clb_in,
bottom_clb... | 6.680381 |
module tile_8x8 (
clk,
scan_clk,
clb_scan_in,
clb_scan_out,
clb_scan_en,
conn_scan_in,
conn_scan_out,
conn_scan_en,
reset,
left_in,
right_in,
top_in,
bottom_in,
left_out,
right_out,
top_out,
bottom_out,
left_clb_out,
left_clb_in,
bottom_clb... | 7.04754 |
module tile_8x4 (
clk,
scan_clk,
clb_scan_in,
clb_scan_out,
clb_scan_en,
conn_scan_in,
conn_scan_out,
conn_scan_en,
reset,
left_in,
right_in,
top_in,
bottom_in,
left_out,
right_out,
top_out,
bottom_out,
left_clb_out,
left_clb_in,
bottom_clb... | 7.061012 |
module tile_8x2 (
clk,
scan_clk,
clb_scan_in,
clb_scan_out,
clb_scan_en,
conn_scan_in,
conn_scan_out,
conn_scan_en,
reset,
left_in,
right_in,
top_in,
bottom_in,
left_out,
right_out,
top_out,
bottom_out,
left_clb_out,
left_clb_in,
bottom_clb... | 7.119048 |
module tile_cache (
input reset,
input clk,
input cache_req,
input [19:0] cache_addr,
output reg cache_valid,
output [31:0] cache_data,
input [31:0] rom_data,
input rom_valid,
output reg rom_req,
output reg [19:0] rom_addr
);
reg [19:9] tag [511:0];
reg [511:0] val... | 7.420221 |
module flipflop (
input wire [0:0] clk
, input wire [0:0] D
, output reg [0:0] Q
, input wire [0:0] prog_done // programming finished
, input wire [0:0] prog_data // mode: enabled (not disabled)
);
always @(posedge clk) begin
if (~prog_done || ~prog_data) begin
Q <= 1'b0;
en... | 6.626138 |
module scanchain_data_d17 (
input wire [0:0] prog_clk
, input wire [0:0] prog_rst
, input wire [0:0] prog_done
, input wire [0:0] prog_we
, input wire [1 - 1:0] prog_din
, output reg [17 - 1:0] prog_data
, output wire [ 1 - 1:0] prog_dout
);
localparam CHAIN_BITCOUNT = 17;
localpar... | 7.770095 |
module prga_simple_buf (
input wire [0:0] C,
input wire [0:0] D,
output reg [0:0] Q
);
always @(posedge C) begin
Q <= D;
end
endmodule
| 7.13912 |
module prga_simple_bufr (
input wire [0:0] C,
input wire [0:0] R,
input wire [0:0] D,
output reg [0:0] Q
);
always @(posedge C) begin
if (R) begin
Q <= 1'b0;
end else begin
Q <= D;
end
end
endmodule
| 7.13912 |
module scanchain_delim (
input wire [0:0] prog_clk
, input wire [0:0] prog_rst
, input wire [0:0] prog_done
, input wire [0:0] prog_we
, input wire [1 - 1:0] prog_din
, output reg [0:0] prog_we_o
, output reg [1 - 1:0] prog_dout
);
always @(posedge prog_clk) begin
if (prog_rst) be... | 7.198827 |
module scanchain_data_d2 (
input wire [0:0] prog_clk
, input wire [0:0] prog_rst
, input wire [0:0] prog_done
, input wire [0:0] prog_we
, input wire [1 - 1:0] prog_din
, output reg [2 - 1:0] prog_data
, output wire [1 - 1:0] prog_dout
);
localparam CHAIN_BITCOUNT = 2;
localparam C... | 7.770095 |
module scanchain_data_d3 (
input wire [0:0] prog_clk
, input wire [0:0] prog_rst
, input wire [0:0] prog_done
, input wire [0:0] prog_we
, input wire [1 - 1:0] prog_din
, output reg [3 - 1:0] prog_data
, output wire [1 - 1:0] prog_dout
);
localparam CHAIN_BITCOUNT = 3;
localparam C... | 7.770095 |
module flipflop (
input wire [0:0] clk
, input wire [0:0] D
, output reg [0:0] Q
, input wire [0:0] prog_done // programming finished
, input wire [0:0] prog_data // mode: enabled (not disabled)
);
always @(posedge clk) begin
if (~prog_done || ~prog_data) begin
Q <= 1'b0;
en... | 6.626138 |
module scanchain_data_d17 (
input wire [0:0] prog_clk
, input wire [0:0] prog_rst
, input wire [0:0] prog_done
, input wire [0:0] prog_we
, input wire [1 - 1:0] prog_din
, output reg [17 - 1:0] prog_data
, output wire [ 1 - 1:0] prog_dout
);
localparam CHAIN_BITCOUNT = 17;
localpar... | 7.770095 |
module scanchain_data_d1 (
input wire [0:0] prog_clk
, input wire [0:0] prog_rst
, input wire [0:0] prog_done
, input wire [0:0] prog_we
, input wire [1 - 1:0] prog_din
, output reg [1 - 1:0] prog_data
, output wire [1 - 1:0] prog_dout
);
localparam CHAIN_BITCOUNT = 1;
localparam C... | 7.770095 |
module tile_memory (
input clk,
wen,
ren,
input [11:0] waddr,
raddr,
input [5:0] wdata,
output reg [5:0] rdata
);
reg [5:0] mem[0:4095]; // enough memory for 80x50 map of tiles // uses ~6 BRAMS of Ice40
always @(posedge clk) begin
if (ren) rdata <= mem[raddr];
if (wen) mem[waddr... | 6.881561 |
module tile_ram (
addra,
addrb,
clka,
clkb,
dina,
doutb,
wea
);
input [10 : 0] addra;
input [10 : 0] addrb;
input clka;
input clkb;
input [7 : 0] dina;
output [7 : 0] doutb;
input wea;
// synopsys translate_off
BLKMEMDP_V6_3 #(11, // c_addra_width
11, // c_addrb_wid... | 7.132429 |
module tile_rom (
clk,
addr,
rdata
);
parameter ADDR_WIDTH = 14;
parameter DATA_WIDTH = 8;
parameter ROM_DATA_FILE = "tiles.mem";
input clk;
input [ADDR_WIDTH-1:0] addr;
output reg [DATA_WIDTH-1:0] rdata;
reg [DATA_WIDTH-1:0] MY_ROM[0:2**ADDR_WIDTH-1];
initial $readmemb(ROM_DATA_FILE, MY_RO... | 7.868442 |
module tilting_registers (
clk,
rst,
D0_in,
D1_in,
D2_in,
D3_in,
D4_in,
D5_in,
D6_in,
D7_in,
D0_out,
D1_out,
D2_out,
D3_out,
D4_out,
D5_out,
D6_out,
D7_out
);
parameter wl = 8;
input clk, rst;
input [wl-1:0] D0_in, D1_in, D2_in, D3_in, D4_i... | 6.663622 |
module timers_frc #(
parameter TIMER_WIDTH = 8,
parameter TIMER_PULSE_EXTD = 0
) (
input wire timer_clk,
input wire timer_resetn,
input wire timer_en,
input wire timer_mode,
input wire timerhw... | 7.766675 |
module test;
/* Make a reset that pulses once. */
reg clk = 0;
reg [7:0] trg_wrd;
reg fifo_empty;
wire re;
wire [6:0] out;
initial begin
$dumpfile("test.vcd");
$dumpvars(0, test);
fifo_empty = 1'b0;
trg_wrd = 8'b00000000;
#1 rst = 1'b1;
#1 rst = 1'b0;
#1 trg_wrd = 8'b100000... | 7.230422 |
module TimeAverager (
iCLK,
iVGA_BLANK,
iVGA_X,
iVGA_Y,
iRed,
iGreen,
iBlue,
oRed,
oGreen,
oBlue,
oSRAM_WE_N,
oSRAM_ADDR,
SRAM_DQ
);
input iCLK;
input iVGA_BLANK;
input [9:0] iVGA_X, iVGA_Y; //Address requested by VGA Ctrl
input [4:0] iRed, iGreen, iBlue;
... | 7.672321 |
module Time_Cnt (
CLK,
RST,
TIME_SEC
);
input CLK;
input RST;
output reg [15:0] TIME_SEC = 0;
integer time_f = 0;
always @(negedge CLK) begin
if (RST) begin
time_f <= 0;
TIME_SEC <= 0;
end else begin
if (time_f < 999999) begin
time_f <= time_f + 1;
end el... | 6.832748 |
module timecount2 (
input wire clock, // prescaler
input wire Prescale_EN, // DW 2005.06.21 Prescale Enable
input wire reset, // resetgen
input wire increment, // fsm
input wire setctzero, // fsm
input wire setctotwo, // fsm
o... | 7.530242 |
module timeCounter (
input CLK,
input RST,
output reg [15:0] Time
);
integer counter = 0;
always @(posedge CLK) begin
if (!RST) begin
Time <= 0;
counter <= 0;
end else if ((counter + 1) == 100000000) begin
counter <= 0;
Time <= Time + 1;
end else counter <= counter + ... | 6.991736 |
module timeDivider (
input clk,
input pause,
output reg clockOut
);
reg [23:0] buffer;
initial begin
buffer = 0;
clockOut = 0;
end
always @(posedge clk) begin
if (!pause) buffer <= buffer + 1;
clockOut <= &buffer;
end
endmodule
| 6.601571 |
module timed_monoflop (
input wire clock,
input wire enable,
input wire [PulseLengthWidth-1:0] pulselength,
input wire trigger,
output wire q
);
parameter PulseLengthWidth = 4;
reg load = 1'b0;
reg [PulseLengthWidth-1:0] Countdown = 0;
assign q = |Countdown;
always @(posedge trigger or ... | 7.321023 |
module timed_tester #(
parameter WIDTH = 1
) (
input wire clk,
input wire [WIDTH-1:0] expected_value,
input wire [WIDTH-1:0] mask,
input wire tgen,
input wire [WIDTH-1:0] signal,
output reg [WIDTH-1:0] filtered_value,
output reg [ WIDTH:1] fail
);
always ... | 7.732413 |
module timegen (
clock,
reset,
reset_count,
fastwatch,
one_second,
one_minute
);
input clock, reset, reset_count, //Resets the timegen when you set a new time
fastwatch;
output one_second, one_minute;
reg [13:0] count;
reg one_second;
reg one_minute_reg;
reg one_minute;
... | 6.549803 |
module timekeeper #(
parameter SR_TIME_HI = 0,
parameter SR_TIME_LO = 1,
parameter SR_TIME_CTRL = 2
) (
input clk,
input reset,
input pps,
input sync_in,
input strobe,
input set_stb,
input [7:0] set_addr,
input [31:0] set_data,
output reg [63:0] vita_time,
output ... | 6.937626 |
module timekeeper_legacy #(
parameter SR_TIME_HI = 0,
parameter SR_TIME_LO = 1,
parameter SR_TIME_CTRL = 2,
parameter INCREMENT = 64'h1
) (
input clk,
input reset,
input pps,
input sync_in,
input strobe,
input set_stb,
input [7:0] set_addr,
input [31:0] set_data,
outp... | 7.097456 |
module timem (
input clk,
input [`HASTI_ADDR_WIDTH-1:0] addr,
input read,
input write,
input [`HASTI_SIZE_WIDTH-1:0] size,
input [ `HASTI_BUS_WIDTH-1:0] wdata,
output [ `HASTI_BUS_WIDTH-1:0] rdata
);
reg [3:0] w... | 7.807872 |
module v_rams_20c (
clk,
we,
addr,
din,
dout
);
input clk;
input we;
input [11:0] addr;
input [7:0] din;
output [7:0] dout;
reg [7:0] ram [0:4095];
reg [7:0] dout;
initial begin
$readmemh("ram.data0", ram);
end
always @(posedge clk) begin
if (we) ram[addr] <= din;
do... | 6.604807 |
module v_rams_21c (
clk,
we,
addr,
din,
dout
);
input clk;
input we;
input [11:0] addr;
input [7:0] din;
output [7:0] dout;
reg [7:0] ram [0:4095];
reg [7:0] dout;
initial begin
$readmemh("ram.data1", ram);
end
always @(posedge clk) begin
if (we) ram[addr] <= din;
do... | 6.648021 |
module v_rams_22c (
clk,
we,
addr,
din,
dout
);
input clk;
input we;
input [11:0] addr;
input [7:0] din;
output [7:0] dout;
reg [7:0] ram [0:4095];
reg [7:0] dout;
initial begin
$readmemh("ram.data2", ram);
end
always @(posedge clk) begin
if (we) ram[addr] <= din;
do... | 6.518002 |
module v_rams_23c (
clk,
we,
addr,
din,
dout
);
input clk;
input we;
input [11:0] addr;
input [7:0] din;
output [7:0] dout;
reg [7:0] ram [0:4095];
reg [7:0] dout;
initial begin
$readmemh("ram.data3", ram);
end
always @(posedge clk) begin
if (we) ram[addr] <= din;
do... | 6.829322 |
module TimeMod (
input signed [17:0] l_audio_in,
input signed [17:0] r_audio_in,
input ready,
input clock,
input reset,
input [9:0] controls,
output signed [17:0] l_audio_out,
output signed [17:0] r_audio_out
);
//Echo variables
wire e_d;
wire e_u;
reg old_e_d = 0;
reg old_e_u ... | 6.907819 |
module timeofDayReceiver (
input Clock,
input Reset,
input [ 7:0] EventStream,
output reg [ 9:0] tooManyCount = 0,
output reg [ 9:0] tooFewCount = 0,
output reg [ 9:0] outOfSeqCount = 0,
output wire [63:0] TimeStamp
);
localparam SECONDS_WIDTH = 32;
lo... | 6.724339 |
module timeout (
input wire clk,
input wire [7:0] Enable,
input wire Enable_Init_or_Resp,
input wire reset,
input wire auth_msg_ready,
input wire [31:0] current_timeout,
output wire Error_Busy
);
reg [31:0] Timeout_counter = 0;
reg Error_Busy_temp = 0;
always @(posedge clk) begin
... | 6.788577 |
module connection_outTime_inspector (
reset,
clk,
idx_agingTb,
data_agingTb,
rdValid_agingTb,
wrValid_agingTb,
ctx_agingTb,
agingInfo_valid,
agingInfo,
cur_timestamp
);
/* width or depth or words info of signals
*/
parameter w_agingInfo = 16, // width of aging info to build... | 6.890324 |
module TimePulGenerator (
CLK,
RST,
SW,
CP,
Sublevel
);
input CLK, RST;
input [4:0] SW;
output CP;
output reg [3:0] Sublevel;
reg [15:0] Count;
reg [15:0] CountMAX;
reg div_CLK;
//根据表格来确定计数器和Sublevel
always @(posedge CLK) begin
case (SW)
5'b00000: begin
CountMAX =... | 7.221055 |
module timepulse #(
parameter CLK_PER_NS = 40,
parameter PULSE_PER_NS = 5120
) (
/* clock and reset */
input clk_i,
input rst_i,
/* output */
output tp_o
);
`define MAX_COUNT (PULSE_PER_NS/CLK_PER_NS)
`define MAX_COUNT_SIZE ($clog2(`MAX_COUNT))
/* Display parameters in simulation... | 7.830303 |
module Timer_tb;
parameter HALF_PERIOD = 0.5;
reg load, clr, clk, en;
reg [3:0] data;
wire [3:0] sec_ones, sec_tens, mins;
wire zero;
always #HALF_PERIOD clk = ~clk;
Timer timer (
load,
clr,
clk,
en,
data,
sec_ones,
sec_tens,
mins,
zero
);
init... | 6.642052 |
module Timer (
input wire reset,
input wire count,
input wire clk,
input wire signed [8:0] adder,
output wire [3:0] seconds0,
output wire [3:0] seconds1,
output wire [3:0] minutes0
);
reg [8:0] seconds;
assign minutes0 = seconds / 60;
assign seconds1 = (seconds % 60) / 10;
assign s... | 6.729771 |
module TIMER32 (
input wire clk,
input wire rst,
output reg [31:0] TMR,
input wire [31:0] PRE,
input wire [31:0] TMRCMP,
output reg TMROV,
input wire TMROVCLR,
input wire TMREN
);
reg [31:0] clkdiv;
wire timer_clk = (clkdiv == PRE);
wire tmrov = (TMR == TMRCMP);
// Prescalar
... | 8.011137 |
module timer_8253 (
input CS,
input WR,
input [1:0] addr,
input [7:0] din,
output wire [7:0] dout,
input CLK_25,
input clk, // cpu CLK
output out0,
output out2
);
reg [8:0] rclk = 0; // rclk[8] oscillates at 1193181.8181... Hz
reg [1:0] cclk = 0;
always @(posedge CLK_25) be... | 6.56733 |
module TimerEcclesiaMorain (
input CLOCK_50,
input FPGA_RESET_N,
input [9:0] SW,
input [3:0] KEY,
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX4,
output [6:0] HEX5,
output [9:0] LEDR
);
// =====================================... | 7.331134 |
module TimerInput_tb;
reg [9:0] kbd;
reg enn, clk;
wire [3:0] D;
wire loadn, pgt_1Hz;
always #5 clk = ~clk;
TimerInput DUT (
kbd,
enn,
clk,
D,
loadn,
pgt_1Hz
);
initial begin
clk = 0;
$dumpfile("TimerInput.vcd");
$dumpvars(0, TimerInput_tb);
enn = ... | 7.167681 |
module TimerInput (
input wire [9:0] kbd,
input wire enn,
clk,
output wire [3:0] D,
output wire loadn,
pgt_1Hz
);
wire clk1hz, delcount;
KeyboardCoder coder (
kbd,
enn,
D,
loadn
);
FrequencyDelayer_1hz freqdel (
clk,
clk1hz
);
Counter0_7 counter (... | 7.448537 |
module timer1 (
enable,
clk,
reset,
setbit,
curr_state
);
input enable, clk, reset;
input [1:0] curr_state;
wire d0, d1;
reg [1:0] q;
output reg [3:0] setbit;
assign d0 = ~q[0];
assign d1 = q[0] ^ q[1];
always @(posedge clk or negedge reset) begin
if (~reset) begin
q = ... | 6.616152 |
module timer4 (
enable,
clk,
reset,
setbit
);
input enable, clk, reset;
wire d0, d1;
reg [1:0] q;
output reg [3:0] setbit;
assign d0 = ~q[0];
assign d1 = q[0] ^ q[1];
always @(posedge clk or negedge reset) begin
if (~reset) begin
q = 2'b00;
end else begin
if (enable... | 6.547903 |
module timer_1_32_l (
input clk,
resetn,
enable,
output time_up
);
reg [25:0] count;
wire [ 9:0] dividend;
assign dividend = 10'd32;
wire [25:0] initial_value, check_value;
assign initial_value = 26'd50000000;
assign check_value = initial_value / dividend;
always @(posedge clk) begin
... | 6.71649 |
module timer_s (
input clk,
resetn,
enable,
input [25:0] dividend,
output time_up
);
reg [25:0] count;
wire [25:0] check_value;
assign check_value = 26'd50000000 / dividend;
always @(posedge clk) begin
if (!resetn) count <= check_value;
else if (enable) begin
if (count == 26'... | 6.799927 |
module timers_tb;
reg enable, clk, reset;
wire [3:0] setbit1, setbit2, setbit3, setbit4;
timer1 t1 (
enable,
clk,
reset,
setbit1
);
timer2 t2 (
enable,
clk,
reset,
setbit2
);
timer3 t3 (
enable,
clk,
reset,
setbit3
);
timer4 t4 ... | 6.860182 |
module timers_top ( /*AUTOARG*/
// Outputs
ANODE,
CATHODE,
// Inputs
CLK_IN,
RESET_IN
);
input CLK_IN;
input RESET_IN;
output [3:0] ANODE;
output [7:0] CATHODE;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire CLK_OUT; // From... | 6.610104 |
module timer_1sec (
output tick,
input reset,
clk,
en
);
localparam CLOCK_FREQ = 50000000 / 4;
reg [26:0] timer_reg;
wire [26:0] timer_next;
//registors
always @(posedge clk, posedge reset)
if (reset) timer_reg <= 0;
else timer_reg <= timer_next;
//next state logic
assign time... | 6.552668 |
module timer_1sec_fsm (
output reg timer_up_tick,
input reset,
clk,
start
);
localparam [1:0] paused = 2'b00, running = 2'b01, time_up = 2'b10;
reg en, r_set;
wire tick;
timer_1sec timer_unit (
.tick(tick),
.clk(clk),
.reset(r_set),
.en(en)
);
reg [1:0] state_reg,... | 7.906064 |
module Timer_adder_testbench;
/* Inicialização das variáveis de input */
reg count_tb, reset_tb, clk_tb;
reg signed [8:0] adder_tb;
/* Inicialização da variáveis de output */
wire [3:0] seconds0_tb, seconds1_tb, minutes0_tb;
/* Inicialização do módulo a ser testado */
Timer UUT (
.reset(reset_t... | 7.185424 |
module timer_apb #(
parameter NUM_TIMER = 2
, FREQUENCY = 1_000_000 // frequency of clk_timer
) (
input wire PRESETn
, input wire PCLK
, input wire PSEL
, input wire PENABLE
, input wire [ 31:0] PADDR
, input... | 6.974668 |
module timer_cntrl (
input wire clk_i,
input wire rstn_i,
input wire cfg_start_i,
input wire cfg_stop_i,
input wire cfg_rst_i,
input wire cfg_update_i,
input wire cfg_arm_i,
output reg ctrl_cnt_upd_o,
output reg ctrl_all_upd_o,
output wire ctrl_active_o,
output reg ctrl_... | 6.747358 |
module timer_control_level2 (
keypad,
enable_n,
clock_100Hz,
D,
load_n,
pgt_1Hz
);
input [9:0] keypad;
input enable_n, clock_100Hz;
output wire [3:0] D;
output wire load_n, pgt_1Hz;
wire clock_1Hz, data_valid, delayed_data_valid;
priority_encoder encoder (
.keypad(keypad),
... | 6.879247 |
module timer_control_level2_tb;
reg [9:0] keypad_tb;
reg enable_n_tb, clock_100Hz_tb;
wire [3:0] D_tb;
wire load_n_tb, pgt_1Hz_tb;
timer_control_level2 uut (
keypad_tb,
enable_n_tb,
clock_100Hz_tb,
D_tb,
load_n_tb,
pgt_1Hz_tb
);
initial begin
$dumpfile("./wave_f... | 6.879247 |
module timer_display (
input [10:0] hcount, // Screen placement
input [10:0] vcount,
input [ 9:0] time_remaining, // Time left
input blank,
input clk,
input rst,
output r_timer, // Colors to display time
output g_timer,
outpu... | 7.310348 |
module TM (
TMCLK,
DSPCLK,
T_RST,
TMODE,
DMD,
selTSR,
selTCR,
selTPR,
TSR_we,
TCR_we,
TPR_we,
MSTAT5,
TMOUT,
MMR_web,
ICE_ST,
`ifdef FD_DFT
/* dft */ SCAN_TEST,
`endif
TINT
);
input [15:0] DMD;
input TMCLK;
input DSPCLK;
input T_RST;
input... | 7.473647 |
module TIMER_fjl (
input SYSCLK,
input RST_B,
input [2:0] TIME_MIN,
input [5:0] TIME_SEC,
input START,
output reg [2:0] MINUTE,
output reg [5:0] SECOND,
output reg TIME_UP
);
reg flag;
always @(posedge TIME_UP, posedge START) begin
if (TIME_UP) flag <= 0;
else flag = 1;
en... | 7.211665 |
module TIMER_fjl_tb;
//reg count_flag;
reg clk = 0;
reg rst = 0;
reg [2:0] minute_in = 3'd0;
reg [5:0] second_in = 6'd0;
reg start = 0;
wire [2:0] minute_out;
wire [5:0] second_out;
wire time_up;
always begin
#5 clk = ~clk;
end
initial begin
rst = 0;
start = 0;
//count_flag = ... | 6.760316 |
module Timer_hull (
Clk,
rst_n,
Enable,
Start,
Clr,
Dir,
Dout1
);
parameter Bit = 32;
input Clk, rst_n, Enable, Clr, Dir, Start;
output [Bit-1:0] Dout1;
reg [Bit-1:0] Dout, Dout1;
always @(posedge Clk or negedge Clr or negedge rst_n) begin
if (rst_n == 1'b0) begin
Dou... | 7.034946 |
module timer_input #(
parameter BITS = 4
) (
input clk,
input reset_n,
input enable,
input [BITS - 1:0] FINAL_VALUE,
// output [BITS - 1:0] Q,
output done
);
reg [BITS - 1:0] Q_reg, Q_next;
always @(posedge clk, negedge reset_n) begin
if (~reset_n) Q_reg <= 'b0;
else if (ena... | 6.618852 |
module timer_input_and_control_module (
output wire [3:0] D,
output wire loadn,
output wire pgt_1Hz,
input [9:0] numpad,
input enablen,
input clock_100Hz
);
wire dataValid;
numpad_encoder encoder (
.BCDout(D),
.validData(dataValid),
.enablen(enablen),
.numpad(numpad... | 8.252794 |
module.v"
module test;
wire [3:0] D;
wire loadn;
wire pgt_1Hz;
reg [9:0] numpad;
reg enablen;
reg clock_100Hz;
timer_input_and_control_module modulo(
.D(D),
.loadn(loadn),
.pgt_1Hz(pgt_1Hz),
.numpad(numpad),
.enablen(enablen),
.clock_100Hz(... | 6.67459 |
module timer_input_tb ();
localparam BITS = 16;
reg clk, reset_n, enable;
reg [BITS - 1:0] FINAL_VALUE;
wire done;
// Instantiate module under test
timer_input #(
.BITS(BITS)
) uut (
.clk(clk),
.reset_n(reset_n),
.enable(enable),
.FINAL_VALUE(FINAL_VALUE),
.done(done)... | 8.015644 |
module `VARIANT`TIMER_MICRO_REG
#(parameter BASE_ADDR = 4'h0,
parameter BASE_WIDTH = 4,
parameter ADDR_WIDTH = 8
)(
input wire clk,
input wire reset,
input wire cs,
input wire wr,
input ... | 7.116795 |
module timer_N_bits #(
parameter N = 4
) (
input clk,
load,
enable,
input [N-1:0] data,
output out
);
reg [N-1:0] count;
always @(posedge clk)
if (load) count <= data;
else if (enable) count <= count - 1;
else count <= count;
assign out = (count == 0);
endmodule
| 6.77748 |
module timer_parameter #(
parameter FINAL_VALUE = 255
) (
input clk,
input reset_n,
input enable,
// output [BITS - 1:0] Q, // we don't care about the value of the counter
output done
);
localparam BITS = $clog2(FINAL_VALUE);
reg [BITS - 1:0] Q_reg, Q_next;
always @(posedge clk, n... | 7.66581 |
module timer_parameter_tb ();
localparam FINAL_VALUE = 49_999;
localparam BITS = $clog2(FINAL_VALUE);
reg clk, reset_n, enable;
wire done;
// Instantiate module under test
timer_parameter #(
.FINAL_VALUE(FINAL_VALUE)
) uut (
.clk(clk),
.reset_n(reset_n),
.enable(enable),
.d... | 7.66581 |
module generates a one clock pulse
* at a frequency specified by the input rate_ms.
* Valid range is 1 .. 255 ms.
*
* Status: In development
*
* Author : Brandon Blodget
* Create Date: 10/13/2019
*
*****************************
*/
/*
*****************************
*
* Copyright (C) 2019 by Brandon Blodget <brandon.blod... | 7.192867 |
module timer_send (
input clk,
input rst_n,
input en,
input tx_busy,
output reg [7:0] tx_dout,
output reg tx_dout_vld
);
//
parameter BYTE_NUM = 19; //һη19ֽ
reg [(BYTE_NUM*8)-1:0] send_data; //Ĵ淢Ϣ
reg en_flag; //ģ... | 7.023341 |
module timer_setting (
input clk,
input [1:0] switch_state,
input button_left,
input button_right,
input button_increase,
input button_decrease,
input switch_confirm,
output reg [23:0] set_timer_display, //this is the pattern that is going to be displayed
//remember you also want to... | 7.761972 |
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