code stringlengths 35 6.69k | score float64 6.5 11.5 |
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module td_fused_top_tdf6_filters_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 12;
parameter MEM_SIZE = 4096;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
wire [AWIDTH-1:0] addr0_t0;
reg [AWIDTH-1:0] addr0_t1;
reg [DWIDTH-1:0] q0_t0;
reg [DWIDTH-1:0] q0_t1;
wire [AWIDTH-1:0] addr1_t0;
reg [AWIDTH-1:0] addr1_t1;
wire [DWIDTH-1:0] d1_t0;
wire we1_t0;
reg [DWIDTH-1:0] d1_t1;
reg we1_t1;
assign addr0_t0 = addr0;
assign q0 = q0_t1;
assign addr1_t0 = addr1;
assign d1_t0 = d1;
assign we1_t0 = we1;
always @(posedge clk) begin
if (ce0) begin
addr0_t1 <= addr0_t0;
q0_t1 <= q0_t0;
end
if (ce1) begin
addr1_t1 <= addr1_t0;
d1_t1 <= d1_t0;
we1_t1 <= we1_t0;
end
end
always @(posedge clk) begin
if (ce0) begin
q0_t0 <= ram[addr0_t1];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1_t1) ram[addr1_t1] <= d1_t1;
end
end
endmodule
| 6.827284 |
module td_fused_top_tdf6_filters (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd4096;
parameter AddressWidth = 32'd12;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
td_fused_top_tdf6_filters_ram td_fused_top_tdf6_filters_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.we1(we1),
.d1(d1)
);
endmodule
| 6.827284 |
module td_fused_top_tdf7_adjustments_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 48;
parameter AWIDTH = 8;
parameter MEM_SIZE = 256;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
wire [AWIDTH-1:0] addr0_t0;
reg [AWIDTH-1:0] addr0_t1;
reg [DWIDTH-1:0] q0_t0;
reg [DWIDTH-1:0] q0_t1;
wire [AWIDTH-1:0] addr1_t0;
reg [AWIDTH-1:0] addr1_t1;
wire [DWIDTH-1:0] d1_t0;
wire we1_t0;
reg [DWIDTH-1:0] d1_t1;
reg we1_t1;
assign addr0_t0 = addr0;
assign q0 = q0_t1;
assign addr1_t0 = addr1;
assign d1_t0 = d1;
assign we1_t0 = we1;
always @(posedge clk) begin
if (ce0) begin
addr0_t1 <= addr0_t0;
q0_t1 <= q0_t0;
end
if (ce1) begin
addr1_t1 <= addr1_t0;
d1_t1 <= d1_t0;
we1_t1 <= we1_t0;
end
end
always @(posedge clk) begin
if (ce0) begin
q0_t0 <= ram[addr0_t1];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1_t1) ram[addr1_t1] <= d1_t1;
end
end
endmodule
| 6.827284 |
module td_fused_top_tdf7_adjustments (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd48;
parameter AddressRange = 32'd256;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
td_fused_top_tdf7_adjustments_ram td_fused_top_tdf7_adjustments_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.we1(we1),
.d1(d1)
);
endmodule
| 6.827284 |
module td_fused_top_tdf7_filters_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 17;
parameter MEM_SIZE = 73728;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
wire [AWIDTH-1:0] addr0_t0;
reg [AWIDTH-1:0] addr0_t1;
reg [DWIDTH-1:0] q0_t0;
reg [DWIDTH-1:0] q0_t1;
wire [AWIDTH-1:0] addr1_t0;
reg [AWIDTH-1:0] addr1_t1;
wire [DWIDTH-1:0] d1_t0;
wire we1_t0;
reg [DWIDTH-1:0] d1_t1;
reg we1_t1;
assign addr0_t0 = addr0;
assign q0 = q0_t1;
assign addr1_t0 = addr1;
assign d1_t0 = d1;
assign we1_t0 = we1;
always @(posedge clk) begin
if (ce0) begin
addr0_t1 <= addr0_t0;
q0_t1 <= q0_t0;
end
if (ce1) begin
addr1_t1 <= addr1_t0;
d1_t1 <= d1_t0;
we1_t1 <= we1_t0;
end
end
always @(posedge clk) begin
if (ce0) begin
q0_t0 <= ram[addr0_t1];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1_t1) ram[addr1_t1] <= d1_t1;
end
end
endmodule
| 6.827284 |
module td_fused_top_tdf7_filters (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd73728;
parameter AddressWidth = 32'd17;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
td_fused_top_tdf7_filters_ram td_fused_top_tdf7_filters_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.we1(we1),
.d1(d1)
);
endmodule
| 6.827284 |
module td_fused_top_tdf7_l2_filters_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 13;
parameter MEM_SIZE = 8192;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
wire [AWIDTH-1:0] addr0_t0;
reg [AWIDTH-1:0] addr0_t1;
reg [DWIDTH-1:0] q0_t0;
reg [DWIDTH-1:0] q0_t1;
wire [AWIDTH-1:0] addr1_t0;
reg [AWIDTH-1:0] addr1_t1;
wire [DWIDTH-1:0] d1_t0;
wire we1_t0;
reg [DWIDTH-1:0] d1_t1;
reg we1_t1;
assign addr0_t0 = addr0;
assign q0 = q0_t1;
assign addr1_t0 = addr1;
assign d1_t0 = d1;
assign we1_t0 = we1;
always @(posedge clk) begin
if (ce0) begin
addr0_t1 <= addr0_t0;
q0_t1 <= q0_t0;
end
if (ce1) begin
addr1_t1 <= addr1_t0;
d1_t1 <= d1_t0;
we1_t1 <= we1_t0;
end
end
always @(posedge clk) begin
if (ce0) begin
q0_t0 <= ram[addr0_t1];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1_t1) ram[addr1_t1] <= d1_t1;
end
end
endmodule
| 6.827284 |
module td_fused_top_tdf7_l2_filters (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd8192;
parameter AddressWidth = 32'd13;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
td_fused_top_tdf7_l2_filters_ram td_fused_top_tdf7_l2_filters_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.we1(we1),
.d1(d1)
);
endmodule
| 6.827284 |
module td_fused_top_tdf7_l2_writeOutputs_149_running_sums_ram (
addr0,
ce0,
d0,
we0,
addr1,
ce1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
input [AWIDTH-1:0] addr1;
input ce1;
output reg [DWIDTH-1:0] q1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
//initial begin
// $readmemh("./td_fused_top_tdf7_l2_writeOutputs_149_running_sums_ram.dat", ram);
//end
always @(posedge clk) begin
if (ce0) begin
if (we0) ram[addr0] <= d0;
end
end
always @(posedge clk) begin
if (ce1) begin
q1 <= ram[addr1];
end
end
endmodule
| 6.827284 |
module td_fused_top_tdf7_l2_writeOutputs_149_running_sums (
reset,
clk,
address0,
ce0,
we0,
d0,
address1,
ce1,
q1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
input [AddressWidth - 1:0] address1;
input ce1;
output [DataWidth - 1:0] q1;
td_fused_top_tdf7_l2_writeOutputs_149_running_sums_ram td_fused_top_tdf7_l2_writeOutputs_149_running_sums_ram_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.we0(we0),
.d0(d0),
.addr1(address1),
.ce1(ce1),
.q1(q1)
);
endmodule
| 6.827284 |
module td_fused_top_tdf9_adjustments_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 48;
parameter AWIDTH = 6;
parameter MEM_SIZE = 64;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
wire [AWIDTH-1:0] addr0_t0;
reg [AWIDTH-1:0] addr0_t1;
reg [DWIDTH-1:0] q0_t0;
reg [DWIDTH-1:0] q0_t1;
wire [AWIDTH-1:0] addr1_t0;
reg [AWIDTH-1:0] addr1_t1;
wire [DWIDTH-1:0] d1_t0;
wire we1_t0;
reg [DWIDTH-1:0] d1_t1;
reg we1_t1;
assign addr0_t0 = addr0;
assign q0 = q0_t1;
assign addr1_t0 = addr1;
assign d1_t0 = d1;
assign we1_t0 = we1;
always @(posedge clk) begin
if (ce0) begin
addr0_t1 <= addr0_t0;
q0_t1 <= q0_t0;
end
if (ce1) begin
addr1_t1 <= addr1_t0;
d1_t1 <= d1_t0;
we1_t1 <= we1_t0;
end
end
always @(posedge clk) begin
if (ce0) begin
q0_t0 <= ram[addr0_t1];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1_t1) ram[addr1_t1] <= d1_t1;
end
end
endmodule
| 6.827284 |
module td_fused_top_tdf9_adjustments (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd48;
parameter AddressRange = 32'd64;
parameter AddressWidth = 32'd6;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
td_fused_top_tdf9_adjustments_ram td_fused_top_tdf9_adjustments_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.we1(we1),
.d1(d1)
);
endmodule
| 6.827284 |
module td_fused_top_tdf9_filters_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 14;
parameter MEM_SIZE = 16384;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
wire [AWIDTH-1:0] addr0_t0;
reg [AWIDTH-1:0] addr0_t1;
reg [DWIDTH-1:0] q0_t0;
reg [DWIDTH-1:0] q0_t1;
wire [AWIDTH-1:0] addr1_t0;
reg [AWIDTH-1:0] addr1_t1;
wire [DWIDTH-1:0] d1_t0;
wire we1_t0;
reg [DWIDTH-1:0] d1_t1;
reg we1_t1;
assign addr0_t0 = addr0;
assign q0 = q0_t1;
assign addr1_t0 = addr1;
assign d1_t0 = d1;
assign we1_t0 = we1;
always @(posedge clk) begin
if (ce0) begin
addr0_t1 <= addr0_t0;
q0_t1 <= q0_t0;
end
if (ce1) begin
addr1_t1 <= addr1_t0;
d1_t1 <= d1_t0;
we1_t1 <= we1_t0;
end
end
always @(posedge clk) begin
if (ce0) begin
q0_t0 <= ram[addr0_t1];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1_t1) ram[addr1_t1] <= d1_t1;
end
end
endmodule
| 6.827284 |
module td_fused_top_tdf9_filters (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd16384;
parameter AddressWidth = 32'd14;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
td_fused_top_tdf9_filters_ram td_fused_top_tdf9_filters_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.we1(we1),
.d1(d1)
);
endmodule
| 6.827284 |
module td_fused_top_td_fused_axi_in_p_ram (
addr0,
ce0,
d0,
we0,
addr1,
ce1,
q1,
addr2,
ce2,
q2,
addr3,
ce3,
q3,
addr4,
ce4,
q4,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 2;
parameter MEM_SIZE = 4;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
input [AWIDTH-1:0] addr1;
input ce1;
output reg [DWIDTH-1:0] q1;
input [AWIDTH-1:0] addr2;
input ce2;
output reg [DWIDTH-1:0] q2;
input [AWIDTH-1:0] addr3;
input ce3;
output reg [DWIDTH-1:0] q3;
input [AWIDTH-1:0] addr4;
input ce4;
output reg [DWIDTH-1:0] q4;
input clk;
reg [DWIDTH-1:0] ram0[MEM_SIZE-1:0];
reg [DWIDTH-1:0] ram1[MEM_SIZE-1:0];
reg [DWIDTH-1:0] ram2[MEM_SIZE-1:0];
reg [DWIDTH-1:0] ram3[MEM_SIZE-1:0];
always @(posedge clk) begin
if (ce0) begin
if (we0) ram0[addr0] <= d0;
end
end
always @(posedge clk) begin
if (ce1) begin
q1 <= ram0[addr1];
end
end
always @(posedge clk) begin
if (ce0) begin
if (we0) ram1[addr0] <= d0;
end
end
always @(posedge clk) begin
if (ce2) begin
q2 <= ram1[addr2];
end
end
always @(posedge clk) begin
if (ce0) begin
if (we0) ram2[addr0] <= d0;
end
end
always @(posedge clk) begin
if (ce3) begin
q3 <= ram2[addr3];
end
end
always @(posedge clk) begin
if (ce0) begin
if (we0) ram3[addr0] <= d0;
end
end
always @(posedge clk) begin
if (ce4) begin
q4 <= ram3[addr4];
end
end
endmodule
| 6.827284 |
module td_fused_top_td_fused_axi_in_p (
reset,
clk,
address0,
ce0,
we0,
d0,
address1,
ce1,
q1,
address2,
ce2,
q2,
address3,
ce3,
q3,
address4,
ce4,
q4
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd4;
parameter AddressWidth = 32'd2;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
input [AddressWidth - 1:0] address1;
input ce1;
output [DataWidth - 1:0] q1;
input [AddressWidth - 1:0] address2;
input ce2;
output [DataWidth - 1:0] q2;
input [AddressWidth - 1:0] address3;
input ce3;
output [DataWidth - 1:0] q3;
input [AddressWidth - 1:0] address4;
input ce4;
output [DataWidth - 1:0] q4;
td_fused_top_td_fused_axi_in_p_ram td_fused_top_td_fused_axi_in_p_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.we0(we0),
.d0(d0),
.addr1(address1),
.ce1(ce1),
.q1(q1),
.addr2(address2),
.ce2(ce2),
.q2(q2),
.addr3(address3),
.ce3(ce3),
.q3(q3),
.addr4(address4),
.ce4(ce4),
.q4(q4)
);
endmodule
| 6.827284 |
module td_fused_top_td_fused_final_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 16;
parameter MEM_SIZE = 49000;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
wire [AWIDTH-1:0] addr0_t0;
reg [AWIDTH-1:0] addr0_t1;
reg [DWIDTH-1:0] q0_t0;
reg [DWIDTH-1:0] q0_t1;
wire [AWIDTH-1:0] addr1_t0;
reg [AWIDTH-1:0] addr1_t1;
wire [DWIDTH-1:0] d1_t0;
wire we1_t0;
reg [DWIDTH-1:0] d1_t1;
reg we1_t1;
assign addr0_t0 = addr0;
assign q0 = q0_t1;
assign addr1_t0 = addr1;
assign d1_t0 = d1;
assign we1_t0 = we1;
always @(posedge clk) begin
if (ce0) begin
addr0_t1 <= addr0_t0;
q0_t1 <= q0_t0;
end
if (ce1) begin
addr1_t1 <= addr1_t0;
d1_t1 <= d1_t0;
we1_t1 <= we1_t0;
end
end
always @(posedge clk) begin
if (ce0) begin
q0_t0 <= ram[addr0_t1];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1_t1) ram[addr1_t1] <= d1_t1;
end
end
endmodule
| 6.827284 |
module td_fused_top_td_fused_final_fmaps_memcore (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd49000;
parameter AddressWidth = 32'd16;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
td_fused_top_td_fused_final_fmaps_memcore_ram td_fused_top_td_fused_final_fmaps_memcore_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.we1(we1),
.d1(d1)
);
endmodule
| 6.827284 |
module td_fused_top_td_fused_tdf10_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 12;
parameter MEM_SIZE = 3136;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
wire [AWIDTH-1:0] addr0_t0;
reg [AWIDTH-1:0] addr0_t1;
reg [DWIDTH-1:0] q0_t0;
reg [DWIDTH-1:0] q0_t1;
wire [AWIDTH-1:0] addr1_t0;
reg [AWIDTH-1:0] addr1_t1;
wire [DWIDTH-1:0] d1_t0;
wire we1_t0;
reg [DWIDTH-1:0] d1_t1;
reg we1_t1;
assign addr0_t0 = addr0;
assign q0 = q0_t1;
assign addr1_t0 = addr1;
assign d1_t0 = d1;
assign we1_t0 = we1;
always @(posedge clk) begin
if (ce0) begin
addr0_t1 <= addr0_t0;
q0_t1 <= q0_t0;
end
if (ce1) begin
addr1_t1 <= addr1_t0;
d1_t1 <= d1_t0;
we1_t1 <= we1_t0;
end
end
always @(posedge clk) begin
if (ce0) begin
q0_t0 <= ram[addr0_t1];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1_t1) ram[addr1_t1] <= d1_t1;
end
end
endmodule
| 6.827284 |
module td_fused_top_td_fused_tdf10_fmaps_memcore (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd3136;
parameter AddressWidth = 32'd12;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
td_fused_top_td_fused_tdf10_fmaps_memcore_ram td_fused_top_td_fused_tdf10_fmaps_memcore_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.we1(we1),
.d1(d1)
);
endmodule
| 6.827284 |
module td_fused_top_td_fused_tdf1_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 16;
parameter MEM_SIZE = 50176;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
wire [AWIDTH-1:0] addr0_t0;
reg [AWIDTH-1:0] addr0_t1;
reg [DWIDTH-1:0] q0_t0;
reg [DWIDTH-1:0] q0_t1;
wire [AWIDTH-1:0] addr1_t0;
reg [AWIDTH-1:0] addr1_t1;
wire [DWIDTH-1:0] d1_t0;
wire we1_t0;
reg [DWIDTH-1:0] d1_t1;
reg we1_t1;
assign addr0_t0 = addr0;
assign q0 = q0_t1;
assign addr1_t0 = addr1;
assign d1_t0 = d1;
assign we1_t0 = we1;
always @(posedge clk) begin
if (ce0) begin
addr0_t1 <= addr0_t0;
q0_t1 <= q0_t0;
end
if (ce1) begin
addr1_t1 <= addr1_t0;
d1_t1 <= d1_t0;
we1_t1 <= we1_t0;
end
end
always @(posedge clk) begin
if (ce0) begin
q0_t0 <= ram[addr0_t1];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1_t1) ram[addr1_t1] <= d1_t1;
end
end
endmodule
| 6.827284 |
module td_fused_top_td_fused_tdf1_fmaps_memcore (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd50176;
parameter AddressWidth = 32'd16;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
td_fused_top_td_fused_tdf1_fmaps_memcore_ram td_fused_top_td_fused_tdf1_fmaps_memcore_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.we1(we1),
.d1(d1)
);
endmodule
| 6.827284 |
module td_fused_top_td_fused_tdf3_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 15;
parameter MEM_SIZE = 25088;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
wire [AWIDTH-1:0] addr0_t0;
reg [AWIDTH-1:0] addr0_t1;
reg [DWIDTH-1:0] q0_t0;
reg [DWIDTH-1:0] q0_t1;
wire [AWIDTH-1:0] addr1_t0;
reg [AWIDTH-1:0] addr1_t1;
wire [DWIDTH-1:0] d1_t0;
wire we1_t0;
reg [DWIDTH-1:0] d1_t1;
reg we1_t1;
assign addr0_t0 = addr0;
assign q0 = q0_t1;
assign addr1_t0 = addr1;
assign d1_t0 = d1;
assign we1_t0 = we1;
always @(posedge clk) begin
if (ce0) begin
addr0_t1 <= addr0_t0;
q0_t1 <= q0_t0;
end
if (ce1) begin
addr1_t1 <= addr1_t0;
d1_t1 <= d1_t0;
we1_t1 <= we1_t0;
end
end
always @(posedge clk) begin
if (ce0) begin
q0_t0 <= ram[addr0_t1];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1_t1) ram[addr1_t1] <= d1_t1;
end
end
endmodule
| 6.827284 |
module td_fused_top_td_fused_tdf3_fmaps_memcore (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd25088;
parameter AddressWidth = 32'd15;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
td_fused_top_td_fused_tdf3_fmaps_memcore_ram td_fused_top_td_fused_tdf3_fmaps_memcore_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.we1(we1),
.d1(d1)
);
endmodule
| 6.827284 |
module td_fused_top_td_fused_tdf4_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 14;
parameter MEM_SIZE = 12544;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
wire [AWIDTH-1:0] addr0_t0;
reg [AWIDTH-1:0] addr0_t1;
reg [DWIDTH-1:0] q0_t0;
reg [DWIDTH-1:0] q0_t1;
wire [AWIDTH-1:0] addr1_t0;
reg [AWIDTH-1:0] addr1_t1;
wire [DWIDTH-1:0] d1_t0;
wire we1_t0;
reg [DWIDTH-1:0] d1_t1;
reg we1_t1;
assign addr0_t0 = addr0;
assign q0 = q0_t1;
assign addr1_t0 = addr1;
assign d1_t0 = d1;
assign we1_t0 = we1;
always @(posedge clk) begin
if (ce0) begin
addr0_t1 <= addr0_t0;
q0_t1 <= q0_t0;
end
if (ce1) begin
addr1_t1 <= addr1_t0;
d1_t1 <= d1_t0;
we1_t1 <= we1_t0;
end
end
always @(posedge clk) begin
if (ce0) begin
q0_t0 <= ram[addr0_t1];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1_t1) ram[addr1_t1] <= d1_t1;
end
end
endmodule
| 6.827284 |
module td_fused_top_td_fused_tdf4_fmaps_memcore (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd12544;
parameter AddressWidth = 32'd14;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
td_fused_top_td_fused_tdf4_fmaps_memcore_ram td_fused_top_td_fused_tdf4_fmaps_memcore_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.we1(we1),
.d1(d1)
);
endmodule
| 6.827284 |
module td_fused_top_td_fused_tdf7_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 13;
parameter MEM_SIZE = 6272;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
wire [AWIDTH-1:0] addr0_t0;
reg [AWIDTH-1:0] addr0_t1;
reg [DWIDTH-1:0] q0_t0;
reg [DWIDTH-1:0] q0_t1;
wire [AWIDTH-1:0] addr1_t0;
reg [AWIDTH-1:0] addr1_t1;
wire [DWIDTH-1:0] d1_t0;
wire we1_t0;
reg [DWIDTH-1:0] d1_t1;
reg we1_t1;
assign addr0_t0 = addr0;
assign q0 = q0_t1;
assign addr1_t0 = addr1;
assign d1_t0 = d1;
assign we1_t0 = we1;
always @(posedge clk) begin
if (ce0) begin
addr0_t1 <= addr0_t0;
q0_t1 <= q0_t0;
end
if (ce1) begin
addr1_t1 <= addr1_t0;
d1_t1 <= d1_t0;
we1_t1 <= we1_t0;
end
end
always @(posedge clk) begin
if (ce0) begin
q0_t0 <= ram[addr0_t1];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1_t1) ram[addr1_t1] <= d1_t1;
end
end
endmodule
| 6.827284 |
module td_fused_top_td_fused_tdf7_fmaps_memcore (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd6272;
parameter AddressWidth = 32'd13;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
td_fused_top_td_fused_tdf7_fmaps_memcore_ram td_fused_top_td_fused_tdf7_fmaps_memcore_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.we1(we1),
.d1(d1)
);
endmodule
| 6.827284 |
module FPMult_PrepModule (
clk,
rst,
a,
b,
Sa,
Sb,
Ea,
Eb,
Mp,
InputExc
);
// Input ports
input clk;
input rst;
input [`DWIDTH-1:0] a; // Input A, a 32-bit floating point number
input [`DWIDTH-1:0] b; // Input B, a 32-bit floating point number
// Output ports
output Sa; // A's sign
output Sb; // B's sign
output [`EXPONENT-1:0] Ea; // A's exponent
output [`EXPONENT-1:0] Eb; // B's exponent
output [2*`MANTISSA+1:0] Mp; // Mantissa product
output [4:0] InputExc; // Input numbers are exceptions
// Internal signals // If signal is high...
wire ANaN; // A is a signalling NaN
wire BNaN; // B is a signalling NaN
wire AInf; // A is infinity
wire BInf; // B is infinity
wire [`MANTISSA-1:0] Ma;
wire [`MANTISSA-1:0] Mb;
assign ANaN = &(a[`DWIDTH-2:`MANTISSA]) & |(a[`DWIDTH-2:`MANTISSA]) ; // All one exponent and not all zero mantissa - NaN
assign BNaN = &(b[`DWIDTH-2:`MANTISSA]) & |(b[`MANTISSA-1:0]); // All one exponent and not all zero mantissa - NaN
assign AInf = &(a[`DWIDTH-2:`MANTISSA]) & ~|(a[`DWIDTH-2:`MANTISSA]) ; // All one exponent and all zero mantissa - Infinity
assign BInf = &(b[`DWIDTH-2:`MANTISSA]) & ~|(b[`DWIDTH-2:`MANTISSA]) ; // All one exponent and all zero mantissa - Infinity
// Check for any exceptions and put all flags into exception vector
assign InputExc = {(ANaN | BNaN | AInf | BInf), ANaN, BNaN, AInf, BInf};
//assign InputExc = {(ANaN | ANaN | BNaN |BNaN), ANaN, ANaN, BNaN,BNaN} ;
// Take input numbers apart
assign Sa = a[`DWIDTH-1]; // A's sign
assign Sb = b[`DWIDTH-1]; // B's sign
assign Ea = a[`DWIDTH-2:`MANTISSA]; // Store A's exponent in Ea, unless A is an exception
assign Eb = b[`DWIDTH-2:`MANTISSA]; // Store B's exponent in Eb, unless B is an exception
// assign Ma = a[`MANTISSA_MSB:`MANTISSA_LSB];
// assign Mb = b[`MANTISSA_MSB:`MANTISSA_LSB];
//assign Mp = ({4'b0001, a[`MANTISSA-1:0]}*{4'b0001, b[`MANTISSA-1:9]}) ;
assign Mp = ({1'b1, a[`MANTISSA-1:0]} * {1'b1, b[`MANTISSA-1:0]});
//We multiply part of the mantissa here
//Full mantissa of A
//Bits MANTISSA_MUL_SPLIT_MSB:MANTISSA_MUL_SPLIT_LSB of B
// wire [`ACTUAL_MANTISSA-1:0] inp_A;
// wire [`ACTUAL_MANTISSA-1:0] inp_B;
// assign inp_A = {1'b1, Ma};
// assign inp_B = {{(`MANTISSA-(`MANTISSA_MUL_SPLIT_MSB-`MANTISSA_MUL_SPLIT_LSB+1)){1'b0}}, 1'b1, Mb[`MANTISSA_MUL_SPLIT_MSB:`MANTISSA_MUL_SPLIT_LSB]};
// DW02_mult #(`ACTUAL_MANTISSA,`ACTUAL_MANTISSA) u_mult(.A(inp_A), .B(inp_B), .TC(1'b0), .PRODUCT(Mp));
endmodule
| 7.427166 |
module FPMult_NormalizeModule (
NormM,
NormE,
RoundE,
RoundEP,
RoundM,
RoundMP
);
// Input Ports
input [`MANTISSA-1:0] NormM; // Normalized mantissa
input [`EXPONENT:0] NormE; // Normalized exponent
// Output Ports
output [`EXPONENT:0] RoundE;
output [`EXPONENT:0] RoundEP;
output [`MANTISSA:0] RoundM;
output [`MANTISSA:0] RoundMP;
assign RoundE = NormE - 15;
assign RoundEP = NormE - 14;
assign RoundM = NormM;
assign RoundMP = NormM;
endmodule
| 7.947312 |
module FPMult_RoundModule (
RoundM,
RoundMP,
RoundE,
RoundEP,
Sp,
GRS,
InputExc,
Z,
Flags
);
// Input Ports
input [`MANTISSA:0] RoundM; // Normalized mantissa
input [`MANTISSA:0] RoundMP; // Normalized exponent
input [`EXPONENT:0] RoundE; // Normalized mantissa + 1
input [`EXPONENT:0] RoundEP; // Normalized exponent + 1
input Sp; // Product sign
input GRS;
input [4:0] InputExc;
// Output Ports
output [`DWIDTH-1:0] Z; // Final product
output [4:0] Flags;
// Internal Signals
wire [`EXPONENT:0] FinalE; // Rounded exponent
wire [`MANTISSA:0] FinalM;
wire [`MANTISSA:0] PreShiftM;
assign PreShiftM = GRS ? RoundMP : RoundM; // Round up if R and (G or S)
// Post rounding normalization (potential one bit shift> use shifted mantissa if there is overflow)
assign FinalM = (PreShiftM[`MANTISSA] ? {1'b0, PreShiftM[`MANTISSA:1]} : PreShiftM[`MANTISSA:0]);
assign FinalE = (PreShiftM[`MANTISSA] ? RoundEP : RoundE) ; // Increment exponent if a shift was done
assign Z = {Sp, FinalE[`EXPONENT-1:0], FinalM[`MANTISSA-1:0]}; // Putting the pieces together
assign Flags = InputExc[4:0];
endmodule
| 7.570448 |
module is responsible for taking the inputs
// apart and checking the parts for exceptions.
// The exponent difference is also calculated in this module.
module FPAddSub_PrealignModule(
A,
B,
operation,
Sa,
Sb,
ShiftDet,
InputExc,
Aout,
Bout,
Opout
);
// Input ports
input [`DWIDTH-1:0] A ; // Input A, a 32-bit floating point number
input [`DWIDTH-1:0] B ; // Input B, a 32-bit floating point number
input operation ;
// Output ports
output Sa ; // A's sign
output Sb ; // B's sign
output [9:0] ShiftDet ;
output [4:0] InputExc ; // Input numbers are exceptions
output [`DWIDTH-2:0] Aout ;
output [`DWIDTH-2:0] Bout ;
output Opout ;
// Internal signals // If signal is high...
wire ANaN ; // A is a NaN (Not-a-Number)
wire BNaN ; // B is a NaN
wire AInf ; // A is infinity
wire BInf ; // B is infinity
wire [`EXPONENT-1:0] DAB ; // ExpA - ExpB
wire [`EXPONENT-1:0] DBA ; // ExpB - ExpA
assign ANaN = &(A[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & |(A[`MANTISSA-1:0]) ; // All one exponent and not all zero mantissa - NaN
assign BNaN = &(B[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & |(B[`MANTISSA-1:0]); // All one exponent and not all zero mantissa - NaN
assign AInf = &(A[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & ~|(A[`MANTISSA-1:0]) ; // All one exponent and all zero mantissa - Infinity
assign BInf = &(B[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & ~|(B[`MANTISSA-1:0]) ; // All one exponent and all zero mantissa - Infinity
// Put all flags into exception vector
assign InputExc = {(ANaN | BNaN | AInf | BInf), ANaN, BNaN, AInf, BInf} ;
//assign DAB = (A[30:23] - B[30:23]) ;
//assign DBA = (B[30:23] - A[30:23]) ;
assign DAB = (A[`DWIDTH-2:`MANTISSA] + ~(B[`DWIDTH-2:`MANTISSA]) + 1) ;
assign DBA = (B[`DWIDTH-2:`MANTISSA] + ~(A[`DWIDTH-2:`MANTISSA]) + 1) ;
assign Sa = A[`DWIDTH-1] ; // A's sign bit
assign Sb = B[`DWIDTH-1] ; // B's sign bit
assign ShiftDet = {DBA[4:0], DAB[4:0]} ; // Shift data
assign Opout = operation ;
assign Aout = A[`DWIDTH-2:0] ;
assign Bout = B[`DWIDTH-2:0] ;
endmodule
| 7.391888 |
module determines the larger input operand and
// sets the mantissas, shift and common exponent accordingly.
module FPAddSub_AlignModule (
A,
B,
ShiftDet,
CExp,
MaxAB,
Shift,
Mmin,
Mmax
);
// Input ports
input [`DWIDTH-2:0] A ; // Input A, a 32-bit floating point number
input [`DWIDTH-2:0] B ; // Input B, a 32-bit floating point number
input [9:0] ShiftDet ;
// Output ports
output [`EXPONENT-1:0] CExp ; // Common Exponent
output MaxAB ; // Incidates larger of A and B (0/A, 1/B)
output [4:0] Shift ; // Number of steps to smaller mantissa shift right
output [`MANTISSA-1:0] Mmin ; // Smaller mantissa
output [`MANTISSA-1:0] Mmax ; // Larger mantissa
// Internal signals
//wire BOF ; // Check for shifting overflow if B is larger
//wire AOF ; // Check for shifting overflow if A is larger
assign MaxAB = (A[`DWIDTH-2:0] < B[`DWIDTH-2:0]) ;
//assign BOF = ShiftDet[9:5] < 25 ; // Cannot shift more than 25 bits
//assign AOF = ShiftDet[4:0] < 25 ; // Cannot shift more than 25 bits
// Determine final shift value
//assign Shift = MaxAB ? (BOF ? ShiftDet[9:5] : 5'b11001) : (AOF ? ShiftDet[4:0] : 5'b11001) ;
assign Shift = MaxAB ? ShiftDet[9:5] : ShiftDet[4:0] ;
// Take out smaller mantissa and append shift space
assign Mmin = MaxAB ? A[`MANTISSA-1:0] : B[`MANTISSA-1:0] ;
// Take out larger mantissa
assign Mmax = MaxAB ? B[`MANTISSA-1:0]: A[`MANTISSA-1:0] ;
// Common exponent
assign CExp = (MaxAB ? B[`MANTISSA+`EXPONENT-1:`MANTISSA] : A[`MANTISSA+`EXPONENT-1:`MANTISSA]) ;
endmodule
| 6.986217 |
module FPAddSub_AlignShift1 (
MminP,
Shift,
Mmin
);
// Input ports
input [`MANTISSA-1:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [2:0] Shift; // Shift amount
// Output ports
output [`MANTISSA:0] Mmin; // The smaller mantissa
// Internal signals
reg [ `MANTISSA:0] Lvl1;
reg [ `MANTISSA:0] Lvl2;
wire [2*`MANTISSA+1:0] Stage1;
integer i; // Loop variable
always @(*) begin
// Rotate by 16?
//Lvl1 <= Shift[2] ? {17'b00000000000000001, MminP[22:16]} : {1'b1, MminP};
Lvl1 <= Shift[2] ? {11'b0000000000} : {1'b1, MminP};
end
assign Stage1 = {11'b0, Lvl1};
always @(*) begin // Rotate {0 | 4 | 8 | 12} bits
case (Shift[1:0])
// Rotate by 0
2'b00: Lvl2 <= Stage1[`MANTISSA:0];
// Rotate by 4
2'b01: begin
for (i = 0; i <= `MANTISSA; i = i + 1) begin
Lvl2[i] <= Stage1[i+4];
end /*Lvl2[`MANTISSA:`MANTISSA-3] <= 0;*/
end
// Rotate by 8
2'b10: begin
for (i = 0; i <= `MANTISSA; i = i + 1) begin
Lvl2[i] <= Stage1[i+8];
end /*Lvl2[`MANTISSA:`MANTISSA-7] <= 0;*/
end
// Rotate by 12
2'b11: Lvl2[`MANTISSA:0] <= 0;
//2'b11: begin for (i=0; i<=`MANTISSA; i=i+1) begin Lvl2[i] <= Stage1[i+12]; end Lvl2[`MANTISSA:`MANTISSA-12] <= 0; end
endcase
end
// Assign output to next shift stage
assign Mmin = Lvl2;
endmodule
| 6.969233 |
module FPAddSub_AlignShift2 (
MminP,
Shift,
Mmin
);
// Input ports
input [`MANTISSA:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [1:0] Shift; // Shift amount
// Output ports
output [`MANTISSA:0] Mmin; // The smaller mantissa
// Internal Signal
reg [ `MANTISSA:0] Lvl3;
wire [2*`MANTISSA+1:0] Stage2;
integer j; // Loop variable
assign Stage2 = {11'b0, MminP};
always @(*) begin // Rotate {0 | 1 | 2 | 3} bits
case (Shift[1:0])
// Rotate by 0
2'b00: Lvl3 <= Stage2[`MANTISSA:0];
// Rotate by 1
2'b01: begin
for (j = 0; j <= `MANTISSA; j = j + 1) begin
Lvl3[j] <= Stage2[j+1];
end /*Lvl3[`MANTISSA] <= 0; */
end
// Rotate by 2
2'b10: begin
for (j = 0; j <= `MANTISSA; j = j + 1) begin
Lvl3[j] <= Stage2[j+2];
end /*Lvl3[`MANTISSA:`MANTISSA-1] <= 0;*/
end
// Rotate by 3
2'b11: begin
for (j = 0; j <= `MANTISSA; j = j + 1) begin
Lvl3[j] <= Stage2[j+3];
end /*Lvl3[`MANTISSA:`MANTISSA-2] <= 0;*/
end
endcase
end
// Assign output
assign Mmin = Lvl3; // Take out smaller mantissa
endmodule
| 6.969233 |
module FPAddSub_ExecutionModule (
Mmax,
Mmin,
Sa,
Sb,
MaxAB,
OpMode,
Sum,
PSgn,
Opr
);
// Input ports
input [`MANTISSA-1:0] Mmax; // The larger mantissa
input [`MANTISSA:0] Mmin; // The smaller mantissa
input Sa; // Sign bit of larger number
input Sb; // Sign bit of smaller number
input MaxAB; // Indicates the larger number (0/A, 1/B)
input OpMode; // Operation to be performed (0/Add, 1/Sub)
// Output ports
output [`DWIDTH:0] Sum; // The result of the operation
output PSgn; // The sign for the result
output Opr; // The effective (performed) operation
assign Opr = (OpMode ^ Sa ^ Sb); // Resolve sign to determine operation
// Perform effective operation
assign Sum = (OpMode^Sa^Sb) ? ({1'b1, Mmax, 5'b00000} - {Mmin, 5'b00000}) : ({1'b1, Mmax, 5'b00000} + {Mmin, 5'b00000}) ;
// Assign result sign
assign PSgn = (MaxAB ? Sb : Sa);
endmodule
| 6.632792 |
module FPAddSub_NormalizeModule (
Sum,
Mmin,
Shift
);
// Input ports
input [`DWIDTH:0] Sum; // Mantissa sum including hidden 1 and GRS
// Output ports
output [`DWIDTH:0] Mmin; // Mantissa after 16|0 shift
output [4:0] Shift; // Shift amount
// Determine normalization shift amount by finding leading nought
assign Shift = (
Sum[16] ? 5'b00000 :
Sum[15] ? 5'b00001 :
Sum[14] ? 5'b00010 :
Sum[13] ? 5'b00011 :
Sum[12] ? 5'b00100 :
Sum[11] ? 5'b00101 :
Sum[10] ? 5'b00110 :
Sum[9] ? 5'b00111 :
Sum[8] ? 5'b01000 :
Sum[7] ? 5'b01001 :
Sum[6] ? 5'b01010 :
Sum[5] ? 5'b01011 :
Sum[4] ? 5'b01100 : 5'b01101
// Sum[19] ? 5'b01101 :
// Sum[18] ? 5'b01110 :
// Sum[17] ? 5'b01111 :
// Sum[16] ? 5'b10000 :
// Sum[15] ? 5'b10001 :
// Sum[14] ? 5'b10010 :
// Sum[13] ? 5'b10011 :
// Sum[12] ? 5'b10100 :
// Sum[11] ? 5'b10101 :
// Sum[10] ? 5'b10110 :
// Sum[9] ? 5'b10111 :
// Sum[8] ? 5'b11000 :
// Sum[7] ? 5'b11001 : 5'b11010
);
reg [`DWIDTH:0] Lvl1;
always @(*) begin
// Rotate by 16?
Lvl1 <= Shift[4] ? {Sum[8:0], 8'b00000000} : Sum;
end
// Assign outputs
assign Mmin = Lvl1; // Take out smaller mantissa
endmodule
| 6.905513 |
module FPAddSub_NormalizeShift1 (
MminP,
Shift,
Mmin
);
// Input ports
input [`DWIDTH:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [3:0] Shift; // Shift amount
// Output ports
output [`DWIDTH:0] Mmin; // The smaller mantissa
reg [ `DWIDTH:0] Lvl2;
wire [2*`DWIDTH+1:0] Stage1;
reg [ `DWIDTH:0] Lvl3;
wire [2*`DWIDTH+1:0] Stage2;
integer i; // Loop variable
assign Stage1 = {MminP, MminP};
always @(*) begin // Rotate {0 | 4 | 8 | 12} bits
case (Shift[3:2])
// Rotate by 0
2'b00: //Lvl2 <= Stage1[`DWIDTH:0];
begin
Lvl2 = Stage1[`DWIDTH:0];
end
// Rotate by 4
2'b01: //begin for (i=2*`DWIDTH+1; i>=`DWIDTH+1; i=i-1) begin Lvl2[i-33] <= Stage1[i-4]; end Lvl2[3:0] <= 0; end
begin
Lvl2[`DWIDTH:(`DWIDTH-4)] = Stage1[3:0];
Lvl2[`DWIDTH-4-1:0] = Stage1[`DWIDTH-4];
end
// Rotate by 8
2'b10: //begin for (i=2*`DWIDTH+1; i>=`DWIDTH+1; i=i-1) begin Lvl2[i-33] <= Stage1[i-8]; end Lvl2[7:0] <= 0; end
begin
Lvl2[`DWIDTH:(`DWIDTH-8)] = Stage1[3:0];
Lvl2[`DWIDTH-8-1:0] = Stage1[`DWIDTH-8];
end
// Rotate by 12
2'b11: //begin for (i=2*`DWIDTH+1; i>=`DWIDTH+1; i=i-1) begin Lvl2[i-33] <= Stage1[i-12]; end Lvl2[11:0] <= 0; end
begin
Lvl2[`DWIDTH:(`DWIDTH-12)] = Stage1[3:0];
Lvl2[`DWIDTH-12-1:0] = Stage1[`DWIDTH-12];
end
endcase
end
assign Stage2 = {Lvl2, Lvl2};
always @(*) begin // Rotate {0 | 1 | 2 | 3} bits
case (Shift[1:0])
// Rotate by 0
2'b00: //Lvl3 <= Stage2[`DWIDTH:0];
begin
Lvl3 = Stage2[`DWIDTH:0];
end
// Rotate by 1
2'b01: //begin for (i=2*`DWIDTH+1; i>=`DWIDTH+1; i=i-1) begin Lvl3[i-`DWIDTH-1] <= Stage2[i-1]; end Lvl3[0] <= 0; end
begin
Lvl3[`DWIDTH:(`DWIDTH-1)] = Stage2[3:0];
Lvl3[`DWIDTH-1-1:0] = Stage2[`DWIDTH-1];
end
// Rotate by 2
2'b10: //begin for (i=2*`DWIDTH+1; i>=`DWIDTH+1; i=i-1) begin Lvl3[i-`DWIDTH-1] <= Stage2[i-2]; end Lvl3[1:0] <= 0; end
begin
Lvl3[`DWIDTH:(`DWIDTH-2)] = Stage2[3:0];
Lvl3[`DWIDTH-2-1:0] = Stage2[`DWIDTH-2];
end
// Rotate by 3
2'b11: //begin for (i=2*`DWIDTH+1; i>=`DWIDTH+1; i=i-1) begin Lvl3[i-`DWIDTH-1] <= Stage2[i-3]; end Lvl3[2:0] <= 0; end
begin
Lvl3[`DWIDTH:(`DWIDTH-3)] = Stage2[3:0];
Lvl3[`DWIDTH-3-1:0] = Stage2[`DWIDTH-3];
end
endcase
end
// Assign outputs
assign Mmin = Lvl3; // Take out smaller mantissa
endmodule
| 6.905513 |
module FPAddSub_NormalizeShift2 (
PSSum,
CExp,
Shift,
NormM,
NormE,
ZeroSum,
NegE,
R,
S,
FG
);
// Input ports
input [`DWIDTH:0] PSSum; // The Pre-Shift-Sum
input [`EXPONENT-1:0] CExp;
input [4:0] Shift; // Amount to be shifted
// Output ports
output [`MANTISSA-1:0] NormM; // Normalized mantissa
output [`EXPONENT:0] NormE; // Adjusted exponent
output ZeroSum; // Zero flag
output NegE; // Flag indicating negative exponent
output R; // Round bit
output S; // Final sticky bit
output FG;
// Internal signals
wire MSBShift; // Flag indicating that a second shift is needed
wire [`EXPONENT:0] ExpOF; // MSB set in sum indicates overflow
wire [`EXPONENT:0] ExpOK; // MSB not set, no adjustment
// Calculate normalized exponent and mantissa, check for all-zero sum
assign MSBShift = PSSum[`DWIDTH]; // Check MSB in unnormalized sum
assign ZeroSum = ~|PSSum; // Check for all zero sum
assign ExpOK = CExp - Shift; // Adjust exponent for new normalized mantissa
assign NegE = ExpOK[`EXPONENT]; // Check for exponent overflow
assign ExpOF = CExp - Shift + 1'b1; // If MSB set, add one to exponent(x2)
assign NormE = MSBShift ? ExpOF : ExpOK; // Check for exponent overflow
assign NormM = PSSum[`DWIDTH-1:`EXPONENT+1]; // The new, normalized mantissa
// Also need to compute sticky and round bits for the rounding stage
assign FG = PSSum[`EXPONENT];
assign R = PSSum[`EXPONENT-1];
assign S = |PSSum[`EXPONENT-2:0];
endmodule
| 6.905513 |
module FPAddSub_RoundModule (
ZeroSum,
NormE,
NormM,
R,
S,
G,
Sa,
Sb,
Ctrl,
MaxAB,
Z,
EOF
);
// Input ports
input ZeroSum; // Sum is zero
input [`EXPONENT:0] NormE; // Normalized exponent
input [`MANTISSA-1:0] NormM; // Normalized mantissa
input R; // Round bit
input S; // Sticky bit
input G;
input Sa; // A's sign bit
input Sb; // B's sign bit
input Ctrl; // Control bit (operation)
input MaxAB;
// Output ports
output [`DWIDTH-1:0] Z; // Final result
output EOF;
// Internal signals
wire [ `MANTISSA:0] RoundUpM; // Rounded up sum with room for overflow
wire [`MANTISSA-1:0] RoundM; // The final rounded sum
wire [ `EXPONENT:0] RoundE; // Rounded exponent (note extra bit due to poential overflow )
wire RoundUp; // Flag indicating that the sum should be rounded up
wire FSgn;
wire ExpAdd; // May have to add 1 to compensate for overflow
wire RoundOF; // Rounding overflow
// The cases where we need to round upwards (= adding one) in Round to nearest, tie to even
assign RoundUp = (G & ((R | S) | NormM[0]));
// Note that in the other cases (rounding down), the sum is already 'rounded'
assign RoundUpM = (NormM + 1); // The sum, rounded up by 1
assign RoundM = (RoundUp ? RoundUpM[`MANTISSA-1:0] : NormM); // Compute final mantissa
assign RoundOF = RoundUp & RoundUpM[`MANTISSA]; // Check for overflow when rounding up
// Calculate post-rounding exponent
assign ExpAdd = (RoundOF ? 1'b1 : 1'b0); // Add 1 to exponent to compensate for overflow
assign RoundE = ZeroSum ? 5'b00000 : (NormE + ExpAdd); // Final exponent
// If zero, need to determine sign according to rounding
assign FSgn = (ZeroSum & (Sa ^ Sb)) | (ZeroSum ? (Sa & Sb & ~Ctrl) : ((~MaxAB & Sa) | ((Ctrl ^ Sb) & (MaxAB | Sa)))) ;
// Assign final result
assign Z = {FSgn, RoundE[`EXPONENT-1:0], RoundM[`MANTISSA-1:0]};
// Indicate exponent overflow
assign EOF = RoundE[`EXPONENT];
endmodule
| 7.753919 |
module FPAddSub_ExceptionModule (
Z,
NegE,
R,
S,
InputExc,
EOF,
P,
Flags
);
// Input ports
input [`DWIDTH-1:0] Z; // Final product
input NegE; // Negative exponent?
input R; // Round bit
input S; // Sticky bit
input [4:0] InputExc; // Exceptions in inputs A and B
input EOF;
// Output ports
output [`DWIDTH-1:0] P; // Final result
output [4:0] Flags; // Exception flags
// Internal signals
wire Overflow; // Overflow flag
wire Underflow; // Underflow flag
wire DivideByZero; // Divide-by-Zero flag (always 0 in Add/Sub)
wire Invalid; // Invalid inputs or result
wire Inexact; // Result is inexact because of rounding
// Exception flags
// Result is too big to be represented
assign Overflow = EOF | InputExc[1] | InputExc[0];
// Result is too small to be represented
assign Underflow = NegE & (R | S);
// Infinite result computed exactly from finite operands
assign DivideByZero = &(Z[`MANTISSA+`EXPONENT-1:`MANTISSA]) & ~|(Z[`MANTISSA+`EXPONENT-1:`MANTISSA]) & ~InputExc[1] & ~InputExc[0];
// Invalid inputs or operation
assign Invalid = |(InputExc[4:2]);
// Inexact answer due to rounding, overflow or underflow
assign Inexact = (R | S) | Overflow | Underflow;
// Put pieces together to form final result
assign P = Z;
// Collect exception flags
assign Flags = {Overflow, Underflow, DivideByZero, Invalid, Inexact};
endmodule
| 7.326377 |
module tiny_spi (
// system
input rst_i,
input clk_i,
// memory mapped
input stb_i,
input we_i,
output [31:0] dat_o,
input [31:0] dat_i,
output int_o,
input [2:0] adr_i,
//input cyc_i, // comment out for avalon
//output ack_o, // comment out for avalon
// spi
output MOSI,
output SCLK,
input MISO
);
parameter BAUD_WIDTH = 8;
parameter BAUD_DIV = 0;
parameter SPI_MODE = 0;
parameter BC_WIDTH = 3;
parameter DIV_WIDTH = BAUD_DIV ? $clog2(BAUD_DIV / 2 - 1) : BAUD_WIDTH;
reg [7:0] sr8, bb8;
wire [7:0] sr8_sf;
reg [BC_WIDTH - 1:0] bc, bc_next;
reg [DIV_WIDTH - 1:0] ccr;
reg [DIV_WIDTH - 1:0] cc, cc_next;
wire misod;
wire cstb, wstb, bstb, istb;
reg sck;
reg sf, ld;
reg bba; // buffer flag
reg txren, txeen;
wire txr, txe;
wire cpol, cpha;
reg cpolr, cphar;
wire wr;
wire cyc_i; // comment out for wishbone
wire ack_o; // comment out for wishbone
assign cyc_i = 1'b1; // comment out for wishbone
assign ack_o = stb_i & cyc_i; // zero wait
assign wr = stb_i & cyc_i & we_i & ack_o;
assign wstb = wr & (adr_i == 1);
assign istb = wr & (adr_i == 2);
assign cstb = wr & (adr_i == 3);
assign bstb = wr & (adr_i == 4);
assign sr8_sf = {sr8[6:0], misod};
assign dat_o =
(sr8 & {8{(adr_i == 0)}})
| (bb8 & {8{(adr_i == 1)}})
| ({ txr, txe } & {8{(adr_i == 2)}})
;
parameter IDLE = 0, PHASE1 = 1, PHASE2 = 2;
reg [1:0] spi_seq, spi_seq_next;
always @(posedge clk_i or posedge rst_i)
if (rst_i) spi_seq <= IDLE;
else spi_seq <= spi_seq_next;
always @(posedge clk_i) begin
cc <= cc_next;
bc <= bc_next;
end
always @( /*AS*/ bba or bc or cc or ccr or cpha or cpol or spi_seq) begin
sck = cpol;
cc_next = BAUD_DIV ? (BAUD_DIV / 2 - 1) : ccr;
bc_next = bc;
ld = 1'b0;
sf = 1'b0;
case (spi_seq)
IDLE: begin
if (bba) begin
bc_next = 7;
ld = 1'b1;
spi_seq_next = PHASE2;
end else spi_seq_next = IDLE;
end
PHASE2: begin
sck = (cpol ^ cpha);
if (cc == 0) spi_seq_next = PHASE1;
else begin
cc_next = cc - 1;
spi_seq_next = PHASE2;
end
end
PHASE1: begin
sck = ~(cpol ^ cpha);
if (cc == 0) begin
bc_next = bc - 1;
sf = 1'b1;
if (bc == 0) begin
if (bba) begin
bc_next = 7;
ld = 1'b1;
spi_seq_next = PHASE2;
end else spi_seq_next = IDLE;
end else spi_seq_next = PHASE2;
end else begin
cc_next = cc - 1;
spi_seq_next = PHASE1;
end
end
endcase
end // always @ (...
always @(posedge clk_i) begin
if (cstb) // control reg
{cpolr, cphar} <= dat_i;
else {cpolr, cphar} <= {cpolr, cphar};
if (istb) // irq enable reg
{txren, txeen} <= dat_i;
else {txren, txeen} <= {txren, txeen};
if (bstb) // baud reg
ccr <= dat_i;
else ccr <= ccr;
if (ld) // shift reg
sr8 <= bb8;
else if (sf) sr8 <= sr8_sf;
else sr8 <= sr8;
if (wstb) // buffer reg
bb8 <= dat_i;
else if (ld) bb8 <= (spi_seq == IDLE) ? sr8 : sr8_sf;
else bb8 <= bb8;
end // always @ (posedge clk_i)
always @(posedge clk_i or posedge rst_i) begin
if (rst_i) bba <= 1'b0;
else if (wstb) bba <= 1'b1;
else if (ld) bba <= 1'b0;
else bba <= bba;
end
assign {cpol, cpha} = ((SPI_MODE >= 0) & (SPI_MODE < 4)) ? SPI_MODE : {cpolr, cphar};
assign txe = (spi_seq == IDLE);
assign txr = ~bba;
assign int_o = (txr & txren) | (txe & txeen);
assign SCLK = sck;
assign MOSI = sr8[7];
assign misod = MISO;
endmodule
| 8.081707 |
module of constants
*
* addr out effective
* 1 0 1
* 2 1 1
* 4 + 1
* 8 - 1
* 16 cubic 1
* other 0 0
*/
module const_ (clk, addr, out, effective);
input clk;
input [5:0] addr;
output reg [`WIDTH_D0:0] out;
output reg effective; // active high if out is effective
always @ (posedge clk)
begin
effective <= 1;
case (addr)
1: out <= 0;
2: out <= 1;
4: out <= {6'b000101, 1182'd0};
8: out <= {6'b001001, 1182'd0};
16: out <= {6'b010101, 1182'd0};
default:
begin out <= 0; effective <= 0; end
endcase
end
endmodule
| 6.852447 |
module FSM (
clk,
reset,
rom_addr,
rom_q,
ram_a_addr,
ram_b_addr,
ram_b_w,
pe,
done
);
input clk;
input reset;
output reg [8:0] rom_addr; /* command id. extra bits? */
input [28:0] rom_q; /* command value */
output reg [5:0] ram_a_addr;
output reg [5:0] ram_b_addr;
output ram_b_w;
output reg [10:0] pe;
output reg done;
reg [5:0] state;
parameter START = 0, READ_SRC1 = 1, READ_SRC2 = 2, CALC = 4, WAIT = 8, WRITE = 16, DON = 32;
wire [5:0] dest, src1, src2;
wire [8:0] times;
wire [1:0] op;
assign {dest, src1, op, times, src2} = rom_q;
reg [8:0] count;
always @(posedge clk)
if (reset) state <= START;
else
case (state)
START: state <= READ_SRC1;
READ_SRC1: state <= READ_SRC2;
READ_SRC2:
if (times == 0) state <= DON;
else state <= CALC;
CALC: if (count == 1) state <= WAIT;
WAIT: state <= WRITE;
WRITE: state <= READ_SRC1;
endcase
/* we support two loops */
parameter LOOP1_START = 9'd21, LOOP1_END = 9'd116, LOOP2_START = 9'd288, LOOP2_END = 9'd301;
reg [294:0] loop1, loop2;
always @(posedge clk)
if (reset) rom_addr <= 0;
else if (state == WAIT) begin
if (rom_addr == LOOP1_END && loop1[0]) rom_addr <= LOOP1_START;
else if (rom_addr == LOOP2_END && loop2[0]) rom_addr <= LOOP2_START;
else rom_addr <= rom_addr + 1'd1;
end
always @(posedge clk)
if (reset) loop1 <= ~0;
else if (state == WAIT && rom_addr == LOOP1_END) loop1 <= loop1 >> 1;
always @(posedge clk)
if (reset) loop2 <= ~0;
else if (state == WAIT && rom_addr == LOOP2_END) loop2 <= loop2 >> 1;
always @(posedge clk)
if (reset) count <= 0;
else if (state == READ_SRC1) count <= times;
else if (state == CALC) count <= count - 1'd1;
always @(posedge clk)
if (reset) done <= 0;
else if (state == DON) done <= 1;
else done <= 0;
always @(state, src1, src2)
case (state)
READ_SRC1: ram_a_addr = src1;
READ_SRC2: ram_a_addr = src2;
default: ram_a_addr = 0;
endcase
parameter CMD_ADD=6'd4, CMD_SUB=6'd8, CMD_CUBIC=6'd16,
ADD=2'd0, SUB=2'd1, CUBIC=2'd2, MULT=2'd3;
always @(posedge clk)
case (state)
READ_SRC1:
case (op)
ADD: pe <= 11'b11001000000;
SUB: pe <= 11'b11001000000;
CUBIC: pe <= 11'b11111000000;
MULT: pe <= 11'b11110000000;
default: pe <= 0;
endcase
READ_SRC2:
case (op)
ADD: pe <= 11'b00110000000;
SUB: pe <= 11'b00110000000;
CUBIC: pe <= 0;
MULT: pe <= 11'b00001000000;
default: pe <= 0;
endcase
CALC:
case (op)
ADD: pe <= 11'b00000010001;
SUB: pe <= 11'b00000010001;
CUBIC: pe <= 11'b01010000001;
MULT: pe <= 11'b00000111111;
default: pe <= 0;
endcase
default: pe <= 0;
endcase
always @(state, op, src2, dest)
case (state)
READ_SRC1:
case (op)
ADD: ram_b_addr = CMD_ADD;
SUB: ram_b_addr = CMD_SUB;
CUBIC: ram_b_addr = CMD_CUBIC;
default: ram_b_addr = 0;
endcase
READ_SRC2: ram_b_addr = src2;
WRITE: ram_b_addr = dest;
default: ram_b_addr = 0;
endcase
assign ram_b_w = (state == WRITE) ? 1'b1 : 1'b0;
endmodule
| 6.752458 |
module pairing (
clk,
reset,
sel,
addr,
w,
update,
ready,
i,
o,
done
);
input clk;
input reset; // for the arithmethic core
input sel;
input [5:0] addr;
input w;
input update; // update reg_in & reg_out
input ready; // shift reg_in & reg_out
input i;
output o;
output done;
reg [`WIDTH_D0:0] reg_in, reg_out;
wire [`WIDTH_D0:0] out;
assign o = reg_out[0];
tiny tiny0 (
clk,
reset,
sel,
addr,
w,
reg_in,
out,
done
);
always @(posedge clk) // write LSB firstly
if (update) reg_in <= 0;
else if (ready) reg_in <= {i, reg_in[`WIDTH_D0:1]};
always @(posedge clk) // read LSB firstly
if (update) reg_out <= out;
else if (ready) reg_out <= reg_out >> 1;
endmodule
| 7.568618 |
module PPG (
d,
A,
C
);
input [1:0] d;
input [`WIDTH:0] A;
output [`WIDTH:0] C;
genvar i;
generate
for (i = 0; i < `M; i = i + 1) begin : ppg0
f3_mult f3_mult_0 (
d,
A[2*i+1:2*i],
C[2*i+1:2*i]
);
end
endgenerate
endmodule
| 7.164526 |
module f3m_add (
A,
B,
C
);
input [`WIDTH : 0] A, B;
output [`WIDTH : 0] C;
genvar i;
generate
for (i = 0; i < `M; i = i + 1) begin : aa
f3_add aa (
A[(2*i+1) : 2*i],
B[(2*i+1) : 2*i],
C[(2*i+1) : 2*i]
);
end
endgenerate
endmodule
| 7.024046 |
module ram #(
parameter DATA = 1188,
parameter ADDR = 6
) (
input clk,
// Port A
input wire a_wr,
input wire [ADDR-1:0] a_addr,
input wire [DATA-1:0] a_din,
output reg [DATA-1:0] a_dout,
// Port B
input wire b_wr,
input wire [ADDR-1:0] b_addr,
input wire [DATA-1:0] b_din,
output reg [DATA-1:0] b_dout
);
// Shared memory
reg [DATA-1:0] mem[(2**ADDR)-1:0];
initial begin : init
integer i;
for (i = 0; i < (2 ** ADDR); i = i + 1) mem[i] = 0;
end
// Port A
always @(posedge clk) begin
a_dout <= mem[a_addr];
if (a_wr) begin
a_dout <= a_din;
mem[a_addr] <= a_din;
end
end
// Port B
always @(posedge clk) begin
b_dout <= mem[b_addr];
if (b_wr) begin
b_dout <= b_din;
mem[b_addr] <= b_din;
end
end
endmodule
| 7.30525 |
module tiny (
clk,
reset,
sel,
addr,
w,
data,
out,
done
);
input clk, reset;
input sel;
input [5:0] addr;
input w;
input [`WIDTH_D0:0] data;
output [`WIDTH_D0:0] out;
output done;
/* for FSM */
wire [5:0] fsm_addr;
/* for RAM */
wire [5:0] ram_a_addr, ram_b_addr;
wire [`WIDTH_D0:0] ram_b_data_in;
wire ram_a_w, ram_b_w;
wire [`WIDTH_D0:0] ram_a_data_out, ram_b_data_out;
/* for const */
wire [`WIDTH_D0:0] const0_out, const1_out;
wire const0_effective, const1_effective;
/* for muxer */
wire [`WIDTH_D0:0] muxer0_out, muxer1_out;
/* for ROM */
wire [ 8:0] rom_addr;
wire [28:0] rom_q;
/* for PE */
wire [10:0] pe_ctrl;
assign out = ram_a_data_out;
select select0 (
sel,
addr,
fsm_addr,
w,
ram_a_addr,
ram_a_w
);
rom rom0 (
clk,
rom_addr,
rom_q
);
FSM fsm0 (
clk,
reset,
rom_addr,
rom_q,
fsm_addr,
ram_b_addr,
ram_b_w,
pe_ctrl,
done
);
const_
const0 (
clk,
ram_a_addr,
const0_out,
const0_effective
),
const1 (
clk,
ram_b_addr,
const1_out,
const1_effective
);
ram ram0 (
clk,
ram_a_w,
ram_a_addr,
data,
ram_a_data_out,
ram_b_w,
ram_b_addr[5:0],
ram_b_data_in,
ram_b_data_out
);
muxer
muxer0 (
ram_a_data_out,
const0_out,
const0_effective,
muxer0_out
),
muxer1 (
ram_b_data_out,
const1_out,
const1_effective,
muxer1_out
);
PE pe0 (
clk,
reset,
pe_ctrl,
muxer1_out,
muxer0_out[`WIDTH:0],
muxer0_out[`WIDTH:0],
ram_b_data_in[`WIDTH:0]
);
assign ram_b_data_in[`WIDTH_D0:`WIDTH+1] = 0;
endmodule
| 6.906849 |
module select (
sel,
addr_in,
addr_fsm_in,
w_in,
addr_out,
w_out
);
input sel;
input [5:0] addr_in;
input [5:0] addr_fsm_in;
input w_in;
output [5:0] addr_out;
output w_out;
assign addr_out = sel ? addr_in : addr_fsm_in;
assign w_out = sel & w_in;
endmodule
| 7.910302 |
module muxer (
from_ram,
from_const,
const_effective,
out
);
input [`WIDTH_D0:0] from_ram, from_const;
input const_effective;
output [`WIDTH_D0:0] out;
assign out = const_effective ? from_const : from_ram;
endmodule
| 6.618212 |
module instance
// generated by configure.py
module tiny_user_project(
`ifdef USE_POWER_PINS
inout vccd1,
inout vssd1,
`endif
// IOs
input [`MPRJ_IO_PADS-1:0] io_in,
output [`MPRJ_IO_PADS-1:0] io_out,
output [`MPRJ_IO_PADS-1:0] io_oeb,
);
// pass input and output pins defined in user_defines.v
thorkn_vgaclock_top mod (
io_in[9:8],
io_out[14:10]
);
// all output enabled
assign io_oeb[14:10] = 8'b0;
endmodule
| 6.778253 |
module TitleRom (
input wire [18:0] i_addr,
input wire i_clk2,
output reg [7:0] o_data
);
// (*ROM_STYLE="block"*) reg [7:0] memory_array [0:28854];
// (*ROM_STYLE="block"*) reg [7:0] memory_array [0:436207];
(*ROM_STYLE="block"*) reg [7:0] memory_array[0:111375];
initial begin
$readmemh("namemedium.mem", memory_array);
end
always @(posedge i_clk2) o_data <= memory_array[i_addr];
endmodule
| 6.843604 |
module TitleScene (
input wire [9:0] ix,
input wire [9:0] iy,
input wire iactive,
input wire ibtnC,
input wire iPixCLK,
input wire iCLK,
input wire iPS2Clk,
input wire iPS2Data,
output reg [3:0] oRED,
output reg [3:0] oGREEN,
output reg [3:0] oBLUE,
input wire [3:0] state,
output reg [3:0] nextState
);
wire [15:0] keycode;
wire flag;
KBinput KBinput (
.clk(iCLK),
.kclk(iPS2Clk),
.kdata(iPS2Data),
.dataOut(keycode),
.oflag(flag)
);
// instantiate BeeSprite code
wire TitleSpriteOn; // 1=on, 0=off
wire [7:0] dout; // pixel value from Bee.mem
TitleSprite TitleDisplay (
.xx(ix),
.yy(iy),
.aactive(iactive),
.SpriteOn(TitleSpriteOn),
.dataout(dout),
.Pclk(iPixCLK),
.clk(iCLK)
);
// load colour palette
reg [7:0] palette[0:191]; // 8 bit values from the 192 hex entries in the colour palette
reg [7:0] COL = 0; // background colour palette value
initial begin
$readmemh("palall.mem", palette); // load 192 hex values into "palette"
end
reg de = 0, bde = 0;
reg space = 0, bspace = 0;
always @(posedge iPixCLK) begin
//normal input
if (state == 0) begin
if (ibtnC == 0) bde = 1;
else if (!bde) begin
bspace = 0;
end else if (ibtnC == 1) begin
bspace = 1;
bde = 0;
end
if (keycode[15:8] == 8'hf0) de = 1;
else if (!de) begin
space = 0;
end else if (keycode[7:0] == 8'h29) begin
space = 1;
de = 0;
end
if (space == 1 || bspace) begin
nextState <= 3; //go to menu
end else begin
nextState <= 0;
end
end else begin
de <= 0;
space <= 0;
end
end
always @(posedge iPixCLK && state == 0) begin
if (iactive) begin
if (TitleSpriteOn == 1) begin
oRED <= (palette[(dout*3)]) >> 4; // RED bits(7:4) from colour palette
oGREEN <= (palette[(dout*3)+1]) >> 4; // GREEN bits(7:4) from colour palette
oBLUE <= (palette[(dout*3)+2]) >> 4; // BLUE bits(7:4) from colour palette
end else begin
oRED <= 0; // set RED, GREEN & BLUE
oGREEN <= 0; // to "0" when ix,iy outside of
oBLUE <= 0; // the iactive display area
end
end else begin
oRED <= 0; // set RED, GREEN & BLUE
oGREEN <= 0; // to "0" when ix,iy outside of
oBLUE <= 0; // the iactive display area
end
end
endmodule
| 8.124727 |
module titleScreen (
input clk
, input p_tick
, input [9:0] x
, input [9:0] y
, output reg [7:0] data
);
localparam UnderpugsT = 96;
localparam UnderpugsL = 127;
localparam UnderpugsD = 542;
localparam UnderpugsR = 171;
localparam UnderpugsWidth = 445;
localparam NameT = 126;
localparam NameL = 240;
localparam NameD = 513;
localparam NameR = 349;
localparam NameWidth = 388;
reg [14:0] addr_title;
wire [ 7:0] data_title;
spriteROM #(
.DEPTH(20025),
.DEPTH_BIT(15),
.MEMFILE("underpugs.mem")
) underpug (
.clk (clk),
.addr(addr_title),
.data(data_title)
);
reg [15:0] addr_name;
wire [ 7:0] data_name;
spriteROM #(
.DEPTH(42680),
.DEPTH_BIT(16),
.MEMFILE("name.mem")
) name (
.clk (clk),
.addr(addr_name),
.data(data_name)
);
always @(p_tick) begin
if (x >= UnderpugsT && x <= UnderpugsD && y >= UnderpugsL && y <= UnderpugsR) begin
addr_title = UnderpugsWidth * (y - UnderpugsL) + (x - UnderpugsT);
data = data_title;
end else if (x >= NameT && x <= NameD && y >= NameL && y <= NameR) begin
addr_name = NameWidth * (y - NameL) + (x - NameT);
data = data_name;
end else begin
data = 0;
end
end
endmodule
| 6.697182 |
module TitleSprite (
input wire [9:0] xx, // current x position
input wire [9:0] yy, // current y position
input wire aactive, // high during active pixel drawing
output reg SpriteOn, // 1=on, 0=off
output wire [7:0] dataout, // 8 bit pixel value from Bee.mem
input wire Pclk, // 25MHz pixel clock
input wire clk,
input wire Kclk
);
reg [18:0] address;
TitleRom TitleVRom (
.i_addr(address),
.i_clk2(Pclk),
.o_data(dataout)
);
// setup character positions and sizes
reg [9:0] TitleX = 198; // Bee X start position
reg [8:0] TitleY = 162; // Bee Y start position
localparam TitleWidth = 405; //796;//199; // Bee width in pixels
localparam TitleHeight = 275; //548;//145; // Bee height in pixels
// NokauanRom NokRom (.i_Nokaddr(address),.i_clk2(Pclk),.o_Nokdata(dataout));
// // setup character positions and sizes
// reg [9:0] SpriteX = 312; // Sprite X start position
// reg [8:0] SpriteY = 100; // Sprite Y start position
// localparam SpriteWidth = 176; // Sprite width in pixels
// localparam SpriteHeight = 161; // Sprite height in pixels
always @(posedge Pclk) begin
// EDIT nextState to 3 when Menu is ready
if (aactive) begin // check if xx,yy are within the confines of the Bee character
if (xx == TitleX - 1 && yy == TitleY) begin
address <= 0;
SpriteOn <= 1;
end
if ((xx>TitleX-1) && (xx<TitleX+TitleWidth) && (yy>TitleY-1) && (yy<TitleY+TitleHeight))
begin
address <= address + 1;
SpriteOn <= 1;
end else SpriteOn <= 0;
end
end
endmodule
| 7.754969 |
module title_colorizer #(
parameter MARGIN_X = 256 + 128,
parameter MARGIN_Y = 32,
parameter TITLE_WIDTH = 256, // 2^8
parameter TITLE_HEIGHT = 128, // 2^7
parameter TITLE_ADDR_WIDTH_X = 8,
parameter TITLE_ADDR_WIDTH_Y = 7,
localparam TITLE_ADDR_WIDTH = TITLE_ADDR_WIDTH_X + TITLE_ADDR_WIDTH_Y // computed from the title width and height
) (
input clk, // clock signal
input signed [31:0] pixel_row, // pixel row from the dtg
input signed [31:0] pixel_column, // pixel column from the dtg
output [11:0] title_color // title color at the given pixel coordinates
);
// ==================================================
// DECLARATIONS
// ==================================================
// block RAM
wire [11:0] ram_out;
wire [31:0] read_addr;
// adjusted pixel coordinates, based on the margin
wire signed [31:0] pixel_row_adjusted;
wire signed [31:0] pixel_column_adjusted;
// out-of-title signal
wire out_of_title;
// ==================================================
// INSTANCES
// ==================================================
// store title as block RAM
ram_block #(
.INIT_FILE ("title_04.mem"),
.ADDR_WIDTH(TITLE_ADDR_WIDTH)
) ram_title (
.clk(clk),
.read_addr(read_addr),
.q(ram_out)
);
// ==================================================
// LOGIC
// ==================================================
// determine if the given pixel coordinates out of the title or not
assign out_of_title = !(pixel_row_adjusted >= 0 && pixel_row_adjusted < TITLE_HEIGHT && pixel_column_adjusted >= 0 && pixel_column_adjusted < TITLE_WIDTH);
// adjust pixel coordinates by subtracting the margins
assign pixel_row_adjusted = pixel_row - MARGIN_Y;
assign pixel_column_adjusted = pixel_column - MARGIN_X;
// determine read addres for the RAM, by concatenation pixel coordinates
assign read_addr = {
pixel_row_adjusted[TITLE_ADDR_WIDTH_Y-1:0], pixel_column_adjusted[TITLE_ADDR_WIDTH_X-1:0]
};
// determine title color if NOT out-of-title, 12'h000 otherwise
assign title_color = out_of_title ? 12'h000 : ram_out;
endmodule
| 8.354128 |
module TI_CIC_FILTER_8X2P (
IN1,
IN2,
IN3,
IN4,
CLK_adc1,
CLK_adc1_2,
CLK_adc2,
CLK_adc3,
CLK_adc4,
RES,
ENABLE,
OUT1,
OUT2
);
parameter BW = 6;
input CLK_adc1, CLK_adc1_2, CLK_adc2, CLK_adc3, CLK_adc4, RES, ENABLE;
input signed [BW-1:0] IN1, IN2, IN3, IN4;
output signed [BW+4:0] OUT1, OUT2;
wire signed [BW-1:0] OUT01, OUT02, OUT03, OUT04, OUT05, OUT06, OUT07, OUT08;
wire signed [BW-1:0] IN1_Z, ON1;
DFFR_6B_4 DFF01 (
IN1,
CLK_adc1,
RES,
ENABLE,
IN1_Z,
ON1
);
TI_POLYPHASE_PATH2_kai
POLYPHASE01 (
CLK_adc2,
CLK_adc1_2,
RES,
ENABLE,
IN1_Z,
OUT01,
OUT05
),
POLYPHASE02 (
CLK_adc2,
CLK_adc1_2,
RES,
ENABLE,
IN2,
OUT02,
OUT06
),
POLYPHASE03 (
CLK_adc3,
CLK_adc1_2,
RES,
ENABLE,
IN3,
OUT03,
OUT07
),
POLYPHASE04 (
CLK_adc4,
CLK_adc1_2,
RES,
ENABLE,
IN4,
OUT04,
OUT08
);
TI_POLYPHASE_PATH8X2 POLYPHASE05 (
CLK_adc1_2,
RES,
OUT01,
OUT02,
OUT03,
OUT04,
OUT05,
OUT06,
OUT07,
OUT08,
OUT1,
OUT2
);
endmodule
| 6.540385 |
module TI_Simon_Core (
clk,
data_ina,
data_inb,
data_rdy,
cipher_outa,
cipher_outb,
round_counter,
Done,
Trig
);
//------------------------------------------------ Interfaces
input clk;
input data_ina, data_inb;
input [1:0] data_rdy;
output cipher_outa, cipher_outb;
output reg [6:0] round_counter;
output reg Done, Trig;
//------------------------------------------------
reg [5:0] bit_counter;
reg flag;
wire shifter_enable1, shifter_enable2;
wire lut_ff_enable, fifo_ff_enable;
wire [1:0] s1, s3;
wire s2;
wire keya, keyb;
// bit_counter logic
always @(posedge clk) begin
if (data_rdy == 0) bit_counter <= 0;
else if (flag) bit_counter <= bit_counter + 1;
else bit_counter <= bit_counter;
end
always @(posedge clk) begin
if (data_rdy == 0) flag <= 0;
else if (data_rdy == 3) begin
if (bit_counter == 63) flag <= ~flag;
else flag <= 1;
end else flag <= flag;
end
// round_counter logic
always @(posedge clk) begin
if (data_rdy == 0) round_counter <= 0;
else if (data_rdy == 3 && bit_counter == 63) round_counter <= round_counter + 1;
else round_counter <= round_counter;
end
always @(posedge clk) begin
if (round_counter == 0 && bit_counter == 1) //So it means first 4 rounds
Trig = 1;
else Trig = 0;
if (data_rdy == 3 && round_counter == 67 && bit_counter == 62) Done = 1;
else Done = 0;
end
//------------------------------------------------
/*
data_rdy=0 -> Reset, Idle
data_rdy=1 -> Load Plaintext
data_rdy=2 -> Load Key
data_rdy=3 -> Run (keep at 3 while the block cipher is running)
*/
datapath_simon2share SIMON_DATAPATH (
.clk(clk),
.data_ina(data_ina),
.data_inb(data_inb),
.data_rdy(data_rdy),
.key_ina(keya),
.key_inb(keyb),
.cipher_outa(cipher_outa),
.cipher_outb(cipher_outb),
.round_counter_0(round_counter[0]),
.bit_counter(bit_counter),
.flag(flag)
);
key_schedule_1 SIMON_KEY_EXP_1 (
.clk(clk),
.data_in(data_ina),
.data_rdy(data_rdy),
.key_out(keya),
.bit_counter(bit_counter),
.round_counter(round_counter),
.s2(s2),
.s1(s1),
.s3(s3),
.flag(flag),
.shifter_enable1(shifter_enable1),
.shifter_enable2(shifter_enable2),
.lut_ff_enable(lut_ff_enable),
.fifo_ff_enable(fifo_ff_enable)
);
key_schedule_2 SIMON_KEY_EXP_2 (
.clk(clk),
.data_in(data_inb),
.key_out(keyb),
.bit_counter(bit_counter),
.s2(s2),
.s1(s1),
.s3(s3),
.flag(flag),
.shifter_enable1(shifter_enable1),
.shifter_enable2(shifter_enable2),
.lut_ff_enable(lut_ff_enable),
.fifo_ff_enable(fifo_ff_enable)
);
endmodule
| 7.198812 |
module datapath_simon2share (
clk,
data_ina,
data_inb,
data_rdy,
key_ina,
key_inb,
cipher_outa,
cipher_outb,
round_counter_0,
flag,
bit_counter
);
input clk, data_ina, data_inb;
input key_ina, key_inb;
input [1:0] data_rdy;
input round_counter_0;
input [5:0] bit_counter;
input flag;
output cipher_outa, cipher_outb;
reg s1, s2;
reg [1:0] s3;
wire lut_rol8_shifted_out_a, lut_rol8_shifted_out_b;
reg shifter_enable1, shifter_enable2;
//Selection MUX
always @(*) begin
// For the first 8 bits of each even round OR for all the bits after the first 8 bits in odd rounds OR loading the plaintext
if((round_counter_0==0 && (bit_counter<8 || flag==0))||(round_counter_0==1 && (bit_counter>7 && flag))||(data_rdy==1))
s1 = 1;
else s1 = 0;
if (round_counter_0 == 0) // Even rounds
s2 = 0;
else s2 = 1;
if (data_rdy == 1) // Loading plaintext
s3 = 0;
else if (bit_counter == 63) // Even rounds
s3 = 2;
else begin
if (flag == 0) // Odd rounds
s3 = 1;
else s3 = s3;
end
end
// SHIFTER ENABLES
// Two shift registers are enabled when the plaintext is being loaded (1) or when the block cipher is running (3)
always @(*) begin
if (data_rdy == 1 || (data_rdy == 3 && bit_counter != 63)) begin
shifter_enable1 = 1;
shifter_enable2 = 1;
end else begin
shifter_enable1 = 0;
shifter_enable2 = 0;
end
end
datapath_share dp_a (
clk,
data_ina,
key_ina,
shifter_enable1,
shifter_enable2,
cipher_outa,
lut_rol8_shifted_out_b,
lut_rol8_shifted_out_a,
s1,
s2,
s3
);
datapath_share dp_b (
clk,
data_inb,
key_inb,
shifter_enable1,
shifter_enable2,
cipher_outb,
lut_rol8_shifted_out_a,
lut_rol8_shifted_out_b,
s1,
s2,
s3
);
endmodule
| 7.360755 |
module lut_datapath (
clk,
out,
shift_out2,
key_in,
lut_rol2,
lut_rol1,
lut_rol8,
lut_rol1_shifted,
lut_rol8_ext
);
//------------------------------------------------
input clk, shift_out2, key_in, lut_rol2, lut_rol1, lut_rol8, lut_rol1_shifted, lut_rol8_ext;
output out;
reg intreg;
//------------------------------------------------
//assign lut_outa = shift_out2a ^ key_ina ^ lut_rol2a ^ (lut_rol1a & lut_rol8a) ^ (lut_rol1a & lut_rol8b);
always @(posedge clk) begin
intreg <= shift_out2 ^ lut_rol2 ^ (lut_rol1 & lut_rol8);
end
assign out = key_in ^ (lut_rol1_shifted & lut_rol8_ext) ^ intreg;
endmodule
| 7.909204 |
module key_schedule_2 (
clk,
data_in,
key_out,
bit_counter,
flag,
s2,
s1,
s3,
shifter_enable1,
shifter_enable2,
lut_ff_enable,
fifo_ff_enable
);
//------------------------------------------------
input clk;
input data_in;
//input [1:0] data_rdy;
input [5:0] bit_counter;
input flag;
output key_out;
input s2;
input [1:0] s1, s3;
input shifter_enable1, shifter_enable2;
input lut_ff_enable, fifo_ff_enable;
//------------------------------------------------
reg [59:0] shifter1;
reg [63:0] shifter2;
reg shift_in1, shift_in2;
wire shift_out1, shift_out2;
wire lut_out;
reg lut_in3;
reg c;
reg fifo_ff0, fifo_ff1, fifo_ff2, fifo_ff3;
//(* shreg_extract = "no" *)
reg lut_ff0, lut_ff1, lut_ff2, lut_ff3;
//------------------------------------------------
// Shift Register1 FIFO 60x1 Begin
// 60x1 shift register storing the 60 most significant bits of the upper word of the key
always @(posedge clk) begin
if (shifter_enable1) begin
shifter1 <= {shift_in1, shifter1[59:1]};
end
end
assign shift_out1 = shifter1[0];
// Shift Register1 End
// Shift Register2 FIFO 64x1 Begin
// 64x1 shift register storing the lower word of the key
always @(posedge clk) begin
if (shifter_enable2) begin
shifter2 <= {shift_in2, shifter2[63:1]};
end
end
assign shift_out2 = shifter2[0];
// Shift Register2 End
// 4 flip-flops storing the least significant 4 bits of the upper word in the first round
always @(posedge clk) begin
if (fifo_ff_enable) begin
fifo_ff3 <= shift_out1;
fifo_ff2 <= fifo_ff3;
fifo_ff1 <= fifo_ff2;
fifo_ff0 <= fifo_ff1;
end
end
// 4 flip-flops storing the least significant 4 bits of the upper word after the first round
always @(posedge clk) begin
if (lut_ff_enable) begin
lut_ff3 <= lut_out;
lut_ff2 <= lut_ff3;
lut_ff1 <= lut_ff2;
lut_ff0 <= lut_ff1;
end
end
//FIFO 64x1 Input MUX
always @(*) begin
if (s3 == 1 /*data_rdy==2*/) shift_in2 = fifo_ff0;
else if (s3 == 2 /*data_rdy==3 && (round_counter<1 || bit_counter>3)*/) shift_in2 = fifo_ff0;
else if (s3 == 3 /*data_rdy==3 && bit_counter<4 && round_counter>0*/) shift_in2 = lut_ff0;
else shift_in2 = 1'bx;
end
//LUT >>3 Input MUX
always @(*) begin
if (s2 == 0) lut_in3 = fifo_ff3;
else lut_in3 = lut_ff3;
end
//FIFO 60x1 Input MUX
always @(*) begin
if (s1 == 0) shift_in1 = fifo_ff0;
else if (s1 == 1) shift_in1 = data_in;
else if (s1 == 2) shift_in1 = lut_out;
else if (s1 == 3) shift_in1 = lut_ff0;
else shift_in1 = 1'bx;
end
// The value of c is 1 at the first two cycles of each round only
always @(*) begin
if ((flag && bit_counter == 0) || bit_counter == 1) c = 0;
else c = 1;
end
// New computed key bit
assign lut_out = shift_out2 ^ lut_in3 ^ shift_out1 ^ c;
// Output key bit that is connected to the datapath
assign key_out = shift_out2;
endmodule
| 6.528716 |
module TI_Simon_TopModule (
Din,
Dout,
Drdy,
Dvld,
EN,
BSY,
CLK,
RSTn,
Trig
);
//------------------------------------------------
input [(128*6)-1:0] Din; // Data input
output [127:0] Dout; // Data output
input Drdy; // Data input ready
output Dvld; // Data output valid
input EN; // circuit enable
output BSY; // Busy signal
input CLK; // System clock
input RSTn; // Reset (Low active)
output Trig; // Based on The number of desired rounds can be adjusted
reg Dvld;
wire rst;
wire BSY;
//for simon
reg [127:0] count;
wire [ 6:0] round_counter;
reg [ 1:0] state;
reg [255:0] share_a, share_b, share_c;
wire Done;
reg [127:0] Ser_2_Par;
wire cipher_outa, cipher_outb;
reg [63:0] cout_La, cout_Lb, cout_Ra, cout_Rb;
//------------------------------------------------
assign rst = ~RSTn;
always @(posedge CLK or posedge rst) begin
if (rst) Dvld <= 0;
else if (EN) Dvld <= Done;
end
always @(posedge CLK or posedge rst) begin
if (rst) begin
share_a <= {256{1'h0}};
share_b <= {256{1'h0}};
share_c <= {256{1'h0}};
end else if (EN) begin
if (Drdy) begin
share_a <= Din[767:512];
share_b <= Din[511:256];
share_c <= Din[255:0];
end else begin
share_a <= {1'd0, share_a[255:1]};
share_b <= {1'd0, share_b[255:1]};
share_c <= {1'd0, share_c[255:1]};
end
end
end
always @(posedge CLK or posedge rst) begin
if (rst) state <= 2'b00;
else if (EN) begin
if (Drdy) state <= 2'b10;
else if (count[127] == 1 && state == 2'b10) state <= 2'b01;
else if (count[127] == 1 && state == 2'b01) state <= 2'b11;
if (Done) state <= 2'b00;
end
end
always @(posedge CLK or posedge rst) begin
if (rst) count = 128'b0;
else if (EN) begin
if (Drdy) count = 1;
else count = {count[126:0], count[127]};
if (state == 3) count = 0;
if (Done) count = 0;
end
end
always @(posedge CLK) begin
if (round_counter == 66) begin
cout_Ra <= {cipher_outa, cout_Ra[63:1]};
cout_Rb <= {cipher_outb, cout_Rb[63:1]};
end else if (round_counter == 67) begin
cout_La <= {cipher_outa, cout_La[63:1]};
cout_Lb <= {cipher_outb, cout_Lb[63:1]};
end else begin
cout_Ra <= 0;
cout_Rb <= 0;
cout_La <= 0;
cout_Lb <= 0;
end
end
always @(posedge CLK) begin
if (Dvld) begin
Ser_2_Par <= {cout_La, cout_Ra} ^ {cout_Lb, cout_Rb};
end
end
assign Dout = Ser_2_Par;
assign BSY = &state;
TI_Simon_Core my_simon_core (
.clk(CLK),
.data_rdy(state),
.data_ina(share_a[0]),
.data_inb(share_b[0] ^ share_c[0]),
.cipher_outa(cipher_outa),
.cipher_outb(cipher_outb),
.round_counter(round_counter),
.Done(Done),
.Trig(Trig)
);
endmodule
| 7.933467 |
module: sasebo_simon
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TI_Simon_TopModule_tb;
// Inputs
reg [767:0] Din;
reg Drdy;
reg EN;
reg CLK;
reg RSTn;
// Outputs
wire [127:0] Dout;
wire Dvld;
wire BSY;
wire Trig;
// Instantiate the Unit Under Test (UUT)
TI_Simon_TopModule uut (
.Din(Din),
.Dout(Dout),
.Drdy(Drdy),
.Dvld(Dvld),
.EN(EN),
.BSY(BSY),
.CLK(CLK),
.RSTn(RSTn),
.Trig(Trig)
);
always #5 CLK = ~CLK;
initial begin
// Initialize Inputs
Din = 0;
Drdy = 0;
EN = 0;
CLK = 0;
RSTn = 1;
// Wait 100 ns for global reset to finish
#20;
RSTn = 0;
#40;
RSTn = 1;
EN = 1;
#20;
Din = 768'h63736564207372656c6c6576617211110f0e0d0c0b0a0908070605040302010063736564207372656c6c6576617211110f0e0d0c0b0a0908070605040302010063736564207372656c6c6576617274200f0e0d0c0b0a09080706050403020100;
#10;
Drdy = 1;
#10;
Drdy = 0;
// Add stimulus here
end
endmodule
| 6.844882 |
module tkeep_m3_for_arty_a7_axis_subset_converter_0_1 #(
parameter C_S_AXIS_TDATA_WIDTH = 32,
parameter C_S_AXIS_TUSER_WIDTH = 0,
parameter C_S_AXIS_TID_WIDTH = 0,
parameter C_S_AXIS_TDEST_WIDTH = 0,
parameter C_M_AXIS_TDATA_WIDTH = 32
) (
input [(C_S_AXIS_TDATA_WIDTH == 0 ? 1 : C_S_AXIS_TDATA_WIDTH)-1:0] tdata,
input [(C_S_AXIS_TUSER_WIDTH == 0 ? 1 : C_S_AXIS_TUSER_WIDTH)-1:0] tuser,
input [ (C_S_AXIS_TID_WIDTH == 0 ? 1 : C_S_AXIS_TID_WIDTH)-1:0] tid,
input [(C_S_AXIS_TDEST_WIDTH == 0 ? 1 : C_S_AXIS_TDEST_WIDTH)-1:0] tdest,
input [ (C_S_AXIS_TDATA_WIDTH/8)-1:0] tkeep,
input [ (C_S_AXIS_TDATA_WIDTH/8)-1:0] tstrb,
input tlast,
output [ (C_M_AXIS_TDATA_WIDTH/8)-1:0] tkeep_out
);
assign tkeep_out = {tkeep[2:0]};
endmodule
| 6.853224 |
module tkeep_m3_for_arty_a7_axis_subset_converter_0_2 #(
parameter C_S_AXIS_TDATA_WIDTH = 32,
parameter C_S_AXIS_TUSER_WIDTH = 0,
parameter C_S_AXIS_TID_WIDTH = 0,
parameter C_S_AXIS_TDEST_WIDTH = 0,
parameter C_M_AXIS_TDATA_WIDTH = 32
) (
input [(C_S_AXIS_TDATA_WIDTH == 0 ? 1 : C_S_AXIS_TDATA_WIDTH)-1:0] tdata,
input [(C_S_AXIS_TUSER_WIDTH == 0 ? 1 : C_S_AXIS_TUSER_WIDTH)-1:0] tuser,
input [ (C_S_AXIS_TID_WIDTH == 0 ? 1 : C_S_AXIS_TID_WIDTH)-1:0] tid,
input [(C_S_AXIS_TDEST_WIDTH == 0 ? 1 : C_S_AXIS_TDEST_WIDTH)-1:0] tdest,
input [ (C_S_AXIS_TDATA_WIDTH/8)-1:0] tkeep,
input [ (C_S_AXIS_TDATA_WIDTH/8)-1:0] tstrb,
input tlast,
output [ (C_M_AXIS_TDATA_WIDTH/8)-1:0] tkeep_out
);
assign tkeep_out = {2'b11, tkeep[0:0]};
endmodule
| 6.853224 |
module to convert TKEEP encoding to a byte count. Note that the
output of this module is computed as (popcount(TKEEP) - 1). This takes
advantage of the fact that we disallow a TKEEP of 0 in order to reduce the
number of necessary bits.
This code assumes that there are no gaps between asserted TKEEP bits, and
that the TKEEP signal is "big-endian". In other words,
TKEEP value Comments
11011000 Invalid; gaps not allowed
11111000 Valid
00011111 Invalid; TKEEP is not left-aligned
00110011 Invalid; gaps and not left-aligned
*/
`include "macros.vh"
`define MAX(x,y) (((x)>(y))?(x):(y))
module tkeep_to_len # (
parameter TKEEP_WIDTH = 8
) (
input wire [TKEEP_WIDTH - 1:0] tkeep,
output wire [`MAX($clog2(TKEEP_WIDTH),1) -1:0] len
);
//Special cases for small TKEEP_WIDTH
`genif (TKEEP_WIDTH == 1) begin
assign len = 0;
`else_genif( TKEEP_WIDTH == 2) begin
assign len = tkeep[0];
`else_gen
//This Verilog code is essentially a generic binary encoder
localparam NUM_LEVELS = $clog2(TKEEP_WIDTH);
//Pad TKEEP on the right with zeroes
wire [2**NUM_LEVELS -1:0] tkeep_padded;
localparam PAD_WIDTH = 2**NUM_LEVELS - TKEEP_WIDTH;
if (PAD_WIDTH > 0) begin
assign tkeep_padded = {tkeep, {PAD_WIDTH{1'b0}}};
end else begin
assign tkeep_padded = tkeep;
end
//Wire which stores the one-hot encoding of where the last TKEEP bit
//is situated. This is "right-aligned".
wire [2**NUM_LEVELS -1 -1:0] one_hot;
//Use XORs between adjacent bits to find last set bit
assign one_hot[0] = tkeep_padded[0];
genvar i;
for (i = 1; i < 2**NUM_LEVELS - 1; i = i + 1) begin
assign one_hot[i] = tkeep_padded[i] ^ tkeep_padded[i - 1];
end
//Subsets of bits which have a '0' in a particular position of their
//index. Specifically, subsets[i] is the concatenation of
//
// {one_hot[j] | the (NUM_LEVELS)-bit binary representation of j has a
// zero in bit i}
//
//(hopefully that's clear)
wire [2**(NUM_LEVELS-1) -1:0]subsets[NUM_LEVELS -1:0];
genvar level;
for (level = 0; level < NUM_LEVELS; level = level + 1) begin
//The idea is we will now sweep out the set of indices that have a
//one in bit LEVEL of their index.
for (i = 0; i < 2**(NUM_LEVELS - 1); i = i + 1) begin
wire [NUM_LEVELS - 1 -1:0] other_bits = i;
`define left_bits ((NUM_LEVELS -1) - level)
`define right_bits (level)
wire [NUM_LEVELS -1:0] idx;
if (`right_bits > 0) begin
if (`left_bits > 0) begin
assign idx = {
other_bits[NUM_LEVELS -1 -1 -: `left_bits],
1'b0,
other_bits[`right_bits -1 -: `right_bits]
};
end else begin
assign idx = {
1'b0,
other_bits[`right_bits -1 -: `right_bits]
};
end
end else begin
//Assume it's impossible for both to be zero
assign idx = {
other_bits[NUM_LEVELS -1 -1 -: `left_bits],
1'b0
};
end
`undef left_bits
`undef right_bits
assign subsets[level][i] = one_hot[idx];
end
end
//Finally, take the OR-reduction of the subsets to get the length value
for (i = 0; i < NUM_LEVELS; i = i + 1) begin
assign len[i] = |subsets[i];
end
`endgen
endmodule
| 7.016687 |
module tkeep_to_len_tb #(
parameter TKEEP_WIDTH = 8
);
reg clk = 0;
always #5 clk <= ~clk;
reg [TKEEP_WIDTH -1:0] tkeep = 0;
wire [$clog2(TKEEP_WIDTH) -1:0] len;
initial begin
$dumpfile("tkeep_to_len.vcd");
$dumpvars;
$dumplimit(512000);
#1000 $finish;
end
integer i;
reg [$clog2(TKEEP_WIDTH):0] expected_len = 0;
always @(posedge clk) begin
expected_len = expected_len + 1;
if (expected_len > TKEEP_WIDTH) expected_len = 0;
for (i = 0; i < TKEEP_WIDTH; i = i + 1) begin
tkeep[TKEEP_WIDTH-1-i] <= (i <= expected_len) ? 1'b1 : 1'b0;
end
end
tkeep_to_len #(
.TKEEP_WIDTH(TKEEP_WIDTH)
) DUT (
.tkeep(tkeep),
.len(len)
);
endmodule
| 7.110141 |
module tl (
input rst_n,
input clk,
input pass_request,
output wire [7:0] clock,
output reg red,
output reg yellow,
output reg green
);
parameter A = 0;
parameter B = 1;
parameter C = 2;
reg [1:0] state;
reg [1:0] nstate;
reg [7:0] cnt = 0;
always @(posedge clk, negedge rst_n) begin
if (!rst_n) begin
state <= A;
nstate <= A;
end else state <= nstate;
end
always @(*) begin
case (state)
A: begin
if (cnt == 60) begin
nstate <= B;
end else nstate <= A;
end
B: begin
if (cnt == 5) begin
nstate <= C;
end else nstate <= B;
end
C: begin
if (cnt == 10) begin
nstate <= A;
end else nstate <= C;
end
endcase
end
always @(posedge clk, negedge rst_n, posedge pass_request) begin
if (pass_request) begin
if (state == A) begin
if (cnt <= 50) begin
cnt <= 50;
end
end
end else if (!rst_n) cnt <= 0;
else begin
if (state == A) begin
if (cnt == 60) cnt <= 0;
else cnt <= cnt + 1;
end else if (state == B) begin
if (cnt == 5) cnt <= 0;
else cnt <= cnt + 1;
end else if (state == C) begin
if (cnt == 10) cnt <= 0;
else cnt <= cnt + 1;
end
end
end
assign clock = cnt;
always @(*) begin
if (state == A) begin
green = 1;
yellow = 0;
red = 0;
end else if (state == B) begin
green = 0;
yellow = 1;
red = 0;
end else if (state == C) begin
green = 0;
yellow = 0;
red = 1;
end
end
endmodule
| 7.379785 |
module TL16_6_4 (
input [15:0] x,
input [15:0] y,
output [31:0] p
);
// First complement
wire [15:0] x_abs;
assign x_abs = x ^ {16{x[15]}};
// is upper n-Q bits zero
wire not_zeroUpX;
assign not_zeroUpX = |(x_abs[15:6]);
wire [9:0] x_up;
assign x_up = {x_abs[14:6], 1'b1};
wire [9:0] xTMP;
assign xTMP = not_zeroUpX ? x_up : x_abs[9:0];
// First complement
wire [15:0] y_abs;
assign y_abs = y ^ {16{y[15]}};
// is upper n-Q bits zero
wire not_zeroUpY;
assign not_zeroUpY = |(y_abs[15:6]);
wire [9:0] y_up;
assign y_up = {y_abs[14:6], 1'b1};
wire [9:0] yTMP;
assign yTMP = not_zeroUpY ? y_up : y_abs[9:0];
wire [19:0] pTMP;
wire zeroTMP;
ADAPT_10bit Nested (
xTMP,
yTMP,
zeroTMP,
pTMP
);
wire [1:0] ctrl_sig;
assign ctrl_sig[1] = not_zeroUpX & not_zeroUpY;
assign ctrl_sig[0] = not_zeroUpX ^ not_zeroUpY;
wire [31:0] p_abs;
fixedShift FinalShift (
pTMP,
ctrl_sig,
p_abs
);
wire [31:0] p_tmp;
wire p_sgn;
assign p_sgn = x[15] ^ y[15];
assign p_tmp = {32{p_sgn}} ^ p_abs;
assign p = zeroTMP ? 32'b0 : p_tmp;
endmodule
| 7.086155 |
module fixedShift (
input [19:0] data_i,
input [1:0] shift_i,
output reg [31:0] data_o
);
always @*
case (shift_i)
2'b01: data_o = data_i << 5;
2'b10: data_o = data_i << 10;
default: data_o = data_i;
endcase
endmodule
| 6.581126 |
module ADAPT_10bit (
input [9:0] x,
input [9:0] y,
output zeroTMP,
output [19:0] p
);
// First complement
wire [9:0] x_abs;
assign x_abs = x;
// LOD + Priority Encoder
wire [9:0] k_x0;
wire zero_x0, one_x0;
wire [3:0] k_x0_enc;
LOD10 lod_x0 (
.data_i (x_abs),
.zero_o (zero_x0),
.data_o (k_x0),
.data_enc(k_x0_enc)
);
// LBarrel
wire [3:0] x_shift;
LBarrel Lshift_x0 (
.data_i (x_abs),
.shift_i(k_x0),
.data_o (x_shift)
);
// First complement
wire [9:0] y_abs;
assign y_abs = y;
// LOD + Priority Encoder
wire [9:0] k_y0;
wire zero_y0, one_y0;
wire [3:0] k_y0_enc;
LOD10 lod_y0 (
.data_i (y_abs),
.zero_o (zero_y0),
.data_o (k_y0),
.data_enc(k_y0_enc)
);
// LBarrel
wire [3:0] y_shift;
LBarrel Lshift_y0 (
.data_i (y_abs),
.shift_i(k_y0),
.data_o (y_shift)
);
// Addition
wire [8:0] x_log;
wire [8:0] y_log;
wire [8:0] p_log;
assign x_log = {1'b0, k_x0_enc, x_shift};
assign y_log = {1'b0, k_y0_enc, y_shift};
assign p_log = x_log + y_log;
//
// Antilogarithm stage
wire [19:0] PP_abs; //2*(n-q)
wire [4:0] l1_input;
wire p_sign;
wire [19:0] PP_tmp;
assign l1_input = {1'b1, p_log[3:0]};
L1Barrel L1shift_plog (
.data_i (l1_input),
.shift_i(p_log[8:4]),
.data_o (p)
);
assign zeroTMP = (zero_x0 | zero_y0);
endmodule
| 6.67581 |
module LOD3 (
input [2:0] data_i,
output [2:0] data_o
);
//gates and IO assignments:
assign data_o[2] = data_i[2];
assign data_o[1] = (~data_i[2] & data_i[1]);
assign data_o[0] = (~data_i[2] & ~data_i[1] & data_i[0]);
endmodule
| 7.557238 |
module Muxes2in1Array4 (
input [3:0] data_i,
input select_i,
output [3:0] data_o
);
assign data_o[3] = select_i ? data_i[3] : 1'b0;
assign data_o[2] = select_i ? data_i[2] : 1'b0;
assign data_o[1] = select_i ? data_i[1] : 1'b0;
assign data_o[0] = select_i ? data_i[0] : 1'b0;
endmodule
| 7.798153 |
module LBarrel (
input [9:0] data_i,
input [9:0] shift_i,
output [3:0] data_o
);
assign data_o[3] = |(data_i[8:0] & shift_i[9:1]);
assign data_o[2] = |(data_i[7:0] & shift_i[9:2]);
assign data_o[1] = |(data_i[6:0] & shift_i[9:3]);
assign data_o[0] = 1'b1;
endmodule
| 6.741724 |
module L1Barrel (
input [ 4:0] data_i,
input [ 4:0] shift_i,
output [19:0] data_o
);
reg [23:0] tmp; //2n+w-2q
always @*
case (shift_i)
5'b00000: tmp = data_i;
5'b00001: tmp = data_i << 1;
5'b00010: tmp = data_i << 2;
5'b00011: tmp = data_i << 3;
5'b00100: tmp = data_i << 4;
5'b00101: tmp = data_i << 5;
5'b00110: tmp = data_i << 6;
5'b00111: tmp = data_i << 7;
5'b01000: tmp = data_i << 8;
5'b01001: tmp = data_i << 9;
5'b01010: tmp = data_i << 10;
5'b01011: tmp = data_i << 11;
5'b01100: tmp = data_i << 12;
5'b01101: tmp = data_i << 13;
5'b01110: tmp = data_i << 14;
5'b01111: tmp = data_i << 15;
5'b10000: tmp = data_i << 16;
5'b10001: tmp = data_i << 17;
5'b10010: tmp = data_i << 18;
default: tmp = data_i << 19;
endcase
assign data_o = tmp[23:4];
endmodule
| 6.641517 |
module TL16_7_4 (
input [15:0] x,
input [15:0] y,
output [31:0] p
);
// First complement
wire [15:0] x_abs;
assign x_abs = x ^ {16{x[15]}};
// is upper n-Q bits zero
wire not_zeroUpX;
assign not_zeroUpX = |(x_abs[15:7]);
wire [8:0] x_up;
assign x_up = {x_abs[14:7], 1'b1};
wire [8:0] xTMP;
assign xTMP = not_zeroUpX ? x_up : x_abs[8:0];
// First complement
wire [15:0] y_abs;
assign y_abs = y ^ {16{y[15]}};
// is upper n-Q bits zero
wire not_zeroUpY;
assign not_zeroUpY = |(y_abs[15:7]);
wire [8:0] y_up;
assign y_up = {y_abs[14:7], 1'b1};
wire [8:0] yTMP;
assign yTMP = not_zeroUpY ? y_up : y_abs[8:0];
wire [17:0] pTMP;
wire zeroTMP;
ADAPT_9bit Nested (
xTMP,
yTMP,
zeroTMP,
pTMP
);
wire [1:0] ctrl_sig;
assign ctrl_sig[1] = not_zeroUpX & not_zeroUpY;
assign ctrl_sig[0] = not_zeroUpX ^ not_zeroUpY;
wire [31:0] p_abs;
fixedShift FinalShift (
pTMP,
ctrl_sig,
p_abs
);
wire [31:0] p_tmp;
wire p_sgn;
assign p_sgn = x[15] ^ y[15];
assign p_tmp = {32{p_sgn}} ^ p_abs;
assign p = zeroTMP ? 32'b0 : p_tmp;
endmodule
| 7.009518 |
module fixedShift (
input [17:0] data_i,
input [1:0] shift_i,
output reg [31:0] data_o
);
always @*
case (shift_i)
2'b01: data_o = data_i << 6;
2'b10: data_o = data_i << 12;
default: data_o = data_i;
endcase
endmodule
| 6.581126 |
module ADAPT_9bit (
input [8:0] x,
input [8:0] y,
output zeroTMP,
output [17:0] p
);
// First complement
wire [8:0] x_abs;
assign x_abs = x;
// LOD + Priority Encoder
wire [8:0] k_x0;
wire zero_x0, one_x0;
wire [3:0] k_x0_enc;
LOD9 lod_x0 (
.data_i (x_abs),
.zero_o (zero_x0),
.data_o (k_x0),
.data_enc(k_x0_enc)
);
// LBarrel
wire [3:0] x_shift;
LBarrel Lshift_x0 (
.data_i (x_abs),
.shift_i(k_x0),
.data_o (x_shift)
);
// First complement
wire [8:0] y_abs;
assign y_abs = y;
// LOD + Priority Encoder
wire [8:0] k_y0;
wire zero_y0, one_y0;
wire [3:0] k_y0_enc;
LOD9 lod_y0 (
.data_i (y_abs),
.zero_o (zero_y0),
.data_o (k_y0),
.data_enc(k_y0_enc)
);
// LBarrel
wire [3:0] y_shift;
LBarrel Lshift_y0 (
.data_i (y_abs),
.shift_i(k_y0),
.data_o (y_shift)
);
// Addition
wire [8:0] x_log;
wire [8:0] y_log;
wire [8:0] p_log;
assign x_log = {1'b0, k_x0_enc, x_shift};
assign y_log = {1'b0, k_y0_enc, y_shift};
assign p_log = x_log + y_log;
//
// Antilogarithm stage
wire [17:0] PP_abs; //2*(n-q)
wire [4:0] l1_input;
wire p_sign;
wire [17:0] PP_tmp;
assign l1_input = {1'b1, p_log[3:0]};
L1Barrel L1shift_plog (
.data_i (l1_input),
.shift_i(p_log[8:4]),
.data_o (p)
);
assign zeroTMP = (zero_x0 | zero_y0);
endmodule
| 7.260467 |
module LOD9 (
input [8:0] data_i,
output zero_o,
output [8:0] data_o,
output [3:0] data_enc
);
wire [8:0] z;
wire [2:0] zdet;
wire [2:0] select;
wire zero_h;
wire zero_l;
//*****************************************
// Zero and one detection logic:
//*****************************************
assign zdet[2] = data_i[8];
assign zdet[1] = |(data_i[7:4]);
assign zdet[0] = |(data_i[3:0]);
assign zero_o = ~(zdet[2] | zdet[1] | zdet[0]);
//*****************************************
// LODs:
//*****************************************
LOD4 lod4_2 (
.data_i(data_i[7:4]),
.data_o(z[7:4])
);
LOD4 lod4_1 (
.data_i(data_i[3:0]),
.data_o(z[3:0])
);
assign z[8] = zdet[2];
//*****************************************
// Select signals
//*****************************************
LOD3 Middle (
.data_i(zdet),
.data_o(select)
);
//*****************************************
// Multiplexers :
//*****************************************
wire [8:0] tmp_out;
assign tmp_out[8] = z[8];
assign select[2] = zdet[2];
Muxes2in1Array4 Inst_MUX214_3 (
.data_i (z[7:4]),
.select_i(select[1]),
.data_o (tmp_out[7:4])
);
Muxes2in1Array4 Inst_MUX214_2 (
.data_i (z[3:0]),
.select_i(select[0]),
.data_o (tmp_out[3:0])
);
// Enconding
wire [2:0] low_enc;
assign low_enc = tmp_out[3:1] | tmp_out[7:5];
assign data_enc[3] = select[2];
assign data_enc[2] = select[1];
assign data_enc[1] = low_enc[2] | low_enc[1];
assign data_enc[0] = low_enc[2] | low_enc[0];
// One hot
assign data_o = tmp_out;
endmodule
| 6.798652 |
module LOD3 (
input [2:0] data_i,
output [2:0] data_o
);
//gates and IO assignments:
assign data_o[2] = data_i[2];
assign data_o[1] = (~data_i[2] & data_i[1]);
assign data_o[0] = (~data_i[2] & ~data_i[1] & data_i[0]);
endmodule
| 7.557238 |
module Muxes2in1Array4 (
input [3:0] data_i,
input select_i,
output [3:0] data_o
);
assign data_o[3] = select_i ? data_i[3] : 1'b0;
assign data_o[2] = select_i ? data_i[2] : 1'b0;
assign data_o[1] = select_i ? data_i[1] : 1'b0;
assign data_o[0] = select_i ? data_i[0] : 1'b0;
endmodule
| 7.798153 |
module LBarrel (
input [8:0] data_i,
input [8:0] shift_i,
output [3:0] data_o
);
assign data_o[3] = |(data_i[7:0] & shift_i[8:1]);
assign data_o[2] = |(data_i[6:0] & shift_i[8:2]);
assign data_o[1] = |(data_i[5:0] & shift_i[8:3]);
assign data_o[0] = 1'b1;
endmodule
| 6.741724 |
module L1Barrel (
input [ 4:0] data_i,
input [ 4:0] shift_i,
output [17:0] data_o
);
reg [21:0] tmp; //2n+w-2q
always @*
case (shift_i)
5'b00000: tmp = data_i;
5'b00001: tmp = data_i << 1;
5'b00010: tmp = data_i << 2;
5'b00011: tmp = data_i << 3;
5'b00100: tmp = data_i << 4;
5'b00101: tmp = data_i << 5;
5'b00110: tmp = data_i << 6;
5'b00111: tmp = data_i << 7;
5'b01000: tmp = data_i << 8;
5'b01001: tmp = data_i << 9;
5'b01010: tmp = data_i << 10;
5'b01011: tmp = data_i << 11;
5'b01100: tmp = data_i << 12;
5'b01101: tmp = data_i << 13;
5'b01110: tmp = data_i << 14;
5'b01111: tmp = data_i << 15;
5'b10000: tmp = data_i << 16;
default: tmp = data_i << 17;
endcase
assign data_o = tmp[21:4];
endmodule
| 6.641517 |
module TL16_8_4 (
input [15:0] x,
input [15:0] y,
output [31:0] p
);
// First complement
wire [15:0] x_abs;
assign x_abs = x ^ {16{x[15]}};
// is upper n-Q bits zero
wire not_zeroUpX;
assign not_zeroUpX = |(x_abs[15:8]);
wire [7:0] x_up;
assign x_up = {x_abs[14:8], 1'b1};
wire [7:0] xTMP;
assign xTMP = not_zeroUpX ? x_up : x_abs[7:0];
// First complement
wire [15:0] y_abs;
assign y_abs = y ^ {16{y[15]}};
// is upper n-Q bits zero
wire not_zeroUpY;
assign not_zeroUpY = |(y_abs[15:8]);
wire [7:0] y_up;
assign y_up = {y_abs[14:8], 1'b1};
wire [7:0] yTMP;
assign yTMP = not_zeroUpY ? y_up : y_abs[7:0];
wire [15:0] pTMP;
wire zeroTMP;
ADAPT_8bit Nested (
xTMP,
yTMP,
zeroTMP,
pTMP
);
wire [1:0] ctrl_sig;
assign ctrl_sig[1] = not_zeroUpX & not_zeroUpY;
assign ctrl_sig[0] = not_zeroUpX ^ not_zeroUpY;
wire [31:0] p_abs;
fixedShift FinalShift (
pTMP,
ctrl_sig,
p_abs
);
wire [31:0] p_tmp;
wire p_sgn;
assign p_sgn = x[15] ^ y[15];
assign p_tmp = {32{p_sgn}} ^ p_abs;
assign p = zeroTMP ? 32'b0 : p_tmp;
endmodule
| 7.123827 |
module fixedShift (
input [15:0] data_i,
input [1:0] shift_i,
output reg [31:0] data_o
);
always @*
case (shift_i)
2'b01: data_o = data_i << 7;
2'b10: data_o = data_i << 14;
default: data_o = data_i;
endcase
endmodule
| 6.581126 |
module ADAPT_8bit (
input [7:0] x,
input [7:0] y,
output zeroTMP,
output [15:0] p
);
// First complement
wire [7:0] x_abs;
assign x_abs = x;
// LOD + Priority Encoder
wire [7:0] k_x0;
wire zero_x0, one_x0;
wire [3:0] k_x0_enc;
LOD8 lod_x0 (
.data_i (x_abs),
.zero_o (zero_x0),
.data_o (k_x0),
.data_enc(k_x0_enc)
);
// LBarrel
wire [3:0] x_shift;
LBarrel Lshift_x0 (
.data_i (x_abs),
.shift_i(k_x0),
.data_o (x_shift)
);
// First complement
wire [7:0] y_abs;
assign y_abs = y;
// LOD + Priority Encoder
wire [7:0] k_y0;
wire zero_y0, one_y0;
wire [3:0] k_y0_enc;
LOD8 lod_y0 (
.data_i (y_abs),
.zero_o (zero_y0),
.data_o (k_y0),
.data_enc(k_y0_enc)
);
// LBarrel
wire [3:0] y_shift;
LBarrel Lshift_y0 (
.data_i (y_abs),
.shift_i(k_y0),
.data_o (y_shift)
);
// Addition
wire [8:0] x_log;
wire [8:0] y_log;
wire [8:0] p_log;
assign x_log = {1'b0, k_x0_enc, x_shift};
assign y_log = {1'b0, k_y0_enc, y_shift};
assign p_log = x_log + y_log;
//
// Antilogarithm stage
wire [15:0] PP_abs; //2*(n-q)
wire [5:0] l1_input;
wire p_sign;
wire [15:0] PP_tmp;
assign l1_input = {1'b1, p_log[3:0]};
L1Barrel L1shift_plog (
.data_i (l1_input),
.shift_i(p_log[8:4]),
.data_o (p)
);
assign zeroTMP = (zero_x0 | zero_y0);
endmodule
| 7.369749 |
module LOD8 (
input [7:0] data_i,
output zero_o,
output [7:0] data_o,
output [3:0] data_enc
);
wire [8:0] z;
wire [2:0] zdet;
wire [2:0] select;
wire zero_h;
wire zero_l;
//*****************************************
// Zero and one detection logic:
//*****************************************
assign zdet[2] = 1'b0;
assign zdet[1] = |(data_i[7:4]);
assign zdet[0] = |(data_i[3:0]);
assign zero_o = ~(zdet[2] | zdet[1] | zdet[0]);
//*****************************************
// LODs:
//*****************************************
LOD4 lod4_2 (
.data_i(data_i[7:4]),
.data_o(z[7:4])
);
LOD4 lod4_1 (
.data_i(data_i[3:0]),
.data_o(z[3:0])
);
assign z[8] = zdet[2];
//*****************************************
// Select signals
//*****************************************
LOD3 Middle (
.data_i(zdet),
.data_o(select)
);
//*****************************************
// Multiplexers :
//*****************************************
wire [8:0] tmp_out;
assign tmp_out[8] = z[8];
assign select[2] = zdet[2];
Muxes2in1Array4 Inst_MUX214_3 (
.data_i (z[7:4]),
.select_i(select[1]),
.data_o (tmp_out[7:4])
);
Muxes2in1Array4 Inst_MUX214_2 (
.data_i (z[3:0]),
.select_i(select[0]),
.data_o (tmp_out[3:0])
);
// Enconding
wire [2:0] low_enc;
assign low_enc = tmp_out[3:1] | tmp_out[7:5];
assign data_enc[3] = select[2];
assign data_enc[2] = select[1];
assign data_enc[1] = low_enc[2] | low_enc[1];
assign data_enc[0] = low_enc[2] | low_enc[0];
// One hot
assign data_o = tmp_out;
endmodule
| 6.992495 |
module LOD3 (
input [2:0] data_i,
output [2:0] data_o
);
//gates and IO assignments:
assign data_o[2] = data_i[2];
assign data_o[1] = (~data_i[2] & data_i[1]);
assign data_o[0] = (~data_i[2] & ~data_i[1] & data_i[0]);
endmodule
| 7.557238 |
module Muxes2in1Array4 (
input [3:0] data_i,
input select_i,
output [3:0] data_o
);
assign data_o[3] = select_i ? data_i[3] : 1'b0;
assign data_o[2] = select_i ? data_i[2] : 1'b0;
assign data_o[1] = select_i ? data_i[1] : 1'b0;
assign data_o[0] = select_i ? data_i[0] : 1'b0;
endmodule
| 7.798153 |
module LBarrel (
input [7:0] data_i,
input [7:0] shift_i,
output [3:0] data_o
);
assign data_o[3] = |(data_i[6:0] & shift_i[7:1]);
assign data_o[2] = |(data_i[5:0] & shift_i[7:2]);
assign data_o[1] = |(data_i[4:0] & shift_i[7:3]);
assign data_o[0] = 1'b1;
endmodule
| 6.741724 |
module L1Barrel (
input [ 5:0] data_i,
input [ 4:0] shift_i,
output [15:0] data_o
);
reg [19:0] tmp; //2n+w-2q
always @*
case (shift_i)
5'b00000: tmp = data_i;
5'b00001: tmp = data_i << 1;
5'b00010: tmp = data_i << 2;
5'b00011: tmp = data_i << 3;
5'b00100: tmp = data_i << 4;
5'b00101: tmp = data_i << 5;
5'b00110: tmp = data_i << 6;
5'b00111: tmp = data_i << 7;
5'b01000: tmp = data_i << 8;
5'b01001: tmp = data_i << 9;
5'b01010: tmp = data_i << 10;
5'b01011: tmp = data_i << 11;
5'b01100: tmp = data_i << 12;
5'b01101: tmp = data_i << 13;
5'b01110: tmp = data_i << 14;
default: tmp = data_i << 15;
endcase
assign data_o = tmp[19:4];
endmodule
| 6.641517 |
module tlast_gen #(
parameter TDATA_WIDTH = 8,
parameter MAX_PKT_LENGTH = 256
) (
// Clocks and resets
input aclk,
input resetn,
// Control signals
input [$clog2(MAX_PKT_LENGTH):0] pkt_length,
// Slave interface
input s_axis_tvalid,
output s_axis_tready,
input [TDATA_WIDTH-1:0] s_axis_tdata,
// Master interface
output m_axis_tvalid,
input m_axis_tready,
output m_axis_tlast,
output [ TDATA_WIDTH-1:0] m_axis_tdata,
output [$clog2(MAX_PKT_LENGTH):0] o_cnt
);
// Internal signals
wire new_sample;
reg [$clog2(MAX_PKT_LENGTH):0] cnt;
initial begin
cnt = 0;
end
// Pass through control signals
assign s_axis_tready = m_axis_tready;
assign m_axis_tvalid = s_axis_tvalid;
assign m_axis_tdata = s_axis_tdata;
// Count samples
assign new_sample = s_axis_tvalid & s_axis_tready;
always @(posedge aclk) begin
if (~resetn) cnt <= 0;
else begin
if (new_sample) begin
if (m_axis_tlast) begin
cnt <= 1'b1;
end else begin
cnt <= cnt + 1'b1;
end
end
end
end
// Generate tlast
assign m_axis_tlast = (cnt == pkt_length) & new_sample;
assign o_cnt = cnt;
endmodule
| 8.70195 |
module tlast_gen_NONFUNCTIONAL #(
parameter TDATA_WIDTH = 8,
parameter MAX_PKT_LENGTH = 256
) (
// Clocks and resets
input aclk,
input resetn,
// Control signals
input [$clog2(MAX_PKT_LENGTH):0] pkt_length,
// Slave interface
input s_axis_tvalid,
output s_axis_tready,
input [TDATA_WIDTH-1:0] s_axis_tdata,
// Master interface
output m_axis_tvalid,
input m_axis_tready,
output m_axis_tlast,
output [ TDATA_WIDTH-1:0] m_axis_tdata,
output [$clog2(MAX_PKT_LENGTH):0] o_cnt
);
// Internal signals
wire new_sample;
reg [$clog2(MAX_PKT_LENGTH):0] cnt = 0;
// Pass through control signals
assign s_axis_tready = m_axis_tready;
assign m_axis_tvalid = s_axis_tvalid;
assign m_axis_tdata = s_axis_tdata;
// Count samples
assign new_sample = s_axis_tvalid & s_axis_tready;
always @(posedge aclk) begin
if (~resetn | (m_axis_tlast & new_sample)) cnt <= 0;
else if (new_sample) cnt <= cnt + 1'b1;
end
// Generate tlast
assign m_axis_tlast = (cnt == pkt_length - 1);
assign o_cnt = cnt;
endmodule
| 9.212059 |
module tlast_gen_tb ();
parameter TDATA_WIDTH = 32;
parameter MAX_PKT_LENGTH = 32;
reg aclk;
reg resetn;
reg [$clog2(MAX_PKT_LENGTH):0] pkt_length;
reg force_tlast;
reg s_axis_tvalid;
reg m_axis_tready;
reg [ TDATA_WIDTH-1:0] s_axis_tdata;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [ TDATA_WIDTH-1:0] m_axis_tdata;
wire [$clog2(MAX_PKT_LENGTH):0] o_cnt;
// // For the non functional implementation
// tlast_gen_NONFUNCTIONAL #(
// .TDATA_WIDTH(TDATA_WIDTH),
// .MAX_PKT_LENGTH(MAX_PKT_LENGTH)
// ) u0 (
// // Clocks and resets
// .aclk(aclk),
// .resetn(resetn),
// .pkt_length(pkt_length),
// .s_axis_tvalid(s_axis_tvalid),
// .s_axis_tdata(s_axis_tdata),
// .m_axis_tvalid(m_axis_tvalid),
// .m_axis_tlast(m_axis_tlast),
// .m_axis_tdata(m_axis_tdata),
// .m_axis_tready(m_axis_tready),
// .o_cnt(o_cnt)
// );
// For the functional implementation
tlast_gen #(
.TDATA_WIDTH(TDATA_WIDTH),
.MAX_PKT_LENGTH(MAX_PKT_LENGTH)
) u0 (
// Clocks and resets
.aclk(aclk),
.resetn(resetn),
.pkt_length(pkt_length),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tdata(s_axis_tdata),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tlast(m_axis_tlast),
.m_axis_tdata(m_axis_tdata),
.m_axis_tready(m_axis_tready),
.o_cnt(o_cnt)
);
initial begin
aclk = 1;
resetn = 1;
force_tlast = 0;
s_axis_tvalid = 0;
s_axis_tdata = 6;
pkt_length = 8;
m_axis_tready = 1;
end
always @(*) begin
#1 aclk <= ~aclk;
end
initial begin
#4 s_axis_tvalid = 1;
#2 s_axis_tvalid = 0;
#10 s_axis_tvalid = 1;
#2 s_axis_tvalid = 0;
#10 s_axis_tvalid = 1;
#2 s_axis_tvalid = 0;
#10 s_axis_tvalid = 1;
#2 s_axis_tvalid = 0;
#10 s_axis_tvalid = 1;
#2 s_axis_tvalid = 0;
#10 s_axis_tvalid = 1;
#2 s_axis_tvalid = 0;
#10 s_axis_tvalid = 1;
#2 s_axis_tvalid = 0;
#10 s_axis_tvalid = 1;
#2 s_axis_tvalid = 0;
#10 s_axis_tvalid = 1;
#2 s_axis_tvalid = 0;
#10 s_axis_tvalid = 1;
#2 s_axis_tvalid = 0;
#10 s_axis_tvalid = 1;
#2 s_axis_tvalid = 0;
#10 s_axis_tvalid = 1;
#100 s_axis_tvalid = 0;
#20 $finish;
end
endmodule
| 7.45599 |
module tlast_m3_for_arty_a7_axis_subset_converter_0_1 #(
parameter C_S_AXIS_TID_WIDTH = 1,
parameter C_S_AXIS_TUSER_WIDTH = 0,
parameter C_S_AXIS_TDATA_WIDTH = 0,
parameter C_S_AXIS_TDEST_WIDTH = 0
) (
input [ (C_S_AXIS_TID_WIDTH == 0 ? 1 : C_S_AXIS_TID_WIDTH)-1:0] tid,
input [(C_S_AXIS_TDATA_WIDTH == 0 ? 1 : C_S_AXIS_TDATA_WIDTH)-1:0] tdata,
input [(C_S_AXIS_TUSER_WIDTH == 0 ? 1 : C_S_AXIS_TUSER_WIDTH)-1:0] tuser,
input [(C_S_AXIS_TDEST_WIDTH == 0 ? 1 : C_S_AXIS_TDEST_WIDTH)-1:0] tdest,
input [ (C_S_AXIS_TDATA_WIDTH/8)-1:0] tkeep,
input [ (C_S_AXIS_TDATA_WIDTH/8)-1:0] tstrb,
input [ 0:0] tlast,
output tlast_out
);
assign tlast_out = {tlast};
endmodule
| 7.119378 |
module tlast_m3_for_arty_a7_axis_subset_converter_0_2 #(
parameter C_S_AXIS_TID_WIDTH = 1,
parameter C_S_AXIS_TUSER_WIDTH = 0,
parameter C_S_AXIS_TDATA_WIDTH = 0,
parameter C_S_AXIS_TDEST_WIDTH = 0
) (
input [ (C_S_AXIS_TID_WIDTH == 0 ? 1 : C_S_AXIS_TID_WIDTH)-1:0] tid,
input [(C_S_AXIS_TDATA_WIDTH == 0 ? 1 : C_S_AXIS_TDATA_WIDTH)-1:0] tdata,
input [(C_S_AXIS_TUSER_WIDTH == 0 ? 1 : C_S_AXIS_TUSER_WIDTH)-1:0] tuser,
input [(C_S_AXIS_TDEST_WIDTH == 0 ? 1 : C_S_AXIS_TDEST_WIDTH)-1:0] tdest,
input [ (C_S_AXIS_TDATA_WIDTH/8)-1:0] tkeep,
input [ (C_S_AXIS_TDATA_WIDTH/8)-1:0] tstrb,
input [ 0:0] tlast,
output tlast_out
);
assign tlast_out = {tlast};
endmodule
| 7.119378 |
module TLBEntry (
input clk,
input we,
input [5:0] indexA,
output [24:0] entryA,
output [15:0] pageMaskA, //For instruction lookup
input [5:0] indexB,
output [24:0] entryB,
output [15:0] pageMaskB, //For data lookup
input [4:0] indexC,
output [49:0] entryC,
output [43:0] headerC, //For TLBR; indexC connected to Index register
input [4:0] indexD,
input [49:0] entryD,
input [43:0] headerD //For TLBWI/TLBWR; indexD connected to Index or Random
);
//Complete header and entry info
reg [93:0] tlbPool[31:0];
always @(posedge clk) if (we) tlbPool[indexD] <= {entryD, headerD};
assign {entryC, headerC} = tlbPool[indexC];
//PageMask
reg [15:0] pageMaskPool[31:0];
always @(posedge clk) if (we) pageMaskPool[indexD] <= headerD[`PageMask];
assign pageMaskA = pageMaskPool[indexA[4:0]];
assign pageMaskB = pageMaskPool[indexB[4:0]];
//Entry info
wire [5:0] entryWriteIndex;
wire [24:0] entryWriteData;
wire entryWe;
reg [24:0] entryPool[63:0];
always @(posedge clk) if (entryWe) entryPool[entryWriteIndex] <= entryWriteData;
assign entryA = entryPool[indexA];
assign entryB = entryPool[indexB];
reg we_reg;
reg [4:0] indexD_reg;
reg [24:0] dataIn_reg;
always @(posedge clk) begin
we_reg <= we;
indexD_reg <= indexD;
dataIn_reg <= entryD[49:25];
end
assign entryWriteIndex = we_reg ? {1'b1, indexD_reg} : {1'b0, indexD};
assign entryWriteData = we_reg ? dataIn_reg : entryD[24:0];
assign entryWe = we | we_reg;
integer i;
initial begin
for (i = 0; i < 32; i = i + 1) begin
tlbPool[i] = 0;
pageMaskPool[i] = 0;
end
for (i = 0; i < 64; i = i + 1) entryPool[i] = 0;
// pageMaskPool[30] = 16'hffff;
// pageMaskPool[31] = 16'hffff;
// entryPool[60] = {20'h00000, 5'b01011};
// entryPool[61] = {20'h10000, 5'b01011};
// entryPool[62] = {20'h00000, 5'b01111};
// entryPool[63] = {20'h10000, 5'b01111};
end
endmodule
| 7.096949 |
module TLBRNG (
input clk,
input rst,
input next,
input [4:0] regWired,
output reg [4:0] regRandom = 5'd31
);
reg [17:0] prng = 18'h143fd;
wire [35:0] product = prng * (32 - regWired);
always @(posedge clk)
if (rst) regRandom <= 5'd31;
else if (next) regRandom <= product[22:18] + regWired;
always @(posedge clk) if (next) prng <= (65521 * prng + 1); //Higher bits are truncated
endmodule
| 6.854459 |
module tlb_cache (
input reset,
input clk,
input [ 3:0] s_index,
input s_found,
input [19:0] s_pfn,
input [ 2:0] s_c,
input s_d,
input s_v,
input [31:0] inst_VA,
input [31:0] cp0_entryhi,
output inst_tlb_req_en,
input inst_addr_ok,
input inst_tlb_exception,
input inst_use_tlb,
input tlb_write,
output [19 : 0] inst_pfn,
output [ 2:0] inst_tlb_c,
output [ 3:0] inst_tlb_index,
output inst_tlb_v,
output inst_tlb_d,
output inst_tlb_found
);
reg [1 : 0] state;
reg [1 : 0] nextstate;
reg [18:0] vpn2;
reg [3:0] index;
reg odd_page;
reg [7 : 0] asid;
reg [19 : 0] pfn;
reg [2 : 0] tlb_c;
reg tlb_v;
reg tlb_d;
reg tlb_found;
reg tlb_valid;
wire tlb_hit;
assign tlb_hit = tlb_valid & (inst_VA[31:13] == vpn2) & (inst_VA[12] == odd_page) & (cp0_entryhi[7:0] == asid);
always @(posedge clk) begin
if (reset) state <= 2'd0;
else state <= nextstate;
end
always @(*) begin
case (state)
2'b00: nextstate = (!tlb_hit & inst_use_tlb) ? 2'b01 : 2'b00;
2'b01: nextstate = 2'b10;
2'b10: nextstate = (inst_addr_ok | inst_tlb_exception) ? 2'b00 : 2'b10;
default: nextstate = 2'b00;
endcase
end
always @(posedge clk) begin
if (reset) tlb_valid <= 1'b0;
else if (tlb_write) tlb_valid <= 1'b0;
else if (state == 2'b01) tlb_valid <= 1'b1;
end
always @(posedge clk) begin
if (reset) begin
vpn2 <= 19'd0;
odd_page <= 1'b0;
asid <= 8'd0;
index <= 4'd0;
pfn <= 20'd0;
tlb_c <= 3'd0;
tlb_d <= 1'b0;
tlb_v <= 1'b0;
tlb_found <= 1'b0;
end else if (state == 2'b01) begin
vpn2 <= inst_VA[31:13];
odd_page <= inst_VA[12];
asid <= cp0_entryhi[7:0];
index <= s_index;
pfn <= s_pfn;
tlb_c <= s_c;
tlb_v <= s_v;
tlb_d <= s_d;
tlb_found <= s_found;
end
end
assign inst_pfn = pfn;
assign inst_tlb_c = tlb_c;
assign inst_tlb_v = tlb_v;
assign inst_tlb_d = tlb_d;
assign inst_tlb_found = tlb_found;
assign inst_tlb_index = index;
assign inst_tlb_req_en = ((tlb_hit | !inst_use_tlb) & (state == 2'b00)) | (state == 2'b10);
endmodule
| 7.474601 |
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