code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module td_fused_top_tdf6_filters_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 12;
parameter MEM_SIZE = 4096;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DW... | 6.827284 |
module td_fused_top_tdf6_filters (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd4096;
parameter AddressWidth = 32'd12;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
outpu... | 6.827284 |
module td_fused_top_tdf7_adjustments_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 48;
parameter AWIDTH = 8;
parameter MEM_SIZE = 256;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [... | 6.827284 |
module td_fused_top_tdf7_adjustments (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd48;
parameter AddressRange = 32'd256;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
out... | 6.827284 |
module td_fused_top_tdf7_filters_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 17;
parameter MEM_SIZE = 73728;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [D... | 6.827284 |
module td_fused_top_tdf7_filters (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd73728;
parameter AddressWidth = 32'd17;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
outp... | 6.827284 |
module td_fused_top_tdf7_l2_filters_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 13;
parameter MEM_SIZE = 8192;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input ... | 6.827284 |
module td_fused_top_tdf7_l2_filters (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd8192;
parameter AddressWidth = 32'd13;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
ou... | 6.827284 |
module td_fused_top_tdf7_l2_writeOutputs_149_running_sums_ram (
addr0,
ce0,
d0,
we0,
addr1,
ce1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
input [AWIDTH-1:0] ad... | 6.827284 |
module td_fused_top_tdf7_l2_writeOutputs_149_running_sums (
reset,
clk,
address0,
ce0,
we0,
d0,
address1,
ce1,
q1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0... | 6.827284 |
module td_fused_top_tdf9_adjustments_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 48;
parameter AWIDTH = 6;
parameter MEM_SIZE = 64;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [D... | 6.827284 |
module td_fused_top_tdf9_adjustments (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd48;
parameter AddressRange = 32'd64;
parameter AddressWidth = 32'd6;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
outp... | 6.827284 |
module td_fused_top_tdf9_filters_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 14;
parameter MEM_SIZE = 16384;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [D... | 6.827284 |
module td_fused_top_tdf9_filters (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd16384;
parameter AddressWidth = 32'd14;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
outp... | 6.827284 |
module td_fused_top_td_fused_axi_in_p_ram (
addr0,
ce0,
d0,
we0,
addr1,
ce1,
q1,
addr2,
ce2,
q2,
addr3,
ce3,
q3,
addr4,
ce4,
q4,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 2;
parameter MEM_SIZE = 4;
input [AWIDTH-1:0] addr0;
input ce0... | 6.827284 |
module td_fused_top_td_fused_axi_in_p (
reset,
clk,
address0,
ce0,
we0,
d0,
address1,
ce1,
q1,
address2,
ce2,
q2,
address3,
ce3,
q3,
address4,
ce4,
q4
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd4;
parameter AddressWidth = ... | 6.827284 |
module td_fused_top_td_fused_final_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 16;
parameter MEM_SIZE = 49000;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input... | 6.827284 |
module td_fused_top_td_fused_final_fmaps_memcore (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd49000;
parameter AddressWidth = 32'd16;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
i... | 6.827284 |
module td_fused_top_td_fused_tdf10_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 12;
parameter MEM_SIZE = 3136;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ... | 6.827284 |
module td_fused_top_td_fused_tdf10_fmaps_memcore (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd3136;
parameter AddressWidth = 32'd12;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
in... | 6.827284 |
module td_fused_top_td_fused_tdf1_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 16;
parameter MEM_SIZE = 50176;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ... | 6.827284 |
module td_fused_top_td_fused_tdf1_fmaps_memcore (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd50176;
parameter AddressWidth = 32'd16;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
in... | 6.827284 |
module td_fused_top_td_fused_tdf3_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 15;
parameter MEM_SIZE = 25088;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ... | 6.827284 |
module td_fused_top_td_fused_tdf3_fmaps_memcore (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd25088;
parameter AddressWidth = 32'd15;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
in... | 6.827284 |
module td_fused_top_td_fused_tdf4_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 14;
parameter MEM_SIZE = 12544;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ... | 6.827284 |
module td_fused_top_td_fused_tdf4_fmaps_memcore (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd12544;
parameter AddressWidth = 32'd14;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
in... | 6.827284 |
module td_fused_top_td_fused_tdf7_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 13;
parameter MEM_SIZE = 6272;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input c... | 6.827284 |
module td_fused_top_td_fused_tdf7_fmaps_memcore (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd6272;
parameter AddressWidth = 32'd13;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
inp... | 6.827284 |
module FPMult_PrepModule (
clk,
rst,
a,
b,
Sa,
Sb,
Ea,
Eb,
Mp,
InputExc
);
// Input ports
input clk;
input rst;
input [`DWIDTH-1:0] a; // Input A, a 32-bit floating point number
input [`DWIDTH-1:0] b; // Input B, a 32-bit floating point number
// Output ports
ou... | 7.427166 |
module FPMult_NormalizeModule (
NormM,
NormE,
RoundE,
RoundEP,
RoundM,
RoundMP
);
// Input Ports
input [`MANTISSA-1:0] NormM; // Normalized mantissa
input [`EXPONENT:0] NormE; // Normalized exponent
// Output Ports
output [`EXPONENT:0] RoundE;
output [`EXPONENT:0] RoundEP;
outp... | 7.947312 |
module FPMult_RoundModule (
RoundM,
RoundMP,
RoundE,
RoundEP,
Sp,
GRS,
InputExc,
Z,
Flags
);
// Input Ports
input [`MANTISSA:0] RoundM; // Normalized mantissa
input [`MANTISSA:0] RoundMP; // Normalized exponent
input [`EXPONENT:0] RoundE; // Normalized mantissa + 1
inpu... | 7.570448 |
module is responsible for taking the inputs
// apart and checking the parts for exceptions.
// The exponent difference is also calculated in this module.
module FPAddSub_PrealignModule(
A,
B,
operation,
Sa,
Sb,
ShiftDet,
InputExc,
Aout,
Bout,
Opout
);
// Input ports
input [`DWIDTH-... | 7.391888 |
module determines the larger input operand and
// sets the mantissas, shift and common exponent accordingly.
module FPAddSub_AlignModule (
A,
B,
ShiftDet,
CExp,
MaxAB,
Shift,
Mmin,
Mmax
);
// Input ports
input [`DWIDTH-2:0] A ; // Input A, a 32-bit floating point number
input [`DWIDT... | 6.986217 |
module FPAddSub_AlignShift1 (
MminP,
Shift,
Mmin
);
// Input ports
input [`MANTISSA-1:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [2:0] Shift; // Shift amount
// Output ports
output [`MANTISSA:0] Mmin; // The smaller mantissa
// Internal signals
reg [ `MANTISSA:0] Lv... | 6.969233 |
module FPAddSub_AlignShift2 (
MminP,
Shift,
Mmin
);
// Input ports
input [`MANTISSA:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [1:0] Shift; // Shift amount
// Output ports
output [`MANTISSA:0] Mmin; // The smaller mantissa
// Internal Signal
reg [ `MANTISSA:0] Lvl3;... | 6.969233 |
module FPAddSub_ExecutionModule (
Mmax,
Mmin,
Sa,
Sb,
MaxAB,
OpMode,
Sum,
PSgn,
Opr
);
// Input ports
input [`MANTISSA-1:0] Mmax; // The larger mantissa
input [`MANTISSA:0] Mmin; // The smaller mantissa
input Sa; // Sign bit of larger number
input Sb; // Sign bit of sm... | 6.632792 |
module FPAddSub_NormalizeModule (
Sum,
Mmin,
Shift
);
// Input ports
input [`DWIDTH:0] Sum; // Mantissa sum including hidden 1 and GRS
// Output ports
output [`DWIDTH:0] Mmin; // Mantissa after 16|0 shift
output [4:0] Shift; // Shift amount
// Determine normalization shift amount by findin... | 6.905513 |
module FPAddSub_NormalizeShift1 (
MminP,
Shift,
Mmin
);
// Input ports
input [`DWIDTH:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [3:0] Shift; // Shift amount
// Output ports
output [`DWIDTH:0] Mmin; // The smaller mantissa
reg [ `DWIDTH:0] Lvl2;
wire [2*`DWIDTH+1... | 6.905513 |
module FPAddSub_NormalizeShift2 (
PSSum,
CExp,
Shift,
NormM,
NormE,
ZeroSum,
NegE,
R,
S,
FG
);
// Input ports
input [`DWIDTH:0] PSSum; // The Pre-Shift-Sum
input [`EXPONENT-1:0] CExp;
input [4:0] Shift; // Amount to be shifted
// Output ports
output [`MANTISSA-1:0... | 6.905513 |
module FPAddSub_RoundModule (
ZeroSum,
NormE,
NormM,
R,
S,
G,
Sa,
Sb,
Ctrl,
MaxAB,
Z,
EOF
);
// Input ports
input ZeroSum; // Sum is zero
input [`EXPONENT:0] NormE; // Normalized exponent
input [`MANTISSA-1:0] NormM; // Normalized mantissa
input R; // Round... | 7.753919 |
module FPAddSub_ExceptionModule (
Z,
NegE,
R,
S,
InputExc,
EOF,
P,
Flags
);
// Input ports
input [`DWIDTH-1:0] Z; // Final product
input NegE; // Negative exponent?
input R; // Round bit
input S; // Sticky bit
input [4:0] InputExc; // Exceptions in inputs A and B
inpu... | 7.326377 |
module tiny_spi (
// system
input rst_i,
input clk_i,
// memory mapped
input stb_i,
input we_i,
output [31:0] dat_o,
input [31:0] dat_i,
output int_o,
input [2:0] adr_i,
//input cyc_i, // comment out for avalon
//output ack_o, // comment out for avalon
// spi
... | 8.081707 |
module of constants
*
* addr out effective
* 1 0 1
* 2 1 1
* 4 + 1
* 8 - 1
* 16 cubic 1
* other 0 0
*/
module const_ (clk, addr, out, effective);
input clk;
input [5:0] addr;
output reg [`WIDTH_D0:0] out;
output reg effective; // active high if out... | 6.852447 |
module FSM (
clk,
reset,
rom_addr,
rom_q,
ram_a_addr,
ram_b_addr,
ram_b_w,
pe,
done
);
input clk;
input reset;
output reg [8:0] rom_addr; /* command id. extra bits? */
input [28:0] rom_q; /* command value */
output reg [5:0] ram_a_addr;
output reg [5:0] ram_b_addr;
ou... | 6.752458 |
module pairing (
clk,
reset,
sel,
addr,
w,
update,
ready,
i,
o,
done
);
input clk;
input reset; // for the arithmethic core
input sel;
input [5:0] addr;
input w;
input update; // update reg_in & reg_out
input ready; // shift reg_in & reg_out
input i;
output o... | 7.568618 |
module PPG (
d,
A,
C
);
input [1:0] d;
input [`WIDTH:0] A;
output [`WIDTH:0] C;
genvar i;
generate
for (i = 0; i < `M; i = i + 1) begin : ppg0
f3_mult f3_mult_0 (
d,
A[2*i+1:2*i],
C[2*i+1:2*i]
);
end
endgenerate
endmodule
| 7.164526 |
module f3m_add (
A,
B,
C
);
input [`WIDTH : 0] A, B;
output [`WIDTH : 0] C;
genvar i;
generate
for (i = 0; i < `M; i = i + 1) begin : aa
f3_add aa (
A[(2*i+1) : 2*i],
B[(2*i+1) : 2*i],
C[(2*i+1) : 2*i]
);
end
endgenerate
endmodule
| 7.024046 |
module ram #(
parameter DATA = 1188,
parameter ADDR = 6
) (
input clk,
// Port A
input wire a_wr,
input wire [ADDR-1:0] a_addr,
input wire [DATA-1:0] a_din,
output reg [DATA-1:0] a_dout,
// Port B
input wire b_wr,
input wire [ADDR-1:0] b_addr,
... | 7.30525 |
module tiny (
clk,
reset,
sel,
addr,
w,
data,
out,
done
);
input clk, reset;
input sel;
input [5:0] addr;
input w;
input [`WIDTH_D0:0] data;
output [`WIDTH_D0:0] out;
output done;
/* for FSM */
wire [5:0] fsm_addr;
/* for RAM */
wire [5:0] ram_a_addr, ram_b_addr;
... | 6.906849 |
module select (
sel,
addr_in,
addr_fsm_in,
w_in,
addr_out,
w_out
);
input sel;
input [5:0] addr_in;
input [5:0] addr_fsm_in;
input w_in;
output [5:0] addr_out;
output w_out;
assign addr_out = sel ? addr_in : addr_fsm_in;
assign w_out = sel & w_in;
endmodule
| 7.910302 |
module muxer (
from_ram,
from_const,
const_effective,
out
);
input [`WIDTH_D0:0] from_ram, from_const;
input const_effective;
output [`WIDTH_D0:0] out;
assign out = const_effective ? from_const : from_ram;
endmodule
| 6.618212 |
module instance
// generated by configure.py
module tiny_user_project(
`ifdef USE_POWER_PINS
inout vccd1,
inout vssd1,
`endif
// IOs
input [`MPRJ_IO_PADS-1:0] io_in,
output [`MPRJ_IO_PADS-1:0] io_out,
output [`MPRJ_IO_PADS-1:0] io_oeb,
);
// pass input and output pins defined in user_defines.v... | 6.778253 |
module TitleRom (
input wire [18:0] i_addr,
input wire i_clk2,
output reg [7:0] o_data
);
// (*ROM_STYLE="block"*) reg [7:0] memory_array [0:28854];
// (*ROM_STYLE="block"*) reg [7:0] memory_array [0:436207];
(*ROM_STYLE="block"*) reg [7:0] memory_array[0:111375];
initial begin
$readmemh(... | 6.843604 |
module TitleScene (
input wire [9:0] ix,
input wire [9:0] iy,
input wire iactive,
input wire ibtnC,
input wire iPixCLK,
input wire iCLK,
input wire iPS2Clk,
input wire iPS2Data,
output reg [3:0] oRED,
output reg [3:0] oGREEN,
output reg [3:0] oBLUE,
input wire [3:0] st... | 8.124727 |
module titleScreen (
input clk
, input p_tick
, input [9:0] x
, input [9:0] y
, output reg [7:0] data
);
localparam UnderpugsT = 96;
localparam UnderpugsL = 127;
localparam UnderpugsD = 542;
localparam UnderpugsR = 171;
localparam UnderpugsWidth = 445;
localparam NameT = 126;
localpar... | 6.697182 |
module TitleSprite (
input wire [9:0] xx, // current x position
input wire [9:0] yy, // current y position
input wire aactive, // high during active pixel drawing
output reg SpriteOn, // 1=on, 0=off
output wire [7:0] dataout, // 8 bit pixel value from Bee.mem
input wire Pclk, // 25MHz pixe... | 7.754969 |
module title_colorizer #(
parameter MARGIN_X = 256 + 128,
parameter MARGIN_Y = 32,
parameter TITLE_WIDTH = 256, // 2^8
parameter TITLE_HEIGHT = 128, // 2^7
parameter TITLE_ADDR_WIDTH_X = 8,
parameter TITLE_ADDR_WIDTH_Y = 7,
localparam TITLE_ADDR_WIDTH = TITLE_ADDR_WIDTH_X + TITLE_ADDR_WIDT... | 8.354128 |
module TI_CIC_FILTER_8X2P (
IN1,
IN2,
IN3,
IN4,
CLK_adc1,
CLK_adc1_2,
CLK_adc2,
CLK_adc3,
CLK_adc4,
RES,
ENABLE,
OUT1,
OUT2
);
parameter BW = 6;
input CLK_adc1, CLK_adc1_2, CLK_adc2, CLK_adc3, CLK_adc4, RES, ENABLE;
input signed [BW-1:0] IN1, IN2, IN3, IN4;
... | 6.540385 |
module TI_Simon_Core (
clk,
data_ina,
data_inb,
data_rdy,
cipher_outa,
cipher_outb,
round_counter,
Done,
Trig
);
//------------------------------------------------ Interfaces
input clk;
input data_ina, data_inb;
input [1:0] data_rdy;
output cipher_outa, cipher_outb;
outp... | 7.198812 |
module datapath_simon2share (
clk,
data_ina,
data_inb,
data_rdy,
key_ina,
key_inb,
cipher_outa,
cipher_outb,
round_counter_0,
flag,
bit_counter
);
input clk, data_ina, data_inb;
input key_ina, key_inb;
input [1:0] data_rdy;
input round_counter_0;
input [5:0] bit_cou... | 7.360755 |
module lut_datapath (
clk,
out,
shift_out2,
key_in,
lut_rol2,
lut_rol1,
lut_rol8,
lut_rol1_shifted,
lut_rol8_ext
);
//------------------------------------------------
input clk, shift_out2, key_in, lut_rol2, lut_rol1, lut_rol8, lut_rol1_shifted, lut_rol8_ext;
output out;
reg... | 7.909204 |
module key_schedule_2 (
clk,
data_in,
key_out,
bit_counter,
flag,
s2,
s1,
s3,
shifter_enable1,
shifter_enable2,
lut_ff_enable,
fifo_ff_enable
);
//------------------------------------------------
input clk;
input data_in;
//input [1:0] data_rdy;
input [5:0] bit... | 6.528716 |
module TI_Simon_TopModule (
Din,
Dout,
Drdy,
Dvld,
EN,
BSY,
CLK,
RSTn,
Trig
);
//------------------------------------------------
input [(128*6)-1:0] Din; // Data input
output [127:0] Dout; // Data output
input Drdy; // Data input ready
output Dvld; // Data output vali... | 7.933467 |
module: sasebo_simon
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TI_Simon_TopModule_tb;
// Inputs
reg [767:0] Din;
reg Drdy;
reg EN;
reg CLK;
reg RSTn;
// Outputs
wire ... | 6.844882 |
module tkeep_m3_for_arty_a7_axis_subset_converter_0_1 #(
parameter C_S_AXIS_TDATA_WIDTH = 32,
parameter C_S_AXIS_TUSER_WIDTH = 0,
parameter C_S_AXIS_TID_WIDTH = 0,
parameter C_S_AXIS_TDEST_WIDTH = 0,
parameter C_M_AXIS_TDATA_WIDTH = 32
) (
input [(C_S_AXIS_TDATA_WIDTH == 0 ? 1 : C_S_AXIS_TDAT... | 6.853224 |
module tkeep_m3_for_arty_a7_axis_subset_converter_0_2 #(
parameter C_S_AXIS_TDATA_WIDTH = 32,
parameter C_S_AXIS_TUSER_WIDTH = 0,
parameter C_S_AXIS_TID_WIDTH = 0,
parameter C_S_AXIS_TDEST_WIDTH = 0,
parameter C_M_AXIS_TDATA_WIDTH = 32
) (
input [(C_S_AXIS_TDATA_WIDTH == 0 ? 1 : C_S_AXIS_TDAT... | 6.853224 |
module to convert TKEEP encoding to a byte count. Note that the
output of this module is computed as (popcount(TKEEP) - 1). This takes
advantage of the fact that we disallow a TKEEP of 0 in order to reduce the
number of necessary bits.
This code assumes that there are no gaps between asserted TKEEP bits, and
that the ... | 7.016687 |
module tkeep_to_len_tb #(
parameter TKEEP_WIDTH = 8
);
reg clk = 0;
always #5 clk <= ~clk;
reg [TKEEP_WIDTH -1:0] tkeep = 0;
wire [$clog2(TKEEP_WIDTH) -1:0] len;
initial begin
$dumpfile("tkeep_to_len.vcd");
$dumpvars;
$dumplimit(512000);
#1000 $finish;
end
integer i;
reg [$clog2... | 7.110141 |
module tl (
input rst_n,
input clk,
input pass_request,
output wire [7:0] clock,
output reg red,
output reg yellow,
output reg green
);
parameter A = 0;
parameter B = 1;
parameter C = 2;
reg [1:0] state;
reg [1:0] nstate;
reg [7:0] cnt = 0;
always @(posedge clk, negedge rst_n)... | 7.379785 |
module TL16_6_4 (
input [15:0] x,
input [15:0] y,
output [31:0] p
);
// First complement
wire [15:0] x_abs;
assign x_abs = x ^ {16{x[15]}};
// is upper n-Q bits zero
wire not_zeroUpX;
assign not_zeroUpX = |(x_abs[15:6]);
wire [9:0] x_up;
assign x_up = {x_abs[14:6], 1'b1};
wire [9:0... | 7.086155 |
module fixedShift (
input [19:0] data_i,
input [1:0] shift_i,
output reg [31:0] data_o
);
always @*
case (shift_i)
2'b01: data_o = data_i << 5;
2'b10: data_o = data_i << 10;
default: data_o = data_i;
endcase
endmodule
| 6.581126 |
module ADAPT_10bit (
input [9:0] x,
input [9:0] y,
output zeroTMP,
output [19:0] p
);
// First complement
wire [9:0] x_abs;
assign x_abs = x;
// LOD + Priority Encoder
wire [9:0] k_x0;
wire zero_x0, one_x0;
wire [3:0] k_x0_enc;
LOD10 lod_x0 (
.data_i (x_abs),
.zero_o (z... | 6.67581 |
module LOD3 (
input [2:0] data_i,
output [2:0] data_o
);
//gates and IO assignments:
assign data_o[2] = data_i[2];
assign data_o[1] = (~data_i[2] & data_i[1]);
assign data_o[0] = (~data_i[2] & ~data_i[1] & data_i[0]);
endmodule
| 7.557238 |
module Muxes2in1Array4 (
input [3:0] data_i,
input select_i,
output [3:0] data_o
);
assign data_o[3] = select_i ? data_i[3] : 1'b0;
assign data_o[2] = select_i ? data_i[2] : 1'b0;
assign data_o[1] = select_i ? data_i[1] : 1'b0;
assign data_o[0] = select_i ? data_i[0] : 1'b0;
endmodule
| 7.798153 |
module LBarrel (
input [9:0] data_i,
input [9:0] shift_i,
output [3:0] data_o
);
assign data_o[3] = |(data_i[8:0] & shift_i[9:1]);
assign data_o[2] = |(data_i[7:0] & shift_i[9:2]);
assign data_o[1] = |(data_i[6:0] & shift_i[9:3]);
assign data_o[0] = 1'b1;
endmodule
| 6.741724 |
module L1Barrel (
input [ 4:0] data_i,
input [ 4:0] shift_i,
output [19:0] data_o
);
reg [23:0] tmp; //2n+w-2q
always @*
case (shift_i)
5'b00000: tmp = data_i;
5'b00001: tmp = data_i << 1;
5'b00010: tmp = data_i << 2;
5'b00011: tmp = data_i << 3;
5'b00100: tmp = data... | 6.641517 |
module TL16_7_4 (
input [15:0] x,
input [15:0] y,
output [31:0] p
);
// First complement
wire [15:0] x_abs;
assign x_abs = x ^ {16{x[15]}};
// is upper n-Q bits zero
wire not_zeroUpX;
assign not_zeroUpX = |(x_abs[15:7]);
wire [8:0] x_up;
assign x_up = {x_abs[14:7], 1'b1};
wire [8:0... | 7.009518 |
module fixedShift (
input [17:0] data_i,
input [1:0] shift_i,
output reg [31:0] data_o
);
always @*
case (shift_i)
2'b01: data_o = data_i << 6;
2'b10: data_o = data_i << 12;
default: data_o = data_i;
endcase
endmodule
| 6.581126 |
module ADAPT_9bit (
input [8:0] x,
input [8:0] y,
output zeroTMP,
output [17:0] p
);
// First complement
wire [8:0] x_abs;
assign x_abs = x;
// LOD + Priority Encoder
wire [8:0] k_x0;
wire zero_x0, one_x0;
wire [3:0] k_x0_enc;
LOD9 lod_x0 (
.data_i (x_abs),
.zero_o (zer... | 7.260467 |
module LOD9 (
input [8:0] data_i,
output zero_o,
output [8:0] data_o,
output [3:0] data_enc
);
wire [8:0] z;
wire [2:0] zdet;
wire [2:0] select;
wire zero_h;
wire zero_l;
//*****************************************
// Zero and one detection logic:
//*************************************... | 6.798652 |
module LOD3 (
input [2:0] data_i,
output [2:0] data_o
);
//gates and IO assignments:
assign data_o[2] = data_i[2];
assign data_o[1] = (~data_i[2] & data_i[1]);
assign data_o[0] = (~data_i[2] & ~data_i[1] & data_i[0]);
endmodule
| 7.557238 |
module Muxes2in1Array4 (
input [3:0] data_i,
input select_i,
output [3:0] data_o
);
assign data_o[3] = select_i ? data_i[3] : 1'b0;
assign data_o[2] = select_i ? data_i[2] : 1'b0;
assign data_o[1] = select_i ? data_i[1] : 1'b0;
assign data_o[0] = select_i ? data_i[0] : 1'b0;
endmodule
| 7.798153 |
module LBarrel (
input [8:0] data_i,
input [8:0] shift_i,
output [3:0] data_o
);
assign data_o[3] = |(data_i[7:0] & shift_i[8:1]);
assign data_o[2] = |(data_i[6:0] & shift_i[8:2]);
assign data_o[1] = |(data_i[5:0] & shift_i[8:3]);
assign data_o[0] = 1'b1;
endmodule
| 6.741724 |
module L1Barrel (
input [ 4:0] data_i,
input [ 4:0] shift_i,
output [17:0] data_o
);
reg [21:0] tmp; //2n+w-2q
always @*
case (shift_i)
5'b00000: tmp = data_i;
5'b00001: tmp = data_i << 1;
5'b00010: tmp = data_i << 2;
5'b00011: tmp = data_i << 3;
5'b00100: tmp = data... | 6.641517 |
module TL16_8_4 (
input [15:0] x,
input [15:0] y,
output [31:0] p
);
// First complement
wire [15:0] x_abs;
assign x_abs = x ^ {16{x[15]}};
// is upper n-Q bits zero
wire not_zeroUpX;
assign not_zeroUpX = |(x_abs[15:8]);
wire [7:0] x_up;
assign x_up = {x_abs[14:8], 1'b1};
wire [7:... | 7.123827 |
module fixedShift (
input [15:0] data_i,
input [1:0] shift_i,
output reg [31:0] data_o
);
always @*
case (shift_i)
2'b01: data_o = data_i << 7;
2'b10: data_o = data_i << 14;
default: data_o = data_i;
endcase
endmodule
| 6.581126 |
module ADAPT_8bit (
input [7:0] x,
input [7:0] y,
output zeroTMP,
output [15:0] p
);
// First complement
wire [7:0] x_abs;
assign x_abs = x;
// LOD + Priority Encoder
wire [7:0] k_x0;
wire zero_x0, one_x0;
wire [3:0] k_x0_enc;
LOD8 lod_x0 (
.data_i (x_abs),
.zero_o (zer... | 7.369749 |
module LOD8 (
input [7:0] data_i,
output zero_o,
output [7:0] data_o,
output [3:0] data_enc
);
wire [8:0] z;
wire [2:0] zdet;
wire [2:0] select;
wire zero_h;
wire zero_l;
//*****************************************
// Zero and one detection logic:
//*************************************... | 6.992495 |
module LOD3 (
input [2:0] data_i,
output [2:0] data_o
);
//gates and IO assignments:
assign data_o[2] = data_i[2];
assign data_o[1] = (~data_i[2] & data_i[1]);
assign data_o[0] = (~data_i[2] & ~data_i[1] & data_i[0]);
endmodule
| 7.557238 |
module Muxes2in1Array4 (
input [3:0] data_i,
input select_i,
output [3:0] data_o
);
assign data_o[3] = select_i ? data_i[3] : 1'b0;
assign data_o[2] = select_i ? data_i[2] : 1'b0;
assign data_o[1] = select_i ? data_i[1] : 1'b0;
assign data_o[0] = select_i ? data_i[0] : 1'b0;
endmodule
| 7.798153 |
module LBarrel (
input [7:0] data_i,
input [7:0] shift_i,
output [3:0] data_o
);
assign data_o[3] = |(data_i[6:0] & shift_i[7:1]);
assign data_o[2] = |(data_i[5:0] & shift_i[7:2]);
assign data_o[1] = |(data_i[4:0] & shift_i[7:3]);
assign data_o[0] = 1'b1;
endmodule
| 6.741724 |
module L1Barrel (
input [ 5:0] data_i,
input [ 4:0] shift_i,
output [15:0] data_o
);
reg [19:0] tmp; //2n+w-2q
always @*
case (shift_i)
5'b00000: tmp = data_i;
5'b00001: tmp = data_i << 1;
5'b00010: tmp = data_i << 2;
5'b00011: tmp = data_i << 3;
5'b00100: tmp = data... | 6.641517 |
module tlast_gen #(
parameter TDATA_WIDTH = 8,
parameter MAX_PKT_LENGTH = 256
) (
// Clocks and resets
input aclk,
input resetn,
// Control signals
input [$clog2(MAX_PKT_LENGTH):0] pkt_length,
// Slave interface
input s_axis_tvalid,
output ... | 8.70195 |
module tlast_gen_NONFUNCTIONAL #(
parameter TDATA_WIDTH = 8,
parameter MAX_PKT_LENGTH = 256
) (
// Clocks and resets
input aclk,
input resetn,
// Control signals
input [$clog2(MAX_PKT_LENGTH):0] pkt_length,
// Slave interface
input s_axis_tvalid,
output ... | 9.212059 |
module tlast_gen_tb ();
parameter TDATA_WIDTH = 32;
parameter MAX_PKT_LENGTH = 32;
reg aclk;
reg resetn;
reg [$clog2(MAX_PKT_LENGTH):0] pkt_length;
reg force_tlast;
reg s_axis_tvalid;
reg ... | 7.45599 |
module tlast_m3_for_arty_a7_axis_subset_converter_0_1 #(
parameter C_S_AXIS_TID_WIDTH = 1,
parameter C_S_AXIS_TUSER_WIDTH = 0,
parameter C_S_AXIS_TDATA_WIDTH = 0,
parameter C_S_AXIS_TDEST_WIDTH = 0
) (
input [ (C_S_AXIS_TID_WIDTH == 0 ? 1 : C_S_AXIS_TID_WIDTH)-1:0] tid,
input [(C_S_AXIS_T... | 7.119378 |
module tlast_m3_for_arty_a7_axis_subset_converter_0_2 #(
parameter C_S_AXIS_TID_WIDTH = 1,
parameter C_S_AXIS_TUSER_WIDTH = 0,
parameter C_S_AXIS_TDATA_WIDTH = 0,
parameter C_S_AXIS_TDEST_WIDTH = 0
) (
input [ (C_S_AXIS_TID_WIDTH == 0 ? 1 : C_S_AXIS_TID_WIDTH)-1:0] tid,
input [(C_S_AXIS_T... | 7.119378 |
module TLBEntry (
input clk,
input we,
input [5:0] indexA,
output [24:0] entryA,
output [15:0] pageMaskA, //For instruction lookup
input [5:0] indexB,
output [24:0] entryB,
output [15:0] pageMaskB, //For data lookup
input [4:0] indexC,
output [49:0] entryC,
output [43:0] he... | 7.096949 |
module TLBRNG (
input clk,
input rst,
input next,
input [4:0] regWired,
output reg [4:0] regRandom = 5'd31
);
reg [17:0] prng = 18'h143fd;
wire [35:0] product = prng * (32 - regWired);
always @(posedge clk)
if (rst) regRandom <= 5'd31;
else if (next) regRandom <= product[22:18] + re... | 6.854459 |
module tlb_cache (
input reset,
input clk,
input [ 3:0] s_index,
input s_found,
input [19:0] s_pfn,
input [ 2:0] s_c,
input s_d,
input s_v,
input [31:0] inst_VA,
input [31:0] cp0_entryhi,
output inst_tlb_req_en,
input inst_addr_ok,
... | 7.474601 |
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