code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module tm_testbench ();
localparam DATA_WIDTH_IN = 18;
localparam DATA_WIDTH_OUT = 18;
reg signed clk;
reg signed rst_n;
reg signed halt_ctrl;
reg signed [ 5:0] tm64_ctrl;
reg signed [DATA_WIDTH_IN-1:0] din_real;
reg signed [DATA... | 7.373333 |
module twiddle64_0 #(
parameter DATA_WIDTH = 14
) (
input wire signed [DATA_WIDTH-1:0] din_real,
input wire signed [DATA_WIDTH-1:0] din_imag,
output wire signed [DATA_WIDTH-1:0] dout_rere,
output wire signed [DATA_WIDTH-1:0] dout_imim,
output wire signed [DATA_WIDTH-1:0] dout_reim,
output ... | 7.511271 |
module twiddle64_1 #(
parameter DATA_WIDTH = 14
) (
input signed [DATA_WIDTH-1:0] din_real,
input signed [DATA_WIDTH-1:0] din_imag,
output signed [DATA_WIDTH-1:0] dout_rere,
output signed [DATA_WIDTH-1:0] dout_imim,
output signed [DATA_WIDTH-1:0] dout_reim,
output signed [DATA_WIDTH-1:0] d... | 6.918234 |
module twiddle64_2 #(
parameter DATA_WIDTH = 14
) (
input wire signed [DATA_WIDTH-1:0] din_real,
input wire signed [DATA_WIDTH-1:0] din_imag,
output wire signed [DATA_WIDTH-1:0] dout_rere,
output wire signed [DATA_WIDTH-1:0] dout_imim,
output wire signed [DATA_WIDTH-1:0] dout_reim,
output ... | 7.168156 |
module twiddle64_3 #(
parameter DATA_WIDTH = 14
) (
input wire signed [DATA_WIDTH-1:0] din_real,
input wire signed [DATA_WIDTH-1:0] din_imag,
output wire signed [DATA_WIDTH-1:0] dout_rere,
output wire signed [DATA_WIDTH-1:0] dout_imim,
output wire signed [DATA_WIDTH-1:0] dout_reim,
output ... | 7.472133 |
module twiddle64_4 #(
parameter DATA_WIDTH = 14
) (
input wire signed [DATA_WIDTH-1:0] din_real,
input wire signed [DATA_WIDTH-1:0] din_imag,
output wire signed [DATA_WIDTH-1:0] dout_rere,
output wire signed [DATA_WIDTH-1:0] dout_imim,
output wire signed [DATA_WIDTH-1:0] dout_reim,
output ... | 7.362297 |
module twiddle64_5 #(
parameter DATA_WIDTH = 14
) (
input wire signed [DATA_WIDTH-1:0] din_real,
input wire signed [DATA_WIDTH-1:0] din_imag,
output wire signed [DATA_WIDTH-1:0] dout_rere,
output wire signed [DATA_WIDTH-1:0] dout_imim,
output wire signed [DATA_WIDTH-1:0] dout_reim,
output ... | 7.181315 |
module twiddle64_6 #(
parameter DATA_WIDTH = 14
) (
input wire signed [DATA_WIDTH-1:0] din_real,
input wire signed [DATA_WIDTH-1:0] din_imag,
output wire signed [DATA_WIDTH-1:0] dout_rere,
output wire signed [DATA_WIDTH-1:0] dout_imim,
output wire signed [DATA_WIDTH-1:0] dout_reim,
output ... | 6.972645 |
module twiddle64_7 #(
parameter DATA_WIDTH = 14
) (
input wire signed [DATA_WIDTH-1:0] din_real,
input wire signed [DATA_WIDTH-1:0] din_imag,
output wire signed [DATA_WIDTH-1:0] dout_rere,
output wire signed [DATA_WIDTH-1:0] dout_imim,
output wire signed [DATA_WIDTH-1:0] dout_reim,
output ... | 7.309479 |
module twiddle64_8 #(
parameter DATA_WIDTH = 14
) (
input wire signed [DATA_WIDTH-1:0] din_real,
input wire signed [DATA_WIDTH-1:0] din_imag,
output wire signed [DATA_WIDTH-1:0] dout_rere,
output wire signed [DATA_WIDTH-1:0] dout_imim,
output wire signed [DATA_WIDTH-1:0] dout_reim,
output ... | 6.980159 |
module twiddle64_part2 #(
parameter DATA_WIDTH = 14,
parameter TWIDDLE = 0
) (
input wire signed [DATA_WIDTH-1:0] din_real,
input wire signed [DATA_WIDTH-1:0] din_imag,
input wire signed [ DATA_WIDTH:0] tmp0_rere,
input wire signed [ DATA_WIDTH:0] tmp0_imim,
input wire signed [ DATA_... | 6.796218 |
module TNBUFFX16 (
INP,
ENB,
Z
);
input INP;
input ENB;
output Z;
bufif1 U0 (Z, INP, ENB);
specify
specparam
tdelay_INP_Z_01_0=0.01,
tdelay_INP_Z_10_0=0.01,
tdelay_ENB_Z_Z1_0=0.01,
tdelay_ENB_Z_Z0_0=0.01,
tdelay_ENB_Z_01_0=0.01,
tdelay_ENB_Z_10_0=0.01;
(INP + => Z) = (tdelay_INP_Z_01_0,... | 6.546464 |
module TNBUFFX8 (
INP,
ENB,
Z
);
input INP;
input ENB;
output Z;
bufif1 U0 (Z, INP, ENB);
specify
specparam
tdelay_INP_Z_01_0=0.01,
tdelay_INP_Z_10_0=0.01,
tdelay_ENB_Z_Z1_0=0.01,
tdelay_ENB_Z_Z0_0=0.01,
tdelay_ENB_Z_01_0=0.01,
tdelay_ENB_Z_10_0=0.01;
(INP + => Z) = (tdelay_INP_Z_01_0, ... | 6.58734 |
module TNKIIICoreClocks_Cen (
input wire i_clk,
output wire clk_13p4_cen,
output wire clk_13p4,
output wire clk_13p4b_cen,
output wire clk_13p4b,
output wire clk_6p7_cen,
output wire clk_6p7b_cen,
output wire clk_3p35_cen,
output wire clk_3p35b_cen,
output wire clk_4_cen,
ou... | 7.267132 |
module receives scan code, and returns corresponding ASCII code.
module toASCII(
input [7:0]data,
output [7:0]asdata
);
(* ram_init_file = "ascii.mif" *)reg [7:0] toascii [255:0];
assign asdata = toascii[data];
//ROM
endmodule
| 7.18918 |
module TODO (
input reloj,
input resetM,
input Boton_B,
input Boton_R,
input Boton_G,
output [3:0] R,
output [3:0] G,
output [3:0] B,
output H_Sync,
output V_Sync,
output H_Sync2,
output V_Sync2,
output BIT_FUENTE,
output H_ON,
output V_ON,
output R2,
... | 7.449721 |
module TODO_tb(
);
reg reloj;
reg resetM;
reg Boton_B,Boton_R,Boton_G;
<<<<<<< HEAD
wire H_Sync,H_Sync2,V_Sync,V_Sync2,BIT_FUENTE,H_ON,V_ON,R2,G2,B2;
=======
wire H_Sync,V_Sync,BIT_FUENTE,H_ON,V_ON;
>>>>>>> 577cc9a1689b628be444f2603bb3fba1a29a7b4d
wire [3:0] R;
... | 7.108934 |
module toe_ack_delay_ack_table_V_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 12;
parameter AWIDTH = 14;
parameter MEM_SIZE = 10000;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q... | 8.242296 |
module toe_ack_delay_ack_table_V (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd12;
parameter AddressRange = 32'd10000;
parameter AddressWidth = 32'd14;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
... | 8.242296 |
module toe_ap_rst_if #(
parameter RESET_ACTIVE_LOW = 0
) (
input wire din,
output wire dout
);
assign dout = (RESET_ACTIVE_LOW == 1) ? ~din : din;
endmodule
| 8.492718 |
module toe_free_port_table_freePortTable_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 1;
parameter AWIDTH = 15;
parameter MEM_SIZE = 32768;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH... | 7.440096 |
module toe_free_port_table_freePortTable (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd1;
parameter AddressRange = 32'd32768;
parameter AddressWidth = 32'd15;
input reset;
input clk;
input [AddressWidth - 1:0] addre... | 7.440096 |
module toe_m_axis_listen_port_rsp_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
output wire TVALID,
input wire TREADY,
output wire [7:0] TDATA,
// User signals
input wire [0:0] listenPortRsp_V_din,
output wire listenPortRsp_V_full_... | 8.287233 |
module toe_m_axis_listen_port_rsp_fifo #(
parameter DATA_BITS = 8,
DEPTH_BITS = 4
) (
input wire clk,
input wire aclr,
output wire empty_n,
output wire full_n,
input wire read,
input wire ... | 8.287233 |
module toe_m_axis_listen_port_rsp_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [... | 8.287233 |
module toe_m_axis_notification_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
output wire TVALID,
input wire TREADY,
output wire [87:0] TDATA,
// User signals
input wire [80:0] notification_V_din,
output wire notification_V_ful... | 7.778493 |
module toe_m_axis_notification_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1... | 7.778493 |
module toe_m_axis_open_conn_rsp_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
output wire TVALID,
input wire TREADY,
output wire [23:0] TDATA,
// User signals
input wire [16:0] openConnRsp_V_din,
output wire openConnRsp_V_full... | 8.959194 |
module toe_m_axis_open_conn_rsp_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-... | 8.959194 |
module toe_m_axis_rxread_cmd_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
output wire TVALID,
input wire TREADY,
output wire [71:0] TDATA,
// User signals
input wire [71:0] rxBufferReadCmd_V_din,
output wire rxBufferReadCmd_V... | 8.494329 |
module toe_m_axis_rxread_cmd_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:0... | 8.494329 |
module toe_m_axis_rxwrite_cmd_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
output wire TVALID,
input wire TREADY,
output wire [71:0] TDATA,
// User signals
input wire [71:0] rxBufferWriteCmd_V_din,
output wire rxBufferWriteCm... | 8.494329 |
module toe_m_axis_rxwrite_cmd_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:... | 8.494329 |
module toe_m_axis_rxwrite_data_fifo #(
parameter DATA_BITS = 8,
DEPTH_BITS = 4
) (
input wire clk,
input wire aclr,
output wire empty_n,
output wire full_n,
input wire read,
input wire wri... | 8.494329 |
module toe_m_axis_rxwrite_data_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1... | 8.494329 |
module toe_m_axis_rx_data_rsp_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
output wire TVALID,
input wire TREADY,
output wire [63:0] TDATA,
output wire [ 7:0] TKEEP,
output wire [ 0:0] TLAST,
// User signals
input wire [63:0] rx... | 8.494329 |
module toe_m_axis_rx_data_rsp_fifo #(
parameter DATA_BITS = 8,
DEPTH_BITS = 4
) (
input wire clk,
input wire aclr,
output wire empty_n,
output wire full_n,
input wire read,
input wire writ... | 8.494329 |
module toe_m_axis_rx_data_rsp_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:... | 8.494329 |
module toe_m_axis_rx_data_rsp_metadata_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
output wire TVALID,
input wire TREADY,
output wire [15:0] TDATA,
// User signals
input wire [15:0] rxDataRspMeta_V_V_din,
output wire rxDataR... | 8.494329 |
module toe_m_axis_rx_data_rsp_metadata_fifo #(
parameter DATA_BITS = 8,
DEPTH_BITS = 4
) (
input wire clk,
input wire aclr,
output wire empty_n,
output wire full_n,
input wire read,
input wire ... | 8.494329 |
module toe_m_axis_rx_data_rsp_metadata_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output w... | 8.494329 |
module toe_m_axis_session_lup_req_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
output wire TVALID,
input wire TREADY,
output wire [103:0] TDATA,
// User signals
input wire [ 96:0] sessionLookup_req_V_din,
output wire ses... | 7.910423 |
module toe_m_axis_session_lup_req_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [... | 7.910423 |
module toe_m_axis_session_upd_req_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
output wire TVALID,
input wire TREADY,
output wire [111:0] TDATA,
// User signals
input wire [111:0] sessionUpdate_req_V_din,
output wire ses... | 7.910423 |
module toe_m_axis_session_upd_req_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [... | 7.910423 |
module toe_m_axis_tcp_data_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
output wire TVALID,
input wire TREADY,
output wire [63:0] TDATA,
output wire [ 7:0] TKEEP,
output wire [ 0:0] TLAST,
// User signals
input wire [72:0] ipTxD... | 7.873669 |
module toe_m_axis_tcp_data_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:0] ... | 7.873669 |
module toe_m_axis_txread_cmd_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
output wire TVALID,
input wire TREADY,
output wire [71:0] TDATA,
// User signals
input wire [71:0] txBufferReadCmd_V_din,
output wire txBufferReadCmd_V... | 8.66842 |
module toe_m_axis_txread_cmd_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:0... | 8.66842 |
module toe_m_axis_txwrite_cmd_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
output wire TVALID,
input wire TREADY,
output wire [71:0] TDATA,
// User signals
input wire [71:0] txBufferWriteCmd_V_din,
output wire txBufferWriteCm... | 8.66842 |
module toe_m_axis_txwrite_cmd_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:... | 8.66842 |
module toe_m_axis_txwrite_data_fifo #(
parameter DATA_BITS = 8,
DEPTH_BITS = 4
) (
input wire clk,
input wire aclr,
output wire empty_n,
output wire full_n,
input wire read,
input wire wri... | 8.66842 |
module toe_m_axis_txwrite_data_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1... | 8.66842 |
module toe_m_axis_tx_data_rsp_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
output wire TVALID,
input wire TREADY,
output wire [23:0] TDATA,
// User signals
input wire [16:0] txDataRsp_V_V_din,
output wire txDataRsp_V_V_full_n... | 8.66842 |
module toe_m_axis_tx_data_rsp_fifo #(
parameter DATA_BITS = 8,
DEPTH_BITS = 4
) (
input wire clk,
input wire aclr,
output wire empty_n,
output wire full_n,
input wire read,
input wire writ... | 8.66842 |
module toe_m_axis_tx_data_rsp_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:... | 8.66842 |
module toe_probe_timer_probeTimerTable_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 33;
parameter AWIDTH = 14;
parameter MEM_SIZE = 10000;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-... | 6.885215 |
module toe_probe_timer_probeTimerTable (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd33;
parameter AddressRange = 32'd10000;
parameter AddressWidth = 32'd14;
input reset;
input clk;
input [AddressWidth - 1:0] addres... | 6.885215 |
module toe_rx_sar_table_rx_table_appd_V_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 14;
parameter MEM_SIZE = 10000;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_styl... | 7.224988 |
module toe_rx_sar_table_rx_table_appd_V (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd10000;
parameter AddressWidth = 32'd14;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [... | 7.224988 |
module toe_rx_sar_table_rx_table_recvd_V_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 14;
parameter MEM_SIZE = 10000;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_sty... | 7.224988 |
module toe_rx_sar_table_rx_table_recvd_V (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd10000;
parameter AddressWidth = 32'd14;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input ... | 7.224988 |
module toe_state_table_state_table_1_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 4;
parameter AWIDTH = 14;
parameter MEM_SIZE = 10000;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input ... | 7.135654 |
module toe_state_table_state_table_1 (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd4;
parameter AddressRange = 32'd10000;
parameter AddressWidth = 32'd14;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
o... | 7.135654 |
module toe_s_axis_close_conn_req_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
input wire TVALID,
output wire TREADY,
input wire [15:0] TDATA,
// User signals
output wire [15:0] closeConnReq_V_V_dout,
output wire closeConnReq_... | 8.260126 |
module toe_s_axis_close_conn_req_fifo #(
parameter DATA_BITS = 8,
DEPTH_BITS = 4
) (
input wire clk,
input wire aclr,
output wire empty_n,
output wire full_n,
input wire read,
input wire w... | 8.260126 |
module toe_s_axis_close_conn_req_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N... | 8.260126 |
module toe_s_axis_listen_port_req_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
input wire TVALID,
output wire TREADY,
input wire [15:0] TDATA,
// User signals
output wire [15:0] listenPortReq_V_V_dout,
output wire listenPortR... | 7.814297 |
module toe_s_axis_listen_port_req_fifo #(
parameter DATA_BITS = 8,
DEPTH_BITS = 4
) (
input wire clk,
input wire aclr,
output wire empty_n,
output wire full_n,
input wire read,
input wire ... | 7.814297 |
module toe_s_axis_listen_port_req_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [... | 7.814297 |
module toe_s_axis_open_conn_req_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
input wire TVALID,
output wire TREADY,
input wire [47:0] TDATA,
// User signals
output wire [47:0] openConnReq_V_dout,
output wire openConnReq_V_emp... | 8.231243 |
module toe_s_axis_open_conn_req_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-... | 8.231243 |
module toe_s_axis_rxread_data_fifo #(
parameter DATA_BITS = 8,
DEPTH_BITS = 4
) (
input wire clk,
input wire aclr,
output wire empty_n,
output wire full_n,
input wire read,
input wire writ... | 7.789307 |
module toe_s_axis_rxread_data_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:... | 7.789307 |
module toe_s_axis_rxwrite_sts_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
input wire TVALID,
output wire TREADY,
input wire [7:0] TDATA,
// User signals
output wire [7:0] rxBufferWriteStatus_V_dout,
output wire rxBufferWriteStatu... | 7.789307 |
module toe_s_axis_rxwrite_sts_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:... | 7.789307 |
module toe_s_axis_rx_data_req_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
input wire TVALID,
output wire TREADY,
input wire [31:0] TDATA,
// User signals
output wire [31:0] rxDataReq_V_dout,
output wire rxDataReq_V_empty_n,
... | 7.789307 |
module toe_s_axis_rx_data_req_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:... | 7.789307 |
module toe_s_axis_session_lup_rsp_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
input wire TVALID,
output wire TREADY,
input wire [15:0] TDATA,
// User signals
output wire [15:0] sessionLookup_rsp_V_dout,
output wire sessionLo... | 7.981393 |
module toe_s_axis_session_lup_rsp_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [... | 7.981393 |
module toe_s_axis_session_upd_rsp_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
input wire TVALID,
output wire TREADY,
input wire [15:0] TDATA,
// User signals
output wire [15:0] sessionUpdate_rsp_V_dout,
output wire sessionUp... | 7.981393 |
module toe_s_axis_session_upd_rsp_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [... | 7.981393 |
module toe_s_axis_tcp_data_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
input wire TVALID,
output wire TREADY,
input wire [63:0] TDATA,
input wire [ 7:0] TKEEP,
input wire [ 0:0] TLAST,
// User signals
output wire [63:0] ipRxD... | 7.593196 |
module toe_s_axis_tcp_data_fifo #(
parameter DATA_BITS = 8,
DEPTH_BITS = 4
) (
input wire clk,
input wire aclr,
output wire empty_n,
output wire full_n,
input wire read,
input wire write,
... | 7.593196 |
module toe_s_axis_tcp_data_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:0] ... | 7.593196 |
module toe_s_axis_txread_data_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
input wire TVALID,
output wire TREADY,
input wire [63:0] TDATA,
input wire [ 7:0] TKEEP,
input wire [ 0:0] TLAST,
// User signals
output wire [72:0] tx... | 7.971983 |
module toe_s_axis_txread_data_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:... | 7.971983 |
module toe_s_axis_txwrite_sts_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
input wire TVALID,
output wire TREADY,
input wire [7:0] TDATA,
// User signals
output wire [7:0] txBufferWriteStatus_V_dout,
output wire txBufferWriteStatu... | 7.971983 |
module toe_s_axis_txwrite_sts_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:... | 7.971983 |
module toe_s_axis_tx_data_req_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
input wire TVALID,
output wire TREADY,
input wire [63:0] TDATA,
input wire [ 7:0] TKEEP,
input wire [ 0:0] TLAST,
// User signals
output wire [63:0] tx... | 7.971983 |
module toe_s_axis_tx_data_req_fifo #(
parameter DATA_BITS = 8,
DEPTH_BITS = 4
) (
input wire clk,
input wire aclr,
output wire empty_n,
output wire full_n,
input wire read,
input wire writ... | 7.971983 |
module toe_s_axis_tx_data_req_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:... | 7.971983 |
module toe_s_axis_tx_data_req_metadata_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
input wire TVALID,
output wire TREADY,
input wire [15:0] TDATA,
// User signals
output wire [15:0] txDataReqMeta_V_V_dout,
output wire txData... | 7.971983 |
module toe_s_axis_tx_data_req_metadata_fifo #(
parameter DATA_BITS = 8,
DEPTH_BITS = 4
) (
input wire clk,
input wire aclr,
output wire empty_n,
output wire full_n,
input wire read,
input wire ... | 7.971983 |
module toe_s_axis_tx_data_req_metadata_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output w... | 7.971983 |
module toe_tx_app_table_app_table_ackd_V_ram (
addr0,
ce0,
d0,
we0,
addr1,
ce1,
d1,
we1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 14;
parameter MEM_SIZE = 10000;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
input [AWIDTH-1:0... | 7.879755 |
module toe_tx_app_table_app_table_ackd_V (
reset,
clk,
address0,
ce0,
we0,
d0,
address1,
ce1,
we1,
d1,
q1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd10000;
parameter AddressWidth = 32'd14;
input reset;
input clk;
input [AddressWidth - 1:0] addr... | 7.879755 |
module toe_tx_sar_table_tx_table_app_V_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 14;
parameter MEM_SIZE = 10000;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-... | 7.363764 |
module toe_tx_sar_table_tx_table_app_V (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd10000;
parameter AddressWidth = 32'd14;
input reset;
input clk;
input [AddressWidth - 1:0] addres... | 7.363764 |
module toe_tx_sar_table_tx_table_cong_window_V_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
d1,
we1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 14;
parameter MEM_SIZE = 10000;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
out... | 7.363764 |
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