code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module TLB_entry (
//时钟信号
input wire clk,
input wire rst,
//VA-PA通道
//命令通道
input wire read,
input wire write,
input wire execute,
input wire access_rdy, //cache准备好，表示一次访问结束，TLB计数器加1
//地址通道
input wire [63:0] addr_va,
//反馈通道
//output wire load_page_fault,
//outpu... | 7.412594 |
module TLB_line_select (
//entry0
input wire entry0_valid, //该TLB entry有效
input wire [11:0] entry0_acc_count, //访问计数
input wire entry0_PTE_G, //全局有效
//entry1
input wire entry1_valid, //该TLB entry有效
input wire [11:0] entry1_acc_count, //访问计数
input wire entry1_PTE_G, //全局有效
//ent... | 7.755038 |
module tlb_lookup (
input [6:0] io_ptw_ptbr_asid,
input [26:0] io_req_bits_vpn,
input [33:0] tags_0,
input [33:0] tags_1,
input [33:0] tags_2,
input [33:0] tags_3,
input [33:0] tags_4,
input [33:0] tags_5,
input [33:0] tags_6,
input [33:0] tags_7,
input [7:0] valid,
input... | 6.552112 |
module tlb_req_trans (
input [1:0] state,
input io_ptw_resp_valid,
input tlb_miss,
input [33:0] r_refill_tag,
input r_req_instruction,
input r_req_store,
input io_ptw_status_pum,
input io_ptw_status_mxr,
input [1:0] io_ptw_status_prv,
output io_req_ready,
output io_ptw_req_v... | 7.405594 |
module TLB_select_cell (
//entry0
input wire [1:0] id0,
input wire entry0_valid, //该TLB entry有效
input wire [11:0] entry0_acc_count, //访问计数
input wire entry0_PTE_G, //全局有效
//entry1
input wire [1:0] id1,
input wire entry1_valid, //该TLB entry有效
input wire [11:0] entry1_acc_count, /... | 6.707642 |
module tlb_way_testbench;
`include "../sync_clk_gen_template.vh"
`include "armleocpu_defines.vh"
initial begin
#500 $finish;
end
reg [1:0] command;
// invalidate
reg [ENTRIES_W-1:0] invalidate_set_index;
// write
reg [7:0] accesstag_w;
reg [21:0] phys_w;
reg [19:0] virtual_address_w;
//... | 6.70855 |
module TLB_exp_handler (
input s0_found,
input s0_en,
input [1:0] s0_mem_type,
input s0_dmw_hit,
input found_v0,
input found_d0,
input [1:0] s0_plv,
input [1:0] found_plv0,
output [6:0] s0_exception,
input [31:0] s0_vaddr,
input s1_found,
input s1_en,
input [1:0] s1... | 6.76263 |
module tlc_test;
reg a, b;
reg clock;
reg reset;
wire [2:0] st;
wire RA, RB, YA, YB, GA, GB;
tlc uut (
clock,
reset,
a,
b,
RA,
YA,
GA,
RB,
YB,
GB,
st
);
initial begin
$dumpfile("tlc.vcd");
$dumpvars(0, tlc_test);
clock = 0;
... | 6.936445 |
module tlc5615b (
input wire clk, //50M
input wire rst_n,
output reg sclk, //1M
output wire cs,
output wire din,
input wire [9:0] datain
);
parameter D_N = 50 - 1;
reg [5:0] div_cnt;
reg [3:0] shift_cnt;
reg shift_en;
reg shift_flag;
reg shift... | 7.361991 |
module TLDA_master_interface (
// clock and reset
input clk,
input resetn,
// avalon master signals
input master_waitrequest,
output reg [31:0] master_address,
output reg master_write,
output reg [15:0] master_writedata,
output [1:0] master_byteenable,
// signals for LDA ... | 8.957208 |
module TLDA_peripheral (
// clock and reset signals
input csi_clockreset_clk,
input csi_clockreset_resetn,
// avalon slave signals
input avs_slave_chipselect,
input [2:0] avs_slave_address,
input avs_slave_read,
input avs_slave_write,
input [31:0] avs_slave_writedata,
... | 8.561742 |
module TLDA_slave_interface (
// clock and reset
input clk,
input resetn,
// avalon slave signals
input slave_chipselect,
input [ 2:0] slave_address,
input slave_read,
input slave_write,
input [31:0] slave_writedata,
output reg [31:0... | 7.502948 |
module greenscreen (
input wire [2:0] ri,
input wire [2:0] gi,
input wire [2:0] bi,
output wire [2:0] ro,
output wire [2:0] go,
output wire [2:0] bo,
input wire mono
);
reg [2:0] r;
reg [2:0] g;
reg [2:0] b;
assign go = mono ? r + g + b : gi;
assign ro = mono ? {1'b0, g[2:1]} : r... | 6.849634 |
module tld_pano_g2 (
input wire SYSCLK,
input wire PANO_BUTTON, // nivel bajo al pulsarlo
output wire LED_RED,
output wire LED_GREEN,
output wire LED_BLUE,
output wire GMII_RST_N // reset de la Marvell a nivel bajo
);
assign GMII_RST_N = ~PANO_BUTTON;
// con el boton pulsado, se desac... | 7.450759 |
module tld_sockit (
input wire clk50mhz, // cristal de 50 MHz
output wire [7:0] r, // Salidas R,G,B
output wire [7:0] g, // de 6 bits
output wire [7:0] b, // cada una
output wire hsync, // Sincronismos horizontal
output wire vsync, // y vertical
output wire VGA_CLK,
output wir... | 7.971645 |
module tld_unamiga (
input wire clk50mhz, // cristal de 50 MHz
output wire [5:0] r, // Salidas R,G,B
output wire [5:0] g, // de 6 bits
output wire [5:0] b, // cada una
output wire hsync, // Sincronismos horizontal
output wire vsync // y vertical
);
wire [7:0] r8b, g8b, b8b;
assig... | 7.970068 |
module tld_fantasma_zxdos (
input wire clk50mhz, // cristal de 50 MHz
output wire [5:0] r, // Salidas R,G,B
output wire [5:0] g, // de 6 bits
output wire [5:0] b, // cada una
output wire hsync, // Sincronismos horizontal
output wire vsync // y vertical
);
wire [7:0] r8b, g8b, b8b;
... | 7.222478 |
module tld_fantasma_zxuno (
input wire clk50mhz, // cristal de 50 MHz
output wire [2:0] r, // Salidas R,G,B
output wire [2:0] g, // de 3 bits
output wire [2:0] b, // cada una
output wire hsync, // Sincronismos horizontal
output wire vsync, // y vertical
output wire stdn, // con... | 7.222478 |
module tld_zxuno_v2 (
input wire clk50mhz,
output wire [2:0] r,
output wire [2:0] g,
output wire [2:0] b,
output wire hsync,
output wire vsync,
input wire ear,
inout wire clkps2,
inout wire dataps2,
inout wire mouseclk,
inout wire mousedata,
output wire audio_out_left,
... | 7.672643 |
module tld_zxuno_v3 (
input wire clk50mhz,
output wire [2:0] r,
output wire [2:0] g,
output wire [2:0] b,
output wire hsync,
output wire vsync,
input wire ear,
inout wire clkps2,
inout wire dataps2,
inout wire mouseclk,
inout wire mousedata,
output wire audio_out_left,
... | 7.855313 |
module tld_zxuno_v4 (
input wire clk50mhz,
output wire [2:0] r,
output wire [2:0] g,
output wire [2:0] b,
output wire hsync,
output wire vsync,
input wire ear,
inout wire clkps2,
inout wire dataps2,
inout wire mouseclk,
inout wire mousedata,
output wire audio_out_left,
... | 7.538829 |
module TLI4970 (
input clk,
input reset,
input read,
input address,
output signed [31:0] readdata,
output waitrequest,
input spi_miso,
output [NUMBER_OF_SENSORS-1:0] spi_cs,
output spi_clk
);
assign readdata = current[address];
parameter NUMBER_OF_SENSORS = 2;
parameter CLOCK... | 7.419307 |
module: uart_tlm
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tlm_tb;
// Inputs
reg fpgaClk_i;
reg clk_fb;
// Outputs
wire [2:0] chan_io;
wire clk_en;
wire sd_clk;
wire ... | 7.112422 |
module tlp_s_axi_cntrl ( /*AUTOARG*/
// Outputs
AWVALID,
AWADDR,
AWPROT,
AWREGION,
AWLEN,
AWSIZE,
AWBURST,
AWLOCK,
AWCACHE,
AWQOS,
AWID,
AWUSER,
WVALID,
WDATA,
WSTRB,
WLAST,
WUSER,
BREADY,
ARVALID,
ARADDR,
ARPROT,
ARREGION,
... | 7.080645 |
module tlp_tx #(
DOUBLE_WORD = 32, // 双字，32位
HEADER_SIZE = 4 * DOUBLE_WORD, // Header4个双字，取决于host内存空间是否大于4GB
TLP_DATA_WIDTH = 8 * DOUBLE_WORD // 数据荷载8个双字
) (
input clk,
input rst_n,
input in_ready,
output reg [T... | 7.102726 |
module tlu_incr64 (
in,
out
);
input [63:0] in;
output [63:0] out; // result of increment
assign out = in + 64'h01;
endmodule
| 7.099215 |
module TLV320 (
input clock,
output reg nCS,
output reg MOSI,
output reg SCLK,
output CMODE
);
reg [ 2:0] load;
reg [ 3:0] TLV;
reg [15:0] TLV_data;
reg [ 3:0] bit_cnt;
// Set up TLV320 data to send
always @* begin
case (load)
//3'd0: TLV_data = 16'h8889; // simulation test ... | 8.13493 |
module TLV320_SPI (
clk,
CMODE,
nCS,
MOSI,
SSCK,
boost,
line,
line_in_gain
);
input wire clk;
output wire CMODE;
output reg nCS;
output reg MOSI;
output reg SSCK;
input wire boost;
input wire line; // set when using line rather than mic input
input wire [4:0] line_in_ga... | 7.81941 |
module top (
input clk,
output tlvds_p,
output tlvds_n,
input key_i
);
wire key = key_i ^ `INV_BTN;
reg [24:0] ctr_q;
wire [24:0] ctr_d;
wire i_tick;
// Sequential code (flip-flop)
always @(posedge clk) ctr_q <= ctr_d;
// Combinational code (boolean logic)
assign ctr_d = ctr_q + 1'... | 7.233807 |
module tl_cntr_w_left (
clk,
reset_n,
Ta,
Tb,
Tal,
Tbl,
La,
Lb
);
input clk, reset_n, Ta, Tb, Tal, Tbl; // 6 inputs
output [1:0] La, Lb; // 2bits 2 outputs
wire [2:0] next_state; // 3bits wire
wire [2:0] state; // 3bits wire
_register3_r U0_register3_r (
.clk(clk),
... | 6.967823 |
module tl_cntr_w_left_be (
clk,
reset_n,
Ta,
Tb,
Tal,
Tbl,
La,
Lb
);
input clk, reset_n, Ta, Tb, Tal, Tbl; // 6 inputs
output [1:0] La, Lb; // 2 bits 2 output
wire [2:0] next_state; // 3bits wire
wire [2:0] state; // 3bits wire
_register3_r U0_register3_r (
.clk(clk... | 6.967823 |
module TL_Math2 (
clock,
reset,
start,
addIn,
subIn,
L_subIn,
T_op,
PIT_MIN,
PIT_MAX,
addOutA,
addOutB,
subOutA,
subOutB,
L_subOutA,
L_subOutB,
T0_min,
T0_max,
done
);
`include "paramList.v"
//inputs
input clock;
input reset;
input star... | 6.871475 |
module LFSR (
out,
clk,
rst
);
output reg [4:0] out;
input clk, rst;
wire feedback;
assign feedback = ~(out[2] ^ out[4]);
always @(posedge clk, posedge rst) begin
if (rst) out = 5'b0;
else out = {out[3:0], feedback};
end
endmodule
| 7.001839 |
module tm1637_tb;
reg clk, rst;
reg [7:0] data_byte;
reg data_latch, data_stop_bit;
wire busy, scl_en, scl_out, sda_en, sda_out;
reg sda_in;
tm1637 u_tm1637 (
.clk (clk),
.rst (rst),
.data_latch (data_latch),
.data_byte (data_byte),
.data_stop_bit(data... | 7.15832 |
module TM1638 (
reset,
clock,
data_in,
data_io,
strobe
);
input reset;
input clock;
input [7:0] data_in;
tri0 reset;
tri0 [7:0] data_in;
output data_io;
output strobe;
reg data_io;
reg reg_data_io;
reg strobe;
reg [8:0] fstate;
reg [8:0] reg_fstate;
parameter state1=0,stat... | 6.742421 |
module tm1638BtmDisp (
input wire CLK_IN,
input wire RST_IN,
output wire TM1638_STB,
output wire TM1638_CLK,
inout wire TM1638_DIO
);
parameter CLOCK_SLOW = 6; // Work in reel: drive1=[2-15] openDrain=[6-15]
parameter WRITE_SLOW = 0; // Nice with 20 for humain reading
parameter READ_SLOW... | 6.686042 |
module tm1638BtmDisp_tb();
reg CLK_IN;
reg RST_IN;
wire TM1638_STB;
wire TM1638_CLK;
tri1 TM1638_DIO;
reg [7:0] byte;
reg dio;
reg [2:0] hexaIndex;
glbl glbl();
defparam uut.CLOCK_SLOW = 0;
defparam uut.WRITE_SLOW = 0;
defparam uut.READ_SLOW = 0;
tm1638BtmDisp uut(
.CLK_IN(CLK_IN),
.RST_IN(RST_IN),
.TM1638_STB(... | 6.686042 |
module tm1638Cpt (
input wire CLK_IN,
input wire RST_IN,
output wire TM1638_STB,
output wire TM1638_CLK,
output wire TM1638_DIO
);
parameter CLOCK_SLOW = 5; // Work in reel between 2 and 15
parameter WRITE_SLOW = 20; // Nice with 20 for humain reading
wire tm1638Ready;
wire [7:0] tm163... | 6.778358 |
module tm1638Cpt_tb();
reg CLK_IN;
reg RST_IN;
wire TM1638_STB;
wire TM1638_CLK;
tri1 TM1638_DIO;
reg [7:0] byte;
glbl glbl();
defparam uut.CLOCK_SLOW = 0;
defparam uut.WRITE_SLOW = 0;
tm1638Cpt uut(
.CLK_IN(CLK_IN),
.RST_IN(RST_IN),
.TM1638_STB(TM1638_STB),
.TM1638_CLK(TM1638_CLK),
.TM1638_DIO(TM1638_DIO)
);... | 6.526589 |
module tm1638SegHex4 (
input wire CLK_IN,
input wire RST_IN,
input wire READY,
output reg READ_BUTTON,
output reg WRITE_SEG,
output reg [2:0] SEG_INDEX,
output wire [3:0] SEG_DATA,
input wire [31:0] SEG_HEX_ALL
);
localparam WRITE_SLOW = 5; // Nice with 20 for humain reading
localp... | 6.815954 |
module TB_TM1638_LED_KEY_DRV #(
parameter C_C = 10.0
)(
) ;
reg CK ;
initial begin
CK <= 1'b1 ;
forever begin
#( C_C /2) ;
CK <= ~ CK ;
end
end
reg XARST ;
initial begin
XARST <= 1'b1 ;
#( 0.1 * C_C) ;
XARST <= 1'... | 7.122013 |
module TM1638_shifter (
reset,
clock,
data_in,
data_io,
strobe
);
input reset;
input clock;
input [7:0] data_in;
tri0 reset;
tri0 [7:0] data_in;
output data_io;
output strobe;
reg data_io;
reg reg_data_io;
reg strobe;
reg [8:0] fstate;
reg [8:0] reg_fstate;
parameter state... | 6.612541 |
module tMDR;
wire [15:0] bus;
reg rOutEn, readEn, writeEn, reset;
wire [15:0] dToWriteOut;
reg [15:0] dReadIn;
MDR mdr (
bus,
dReadIn,
dToWriteOut,
readEn,
writeEn,
rOutEn,
reset
);
initial begin
rOutEn = 0;
#5 dReadIn = 16'd5;
readEn = 1;
#5 r... | 6.739352 |
module tmds_decode (
input clk,
input [9:0] in,
output data_valid,
output sync_valid,
output ctrl_valid,
output [7:0] data,
output [1:0] sync, // hsync/vsync
output [3:0] ctrl // audio header?
);
// the sync control bits are encoded with four specific patterns
parameter CTRL_00 = 1... | 7.591102 |
module tmdstest (
// {{{
// (i_clk, i_dtype, i_ctl, i_color, o_ctl, o_color);
input wire i_clk,
input wire [1:0] i_dtype,
input wire [1:0] i_ctl,
input wire [7:0] i_color,
//
output reg [1:0] o_ctl,
output reg [7:0] o_color
// }}}
);
// Local declarations
// {{{
reg [9:0] ... | 7.028243 |
module TMDS_8b10b_enc (
input rst,
input [7:0] d,
input [1:0] c,
input den,
input clk,
output [9:0] q
);
// I. fázis: q_m kiszámítása invert_d_m alapján
reg [7:0] d_m;
wire [8:0] q_m;
wire invert_d_m;
assign q_m = {~invert_d_m, d_m[7:0]};
always @(*) begin
if (rst) d_m <= 8'b0... | 6.722801 |
module used for simulation to test the encoder
// By Liam Davey (3/3/2011)
`timescale 1ns / 1ps
module tmds_decode (
input clk, input rst,
input [9:0] q_in,
output reg [7:0] d,
output reg c0,
output reg c1,
output reg de,
output reg signed [7:0] cnt);
reg [9:0] s1_q_in;
wire [7:0] d_q;
reg c0_1, c1_1, de_1... | 7.055139 |
module tmds_encoder_dvi (
input wire i_clk, // clock
input wire i_rst, // reset (active high)
input wire [7:0] i_data, // colour data
input wire [1:0] i_ctrl, // control data
input wire i_de, // display enable (active high)
output reg [9:0] o_tmds // encoded TM... | 6.697413 |
module tmds_encode_dvi_tb ();
reg rst;
reg clk;
reg [7:0] data;
reg [1:0] ctrl;
reg de;
wire [9:0] tmds;
reg [8:0] cycle;
// encoded TMDS data $display(...) is within tmds_encoder_dvi.v
initial begin
$display("\t 1s B O");
clk = 1;
rst = 1;
de = 0;
ctrl = ... | 7.516153 |
module tmds_encoder_tb ();
parameter CLOCKPERIOD = 10;
reg reset;
reg clock;
reg disp_en;
reg [1:0] ctrl;
reg [7:0] data;
wire [9:0] tmds;
// for counting the cycles
reg [15:0] cycle;
// module, parameters, instance, ports
tmds_encoder #() tmds_encoder (
.clk(clock),
.reset(r... | 6.697413 |
module tmds_encode_tb;
// Inputs
reg clk;
reg rst;
reg [7:0] d;
reg de;
reg c0;
reg c1;
// Outputs
wire [9:0] q_out;
wire [7:0] d_out;
wire de_out, c0_out, c1_out;
wire signed [7:0] count_out;
// Instantiate the Unit Under Test (UUT)
tmds_encode uut (
.clk(clk),
.rst(rst),
... | 6.69946 |
module TMDS_Serializer (
input [9:0] RedEncoded,
input [9:0] BlueEncoded,
input [9:0] GreenEncoded,
input PixClk,
input PixClk5,
output [3:0] TMDS /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */
);
wire Sync;
ClockSync CS (
.PixClk(PixClk),
.PixClk5(PixClk5),
... | 6.570039 |
module tmds_test (
input clk,
input enable,
output [3:0] tmds_p,
output [3:0] tmds_n
);
reg enable_r = 0;
reg test_a = 0, test_b = 0, test_c = 0, test_d = 0;
always @(posedge clk) begin
enable_r <= enable; // cross clock domains
test_a <= ~test_b & enable_r;
test_b <= test_a;
... | 7.55116 |
module tmds_test_tb;
integer cc;
reg clk, fail = 0;
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("tmds_test.vcd");
$dumpvars(5, tmds_test_tb);
end
$display("Non-checking testbench. Will always PASS");
for (cc = 0; cc < 100; cc = cc + 1) begin
clk = 0;
#2;
... | 7.288587 |
module tmds_top (
input wire pix_clk,
input wire sys_rst,
output wire [9:0] tmds_0,
output wire [9:0] tmds_1,
output wire [9:0] tmds_2,
output wire [9:0] tmds_3
);
//1920x1080@60Hz
parameter HPIXELS_HDTV1080P = 12'd1920; //Horizontal Live Pixels
parameter VLINES_HDTV1080P ... | 7.76149 |
module tmec_decode #(
parameter N = 15,
parameter K = 5,
parameter T = 3, /* Correctable errors */
parameter OPTION = "SERIAL"
) (
input clk,
input start,
input data_in,
output reg ready = 1,
output reg output_valid = 0,
output reg data_out = 0
);
`include "bch.vh"
localpa... | 7.797956 |
module tmec_decode_serial #(
parameter M = 4,
parameter T = 3 /* Correctable errors */
) (
input clk,
input syn_done,
input bsel,
input [log2(T)-1:0] bch_n,
input [M-1:0] syn1,
input [M*(2*T-1)-1:0] syn_shuffled,
output syn_shuffle,
output next_l,
output ch_start,
outp... | 6.724826 |
module Brightness_Adjustor (
input_pixel,
output_pixel
);
input [15:0] input_pixel;
output reg [15:0] output_pixel;
always @(*) begin
if (input_pixel[15]) output_pixel = {1'b1, input_pixel[15:1]} + 16'd50;
else output_pixel = {1'b0, input_pixel[15:1]} + 16'd50;
end
endmodule
| 7.196841 |
module TMM2064P #(
parameter FILE_NAME = "",
// CY6264 timing and naming conventions (or thereabouts)
parameter tAA = "0:100:100", // address access time
parameter tOHA = "10", // output data hold time from address change
parameter tACE = "0:100:100", // CE access time
parameter tLZCE = "10",... | 8.638044 |
module tmm_c (
input clk,
input rst_n,
input [19:0] m,
output reg clk_out
);
reg [19:0] count;
always @(posedge clk) begin
if (!rst_n) begin
count <= 0;
clk_out <= 0;
end else if (count == m - 1) begin
clk_out <= ~clk_out;
count <= 0;
end else if (count == ... | 6.544512 |
module tmm_c1 (
input clk,
input rst_n,
input [19:0] m,
output reg clk_out
);
reg [19:0] count;
always @(posedge clk) begin
if (!rst_n) begin
count <= 0;
clk_out <= 0;
end else if (count == m - 1) begin
clk_out <= ~clk_out;
count <= 0;
end else if (count ==... | 6.511921 |
module tmm_c2 (
input clk,
input rst_n,
input [19:0] m,
output reg clk_out
);
reg [19:0] count;
always @(posedge clk) begin
if (!rst_n) begin
count <= 0;
clk_out <= 0;
end else if (count == m - 1) begin
clk_out <= ~clk_out;
count <= 0;
end else if (count ==... | 6.502182 |
module TMON(
//inputs
RSTN,
ECLK,
TCLK,
//outputs
TSTOP,
TVAL,
);
//inputs
input RSTN;
input ECLK;
input TCLK;
... | 7.206186 |
module branching_mechanism(
input [31:0] pc_in,
input [31:0] dest_addr,
input [31:0] reg1,
input [1:0] branch_control_signal,
input [5:0] ins_func_code,
input [2:0] alu_flag,
input rst,
input clk,
output reg [31:0] pc_out,
output reg [31:0] ref
);
/*
name ins_f... | 8.68257 |
module TmpImage_Test_bench ();
reg clk;
wire clkout;
wire [7:0] scaler;
reg rst;
TempImgCreator uut (
.CLK(clk),
.CLKOUT(clkout),
.dataOut(scaler),
.reset(rst)
);
initial begin
clk = 0;
forever begin
#1 clk = ~clk;
end
end
initial begin
$display("Test... | 6.536572 |
module tmp_FakeMouse (
input clk,
input upBtn,
input downBtn,
input leftBtn,
input rightBtn,
output reg [9:0] xPos,
output reg [9:0] yPos
);
initial begin
xPos = 320;
yPos = 240;
end
///////////////////////////////////////////////////////////////
//Flags for the control o... | 6.997715 |
module mealyFSM (
output reg o_d,
input i_d,
input clk,
input reset_n
);
parameter IDLE = 2'b00;
parameter S0 = 2'b01;
// inner state/next_state
reg [1:0] state, next_state;
reg o_d_next;
//state
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
state <= IDLE;
... | 9.012849 |
module timer_controller #(
parameter DIV = `TMR_DIV // 0<DIV<=65536
) (
input wire clk,
input wire rstn, // sync
output wire interrupt,
// user interface
input wire [$clog2(`TMR_SIZE)-1:0] addr,
input wire w_rb,
input wire [ `BUS_ACC_WIDTH-1:0] acc,
ou... | 6.879247 |
module timer0_tb;
//---------------------------------------------------------------------------//
//--------------------Constant Parameter-------------------------------------//
//---------------------------------------------------------------------------//
localparam integer PERIOD = 50; // 20 MHz cloc... | 6.856016 |
module timer0_tb;
//---------------------------------------------------------------------------//
//--------------------Constant Parameter-------------------------------------//
//---------------------------------------------------------------------------//
localparam integer PERIOD = 50; // 20 MHz cloc... | 6.856016 |
module TMR32_tb;
reg clk;
reg rst_n;
wire [31:0] TMR;
wire [31:0] CAPTURE;
reg [15:0] PRE;
reg [31:0] CMP;
reg [31:0] LOAD;
wire OVF;
wire CMPF;
wire EEVF; // Trigger event flag for Capture mode.
reg OVF_CLR;
reg CMPF_CLR;
reg EE... | 6.777026 |
module tmr_wrapper (
input wire clk,
input wire rstn,
input wire [ `XLEN-1:0] p_addr, // byte addr
input wire p_w_rb,
input wire [$clog2(`BUS_ACC_CNT)-1:0] p_acc,
output wire [ `BUS_WIDTH-1:0] p_rdata,
input wire [ `BUS_WIDTH... | 7.586999 |
module tmu2_adrgen #(
parameter fml_depth = 26
) (
input sys_clk,
input sys_rst,
output busy,
input pipe_stb_i,
output pipe_ack_o,
input [10:0] dx_c,
input [10:0] dy_c,
input [16:0] tx_c,
input [16:0] ty_c,
input [fml_depth-1-1:0] dst_fbuf, /* in 16-bit words */
input... | 7.249982 |
module tmu2_alpha #(
parameter fml_depth = 26
) (
input sys_clk,
input sys_rst,
output busy,
input [5:0] alpha,
input additive,
input pipe_stb_i,
output pipe_ack_o,
input [15:0] color,
input [fml_depth-1-1:0] dadr, /* in 16-bit words */
input [15:0] dcolor,
output pi... | 7.513079 |
module tmu2_buffer #(
parameter width = 8,
parameter depth = 1 /* < log2 of the storage size, in words */
) (
input sys_clk,
input sys_rst,
output busy,
input pipe_stb_i,
output pipe_ack_o,
input [width-1:0] dat_i,
output pipe_stb_o,
input pipe_ack_i,
output [width-1:0] ... | 8.264058 |
module tmu2_burst #(
parameter fml_depth = 26
) (
input sys_clk,
input sys_rst,
input flush,
output reg busy,
input pipe_stb_i,
output pipe_ack_o,
input [15:0] color,
input [fml_depth-1-1:0] dadr, /* in 16-bit words */
output reg pipe_stb_o,
input pipe_ack_i,
output r... | 7.408583 |
module tmu2_clamp (
input sys_clk,
input sys_rst,
output busy,
input pipe_stb_i,
output pipe_ack_o,
input signed [11:0] dx,
input signed [11:0] dy,
input signed [17:0] tx,
input signed [17:0] ty,
input [10:0] tex_hres,
input [10:0] tex_vres,
input [10:0] dst_hres,
... | 8.12267 |
module tmu2_decay #(
parameter fml_depth = 26
) (
input sys_clk,
input sys_rst,
output busy,
input [5:0] brightness,
input chroma_key_en,
input [15:0] chroma_key,
input pipe_stb_i,
output pipe_ack_o,
input [15:0] color,
input [fml_depth-1-1:0] dadr,
output pipe_stb_o,... | 7.460965 |
module tmu2_divider17 (
input sys_clk,
input sys_rst,
input start,
input [16:0] dividend,
input [16:0] divisor,
output ready,
output [16:0] quotient,
output [16:0] remainder
);
reg [33:0] qr;
assign remainder = qr[33:17];
assign quotient = qr[16:0];
reg [4:0] counter;
ass... | 6.992145 |
module tmu2_dpram #(
parameter depth = 11, /* < log2 of the capacity in words */
parameter width = 32
) (
input sys_clk,
input [depth-1:0] ra,
input re,
output [width-1:0] rd,
input [depth-1:0] wa,
input we,
input [width-1:0] wd
);
reg [width-1:0] ram [0:(1 << depth)-1];
reg... | 6.711363 |
module tmu2_fdest #(
parameter fml_depth = 26
) (
input sys_clk,
input sys_rst,
output [fml_depth-1:0] fml_adr,
output reg fml_stb,
input fml_ack,
input [63:0] fml_di,
input flush,
output busy,
input fetch_en,
input pipe_stb_i,
output reg pipe_ack_o,
input [15:0]... | 7.72567 |
module tmu2_fetchtexel #(
parameter depth = 2,
parameter fml_depth = 26
) (
input sys_clk,
input sys_rst,
output busy,
input pipe_stb_i,
output pipe_ack_o,
input [fml_depth-5-1:0] fetch_adr,
output pipe_stb_o,
input pipe_ack_i,
output [255:0] fetch_dat,
output reg [fm... | 7.942828 |
module tmu2_fifo64to256 #(
parameter depth = 2 /* < log2 of the capacity, in 256-bit words */
) (
input sys_clk,
input sys_rst,
output w8avail,
input we,
input [63:0] wd,
output ravail,
input re,
output [255:0] rd
);
reg [63:0] storage1[0:(1 << depth)-1];
reg [63:0] storage2[... | 7.024547 |
module tmu2_hdiv (
input sys_clk,
input sys_rst,
output busy,
input pipe_stb_i,
output reg pipe_ack_o,
input signed [11:0] x,
input signed [11:0] y,
input signed [17:0] tsx,
input signed [17:0] tsy,
input diff_x_positive,
input [16:0] diff_x,
input diff_y_positive,
... | 8.417747 |
module tmu2_hdivops (
input sys_clk,
input sys_rst,
output busy,
input pipe_stb_i,
output pipe_ack_o,
input signed [11:0] x,
input signed [11:0] y,
input signed [17:0] tsx,
input signed [17:0] tsy,
input signed [17:0] tex,
input signed [17:0] tey,
output reg pipe_stb_o... | 7.083673 |
module tmu2_hinterp (
input sys_clk,
input sys_rst,
output busy,
input pipe_stb_i,
output pipe_ack_o,
input signed [11:0] x,
input signed [11:0] y,
input signed [17:0] tsx,
input signed [17:0] tsy,
input diff_x_positive,
input [16:0] diff_x_q,
input [16:0] diff_x_r,
... | 7.460486 |
module tmu2_mask (
input sys_clk,
input sys_rst,
output busy,
input pipe_stb_i,
output pipe_ack_o,
input signed [11:0] dx,
input signed [11:0] dy,
input signed [17:0] tx,
input signed [17:0] ty,
input [17:0] tex_hmask,
input [17:0] tex_vmask,
output reg pipe_stb_o,
... | 7.815317 |
module tmu2_mult2 (
input sys_clk,
input ce,
input [12:0] a,
input [12:0] b,
output reg [25:0] p
);
reg [25:0] temp;
always @(posedge sys_clk) begin
if (ce) begin
temp <= a * b;
p <= temp;
end
end
endmodule
| 6.532892 |
module tmu2_mult2 (
input sys_clk,
input ce,
input [12:0] a,
input [12:0] b,
output [25:0] p
);
DSP48 #(
.AREG(1), // Number of pipeline registers on the A input, 0, 1 or 2
.BREG(1), // Number of pipeline registers on the B input, 0, 1 or 2
.B_INPUT("DIRECT"), // B input D... | 6.532892 |
module tmu2_pixout #(
parameter fml_depth = 26
) (
input sys_clk,
input sys_rst,
output reg busy,
input pipe_stb_i,
output reg pipe_ack_o,
input [fml_depth-5-1:0] burst_addr,
input [15:0] burst_sel,
input [255:0] burst_do,
output reg [fml_depth-1:0] fml_adr,
output reg fml... | 7.094597 |
module tmu2_qpram #(
parameter depth = 11 /* < log2 of the capacity in bytes */
) (
input sys_clk,
input [depth-1:0] raa, /* < in bytes, 16-bit aligned */
output reg [15:0] rda,
input [depth-1:0] rab,
output reg [15:0] rdb,
input [depth-1:0] rac,
output reg [15:0] rdc,
input [dept... | 8.471702 |
module tmu2_qpram32 #(
parameter depth = 11 /* < log2 of the capacity in 32-bit words */
) (
input sys_clk,
/* 32-bit read port 1 */
input [depth-1:0] a1,
output [31:0] d1,
/* 32-bit read port 2 */
input [depth-1:0] a2,
output [31:0] d2,
/* 32-bit read port 3 */
input [depth-... | 7.824017 |
module tmu2_qpram32 #(
parameter depth = 11 /* < log2 of the capacity in 32-bit words */
) (
input sys_clk,
/* 32-bit read port 1 */
input [depth-1:0] a1,
output [31:0] d1,
/* 32-bit read port 2 */
input [depth-1:0] a2,
output [31:0] d2,
/* 32-bit read port 3 */
input [depth-... | 7.824017 |
module tmu2_serialize #(
parameter fml_depth = 26
) (
input sys_clk,
input sys_rst,
output reg busy,
input pipe_stb_i,
output reg pipe_ack_o,
input [fml_depth-5-1:0] tadra,
input [fml_depth-5-1:0] tadrb,
input [fml_depth-5-1:0] tadrc,
input [fml_depth-5-1:0] tadrd,
input mi... | 7.010921 |
module tmu2_split #(
parameter cache_depth = 13,
parameter fml_depth = 26
) (
input sys_clk,
input sys_rst,
output busy,
input pipe_stb_i,
output pipe_ack_o,
input [fml_depth-1-1:0] dadr,
input [fml_depth-1:0] tadra,
input [fml_depth-1:0] tadrb,
input [fml_depth-1:0] tadr... | 6.689224 |
module tmu2_vdiv (
input sys_clk,
input sys_rst,
output busy,
input pipe_stb_i,
output reg pipe_ack_o,
input signed [17:0] ax,
input signed [17:0] ay,
input signed [17:0] bx,
input signed [17:0] by,
input diff_cx_positive,
input [16:0] diff_cx,
input diff_cy_positive,
... | 8.552412 |
module tmu2_vdivops (
input sys_clk,
input sys_rst,
output busy,
input pipe_stb_i,
output pipe_ack_o,
input signed [17:0] ax,
input signed [17:0] ay,
input signed [17:0] bx,
input signed [17:0] by,
input signed [17:0] cx,
input signed [17:0] cy,
input signed [17:0] dx,
... | 6.960093 |
module tmu2_vinterp (
input sys_clk,
input sys_rst,
output busy,
input pipe_stb_i,
output pipe_ack_o,
input signed [17:0] ax,
input signed [17:0] ay,
input signed [17:0] bx,
input signed [17:0] by,
input diff_cx_positive,
input [16:0] diff_cx_q,
input [16:0] diff_cx_r,
... | 6.968315 |
module TM_ALU (
clk,
reset,
AvgTxLen, // 8-bit input
InstExed, // 8-bit input
CurTxLen, // 8-bit input
AvgTxLen_new, // 8-bit output
InstExed_new // 8-bit output
);
parameter WIDTH = 8; // Width of inputs
input clk, reset;
input [WIDTH - 1:0] AvgTxLen, CurTxLen;
input [WIDTH... | 7.460141 |
module TM_IF_ID_Stage;
reg clk, rst;
reg [31:0] PC_in, Ins_in;
wire [31:0] PC_out, Ins_out;
IF_ID_Stage stage1 (
PC_in,
Ins_in,
PC_out,
Ins_out,
clk,
rst
);
parameter t = 100;
always #(t / 2) clk = ~clk;
initial begin
$dumpfile("wave.vcd");
$dumpvars;
... | 6.543354 |
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