code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module tx_checkTimeout_dev_mul_65s_67ns_131_6_1 (
clk,
reset,
ce,
din0,
din1,
dout
);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input [din0_WIDT... | 6.500458 |
module tx_checkTimeout_dev_regslice_both #(
parameter DataWidth = 32
) (
input ap_clk,
input ap_rst,
input [DataWidth-1:0] data_in,
input vld_in,
output ack_in,
output [DataWidth-1:0] data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;... | 6.500458 |
module tx_checkTimeout_dev_regslice_both_w1 #(
parameter DataWidth = 1
) (
input ap_clk,
input ap_rst,
input data_in,
input vld_in,
output ack_in,
output data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire B_V_data_1_data... | 6.500458 |
module tx_clk_gen #(
parameter CLK_FREQUENCE = 50_000_000, //hz
BAUD_RATE = 9600 //9600、19200 、38400 、57600 、115200、230400、460800、921600
) (
input clk, //system_clk
input rst_n, //system_reset
input tx_done, //once_tx_done
input tx_start, //once_tx_start
ou... | 7.718982 |
module tx_controller_3bytes (
input clk,
input tx_start,
input [15:0] data_in,
output UART_TxD,
output tx_done
);
reg start_byte_tx_reg = 1'd0; // s_uart_tx
wire local_uart_busy; // s_uart_tx
assign local_uart_ready = ~local_uart_busy;
reg [7:0] tx_byte_reg = 'd0; // s_uart_tx
... | 7.938688 |
module
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tx_control_module(
CLK,
RST_n,
Tx_En_S... | 7.088073 |
module tx_ctrl_phase_tb;
parameter VCD_FILE = "tx_ctrl_phase.vcd";
parameter NUM_LANES = 1;
parameter BEATS_PER_LMFC = 20;
`include "tb_base.v"
reg lmfc_edge = 1'b0;
reg a_sync = 1'b0;
reg b_sync = 1'b0;
wire [31:0] a_ilas_data;
wire [3:0] a_ilas_charisk;
wire [1:0] a_ilas_config_addr;
wire a_i... | 7.280345 |
module TX_DATA_COLLECTION_STATE_MACHINE (
input i_Clk,
input [63:0] number_of_ticks,
input w_TX_Active,
output w_TX_DV,
output [7:0] w_TX_Byte_reg
);
reg [3:0] byte_counter;
reg [7:0] store_nt[7:0];
reg [7:0] w_TX_Byte_reg_0;
reg [2:0] state_TX;
reg w_TX_DV_0;
parameter WAIT_TX = 3'd0,... | 6.748206 |
module tx_dev_mem_management_regslice_both #(
parameter DataWidth = 32
) (
input ap_clk,
input ap_rst,
input [DataWidth-1:0] data_in,
input vld_in,
output ack_in,
output [DataWidth-1:0] data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_stat... | 6.634838 |
module tx_dev_mem_management_regslice_both_w1 #(
parameter DataWidth = 1
) (
input ap_clk,
input ap_rst,
input data_in,
input vld_in,
output ack_in,
output data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire B_V_data_1_da... | 6.634838 |
module tx_dp (
input wire rst,
input wire tx_en,
input wire [7:0] din,
input wire [9:0] bit_cnto,
output reg tx_out
);
always @* begin
casex ({
rst, tx_en, bit_cnto
})
{1'b0, 1'bx, 10'dx} : tx_out = 1'b1; // reset control
{1'b1, 1'b0, 10'dx} : tx_out = 1'b1; // No ... | 7.138003 |
module implements the transmitter PHY for an IEEE-1355 link.
// The TxClk signal determines the actual transmission rate: one bit
// per rising edge of TxClk.
//
// The input-side of this module consists mainly of three signals:
//
// TxReset - if asserted, it forces D and S outputs 0.
// Tx1 - If asserted, it flips D ... | 7.842559 |
module tx_dual_port_ram_8bit #(
parameter DATA_WIDTH = 8,
parameter ADDR_WIDTH = 6
) (
input [(DATA_WIDTH-1):0] data_a,
data_b,
input [(ADDR_WIDTH-1):0] addr_a,
addr_b,
input we_a,
we_b,
clk,
output reg [(DATA_WIDTH-1):0] q_a,
q_b
);
// Declare the RAM variable
reg [DATA... | 8.498193 |
module tx_eight_ten (
input wire clk,
input wire rst,
input wire sel,
input wire set,
input wire [7:0] din,
input wire [19:0] baud,
output wire tx_en,
output wire tx_out,
output wire [9:0] tx_d
);
wire [9:0] bit_cnto;
wire [9:0] bit_cntn;
wire [19:0] baud_cnto;
wire [19:0] ... | 6.951924 |
module tx_eight_ten_cp (
input wire rst,
input wire sel,
input wire set,
input wire baud_clk,
input wire [9:0] bit_cnto,
input wire [19:0] baud,
output reg [9:0] bit_cntn,
output reg tx_en
);
wire valid_baud;
assign valid_baud = (baud >= 20'd15) ? 1'b1 : 1'b0;
a... | 7.463176 |
module tx_eight_ten_dp (
input wire rst,
input wire tx_en,
input wire [9:0] tx_d,
input wire [9:0] bit_cnto,
output reg tx_out
);
always @* begin
casex ({
rst, tx_en, bit_cnto
})
{1'b1, 1'bx, 10'dx} : tx_out = 1'b1; // reset control
{1'b0, 1'b0, 10'dx} : tx_out = 1'... | 7.463176 |
module tx_eight_ten_tb ();
localparam period = 5;
localparam cycle = period * 2;
reg clk;
reg rst;
reg sel;
reg set;
reg [ 7:0] din;
reg [19:0] baud;
wire tx_en;
wire tx_out;
wire [ 9:0] tx_d;
tx_eight_ten tx_eight_ten (
.clk (clk),
... | 7.463176 |
module tx_enc8 ( // input
input CLK_40,
input RST_X,
input VALID,
input SYN_RST,
input [7:0] DATA_IN,
output reg [15:0] DATA_OUT
);
reg [5:0] r_enc0;
wire [5:0] r_enc1, r_enc2, r_enc3, r_enc4, r_enc5, r_enc6, r_enc7, r_enc8;
wire [15:0] code;
assign r_enc1 = {DATA_IN[0], r_enc0[5:1]... | 7.132013 |
module tx_phi #(
parameter C_PCI_DATA_WIDTH = 10'd128,
parameter C_MUX_TYPE = "SHIFT",
parameter C_WIDTH = (C_PCI_DATA_WIDTH + 2 * (clog2s(C_PCI_DATA_WIDTH / 32) + 1))
) ( // Interface: Clocks
input CLK,
// Interface: Resets
input RST_IN,
// Interface: TXC Flow Control
input TXC_TLP_R... | 9.141296 |
module tx_engine_formatter_128 #(
parameter C_PCI_DATA_WIDTH = 9'd128,
// Local parameters
parameter C_TRAFFIC_CLASS = 3'b0,
parameter C_RELAXED_ORDER = 1'b0,
parameter C_NO_SNOOP = 1'b0
) (
input CLK,
input RST,
input [15:0] CONFIG_COMPLETER_ID,
input VALID, ... | 8.607781 |
module tx_engine_formatter_32 #(
parameter C_PCI_DATA_WIDTH = 9'd32,
// Local parameters
parameter C_TRAFFIC_CLASS = 3'b0,
parameter C_RELAXED_ORDER = 1'b0,
parameter C_NO_SNOOP = 1'b0
) (
input CLK,
input RST,
input [15:0] CONFIG_COMPLETER_ID,
input VALID, ... | 8.607781 |
module tx_engine_formatter_64 #(
parameter C_PCI_DATA_WIDTH = 9'd64,
// Local parameters
parameter C_TRAFFIC_CLASS = 3'b0,
parameter C_RELAXED_ORDER = 1'b0,
parameter C_NO_SNOOP = 1'b0
) (
input CLK,
input RST,
input [15:0] CONFIG_COMPLETER_ID,
input VALID, ... | 8.607781 |
module tx_fifo (
rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty,
rd_data_count,
wr_data_count
);
input rst;
input wr_clk;
input rd_clk;
input [63 : 0] din;
input wr_en;
input rd_en;
output [7 : 0] dout;
output full;
output empty;
output [13 : 0... | 7.105997 |
module tx_fifo_ext (
clk,
din,
rd_en,
rst,
wr_en,
dout,
empty,
full,
prog_full
);
input clk;
input [63 : 0] din;
input rd_en;
input rst;
input wr_en;
output [63 : 0] dout;
output empty;
output full;
output prog_full;
// synthesis translate_off
FIFO_GENERATOR... | 6.855826 |
module tx_fill_parts #(
parameter WIDTH = 16
) (
input reset,
input s_ul_clk,
input incb_valid,
output incb_ready,
input [WIDTH-1:0] incb_size,
input [ 4:0] incb_idx,
input decb_valid,
input [WIDTH-1:0] decb_size,
input [ 4:0] de... | 7.314249 |
module tx_frontend #(
parameter BASE = 0,
parameter WIDTH_OUT = 16,
parameter IQCOMP_EN = 1
) (
input clk,
input rst,
input set_stb,
input [7:0] set_addr,
input [31:0] set_data,
input [23:0] tx_i,
input [23:0] tx_q,
input run,
output reg [WIDTH_OUT-1:0] dac_a,
output ... | 6.690853 |
module tx_gate (
out,
sel,
in
);
output out;
input sel, in;
wire sel_bar;
pmos (out, in, sel_bar);
nmos (out, in, sel);
cmos_inverter inv (
sel_bar,
sel
);
pulldown (out);
endmodule
| 6.815097 |
module tx_get (
input clk,
input rst_n,
//ǰ
input pre_frame_vsync,
input pre_frame_href,
input pre_frame_clken,
input [7 : 0] pre_img,
input [7 : 0] A_value,
//
output post_frame_vsync,
output post_frame_href,
... | 7.756549 |
module tx_ibuf #(
parameter AW = 9,
parameter DW = 64
) (
input [AW-1:0] a,
input [DW-1:0] d,
input we,
input [AW-1:0] dpra,
input clk,
input qdpo_clk,
output reg [DW-1:0] qdpo
);
//-----------------------------------------... | 7.694022 |
module is used to replace the K28.5 comma with K28.5+ / K28.6- when
// manchest is enable
// so the received side can detect the polarity according to the received
// K28.5 and K28.6 comma's polarity
// K28.5+: 0011111010 K28.5-: 1100000101 (lsb to msb)
// K28.6+: 0011110110 K28.6-: 1100001001
/... | 9.406588 |
module tx_interrupt_selection (
// selection
input wire [2:0] src_sel,
// src
input wire s00_axis_tlast,
input wire phy_tx_start,
input wire tx_start_from_acc,
input wire tx_end_from_acc,
input wire tx_try_complete,
// to ps interrupt
output reg tx_itrpt
);
always @( src_sel... | 7.390375 |
module tx_intf_ant_selection #(
parameter integer IQ_DATA_WIDTH = 16,
parameter integer DAC_PACK_DATA_WIDTH = 64
) (
input wire [DAC_PACK_DATA_WIDTH-1 : 0] data_in,
input wire [1:0] ant_flag,
output reg [DAC_PACK_DATA_WIDTH-1 : 0] data_out
);
localparam integer MSB_IDX = (DAC_PACK_DATA_WIDTH - 1)... | 6.539945 |
module tx_intf_pl_to_m_axis #(
parameter integer C_M00_AXIS_TDATA_WIDTH = 64
) (
// to m_axis and PS
output wire start_1trans_to_m_axis,
output wire [(C_M00_AXIS_TDATA_WIDTH-1) : 0] data_to_m_axis,
output wire data_ready_to_m_axis,
input wire fulln_from_m_axis,
// start m_axis trans mode
... | 6.968967 |
module tx_lock (
input wire pclk,
input wire rst,
input wire [7:0] data_in,
output reg tx_start,
output reg [7:0] data_out
);
localparam IDLE = 2'b00;
localparam START = 2'b01;
localparam LOCKED = 2'b10;
localparam COUNTER_LIMIT = 28700;
reg [7:0] temp_data;
reg [1:0] state, next_state... | 8.086284 |
module tx_logic (
item_in,
read,
empty,
table_addr,
table_data,
item_out,
n_ena,
n_busy,
s_ena,
s_busy,
e_ena,
e_busy,
w_ena,
w_busy,
l_ena,
l_busy
);
input empty, n_busy, s_busy, e_busy, w_busy, l_busy;
output read, s_ena, n_ena, e_ena, w_ena, l_ena... | 6.742217 |
module TX_MAC_TB ();
reg SYS_CLK;
reg SYS_RST;
reg TX_START;
wire TX_BUSY;
wire [7:0] GMII_TXD;
wire GMII_TX_EN;
reg [7:0] CONTROL_IN;
TX_MAC inst_TX_MAC (
.TX_CLK(SYS_CLK),
.SYS_RST(SYS_RST),
.TX_START(TX_START),
.TX_BUSY(TX_BUSY),
.GMII_TXD(GMII_TXD),
.GMII_TX_EN... | 7.725735 |
module Tx_modifier (
Tx_tick_retreiver,
wen_retreiver,
Tx_tick_Tx,
wen_Tx,
end_address,
address
);
input wen_retreiver;
input Tx_tick_Tx;
input [17:0] address;
input [17:0] end_address;
output wen_Tx;
output Tx_tick_retreiver;
reg mux_out = 0;
//hijack transmit signals when... | 7.054779 |
module
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tx_module(
CLK,
RST_n,
Tx_En_Sig,
... | 7.088073 |
module tx_module_2 #(
parameter BPS = 13'd434
) (
clk,
rst_n,
tx_en_sig,
tx_data,
tx_pin
);
input clk;
input rst_n;
input tx_en_sig;
input [7:0] tx_data;
output reg tx_pin;
/***********************/
/*
//每个bit所占用的clk个数
localparam BPS_50MHz_9600 = 13'd5208; *10 = 5... | 7.091302 |
module tx_module_3 #(
parameter BPS = 13'd434
) (
clk,
rst_n,
tx_en_sig,
tx_data,
tx_done,
tx_pin
);
input clk;
input rst_n;
input tx_en_sig;
input [7:0] tx_data;
output reg tx_done;
output reg tx_pin;
/***********************/
/*
//每个bit所占用的clk个数
localparam BPS_5... | 7.993215 |
module tx_module_before #(
parameter BPS_CLK = 13'd433
) (
clk,
rst_n,
tx_en_sig,
tx_data,
tx_done,
tx_pin
);
input clk;
input rst_n;
input tx_en_sig;
input [7:0] tx_data;
output tx_done;
output tx_pin;
/***********************/
/*
parameter BPS_50MHz_9600 = 13'd520... | 6.723499 |
module TX_MUX #(
// RX/TX interface data width
parameter C_DATA_WIDTH = 64,
parameter TCQ = 1,
// TSTRB width
parameter KEEP_WIDTH = C_DATA_WIDTH / 8
) (
input wire clk,
input wire sys_rst,
// AXIS Output
input wire s_axis_tx_tready,
output wire [C_DATA_WIDTH-1:0] s_axis_tx_tdata... | 9.010156 |
module Tx_Out (
input CLK_I,
RST_I,
input [31:0] DAT_I,
input CYC_I,
WE_I,
STB_I,
output ACK_O,
output reg [31:0] DAT_O,
output reg CYC_O,
STB_O,
output WE_O,
input ACK_I
);
reg [31:0] Pre[0:319];
//assign {datafile[0], dataf... | 7.562738 |
module Tx_outputsel (
input [1:0] STM_ctrl_outputsel
, input Shift_data_bit
, input Parity_data
, output reg outputsel_data_bit
);
parameter Parity = 3;
parameter STOP = 0;
parameter DATA = 2;
parameter START = 1;
always @(*) begin
case (STM_ctrl_outputsel)
STOP: begin
output... | 7.130672 |
module tx_packer ( //FX2 Side
input bus_reset,
input usbclk,
input WR_fx2,
input [15:0] usbdata,
// TX Side
input reset,
input txclk,
output reg [31:0] usbdata_final,
output reg WR_final
);
reg [8:0] write_count;
/* Fix FX2 bug */
always @(posedge usbclk) begin
if (bus_... | 6.914362 |
module tx_packet_ctrl_fifo (
din,
rd_clk,
rd_en,
rst,
wr_clk,
wr_en,
dout,
empty,
full,
overflow,
prog_full
);
input [63 : 0] din;
input rd_clk;
input rd_en;
input rst;
input wr_clk;
input wr_en;
output [63 : 0] dout;
output empty;
output full;
output ov... | 6.681531 |
module tx_packet_fifo (
din,
rd_clk,
rd_en,
rst,
wr_clk,
wr_en,
dout,
empty,
full,
overflow,
prog_full
);
input [63 : 0] din;
input rd_clk;
input rd_en;
input rst;
input wr_clk;
input wr_en;
output [63 : 0] dout;
output empty;
output full;
output overflo... | 6.704782 |
module tx_parity_gen (
tx_data_in,
load,
parity_bit
);
input [7:0] tx_data_in;
input load;
output reg parity_bit;
always @(*)
if (load == 0) parity_bit = 1'b0;
else parity_bit = ^(tx_data_in);
endmodule
| 6.510215 |
module tx_pkt_fifo_8192x256 (
reset_,
wrclk,
wren,
datain,
wrfull,
wrusedw,
rdclk,
rden,
dataout,
rdempty,
rdusedw
);
parameter WIDTH = 256, DEPTH = 1024, PTR = 10;
input wire reset_;
input wire wrclk; // Clk for writing data
inpu... | 7.752925 |
module tx_port_buffer_32 #(
parameter C_FIFO_DATA_WIDTH = 9'd32,
parameter C_FIFO_DEPTH = 512,
// Local parameters
parameter C_FIFO_DEPTH_WIDTH = clog2((2 ** clog2(C_FIFO_DEPTH)) + 1)
) (
input RST,
input CLK,
input [ C_FIFO_DATA_WIDTH-1:0] WR_DATA, // Input data
input ... | 8.219744 |
module accepts transmitter data from the GMII style
// interface from the attached client MAC. At 1 Gbps, this
// GMII transmitter data will be valid on evey clock cycle
// of the 125MHz reference clock; at 100Mbps, this data
// will be repeated for a ten clock perio... | 8.196517 |
module tx_rd_addr_synch (
input clk_out,
input reset_n_clk_out,
input clk_in,
input reset_n_clk_in,
input [9:0] commited_rd_addr_in,
output reg [9:0] commited_rd_addr_out
);
// localparam
localparam s0 = 8'b00000000;
localparam s1 = 8'b00000001;... | 8.13359 |
module tx_responder #(
parameter BASE = 0
) (
input clk,
input reset,
input clear,
input set_stb,
input [7:0] set_addr,
input [31:0] set_data,
input ack_or_error,
input packet_consumed,
input [11:0] seqnum,
input [63:0] error_code,
input [31:0] sid,
input [63:0] vit... | 7.880273 |
module tx_rx_controller (
input clk,
input reset,
input [7:0] data_to_tx,
input rx_done_tick,
input [7:0] data_received, // tie to dout port of rx
output reg tx_start, // tie to tx_start port of tx
output reg [7:0] frame_out, // tie to din port of tx
output reg [7:0] data_recei... | 6.753018 |
module tx_selio_v1_0 #(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 4
) (
// Users to add por... | 6.575733 |
module UART_Protocal_Tx_stm (
input glb_rstn
, input glb_clk
, input CFG_PROT_ctrl_Txen
, input CFG_PROT_ctrl_empty
, input USR_PROT_ctrl_cts
, input CORE_CFG_r_en
, output reg PROT_CORE_ctrl_Txen
, output reg PROT_CORE_ctrl_empty
, output reg [1:0] PROT_CFG_ctrl_Txsel
, output r... | 6.877049 |
module TX_sequence (
input clock,
input reset,
input PB, //PushButton
output reg send16, // Si esta alto, se deben transmitir 16 bits (2 bytes)
input busy, // Si esta alto, la UART se encuentra transmitiendo un dato
output [1:0] stateID // Indica en que estado de la secuencia esta para mostr... | 7.864703 |
module.
// Output a character using RS232 protocol (8N1) and 115200 baud
// Ken Shirriff http://righto.com
module tx_serial(
input clk,
input rst,
input [7:0] char, // Character to output
input send, // High = request a send
output reg out, // Output pin
output busy // High while charact... | 7.826234 |
module tx_shiftr_reg_n #(
parameter BUS_WIDTH = 8
) (
Clk,
Reset,
ALoad,
DataIn,
SO,
Empty
);
input Clk, Reset, ALoad; // Clock, Reset, and Asynchronous Load inputs
input [BUS_WIDTH-1:0] DataIn; // Data to parallel load
output reg SO = 1'b1; // Serial Out
output reg Empty; // Shi... | 6.932792 |
module tx_shift_reg (
Clk,
Reset,
DataIn,
TxOut,
Empty
); // 单字节发送，发送下一个字节需要复位此模块
input Clk, Reset; // 时钟、复位
input [7:0] DataIn; // 待发送数据
output reg TxOut; // 串行输出
output reg Empty; // 移位寄存器空标志
reg [7:0] tmp;
reg [3:0] counter; // 计数变量
always @(posedge Clk, negedge Reset) begin... | 7.005889 |
module tx_sim (
input eth_rstn,
input eth_clkin,
input eth_txen,
input [1:0] eth_txd
);
`include "../rtl/util.vh"
reg crc_rst;
reg crc_vld;
reg [ 7:0] crc_dat;
wire [31:0] crc_code;
wire [31:0] crc_bswap = bswap32(crc_code);
crc32 crc32_inst (
.cl... | 7.62948 |
module TX_SM (
input clk,
input reset,
input HOLD_REG_FULL,
input HOLD_REG_EMPTY,
input DATA_WAIT,
output reg [7:0] dataIn,
output reg TX_VALID,
output reg TX_READY
);
reg [40:0] data;
reg flag;
integer i;
reg [7:0] SYNC, PID, EOP;
initial begin
flag = 0;
dataIn = 0;
... | 7.444751 |
module recieves a byte from the databus and transmit's it serially
// at the configured baud rate
//////////////////////////////////////////////////////////////////////////////////
module tx_spart(
output txd,
output reg tbr,
input clk,rst,
input iorw,
input brg_full, //goes high once every baud
input [7:0] dat... | 7.124804 |
module tx_spart_parity (
output txd,
output reg tbr,
input clk,
rst,
input iorw,
input brg_full, //goes high once every baud
input [7:0] databus,
input [1:0] ioaddr
);
reg [10:0] tx_shift_reg, tx_shift_reg_next;
localparam IDLE = 1'b0;
localparam TRANSMITTING = 1'b1;
reg stat... | 8.1995 |
module tx_spart_tb ();
reg clk, rst;
reg iorw;
reg [1:0] ioaddr;
reg [7:0] databus;
brg_spart BRG (
.clk(clk),
.rst(rst),
.ioaddr(ioaddr),
.databus(databus),
.brg_en(brg_en),
.brg_full(brg_full)
);
tx_spart DUT (
.txd(txd),
.tbr(tbr),
.clk(clk),
... | 6.56871 |
module Tx_specific_CC (
input clock,
input [15:0] to_port,
input udp_rx_active,
input [7:0] udp_rx_data,
output reg EER,
output reg internal_CW,
output reg key_reverse,
output reg iambic,
output reg sidetone,
output reg keyer_mode,
output reg keyer_spacing,
output reg bre... | 7.118738 |
module will called by fpga_top_ft600_tx_mass.v or fpga_top_ft232h_tx_mass.v
//--------------------------------------------------------------------------------------------------------
module tx_specified_len (
input wire rstn,
input wire clk,
// AXI-stream slave
output wire i_trea... | 6.957354 |
module tx_sr (
clk,
n_rst,
data_in,
shift_enable,
load_enable,
data_out
);
input [127:0] data_in;
output [31:0] data_out;
input clk, n_rst, shift_enable, load_enable;
tri clk;
tri n_rst;
tri [127:0] data_in;
tri shift_enable;
tri load_enable;
tri [31:0] data_out;
flexbyte_p... | 7.061752 |
module tx_state (
reset,
a_cnt,
code_sel,
a_send,
current_state,
next_state,
current_ifg,
current_q_det,
next_ifg,
next_q_det,
txdata_i,
txcharisk_i,
txdata_o,
txcharisk_o,
link_status_event,
link_status
);
input reset;
input [4:0] a_cnt;
input code_... | 7.648336 |
module tx_stats_fifo ( /*AUTOARG*/
// Outputs
txsfifo_rdata,
txsfifo_rempty,
// Inputs
clk_xgmii_tx,
reset_xgmii_tx_n,
wb_clk_i,
wb_rst_i,
txsfifo_wdata,
txsfifo_wen
);
input clk_xgmii_tx;
input reset_xgmii_tx_n;
input wb_clk_i;
input wb_rst_i;
input [13:0] txsfifo_w... | 6.984053 |
module TX_Switch #(
parameter REG_WIDTH = 8
) (
//-----------------Input Ports-----------------
input CLK, //ClockSignal
input RESET, //Active high,syn reset
input START, //Start Process
input [REG_WIDTH-1:0] init_delay, // the initial delay from start to pulse
input [REG_WIDTH-1:0] t... | 8.636191 |
module TX_Switch_tb;
parameter REG_WIDTH = 8;
parameter timescale_ref = 1000000; // reference scale based on timescale
parameter CLK_RATE_HZ = 20; // in MHz
//setting up clockticks
localparam integer clockticks = (timescale_ref / CLK_RATE_HZ) / 2.0;
//Signals
reg START;
wire TXD1N;
wire T... | 9.493799 |
module TX_SYNC_GTP
(
output TXENPMAPHASEALIGN,
output TXPMASETPHASE,
output SYNC_DONE,
input USER_CLK,
input RESET
);
//*******************************Register Declarations************************
reg begin_r;
reg phase... | 6.580749 |
module tx_tb ();
//this is the testbench for the tx module independently
reg clk, Rst_n, TxData_Valid;
reg [31:0] TxData;
reg Error_Ack, Rx_Ready, Rx_Error;
wire Tx_Ready, Tx_Error, S_Data;
wire Tx_Ready_net, Tx_Error_net, S_Data_net;
tx DUT (
.Clk_s(clk),
.Rst_n(Rst_n),
.TxData_Valid(... | 6.93599 |
module tx_t (
input MAIN_PAUSE,
output reg clk,
output reg RESET_L,
output reg PUSH_MAIN,
output reg init,
output reg POP_D0,
output reg POP_D1,
output reg [5:0] DATA_IN_TX,
output reg [4:0] main_fifo_low,
output reg [4:0] main_fifo_high,
output reg [4:0] Vco_low,
output ... | 7.194042 |
module tx_tb ();
reg clk;
reg rst_n;
reg TxD_start;
reg Enable;
reg [7:0] TxD_data;
wire TxD;
wire TBR;
tx iDUT (
clk,
rst_n,
TxD_start,
Enable,
TxD_data,
TxD,
TBR
);
initial begin
$dumpfile("test_tx.vcd");
$dumpvars(0, iDUT);
clk = 0;
rst_n... | 7.939113 |
module top (
input clk,
output Tx
);
wire [7:0] w_data;
wire w_Tx_EN;
wire w_RFN;
UART_Tx #(1250) u1 (
.clk(clk),
.data(w_data),
.Tx_EN(w_Tx_EN),
.Tx(Tx),
.RFN(w_RFN)
);
tx t1 (
.clk (clk),
.Tx_EN(w_Tx_EN),
.RFN (w_RFN),
.data (w_data)
);... | 7.233807 |
module UART_Tx #(
parameter CPB = 1250
) // CPB = clocks per bit: 12 MHz / 9600 Baud = 1250
(
input clk,
input [7:0] data,
input Tx_EN,
output Tx,
output RFN // RFN = ready for next (data)
);
// states
localparam START = 0;
localparam TRANSMIT = 1;
local... | 7.336003 |
module tx ( // sends data to UART_Tx to be then serialized and sent over UART to terminal
input clk,
output [7:0] data,
output Tx_EN,
input RFN // RFN = ready for next (data)
);
reg [7:0] r_data;
reg r_Tx_EN;
reg [31:0] counter;
always @(posedge clk) begin
if (coun... | 8.35717 |
module: UART_TX
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tx_test;
// Inputs
reg [7:0] RxD_par;
reg RxD_start;
reg RTS;
reg sys_clk;
wire BaudTick;
// Outputs
wire Tx... | 7.984548 |
module tx_testbench ();
//input
reg [7:0] data_o;
reg clk;
reg receive_ack;
//output
wire txd;
wire LEDmind;
uart_tx uarttx (
.data_o(data_o),
.txd(txd),
.clk(clk),
.receive_ack(receive_ack),
.LEDmind(LEDmind)
);
initial begin
#0 clk = 0;
data_o = 0;
recei... | 7.820584 |
module: can_tx
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Tx_test_internal;
// Inputs
reg [10:0] address;
reg clk;
reg baud_clk;
reg rst;
reg [63:0] data;
reg send_data;... | 8.134321 |
module tx_timer (
input clk,
input rst,
input reg_flush,
input [31:0] reg_tout,
input timer_start,
output reg timer_busy,
output [31:0] timer_cnt
);
reg [25:0] timer;
assign timer_cnt = {6'b0, timer};
always @(posedge c... | 6.834962 |
module tx_top_v ();
reg [11:0] story_tb;
reg clk, reset;
reg [7:0] dat_i;
reg lchar_i, valid_i;
wire d_o, s_o, ready_o;
tx_top top (
.txClk (clk),
.txReset(reset),
.dat_i (dat_i),
.lchar_i(lchar_i),
.valid_i(valid_i),
.d(d_o),
.s(s_o),
.ready_o(ready_o)
... | 6.957977 |
module tx_uart #(
parameter DBIT = 8,
parameter NB_STATE = 2,
parameter SB_TICK = 16
) (
input i_clock,
input i_reset,
input i_tx_start,
input i_s_tick,
input [DBIT-1:0] i_data,
output reg o_tx_done_tick,... | 7.908163 |
module tx_write_dev_MSN_bram_V_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 63;
parameter AWIDTH = 13;
parameter MEM_SIZE = 8192;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDT... | 8.085225 |
module tx_write_dev_MSN_bram_V (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd63;
parameter AddressRange = 32'd8192;
parameter AddressWidth = 32'd13;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output ... | 8.085225 |
module tx_write_dev_MSN_V #(
parameter
DataWidth = 64,
AddressWidth = 13,
AddressRange = 8192
) (
input wire clk,
input wire reset,
input wire [AddressWidth-1:0] address0,
input wire ce0,
input wire w... | 8.085225 |
module tx_write_dev_MSN_V_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 13;
parameter MEM_SIZE = 8192;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "hls_ultra"... | 8.085225 |
module tx_write_dev_regslice_both #(
parameter DataWidth = 32
) (
input ap_clk,
input ap_rst,
input [DataWidth-1:0] data_in,
input vld_in,
output ack_in,
output [DataWidth-1:0] data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire... | 8.085225 |
module tx_write_dev_regslice_both_w1 #(
parameter DataWidth = 1
) (
input ap_clk,
input ap_rst,
input data_in,
input vld_in,
output ack_in,
output data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire B_V_data_1_data_in;
... | 8.085225 |
module tx_write_dev_reset_MSN_V_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 1;
parameter AWIDTH = 13;
parameter MEM_SIZE = 8192;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDT... | 8.085225 |
module tx_write_dev_reset_MSN_V (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd1;
parameter AddressRange = 32'd8192;
parameter AddressWidth = 32'd13;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output ... | 8.085225 |
module tx_wr_addr_synch (
input clk_out,
input reset_n_clk_out,
input clk_in,
input reset_n_clk_in,
input [9:0] commited_wr_addr_in,
output reg [9:0] commited_wr_addr_out
);
// localparam
localparam s0 = 8'b00000000;
localparam s1 = 8'b00000001;... | 7.981102 |
module TYPEA (
input CLK,
input RESET_N,
input CLKEN,
input TDI,
output TDO,
output reg DATA_OUT,
input DATA_IN,
input CAPTURE_DR,
input UPDATE_DR
);
reg tdoInt;
always @(negedge CLK or negedge RESET_N) begin
if (RESET_N == 1'b0) tdoInt <= 1'b0;
else if (CLK == 1'b0)
... | 7.600886 |
module LockingRRArbiter (
input clock,
input reset,
output io_in_0_ready,
input io_in_0_valid,
input [15:0] io_in_0_bits_RouteID,
input [ 5:0] io_in_0_bits_address,
input [15:0] io_in_0_bits_data,
input [ 1:0] io_in_0_bits_mask,
input io_in_... | 7.257641 |
module LockingRRArbiter_1 (
output io_in_0_ready,
input io_in_0_valid,
input io_out_ready,
output io_out_valid
);
assign io_in_0_ready = io_out_ready;
assign io_out_valid = io_in_0_valid;
endmodule
| 7.257641 |
module Demux (
input io_en,
output io_outputs_0_valid
);
wire _T_16;
wire _GEN_3;
assign io_outputs_0_valid = _GEN_3;
assign _T_16 = io_en == 1'h0;
assign _GEN_3 = _T_16 ? 1'h0 : 1'h1;
endmodule
| 7.252853 |
module LockingRRArbiter_2 (
input clock,
output io_in_0_ready,
input io_in_0_valid,
input [15:0] io_in_0_bits_RouteID,
input [15:0] io_in_0_bits_address,
output io_in_1_ready,
input io_in_1_valid,
input [15:0] io_in_1_bits_RouteID,
input [15:... | 7.257641 |
module LockingRRArbiter_3 (
input clock,
input reset,
output io_in_0_ready,
input io_in_0_valid,
input [15:0] io_in_0_bits_addr,
input [ 7:0] io_in_0_bits_tag,
output io_in_1_ready,
input io_in_1_valid,
input [15:0] io_in_1_bits_addr,
... | 7.257641 |
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