code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module frame_counter (
input clk,
resetn,
enable,
input [2:0] color_in,
output frame_enable,
output [2:0] color_out
);
reg [3:0] count;
always @(posedge clk) begin
if (!resetn) count <= 4'b0000;
else if (enable == 1'b1) begin
if (count == 4'b1111) count <= 4'b0000;
else ... | 6.859338 |
module x_counter (
input resetn,
enable,
direction,
output reg [7:0] x_pos
);
always @(negedge enable, negedge resetn) begin
if (!resetn) x_pos <= 8'd60;
else begin
if (direction) x_pos <= x_pos + 1'b1;
else x_pos <= x_pos - 1'b1;
end
end
endmodule
| 6.671091 |
module y_counter (
input resetn,
enable,
direction,
output reg [6:0] y_pos
);
always @(negedge enable, negedge resetn) begin
if (!resetn) y_pos <= 7'd60;
else begin
if (direction) y_pos <= y_pos + 2'd2;
else y_pos <= y_pos - 2'd2;
end
end
endmodule
| 6.612318 |
module r_v (
input clk,
resetn,
input [6:0] y,
output reg direction
);
always @(posedge clk) begin
if (!resetn) direction <= 0;
else begin
if (direction) begin
if (y + 3 > 7'd107) direction <= 1'b0;
else direction <= 1'b1;
end else begin
if (y - 3 < 7'd12) d... | 6.703342 |
module draw (
input clk,
enable,
resetn,
ld_color,
input [7:0] x_in,
input [6:0] y_in,
input [2:0] color_in,
output [7:0] x_out,
output [6:0] y_out,
output [2:0] color_out
);
reg [7:0] x;
reg [6:0] y;
reg [2:0] color;
//reset or load
always @(posedge clk) begin
if... | 7.396902 |
module process (
input clk,
enable,
resetn,
ld_color,
input [2:0] color_in,
output [7:0] x_out,
output [6:0] y_out,
output [2:0] color_out
);
wire [ 7:0] x_pos;
wire [ 6:0] y_pos;
wire [19:0] count0;
wire [ 3:0] count1;
wire x_direction, y_direction;
wire [2:0] color;
wire... | 6.540992 |
module top_module (
input in1,
input in2,
input in3,
output out
);
assign out = (~(in1 ^ in2)) ^ in3;
endmodule
| 7.203305 |
module top_module (
input [1:0] A,
input [1:0] B,
output z
);
assign z = (~(A[0] ^ B[0])) & (~(A[1] ^ B[1]));
endmodule
| 7.203305 |
module Two2OneMux #(
parameter Width = 24
) (
input wire [Width-1:0] din0,
input wire [Width-1:0] din1,
input wire sel,
output wire [Width-1:0] dout
);
assign dout = sel ? din1 : din0;
endmodule
| 7.929578 |
module includes a 2-1 SNN(simplest).
//
// Dependencies: Based on synapses, neurons.
//
// Revision:
// Revision 0.01 - File Created
// 0.1 - Synthesis failed because of limited LUTs. We will try to find a LUT-redundent board for snn.
// Additional Comments: This file is just a test file, which doesn't incl... | 6.588012 |
module Two4DigitDisplay (
Clk,
NumberA,
NumberB,
out7,
en_out
);
parameter NUM_WIDTH = 16;
input Clk;
input [15:0] NumberA;
input [15:0] NumberB;
output [6:0] out7; //seg a, b, ... g
output reg [7:0] en_out;
reg [3:0] in4;
// Use for Structural assignment method
wire [3:0] fi... | 7.958996 |
module TWOadder (
input [31:0] A,
B,
input clk,
rst,
output [31:0] W,
output [31:0] AA,
BB,
output reg [7:0] Aadd,
Badd,
output [1:0] gout,
output cout
);
reg cin, en1, en2, en3, en4;
wire coutadd, en;
wire [7:0] S;
assign en = cout;
always @(*) begin
case (gout... | 6.832364 |
module makes up the leaves of the leading zero detecting tree generated by lzdetector
//given its short length, it should probably simply be incorparted into lzdetector in the length==2 case
module twobitlzd(
output wire p,
output wire v,
input wire a,
input wire b
);
assign p = (!a)&b;
assi... | 7.27518 |
module twoBitMuti (
input [1:0] A,
input [1:0] B,
output [3:0] PRO
);
assign PRO[3] = B[1] & B[0] & A[1] & A[0];
assign PRO[2] = A[1] & B[1] & (~A[0] | ~B[0]);
assign PRO[1] = A[1] & B[1] & (A[0] ^ B[0]) | ~B[1] & B[0] & A[1] | ~A[1] & A[0] & B[1];
assign PRO[0] = A[0] & B[0];
endmodule
| 7.072617 |
module TwoBitSaturationPredictor (
input clk,
input reset_n,
input [`WORD_SIZE-1:0] PC,
input JumpResolved,
BranchResolved,
BranchTaken,
input [`WORD_SIZE-1:0] ResolvedJumpPC,
ResolvedBranchPC,
input [`WORD_SIZE-1:0] ActualJumpTarget,
ActualBranchTarget,
output [`WORD_SIZE-1:... | 9.538702 |
module TwoBitShift (
output data_out,
input data_in
);
assign data_out = data_in << 2;
endmodule
| 8.44379 |
module twobitshifter (
inp,
out
);
input [31:0] inp;
output reg [31:0] out;
always @(inp) out = inp * 4;
endmodule
| 6.578081 |
module top_module (
input [1:0] A,
input [1:0] B,
output z
);
assign z = A == B;
endmodule
| 7.203305 |
module represents a two by one mux.
**********************************************************************/
`timescale 1ns / 1ps
module twobyoneMUX(
input [31:0] A, [31:0] B, input S, output [31:0] c
);
genvar i;
generate
for(i=0; i<32; i=i+1)begin: myblock
mux_2x1 mux(A[i] , B[i] , S, c[... | 7.311982 |
module
// Find additive inverse
//
// License: MIT
//
////////////////////////////////////////////////////////////////////////
`default_nettype None
`timescale 1ns/1ps
module twoComplementer #(parameter N = 4) (output wire[N-1:0] twoComp, input[N-1:0] in);
wire[N:0] total;
assign total = ~in+1;... | 7.423624 |
module TwoDigitDisplay (
Clk,
Number,
out7,
en_out
);
input Clk;
input [6:0] Number;
output [6:0] out7; //seg a, b, ... g
output reg [7:0] en_out;
reg [3:0] in4;
reg [3:0] firstdigit;
reg [3:0] seconddigit;
//--------- --------- --------- --------- //
//-- to use the module SevenSeg... | 8.113622 |
module twodigits (
data,
leds
);
input [6:0] data;
output [13:0] leds;
reg [3:0] digit0, digit1;
initial begin
digit0 = 0;
digit1 = 0;
end
sevenseg led0 (
digit0,
leds[6:0]
);
sevenseg led1 (
digit1,
leds[13:7]
);
always @(data) begin
digit1 = data / 10;... | 6.602591 |
module twoDint_counter32A;
/* Make an init that pulses once. */
reg init = 1;
initial begin
#1200 init = 0;
#5000 $stop;
end
initial begin
$dumpfile("twoDint_counter32A.vcd");
$dumpvars(0, twoDint_counter32A);
end
////// test bench
//////////////////////////////
////// circuit under ... | 6.630717 |
module twoDint_counter32C;
/* Make an init that pulses once. */
reg init = 1;
initial begin
#1200 init = 0;
#5000 $stop;
end
initial begin
$dumpfile("twoDint_counter32C.vcd");
$dumpvars(0, twoDint_counter32C);
end
////// test bench
//////////////////////////////
////// circuit under ... | 6.630717 |
module twoDint_counter_ringA (
output wire [1:0] sum,
input sumCOMP,
output wire [1:0] carryout,
input carryoutCOMP,
input [1:0] carryin,
output carryinCOMP,
input init
);
wire [1:0] A;
wire [1:0] B;
wire [1:0] C;
wire [1:0] D;
wire ACOMP, BCOMP, CCOMP, DCOMP, CCOMP2;
// 4 sta... | 6.630717 |
module Pipecomponent2 (
output [1:0] Z,
input ZCOMP,
input [1:0] A,
output ACOMP,
input init
);
wire enable;
THnotN u0 (
enable,
ZCOMP,
init
);
TH22 u1 (
Z[0],
A[0],
enable
);
TH22 u2 (
Z[1],
A[1],
enable
);
TH12 u5 (
ACOMP,... | 7.182889 |
module Pipecomponent2N (
output [1:0] Z,
input ZCOMP,
input [1:0] A,
output ACOMP,
input init
);
wire enable;
THnotN u0 (
enable,
ZCOMP,
init
);
TH22N u1 (
Z[0],
A[0],
enable,
init
); // rotate rails
TH22N u2 (
Z[1],
A[1],
enab... | 7.182889 |
module Pipecomponent2D (
output [1:0] Z,
input ZCOMP,
input [1:0] A,
output ACOMP,
input init
);
wire enable;
THnot u0 (
enable,
ZCOMP
);
TH22D u1 (
Z[0],
A[0],
enable,
init
);
TH22N u2 (
Z[1],
A[1],
enable,
init
);
TH12 u5 ... | 7.182889 |
module twoDint_counter_ringC (
output wire [1:0] sum,
input sumCOMP,
output wire [1:0] carryout,
input carryoutCOMP,
input [1:0] carryin,
output carryinCOMP,
input init
);
wire [1:0] A;
wire [1:0] B;
wire [1:0] C;
wire [1:0] D;
wire ACOMP, BCOMP, CCOMP, DCOMP, CCOMP2;
// 4 sta... | 6.630717 |
module Pipecomponent2 (
output [1:0] Z,
input ZCOMP,
input [1:0] A,
output ACOMP,
input init
);
wire enable;
THnotN u0 (
enable,
ZCOMP,
init
);
TH22 u1 (
Z[0],
A[0],
enable
);
TH22 u2 (
Z[1],
A[1],
enable
);
TH12 u5 (
ACOMP,... | 7.182889 |
module Pipecomponent2N (
output [1:0] Z,
input ZCOMP,
input [1:0] A,
output ACOMP,
input init
);
wire enable;
THnotN u0 (
enable,
ZCOMP,
init
);
TH22N u1 (
Z[0],
A[0],
enable,
init
); // rotate rails
TH22N u2 (
Z[1],
A[1],
enab... | 7.182889 |
module Pipecomponent2D (
output [1:0] Z,
input ZCOMP,
input [1:0] A,
output ACOMP,
input init
);
wire enable;
THnot u0 (
enable,
ZCOMP
);
TH22D u1 (
Z[0],
A[0],
enable,
init
);
TH22N u2 (
Z[1],
A[1],
enable,
init
);
TH12 u5 ... | 7.182889 |
module twoD_counter32A;
/* Make an init that pulses once. */
reg init = 1;
initial begin
#1200 init = 0;
#5000 $stop;
end
initial begin
$dumpfile("twoD_counter32A.vcd");
$dumpvars(0, twoD_counter32A);
end
////// test bench
//////////////////////////////
////// circuit under test
w... | 6.636592 |
module twoD_counter32B;
/* Make an init that pulses once. */
reg init = 1;
initial begin
#1200 init = 0;
#5000 $stop;
end
initial begin
$dumpfile("twoD_counter32B.vcd");
$dumpvars(0, twoD_counter32B);
end
////// test bench
//////////////////////////////
////// circuit under test
w... | 6.636592 |
module twoD_counter32C;
/* Make an init that pulses once. */
reg init = 1;
initial begin
#1200 init = 0;
#5000 $stop;
end
initial begin
$dumpfile("twoD_counter32C.vcd");
$dumpvars(0, twoD_counter32C);
end
////// test bench
//////////////////////////////
////// circuit under test
w... | 6.636592 |
module Pipecomponent2 (
output [1:0] Z,
input ZCOMP,
input [1:0] A,
output ACOMP,
input init
);
wire enable;
THnotN u0 (
enable,
ZCOMP,
init
);
TH22 u1 (
Z[0],
A[0],
enable
);
TH22 u2 (
Z[1],
A[1],
enable
);
TH12 u5 (
ACOMP,... | 7.182889 |
module Pipecomponent2N (
output [1:0] Z,
input ZCOMP,
input [1:0] A,
output ACOMP,
input init
);
wire enable;
THnotN u0 (
enable,
ZCOMP,
init
);
TH22N u1 (
Z[0],
A[0],
enable,
init
); // rotate rails
TH22N u2 (
Z[1],
A[1],
enab... | 7.182889 |
module Pipecomponent2D (
output [1:0] Z,
input ZCOMP,
input [1:0] A,
output ACOMP,
input init
);
wire enable;
THnot u0 (
enable,
ZCOMP
);
TH22D u1 (
Z[0],
A[0],
enable,
init
);
TH22N u2 (
Z[1],
A[1],
enable,
init
);
TH12 u5 ... | 7.182889 |
module Pipecomponent2 (
output [1:0] Z,
input ZCOMP,
input [1:0] A,
output ACOMP,
input init
);
wire enable;
THnotN u0 (
enable,
ZCOMP,
init
);
TH22 u1 (
Z[0],
A[0],
enable
);
TH22 u2 (
Z[1],
A[1],
enable
);
TH12 u5 (
ACOMP,... | 7.182889 |
module Pipecomponent2N (
output [1:0] Z,
input ZCOMP,
input [1:0] A,
output ACOMP,
input init
);
wire enable;
THnotN u0 (
enable,
ZCOMP,
init
);
TH22N u1 (
Z[0],
A[0],
enable,
init
); // rotate rails
TH22N u2 (
Z[1],
A[1],
enab... | 7.182889 |
module Pipecomponent2D (
output [1:0] Z,
input ZCOMP,
input [1:0] A,
output ACOMP,
input init
);
wire enable;
THnot u0 (
enable,
ZCOMP
);
TH22D u1 (
Z[0],
A[0],
enable,
init
);
TH22N u2 (
Z[1],
A[1],
enable,
init
);
TH12 u5 ... | 7.182889 |
module Pipecomponent2 (
output [1:0] Z,
input ZCOMP,
input [1:0] A,
output ACOMP,
input init
);
wire enable;
THnotN u0 (
enable,
ZCOMP,
init
);
TH22 u1 (
Z[0],
A[0],
enable
);
TH22 u2 (
Z[1],
A[1],
enable
);
TH12 u5 (
ACOMP,... | 7.182889 |
module Pipecomponent2N (
output [1:0] Z,
input ZCOMP,
input [1:0] A,
output ACOMP,
input init
);
wire enable;
THnotN u0 (
enable,
ZCOMP,
init
);
TH22N u1 (
Z[0],
A[0],
enable,
init
); // rotate rails
TH22N u2 (
Z[1],
A[1],
enab... | 7.182889 |
module Pipecomponent2D (
output [1:0] Z,
input ZCOMP,
input [1:0] A,
output ACOMP,
input init
);
wire enable;
THnot u0 (
enable,
ZCOMP
);
TH22D u1 (
Z[0],
A[0],
enable,
init
);
TH22N u2 (
Z[1],
A[1],
enable,
init
);
TH12 u5 ... | 7.182889 |
module top_module (
input in1,
input in2,
input in3,
output out
);
assign out = ~(in1 ^ in2) ^ in3;
endmodule
| 7.203305 |
module BitTwoInOneSelector32Bit (
input [31:0] ZeroInput,
input [31:0] OneInput,
input Control,
output reg [31:0] DataOutput
);
always @(Control or ZeroInput or OneInput) begin
DataOutput = (Control == 1) ? OneInput : ZeroInput;
end
endmodule
| 7.803437 |
module TwoInOneSelector5Bit (
input [4:0] ZeroInput,
input [4:0] OneInput,
input Control,
output reg [4:0] DataOutput
);
always @(Control or ZeroInput or OneInput) begin
DataOutput = (Control == 1) ? OneInput : ZeroInput;
end
endmodule
| 6.849886 |
module twoMultAdd (
W,
X,
U,
h,
b,
out
);
// incoming data signed and fixed width
parameter DATA_WIDTH = 16;
parameter FRACT_WIDTH = 8;
input signed [DATA_WIDTH-1:0] W, X, U, h, b;
output wire [DATA_WIDTH-1:0] out;
// internal regs/wires
wire [DATA_WIDTH+FRACT_WIDTH-1:0] p1, p2;... | 8.381371 |
module twoniv (
output z,
input a,
input sys_clk
);
/*reg r_z = 1'b0;
assign z = r_z;
always @(posedge sys_clk)
begin
r_z <= a;
end*/
assign z = a;
endmodule
| 7.033744 |
module twoPortMem (
writeAddress,
writeClk,
writeEnable,
writeData,
readAddress,
readClk,
readEnable,
readData);
//user defined... | 9.238624 |
module twoPortMemSim (
writeAddress,
writeClk,
writeEnable,
writeData,
readAddress,
readClk,
readEnable,
readData
);
//user defined
parameter addresses = 32;
parameter width = 8;
parameter muxFactor = 0;
parameter writeMask = 1;
//Auto-calculated, user dont touch
local... | 9.26883 |
module TwoPort_SRAM (
CLKA,
CENA,
AA,
QA,
CLKB,
CENB,
WENB,
AB,
DB
);
//parameters
parameter ADDR_BITS = 13;
parameter MEM_SIZE = 8192;
input CLKA, CLKB;
input CENA, CENB;
input WENB;
input [ADDR_BITS-1:0] AA, AB;
input [`INTERNAL_BITS-1:0] DB;
output [`INTERNAL_B... | 7.376651 |
module TwoPort_SRAM_tb;
//parameters
parameter ADDR_BITS = 13;
//inputs
reg CLK;
reg CENA, CENB;
reg WENB;
reg [ADDR_BITS-1:0] AA, AB;
reg [`INTERNAL_BITS-1:0] DB;
//outputs
wire [`INTERNAL_BITS-1:0] QA;
TwoPort_SRAM TS (
.CLKA(CLK),
.CLKB(CLK),
.CENA(CENA),
.CENB(CENB... | 6.767807 |
module my_reg (
input clka,
input clkb,
input a_d,
b_d,
output reg a_q,
b_q
);
initial a_q = 0;
always @(posedge clka) a_q <= a_d;
//cover property ((a_q == 1) && (a_d == 0));
always @(negedge clkb) b_q <= b_d;
endmodule
| 7.230814 |
module TwosComplement #(
parameter N = 8
) (
input [N-1:0] A,
output [N-1:0] O
);
ADD #(
.N(N)
) ADD (
.A (~A),
.B ({N{1'b0}}),
.CI(1'b1),
.S (O),
.CO()
);
endmodule
| 8.45255 |
module complement_16bit (
a,
a_complement
);
input [15:0] a;
output wire [15:0] a_complement;
assign a_complement = {1'b1, 16'b0} - a;
endmodule
| 7.32668 |
module complement_19bit (
a,
a_complement
);
input [18:0] a;
output wire [18:0] a_complement;
assign a_complement = {1'b1, 19'b0} - a;
endmodule
| 6.582878 |
module complement_9bit (
a,
a_complement
);
input [8:0] a;
output wire [9:0] a_complement;
assign a_complement = {1'b1, 9'b0} - {1'b0, a};
endmodule
| 6.889491 |
module twoscompliment (
clk,
reset,
a,
out
);
parameter width = 32;
input clk, reset;
input [width-1:0] a;
output reg [width-1:0] out;
//reg [width-1:0] y;
always @(posedge clk) begin
if (reset) out = 32'b0;
else out = (~a) + 1;
end
//assign out =y;
endmodule
| 7.505089 |
module twoseconds (
input clk,
input rst,
input [11:0] ad, //from adc
input flag, //from adc
output reg convert, //to adc
output reg [11:0] num //to seg
);
parameter cnt_top = 21'd1999999;
//parameter cnt_top=21'd1000;
//generate 2s period
reg [20:0] cnt;
always @(posedge clk or p... | 7.297404 |
module twoComp (
in,
out
);
input [4:0] in;
wire [4:0] semiOUT;
output [4:0] out;
assign semiOUT = ~in;
bit4Adder(
semiOUT, 5'b00001, out
);
endmodule
| 7.614959 |
module bit4Adder (
in1,
in2,
out
);
input [4:0] in1;
input [4:0] in2;
output [4:0] out;
wire c12, c23, c34, c45;
wire useless;
//assign out=5'b11111;
fullAdder bit1 (
in1[0],
in2[0],
1'b0,
out[0],
c12
);
fullAdder bit2 (
in1[1],
in2[1],
c1... | 7.261018 |
module definition
module twos_complement_converter( clk, rst, inp, outp);
input clk, rst, inp;
output outp;
reg state;
reg outp;
//total number of states = 2
parameter S0 = 0, S1 = 1;
always @( posedge clk, posedge rst ) begin
//start state is S0
if( rst ) begin
state <= S0;
outp <= 0;
end
else begin
case(... | 6.923011 |
module twos_Compliment (
input [31 : 0] in,
output [31 : 0] out
);
assign out = (~in + 1);
endmodule
| 7.383534 |
module test;
// Registers
reg clk;
reg en;
reg [7:0] A;
wire [7:0] Output; // The read data
wire ready;
// Initialize varibles
initial begin
#1 en = 0;
A = 8'd12;
clk = 0;
#2 en = 1;
#10 en = 0;
#15 $finish;
end
// Monitoring the output
always @(cl... | 6.888292 |
module twos_to_sign_mag (
in,
out,
sign
);
input [11:0] in;
output [11:0] out;
output sign;
assign sign = in[11];
assign out = (in[11] == 1) ? ~in + 1'b1 : in;
endmodule
| 7.573 |
module TwoToFourDecoder (
input a,
input b,
output q0,
output q1,
output q2,
output q3
);
and (q0, ~a, ~b);
and (q1, ~a, b);
and (q2, a, ~b);
and (q3, a, b);
endmodule
| 7.158165 |
module TwoToOne (
input select,
input [31:0] A,
input [31:0] B,
output wire [31:0] out
);
assign out = (select == 1) ? B : A;
endmodule
| 8.033965 |
module TwoToOneMux #(
parameter integer RV_BIT_NUM_TWO = `RV_BIT_NUM_TWO)
(
input [`MUX_WIDTH_TWO-1:0] sel,
input [(RV_BIT_NUM_TWO*`MUX_OPTION_TWO)-1 : 0] d,
output reg [RV_BIT_NUM_TWO-1:0]q);
always@(*) begin
case( sel )
`muxcasetwo(`MUX_WIDTH_TWO'd0,0)
... | 7.193575 |
module mux2_to_1 (
out,
i0,
i1,
s0
);
output out;
input i0, i1, s0;
reg out;
wire i0, i1, s0;
always @(s0 or i0 or i1) begin
if (s0 == 0) out = i0;
else out = i1;
end
endmodule
| 6.888021 |
module twoway_16bit_mux (
in0,
in1,
sel,
out
);
input sel;
input [15:0] in0, in1;
output reg [15:0] out;
always @(*)
case (sel)
'd0: out = in0;
default out = in1;
endcase
endmodule
| 7.014625 |
module enc4to2 (
ENCout,
FLAG,
ENCin,
EN
);
// Declaration of the input-output
input [3:0] ENCin;
input EN;
output reg [1:0] ENCout;
output FLAG;
assign FLAG = ENCin >= 1 ? 1 : 0;
always @(ENCin) begin
if (EN == 0)
casex (ENCin)
4'b1xxx: ENCout = 3;
4'b01xx: E... | 6.844155 |
module dec2to4 (
DECout,
DECin,
EN
);
// declarations of inputs, outputs, & registers;
input [1:0] DECin;
input EN;
integer i = 0;
output reg [3:0] DECout;
always @(DECin or EN) begin
for (i = 0; i <= 3; i = i + 1)
if ((DECin == i) && (EN)) DECout[i] = 1;
else DECout[i] = 0;
end... | 7.443137 |
module twowire_dtm_connect_monitor (
input wire dck,
input wire drst_n,
input wire di_q,
input wire [3:0] mdropaddr,
output wire connect_now,
input wire connected
);
localparam LFSR_TAPS = 6'h30;
localparam LFSR_INIT = 6'h29;
reg [5:0] lfsr;
wire lfsr_out = lfsr[5];
r... | 7.429738 |
module twowire_dtm_io_flops (
input wire dck,
input wire drst_n,
input wire do,
output wire do_q,
input wire doe,
output wire doe_q,
input wire di,
output wire di_q
);
`TWOWIRE_REG_KEEP_ATTR reg do_reg;
`TWOWIRE_REG_KEEP_ATTR reg doe_reg;
`TWOWIRE_REG_KEEP_ATTR reg di_reg;
always @ (posedge dck or neg... | 7.231774 |
module twox1_32bit (
In0,
In1,
Sel,
out
);
input [31:0] In0, In1;
input Sel;
output [31:0] out;
reg [31:0] out;
always @(In0 or In1 or Sel) begin
case (Sel)
0: out <= In0;
1: out <= In1;
default: out <= 32'hxxxxxxxx;
endcase
end
endmodule
| 7.109293 |
module twoxfourdec (
En,
Inp,
Outp
);
input En;
input [1:0] Inp;
output [3:0] Outp;
reg [3:0] Out;
always @(En or Inp) begin
if (~En) Out <= 4'b1111;
else begin
case (Inp)
2'b00: Out <= 4'b0111;
2'b01: Out <= 4'b1011;
2'b10: Out <= 4'b1101;
2'b1... | 7.595136 |
module: twoxfourdec
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module twoxfourdec_test;
// Inputs
reg En;
reg [1:0] Inp;
// Outputs
wire [3:0] Outp;
// Instantiate the Unit Un... | 7.326359 |
module TwoXOneMUX (
input A,
B,
S,
output C
);
assign C = S ? B : A;
//always @(*)
//begin
// C = (A & ~S )|(S & B);
// end
endmodule
| 7.48674 |
module two_1_mux (
data1,
data0,
sel,
outputdata
);
input [15:0] data0;
input [15:0] data1;
input sel;
output [15:0] outputdata;
reg [15:0] outputdata;
always @(sel or data1 or data0) begin
case (sel)
1'b0: begin
outputdata <= data0;
end
1'b1: begin
ou... | 7.223511 |
module two_4_input_and_gate #(
parameter DELAY = 10
) (
input wire a1,
b1,
c1,
d1,
a2,
b2,
c2,
d2,
output wire y1,
y2
);
and #DELAY (y1, a1, b1, c1, d1);
and #DELAY (y2, a2, b2, c2, d2);
endmodule
| 7.860282 |
module two_4_input_nand_gate #(
parameter DELAY = 10
) (
input wire a1,
b1,
c1,
d1,
a2,
b2,
c2,
d2,
output wire y1,
y2
);
nand #DELAY (y1, a1, b1, c1, d1);
nand #DELAY (y2, a2, b2, c2, d2);
endmodule
| 8.040559 |
module two_bit (
A0,
A1,
B0,
B1,
S0,
S1,
S2,
C2
);
input A0, A1, B1, B0;
output S0, S1, S2, C2;
wire C1;
assign S0 = A0 & B0;
assign S1 = (A0 & B1) ^ (A1 & B0);
assign C1 = (A0 & B1) & (A1 & B0);
assign S2 = C1 ^ (A1 & B1);
assign C2 = C1 & (A1 & B1);
endmodule
| 7.01638 |
module half_adder (
S,
C,
X,
Y
);
input X, Y;
output S, C;
xor a1 (S, X, Y);
and a2 (C, X, Y);
endmodule
| 6.966406 |
module two_bit_adder (
A,
B,
Cin,
Sum,
Carry
);
input [1:0] A, B;
input Cin;
output [1:0] Sum;
output Carry;
wire C1, C2, C3, C4, S0, S1;
half_adder h1 (
S0,
C0,
A[0],
B[0]
);
half_adder h2 (
Sum[0],
C1,
Cin,
S0
);
or o1 (C2, C1, C0... | 6.650749 |
module two_bit_adder_dataflow;
//`include "two_bit_adder.v"
reg [1:0] A, B;
reg Cin;
wire [1:0] Sum;
wire Carry;
two_bit_adder DUT (
A,
B,
Cin,
Sum,
Carry
);
initial begin
$dumpfile("two_bit_adder_dataflow.vcd");
$dumpvars();
end
initial begin
A = 2'b00... | 6.650749 |
module half_adder (
S,
C,
X,
Y
);
input X, Y;
output S, C;
xor a1 (S, X, Y);
and a2 (C, X, Y);
endmodule
| 6.966406 |
module two_bit_adder (
A,
B,
Cin,
Sum,
Carry
);
input [1:0] A, B;
input Cin;
output [1:0] Sum;
output Carry;
wire C1, C2, C3, C4, S0, S1;
half_adder h1 (
S0,
C0,
A[0],
B[0]
);
half_adder h2 (
Sum[0],
C1,
Cin,
S0
);
or o1 (C2, C1, C0... | 6.650749 |
module two_bit_adder_tb;
//`include "two_bit_adder.v"
reg [1:0] A, B;
reg Cin;
wire [1:0] Sum;
wire Carry;
two_bit_adder DUT (
A,
B,
Cin,
Sum,
Carry
);
initial begin
$dumpfile("two_bit_adder_tb.vcd");
$dumpvars();
end
initial begin
A = 2'b00;
B = ... | 6.650749 |
module: two_bit_adder
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module two_bit_adder_top;
// Inputs
reg [1:0] x;
reg [1:0] y;
// Outputs
wire [1:0] z;
wire carry;
// Instant... | 7.237769 |
module d_flipflop (
input CLK,
input R,
input D,
output Q
);
reg Q, Qc;
initial begin
Q = 0;
Qc = 0;
end
always @(posedge CLK) begin
Q <= D;
Qc <= ~D;
if (R) begin
Q <= 0;
Qc <= 1;
end
end
endmodule
| 7.276171 |
module two_bit_comp (
input wire [1:0] x,
y,
output wire answer
);
wire p0, p1, p2, p3;
assign p0 = (~x[1] & ~y[1]) & (~x[0] & ~y[0]);
assign p1 = (~x[1] & ~y[1]) & (x[0] & y[0]);
assign p2 = (x[1] & y[1]) & (~x[0] & ~y[0]);
assign p3 = (x[1] & y[1]) & (x[0] & y[0]);
assign answer = p0 | p1 |... | 7.799052 |
module two_bit_comp2 (
input wire [1:0] x,
y,
output wire answer
);
wire p0, p1;
comp circuit1 (
x[1],
y[1],
p0
);
comp circuit2 (
x[0],
y[0],
p1
);
assign answer = p0 & p1;
endmodule
| 9.006145 |
module two_bit_comp2 (
input wire [1:0] x,
y,
output wire answer
);
assign answer = x == y;
endmodule
| 9.006145 |
module Two_Bit_Comparator (
input [1:0] A, //2-bit INPUT A
input [1:0] B, //2-bit INPUT B
output A_Greater, //OUTPUT BIT A>B
output Equal, //OUTPUT BIT A=B
output B_Greater //OUTPUT BIT A<B
);
////////////////////////WRITE YOUR CODE FROM HERE/////... | 7.18956 |
module two_bit_comp_tb;
reg [1:0] x;
reg [1:0] y;
wire answer;
two_bit_comp2 circuit1 (
x,
y,
answer
);
initial begin
$dumpfile("test.vcd");
$dumpvars(0, two_bit_comp_tb);
x = 2'b00;
y = 2'b00;
#20;
x = 2'b00;
y = 2'b01;
#20;
x = 2'b01;
y = 2'b00;
... | 6.983096 |
module two_bit_down (
CLOCK_50, //50 MHZ clock
KEY, // reset
SW,
Hex0_value,
Hex1_value,
Hex0,
Hex1
);
input CLOCK_50; //50 MHZ clock
input [0:0] KEY; // reset
input [9:9] SW;
input [3:0] Hex0_value, Hex1_value;
output [0:6] Hex0;
output [0:6] Hex1;
reg [2:0] state;
re... | 7.199636 |
module two_by_one_mux (
input [3:0] in0,
input [3:0] in1,
input selector,
output [3:0] Y
);
assign Y = (selector == 0) ? in0 : in1;
endmodule
| 6.590245 |
module two_complementer (
input inp,
input clk,
input reset,
output reg out
);
reg state;
always @(posedge clk, posedge reset) begin
if (reset) state <= 0;
else begin
case (state)
0: begin
if (inp == 0) begin
state <= 0;
out <= 0;
... | 7.955961 |
module: two_complementer
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module two_complementer_tb;
// Inputs
reg inp;
reg clk;
reg reset;
// Outputs
wire out;
// Instantiate the... | 7.282119 |
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