code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module two_compliment25 (
data_in,
data_out
);
input [24:0] data_in;
output [24:0] data_out;
wire [24:0] temp;
//Not
assign temp = ~data_in;
//add 1
adder25 add25 (
.A(temp),
.B(25'b1),
.S(data_out),
.Cout()
);
endmodule
| 6.975868 |
module two_compliment10 (
data_in,
data_out
);
input [9:0] data_in;
output [9:0] data_out;
wire [9:0] temp;
//Not
assign temp = ~data_in;
//add 1
adder10 add10 (
.A(temp),
.B(10'b1),
.S(data_out),
.Cout()
);
endmodule
| 6.975868 |
module two_compliment9 (
data_in,
data_out
);
input [8:0] data_in;
output [8:0] data_out;
wire [8:0] temp;
//Not
assign temp = ~data_in;
//add 1
adder9 add9 (
.A(temp),
.B(9'b1),
.S(data_out),
.Cout()
);
endmodule
| 6.975868 |
module two_compliment8 (
data_in,
data_out
);
input [7:0] data_in;
output [7:0] data_out;
wire [7:0] temp;
//Not
assign temp = ~data_in;
//add 1
adder8 add8 (
.A(temp),
.B(8'b1),
.S(data_out),
.Cout()
);
endmodule
| 6.975868 |
module two_compliment5 (
data_in,
data_out
);
input [4:0] data_in;
output [4:0] data_out;
wire [4:0] temp;
//Not
assign temp = ~data_in;
//add 1
adder5 add5 (
.A(temp),
.B(5'b1),
.S(data_out),
.Cout()
);
endmodule
| 6.975868 |
module two_comp_t (
input [27:0] a_m_shift,
input a_s,
output [27:0] z
);
assign z = a_s ? -a_m_shift : a_m_shift; // 2's complement
endmodule
| 7.926771 |
module two_decimal_vals (
input [7:0] val,
output [6:0] seg7_dig0,
output [6:0] seg7_dig1
);
integer storage;
integer dig0;
integer dig1;
reg [3:0] result_dig0;
reg [3:0] result_dig1;
// Create the module to display the 8 bit result
always @(*) begin
storage = (val[0] * 1) + (val[1] *... | 6.564228 |
module two_decimal_vals_w_neg (
input [7:0] val,
output [6:0] seg7_neg_sign,
output [6:0] seg7_lsb,
output [6:0] seg7_mid,
output [6:0] seg7_msb
);
reg [3:0] result_one_digit;
reg [3:0] result_ten_digit;
reg [3:0] result_hundreds_digit;
reg result_is_negative;
reg [7:0] twos_comp;
... | 6.564228 |
module two_dff_inv_rst (
clk_i,
rst_i,
d_i,
d0_o,
d1_o
);
input wire clk_i;
input wire rst_i;
input wire d_i;
output reg d0_o;
output reg d1_o;
wire int_rst;
assign int_rst = ~rst_i;
always @(posedge clk_i or posedge rst_i) begin
if (rst_i) begin
d0_o <= 0;
end else ... | 7.523038 |
module Two_Digit_Counter (
input clk,
rst,
toggle,
output [6:0] seg_1,
seg_10
);
wire [3:0] bcdout_1, bcdout_10;
wire clk_1hz;
frequencyDivider f (
.rst(rst),
.clkIN(clk),
.clkOUT(clk_1hz)
);
counter c (
.clk(clk_1hz),
.rst(rst),
.toggle(toggle),
... | 7.256582 |
module fht_8x8_core (
rstn,
sclk,
x_valid,
x_data,
fht_2d_valid,
fht_2d_data
);
// Number of input bits
parameter N = 8;
input rstn;
input sclk;
input x_valid;
input [N-1:0] x_data;
output fht_2d_valid;
output [N+5:0] fht_2d_data;
// +++--->>> One-Dimensional Fast Hartley... | 7.889716 |
module fht_bfly_noFF (
a,
b,
c,
d
);
parameter N = 8;
input [N-1:0] a; // input
input [N-1:0] b; // input
output [N : 0] c; // additive output
output [N : 0] d; // subtractive output
assign c = rca_N(a, b);
assign d = rca_N(a, twos_complement(b));
// +---------------------------... | 7.21281 |
module fht_bfly (
rstn,
clk,
valid,
a,
b,
c,
d
);
parameter N = 8;
input rstn;
input clk;
input valid;
input [N-1:0] a; // input
input [N-1:0] b; // input
output [N : 0] c; // additive output
output [N : 0] d; // subtractive output
reg [N-1:0] a_FF;
always @(pos... | 7.43346 |
module mtx_trps_8x8_dpsram (
rstn,
sclk,
// Input
inp_valid,
inp_data,
// Output
mem_data,
mem_valid
);
parameter N = 8;
input rstn;
input sclk;
input inp_valid;
input [N-1:0] inp_data;
output [N-1:0] mem_data;
output mem_valid;
reg [6:0] cnt128d_wr; // Write Mode ... | 6.881801 |
module signed_mult_const_asic (
rstn,
clk,
valid,
a,
p
);
parameter N = 8;
input rstn;
input clk;
input valid;
input [N-1:0] a; // variable - positive/negative
output [N : 0] p; // product output
// FHT constant
//wire [8:0] mult_constant; // always positive
//assign mult_const... | 7.218537 |
module signed_mult_const_fpga (
rstn,
clk,
valid,
a,
p
);
parameter N = 8;
input rstn;
input clk;
input valid;
input signed [N-1:0] a; // variable - positive/negative
output signed [N : 0] p; // product output
// FHT constant
// wire [8:0] mult_constant; // always positive
// a... | 7.218537 |
module: two_d_filter
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module two_d_filter_tb_v;
// Inputs
reg aclr;
reg data_valid_in;
reg clk;
//reg clken;
reg [8:0] coef1_1;
reg [8... | 6.534878 |
module two_flop_cdc (
input wire i_clk,
input wire i_sig,
output wire o_sig
);
reg [1:0] cdc;
always @(posedge i_clk) begin
cdc[0] <= i_sig;
cdc[1] <= cdc[0];
end
assign o_sig = cdc[1];
endmodule
| 7.25602 |
module D_FF (
Q,
D,
CLK
);
input D, CLK;
output Q;
reg Q, NQ;
initial begin
Q = 0;
NQ = 0;
end
always @(posedge CLK) begin
Q <= D;
NQ <= ~D;
end
endmodule
| 7.013014 |
module two_four_decoder (
input [1:0] x,
output reg [3:0] y
);
always @(x) begin
case (x)
0: y = 4'b0001;
1: y = 4'b0010;
2: y = 4'b0100;
3: y = 4'b1000;
endcase
end
endmodule
| 6.560706 |
module two_ip_tb;
wire t_p, t_q;
reg [1:0] inTest;
gate dut (
.a(inTest[1]),
.b(inTest[0]),
.p(t_p),
.q(t_q)
);
initial begin
$monitor(inTest[0], inTest[1], t_p, t_q);
inTest = 2'b00;
#60 inTest = 2'b01;
#60 inTest = 2'b10;
#60 inTest = 2'b11;
#60 $finish;
... | 6.986443 |
module two_level_branch_predictor (
clk,
reset_n,
input_ip,
output_prediction,
input_taken
);
input clk;
input reset_n;
input [63:0] input_ip;
input [0:0] input_taken;
output [0:0] output_prediction;
reg [0:0] output_reg;
reg [1 : 0] branch_table[0:255];
reg [1 : 0] state;
reg ... | 7.330718 |
module two_level_CLA #(
parameter WIDTH_0 = 2,
parameter WIDTH_1 = 2,
parameter GROUP_COUNT = 2
) (
input carry_in,
input [GROUP_COUNT * WIDTH_1 * WIDTH_0 - 1 : 0] x,
input [GROUP_COUNT * WIDTH_1 * WIDTH_0 - 1 : 0] y,
output [GROUP_COUNT * WIDTH_1... | 8.848434 |
module two_mux (
X,
Y,
Z,
CTRL
);
//parameter definitions
parameter N = 32;
input wire [N-1:0] X, Y;
output wire [N-1:0] Z;
input wire CTRL;
//port definitions - customize for different bit widths
assign Z = CTRL ? Y : X;
endmodule
| 8.861062 |
module two_mux_4_to_1 #(
parameter DELAY = 10
) (
input s1_n,
s2_n,
a1,
a0,
d3_1,
d2_1,
d1_1,
d0_1,
d3_2,
d2_2,
d1_2,
d0_2,
output y1,
y2
);
reg y1_reg, y2_reg;
always @(*)
case ({
a1, a0
})
00: begin
y1_reg = d0_1;
y2_... | 6.679689 |
module two_port ( /*autoport*/
//output
rddata1,
rddata2,
ram_address,
ram_data_o,
ram_wr_n,
ram_rd_n,
dataenable,
//input
rst_n,
clk2x,
address1,
wrdata1,
dataenable1,
rd1,
wr1,
address2,
wrdata2,
dataenable2,
rd2,
wr2,
ram_data_i... | 6.729025 |
module two_port_ram_sclk #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 13
) (
input clk,
// Port A for write
input en_a,
input [ADDR_WIDTH-1:0] addr_a,
input [DATA_WIDTH-1:0] data,
// Port B for read
input en_b,
input [ADDR_WIDTH-1:0] addr_b,
output reg [DATA_WIDTH-1:0... | 8.716654 |
module main (
clk
);
input clk;
wire all_shared, is_sharedA, is_sharedB;
wire ND_inA, ND_inB, ndA, ndB;
wire master_outA, master_outB;
wire master_inA, master_inB;
wire inv_outA, inv_outB, invalidate;
wire mem_served;
wire info_availA, info_availB;
wire bus_reqA, bus_reqB;
wire bus_ackA, bus_ack... | 7.779865 |
module main (
clk
);
input clk;
wire all_shared, is_sharedA, is_sharedB;
wire ND_inA, ND_inB, ndA, ndB;
wire master_outA, master_outB;
wire master_inA, master_inB;
wire inv_outA, inv_outB, invalidate;
wire mem_served;
wire info_availA, info_availB;
wire bus_reqA, bus_reqB;
wire bus_ackA, bus_ack... | 7.779865 |
module two_stage_mult (
input [15:0] a,
input [15:0] b,
output [31:0] out,
input clk
);
logic [31:0] register;
logic [31:0] register2;
always @(posedge clk) begin
register <= a * b;
register2 <= register;
end
assign out = register2;
endmodule
| 7.479731 |
module Two_to_Four_MUX45bit (
R0,
R1,
R2,
R3,
QA,
Q
);
input [45:0] R0; //input for each register that could propogate to the output
input [45:0] R1;
input [45:0] R2;
input [45:0] R3;
input [1:0] QA; //address of the selected register to propogate to the output
output reg [45:0] Q... | 7.552459 |
module two_to_one #(
parameter WORD_LEN = 33
) (
input clk,
arst,
input [2*WORD_LEN-1:0] din,
input din_valid,
output din_ready,
output [WORD_LEN-1:0] dout,
input dout_ready,
output dout_valid
);
reg [1:0] holding; // holding 0..2 words
reg [2*WORD_LEN-1:0] storage;
assign... | 7.859118 |
module two_to_one_MUX (
input wire A,
input wire B,
input wire S,
output wire z
// output wire cout
);
//assign z = (A&~S) | (B&S);
assign z = (S == 1'b0) ? A : (S == 1'b1) ? B : 1'bX;
endmodule
| 7.90739 |
module two_to_one_mux_testbench;
reg a, b, s;
wire y;
two_to_one_mux m (
a,
b,
s,
y
);
initial begin
$dumpfile("dump.vcd");
$dumpvars(0, two_to_one_mux_testbench);
end
initial begin
$monitor(a, b, s, y);
s = 1'b0;
a = 1'b0;
b = 1'b0;
#5 a = 1'b0;
... | 7.326213 |
module two_wide_double_buf #(
DATA_WIDTH = 8,
ADDR_WIDTH = 6
) (
input i_clk,
input i_resetn,
// to avoid conflicts we write two values at once at sequential addresses
input [DATA_WIDTH-1 : 0] wdata0,
wdata1,
// input [ADDR_WIDTH-1 : 0] waddr,
input wen,
// output wsync, // sync ... | 8.283039 |
module two_complement (
in,
out
);
input wire [7:0] in;
output wire [7:0] out;
assign out = ~in + 8'b00000001;
endmodule
| 7.955961 |
module tx #(
parameter data_width = 8, //数据宽度
parameter test = 2, //偶校验
parameter stop_width = 1
) //结束符宽度1个高电平
(
input tx_clk,
input rst_n,
input [data_width-1:0] data_in,
input enable,
output reg tx_out
);
localparam IDLE = 3'b000;
localparam S1 = 3'b001; //发送低电平
localparam ... | 7.70951 |
module tx20_io10 (
input I_clk, // NOT USED
input I_rst_n, // NOT USED
input [1:0] I_sel, // NOT USED
input I_pll_areset,
input I_tx_inclock,
input [9:0] i0_p,
in... | 6.847858 |
module tx20_io40 (
input I_clk, // NOT USED
input I_rst_n, // NOT USED
input [1:0] I_sel, // NOT USED
input I_pll_areset,
input I_tx_inclock,
input [9:0] i0_p,
in... | 7.622132 |
module tx_tb ();
reg stm_clk, stm_rst, stm_en, stm_en_tx;
reg [7:0] stm_data;
reg [4:0] i;
reg [9:0] result;
wire tbr_mon, TxD_mon;
tx tx0 (
.clk(stm_clk),
.rst(stm_rst),
.data(stm_data),
.en(stm_en),
.en_tx(stm_en_tx),
.tbr(tbr_mon),
.TxD(TxD_mon)
);
alwa... | 6.93599 |
module tx9_io40 (
input I_clk, // NOT USED
input I_rst_n, // NOT USED
input [1:0] I_sel, // NOT USED
input I_pll_areset,
input I_tx_inclock,
input [39:0] i0_p,
in... | 6.744913 |
module TXBlock (
CONTROL,
DATA,
RST,
CLK,
STATUS,
LINE_OUT
);
parameter BAUD = 9600;
// states
parameter START = 1;
parameter WAIT = 2;
parameter TxBIT = 3;
// statuses
parameter RDY = 0;
parameter BSY = 255;
// control commands
parameter NOP = 0;
parameter SND = 255;
i... | 7.917548 |
module: TXBlock
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TXBLockTest;
// Inputs
reg [7:0] CONTROL;
reg [7:0] DATA;
reg CLK;
// Outputs
wire [7:0] STATUS;
wire LINE_OU... | 7.383826 |
module txchar (
input wire clk, //-- System clock
input wire rstn, //-- Reset (active low)
output wire tx //-- Serial data output
);
//-- Serial Unit instantation
uart_tx #(
.BAUDRATE(`B115200) //-- Set the baudrate
) TX0 (
.clk(clk),
.rstn(rstn),
.data("A"), //-- Fixed ... | 7.244689 |
module txchar_tb ();
//-- Baudrate for the simulation
localparam BAUDRATE = `B115200;
//-- clock tics needed for sending one serial package
localparam SERIAL_CHAR = (BAUDRATE * 10);
//-- System clock
reg clk = 0;
//-- Transmission line
wire tx;
//-- Reset
reg rstn = 0;
//-- Instantiate the... | 8.333383 |
module txclkdivide (
reset,
oscclk,
trcal,
dr,
txclk
);
input reset, oscclk, dr;
input [9:0] trcal; // max: 1023
output txclk;
reg txclk;
reg [6:0] counter;
// trcal3 = 3 * trcal
wire [10:0] trcal2;
assign trcal2[10:1] = trcal;
assign trcal2[0] = 1'b0;
wire [11:0] trcal3;
... | 6.827871 |
module txclkgenerator #(
parameter B = 9600, // Baud rate del dispositivo
F = 50000000, // Frecuencia del clock de la FPGA
N = 32 // Bits necesarios para el contador, 9 para 9600 y 5 para 115200
) (
input wire clk,
reset,
output wire clk_out
);
//signal declaration
reg [N-1:0] r_reg;
... | 7.021605 |
module tb_TxCore;
parameter PARITY = 1;
parameter CLK_PERIOD = 10; //should be %2
// Inputs
reg [7:0] dataIn;
reg loadDataIn;
reg [12:0] clocksPerBit;
reg stopBit2;
wire oddParity = 0; //if 1, parity bit is such that data+parity have an odd number of 1
wire msbFirst = 0; //if 1, bits will be send i... | 7.702301 |
module TxCycleCtrl (
clk,
mkReady,
txReady,
txStart
);
input clk, mkReady, txReady;
output reg txStart;
parameter [7:0] FreqInMHz = 40;
parameter [15:0] FreqOutHz = 5000;
localparam [15:0] PR = ((1000000 * FreqInMHz) / FreqOutHz) - 1;
reg [15:0] Cnt = 16'h0000;
always @(posedge clk) b... | 6.932338 |
module trans_reg (
d_in,
load,
shift,
txd,
clk,
rst
);
input [7:0] d_in;
input load;
input shift;
output txd;
input clk;
input rst;
reg [10:0] t_reg; // transmit register
integer i; // logic variable
// TxD
assign txd = t_reg[0]; // bit 0 is always output to T... | 7.307444 |
module TxData (
input SysClk,
input Reset,
output reg [6:0] HEX7, //
output reg [6:0] HEX6, //
output reg [6:0] HEX5, //
output reg [6:0] HEX4, //
output reg [6:0] HEX3, //
output reg [6:0] HEX2, //
output reg [6:0] HEX1, //
output reg [6:0] HEX0, //
output reg [1... | 6.775672 |
module TXDemo (
input Clock,
input Reset,
input start_tx,
input tx_packet_data_rdy_in,
output [15:0] tx_packet_data_out,
output tx_req_out,
input tx_complete_in,
output reg [8:0] Debug_LEDG
);
assign tx_packet_data_out = rom_data[15:0];
assign tx_req_out = state == wait_for_t... | 8.179048 |
module TxDWrapper (
input Clock,
input Reset,
input [15:0] Data,
input [1:0] RequestToSend,
output [1:0] DataReceivedOut,
output SDO
);
localparam STATE_Idle = 2'b00, STATE_Wait = 2'b01, STATE_TxDStart = 2'b010;
reg [1:0] CurrentState = STATE_Idle;
reg [1:0] NextState = STATE_Idle;
reg... | 7.771106 |
module TxFifo (
busClk,
usbClk,
rstSyncToBusClk,
rstSyncToUsbClk,
fifoREn,
fifoEmpty,
busAddress,
busWriteEn,
busStrobe_i,
busFifoSelect,
busDataIn,
busDataOut,
fifoDataOut
);
//FIFO_DEPTH = ADDR_WIDTH^2
parameter FIFO_DEPTH = 64;
parameter ADDR_WIDTH = 6;
in... | 6.747114 |
module txfifo_packet_composer #(
parameter DATA_WIDTH = 64,
parameter LOCAL_FIFO_DEPTH = 256
) (
clock,
aclr,
data,
rdreq,
wrreq,
almost_full,
empty,
full,
q,
usedw
);
function integer log2;
input integer number;
begin
log2 = 0;
while (2 ** log2 < n... | 6.503782 |
module TxFifo_simlib (
busClk,
usbClk,
rstSyncToBusClk,
rstSyncToUsbClk,
fifoREn,
fifoEmpty,
busAddress,
busWriteEn,
busStrobe_i,
busFifoSelect,
busDataIn,
busDataOut,
fifoDataOut
);
//FIFO_DEPTH = ADDR_WIDTH^2
parameter FIFO_DEPTH = 64;
parameter ADDR_WIDTH = 6... | 6.616674 |
module TxFsm (
output io_dataOut_valid,
input io_dataOut_ready,
output reg io_dataOut_payload_last,
output [511:0] io_dataOut_payload_fragment_data,
output [ 15:0] io_dataOut_payload_fragment_byteNum,
output [ 63:0] io_dataOut_payload_fragment_tkeep,
... | 7.118452 |
module txmit (
din,
tbre,
tsre,
rst,
clk16x,
wrn,
sdo
);
output tbre;
output tsre;
output sdo;
input [7:0] din;
input rst;
input clk16x;
input wrn;
reg tbre;
reg tsre;
reg clk1x_enable;
reg [7:0] tsr;
reg [7:0] tbr;
reg parity;
reg [3:0] clkdiv;
wire clk1x;
... | 7.535853 |
module TXMOD (
output TX,
input CLK,
input [7:0] data,
input valid,
output ready
);
reg TXReg = 1;
assign TX = TXReg;
reg [10:0] dataStore = 1536; // MSB=1, LSB=0
reg writing = 0;
assign ready = (writing == 0);
reg [13:0] writeClock = 0; // which cycle are we in?
reg [ 3:0] writeB... | 6.749078 |
module txrx_tb ();
//this is the testbench for the tx module independently
reg clk, Rst_n, TxData_Valid;
reg [31:0] TxData;
reg Error_Ack;
wire Rx_Ready_synth, Rx_Error_synth;
wire Rx_Ready, Rx_Error;
wire Tx_Ready_synth, Tx_Error_synth, S_Data_synth;
wire Tx_Ready, Tx_Error, S_Data;
// RX/Core Wire... | 7.547806 |
module txrx_tb ();
//this is the testbench for the tx module independently
reg clk, Rst_n, TxData_Valid;
reg [31:0] TxData;
reg Error_Ack;
wire Rx_Ready, Rx_Error;
wire Tx_Ready, Tx_Error, S_Data;
// RX/Core Wires
reg Core_Rcv_Ready = 1'b0;
wire RxData_Valid;
wire [31:0] RxData;
tx DUT (
... | 7.547806 |
module txsettings (
reset,
trcal_in,
m_in,
dr_in,
trext_in,
querycomplete,
trcal_out,
m_out,
dr_out,
trext_out
);
input reset, dr_in, trext_in, querycomplete;
input [9:0] trcal_in;
input [1:0] m_in;
output dr_out, trext_out;
output [9:0] trcal_out;
output [1:0] m_ou... | 7.689918 |
module txstr #(
parameter BAUDRATE = `B115200
) (
input wire clk, //-- System clock
input wire go, //-- When to transmit the string (pulse)
output wire tx //-- Serial data output
);
//-- Serial Unit instantation
uart_tx #(
.BAUDRATE(BAUDRATE) //-- Set the baudrate
) TX0 (
.... | 6.937204 |
module txstr_tb ();
//-- Baudrate for the simulation
localparam BAUDRATE = `B115200;
//-- clock tics needed for sending one serial package
localparam SERIAL_CAR = (BAUDRATE * 10);
//-- System clock
reg clk = 1;
//-- Transmission line
wire tx;
//-- Reset
reg rstn = 0;
//-- Instantiate the e... | 7.973423 |
module TXT (
input clk, // Input 25.175 MHz clock, this is a pixel clock for this VGA mode
input reset, // Input async. active low reset signal
output [9:0] pix_x, // The exact X coordinate of a pixel that is currently being drawn
output [9:0] pix_y, // The exact Y coordinate of a pixel that is cu... | 8.046579 |
module which generates video sync impulses
///////////////////////////////////////////////////////////////
module txtd (
// inputs:
input wire pixel_clock,
input wire [15:0]wrdata,
input wire [12:0]wradr,
input wire wren,
// outputs:
output reg hsync,
output reg vsync,
//high-color test video signal
output... | 6.687535 |
module txtest (
input wire clk,
input wire load,
output reg tx
);
parameter BAUD = `B300;
reg [9:0] shifter;
reg load_r;
wire clk_baud;
always @(posedge clk) begin
load_r <= load;
end
always @(posedge clk) begin
if (load_r == 0) shifter <= {"K", 2'b01};
else if (load_r == ... | 7.489425 |
module txtest2 (
input wire clk,
input wire load,
output reg tx
);
parameter BAUD = `B300;
reg [9:0] shifter;
reg load_r;
wire clk_baud;
always @(posedge clk) begin
load_r <= load;
end
always @(posedge clk) begin
if (load_r == 0) shifter <= {"K", 2'b01};
else if (load_r ==... | 7.654519 |
module txtest2_tb ();
//-- Baudios con los que realizar la simulacion
//-- A 300 baudios, la simulacion tarda mas en realizarse porque los
//-- tiempos son mas largos. A 115200 baudios la simulacion es mucho
//-- mas rapida
localparam BAUD = `B115200;
//-- Tics de reloj para envio de datos a esa velocidad... | 7.543185 |
module txtest2 (
input wire clk,
output reg tx
);
parameter BAUD = `B300;
parameter DELAY = `T_250ms;
reg [9:0] shifter;
reg load_r;
wire clk_baud;
wire load;
always @(posedge clk) begin
load_r <= load;
end
always @(posedge clk) begin
if (load_r == 0) shifter <= {"K", 2'b01};
... | 7.654519 |
module txtest2_tb ();
//-- Baudios con los que realizar la simulacion
//-- A 300 baudios, la simulacion tarda mas en realizarse porque los
//-- tiempos son mas largos. A 115200 baudios la simulacion es mucho
//-- mas rapida
localparam BAUD = `B115200;
//-- Tics de reloj para envio de datos a esa velocidad... | 7.543185 |
module txtest_tb ();
reg clk = 0;
localparam BAUD = `B115200;
//-- Tics de reloj para envio de datos a esa velocidad
//-- Se multiplica por 2 porque el periodo del reloj es de 2 unidades
localparam BITRATE = (BAUD << 1);
//-- Tics necesarios para enviar una trama serie completa, mas un bit adicional
lo... | 7.949722 |
module TxTop (
clk,
rst,
in_data,
para,
s_num,
d_num,
bd_rate,
start,
out_data,
T1200
);
/////////////////////////////////////////////////////////////////////////////////// inputs / outputs
input clk, rst;
input start;
input [7:0] in_data;
//selectors
input [1:0] para... | 7.031263 |
module txt_col (
for_en,
col_bak,
col_for,
r2,
r1,
r0,
g2,
g1,
g0,
b1,
b0
);
parameter BAK_COL_FILE = "";
parameter FOR_COL_FILE = "";
input for_en;
input [3:0] col_bak;
input [3:0] col_for;
wire [7:0] bak_col;
wire [7:0] for_col;
wire [7:0] col;
assign co... | 6.811509 |
module TxUnit (
Clk,
Reset,
Enable,
Load,
TxD,
TRegE,
TBufE,
DataO
);
input Clk; // Clock signal
input Reset; // Reset input
input Enable; // Enable input
input Load; // Load transmit data
output TxD; // RS-232 data output
output TRegE; // Tx register empty
output TB... | 6.53096 |
module tx_24bits (
input CLK,
input RST,
input [19:0] tx_data,
input tx_vld,
output tx
);
wire clk_800;
CLKDIV_800 gen8bits (
.CLK (CLK),
.RST (RST),
.CLK_O(clk_800)
);
reg [19:0] temp_data = 20'b0;
always @(posedge CLK) begin
if (RST) temp_data <= 20'b0;
else i... | 7.057222 |
module tx_4channel_arbiter #(
parameter NUM_DAT_WORDS = 8,
parameter LOG_DAT_WORDS = 4, // enough bits to represent 0..#dat inclusive
parameter CHANID0 = 8'h0,
parameter CHANID1 = 8'h1,
parameter CHANID2 = 8'h2,
parameter CHANID3 = 8'h3
) (
input clk,
arst,
// four input ports
... | 7.025033 |
module tx_64b_tb;
parameter VCD_FILE = "tx_tb.vcd";
parameter NUM_LANES = 1;
parameter NUM_LINKS = 1;
parameter OCTETS_PER_FRAME = 4;
parameter FRAMES_PER_MULTIFRAME = 32;
`include "tb_base.v"
reg [NUM_LINKS-1:0] sync = {NUM_LINKS{1'b1}};
reg [31:0] counter = 'h00;
reg [63:0] tx_data = 'h00000000;
... | 7.880524 |
modules to simplify interface
// Note the MSB and LSB sequence
// LSB first for both input and output data
module TX_8B10B_ENC(
input i_clk
,input i_rst_n
//output for 8b/10b encoder
,input [7:0] i_8b_data
,input i_8b_datak
... | 7.112616 |
module tx_axis_adapter (
input clk_mac,
input rst_n,
output reg tx_vld,
output reg [7:0] tx_dat,
output reg tx_sof,
output reg tx_eof,
input tx_ack,
input [7:0] tx_axis_mac_tdata,
input tx_axis_mac_tvalid,
input tx_axis_mac_tlast,
... | 9.052983 |
module tx_band_gen (
input clk,
input rst,
input band_sig,
output reg clk_bps
);
/////////////////////
parameter SYS_RATE = 100000000;
parameter BAND_RATE = 9600;
parameter CNT_BAND = SYS_RATE / BAND_RATE;
///////////////////////////
reg [13:0] cnt_bps;
always @(posedge clk or posedge rst)... | 7.079829 |
module tx_baudrate_tick_generator #(
parameter baudrate = 32'd9600,
parameter frequency = 32'd100000000 // in Hz
) (
input wire clk,
input wire reset,
input wire enable,
output reg tick
);
reg [31:0] count;
localparam [31:0] count_threshold = frequency / (baudrate * 2);
initial beg... | 7.205239 |
module stimulus();
// reg CLK,RESET;
// wire TICK;
// tx_baudrate_tick_generator #(.baudrate(32'd9600),.frequency(32'd100000000))
// t1(
// .clk(CLK),
// .tick(TICK),
// .reset(RESET)
// );
// initial begin
// $dumpfile("simulation.vcd");
// $dumpvars(0,
// CLK,
// TICK,
// RESET
/... | 6.85176 |
module
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tx_bps_module(
CLK,
RST_n,
Count_Sig,
... | 7.088073 |
module tx_buffer ( // USB Side
input usbclk,
input bus_reset, // Used here for the 257-Hack to fix the FX2 bug
input [15:0] usbdata,
input wire WR,
output reg have_space,
output reg tx_underrun,
input clear_status,
// DSP Side
input txclk,
input reset, // standard DSP-side re... | 7.163892 |
module tx_chain (
input clock,
input reset,
input enable,
input wire [7:0] interp_rate,
input sample_strobe,
input interpolator_strobe,
input wire [31:0] freq,
input wire [15:0] i_in,
input wire [15:0] q_in,
output wire [15:0] i_out,
output wire [15:0] q_out
);
wire [15:0]... | 7.160319 |
module tx_chain_hb (
input clock,
input reset,
input enable,
input wire [7:0] interp_rate,
input sample_strobe,
input interpolator_strobe,
input hb_strobe,
input wire [31:0] freq,
input wire [15:0] i_in,
input wire [15:0] q_in,
output wire [15:0] i_out,
output wire [15:0]... | 7.397822 |
module TX_CHAR_REPLACE#(
parameter AM_INTERVAL = 64 //should be large than the rx deksew fifo depth
)(
input i_clk
,input i_rst_n
//rs encoded data
,input i_sof_in
,input [31:0] i_data_in
,input [3:0] i_data_valid_in
//o... | 6.61175 |
module tx_checkCurrentPacket_dev_regslice_both #(
parameter DataWidth = 32
) (
input ap_clk,
input ap_rst,
input [DataWidth-1:0] data_in,
input vld_in,
output ack_in,
output [DataWidth-1:0] data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_... | 7.081267 |
module tx_checkCurrentPacket_dev_regslice_both_w1 #(
parameter DataWidth = 1
) (
input ap_clk,
input ap_rst,
input data_in,
input vld_in,
output ack_in,
output data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire B_V_data_... | 7.081267 |
module tx_checkCurrentPacket_dev_regslice_forward #(
parameter DataWidth = 32
) (
input ap_clk,
input ap_rst,
input [DataWidth-1:0] data_in,
input vld_in,
output ack_in,
output [DataWidth-1:0] data_out,
output vld_out,
input ack_out,
output apdone_blk
);
localparam W = DataWi... | 7.081267 |
module tx_checkCurrentPacket_dev_regslice_forward_w1 #(
parameter DataWidth = 1
) (
input ap_clk,
input ap_rst,
input data_in,
input vld_in,
output ack_in,
output data_out,
output vld_out,
input ack_out,
output apdone_blk
);
localparam W = 2;
wire [W-1:0] cdata;
wire ... | 7.081267 |
module tx_checkCurrentPacket_dev_regslice_obuf #(
parameter W = 32
) (
input clk,
input reset,
input [W-1:0] cdata,
output cstop,
output reg [W-1:0] odata,
input ostop
);
// Stop the core when buffer full and output not ready
assign cstop = reset ? 1'b1 : (odata[W-1] & ostop);
always... | 7.081267 |
module tx_checkTimeout_dev_header_m_axi_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire sclk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output... | 6.500458 |
module tx_checkTimeout_dev_header_m_axi_fifo #(
parameter DATA_BITS = 8,
DEPTH = 16,
DEPTH_BITS = 4
) (
input wire sclk,
input wire reset,
input wire sclk_en,
output reg empty_n,
output reg ... | 6.500458 |
module tx_checkTimeout_dev_header_m_axi_buffer #(
parameter MEM_STYLE = "block",
DATA_WIDTH = 32,
ADDR_WIDTH = 5,
DEPTH = 32
) (
// system signal
input wire clk,
input wire reset,
input wire sclk_en,
// write
output wire if_fu... | 6.500458 |
module tx_checkTimeout_dev_header_m_axi_decoder #(
parameter DIN_WIDTH = 3
) (
input wire [ DIN_WIDTH-1:0] din,
output reg [2**DIN_WIDTH-1:0] dout
);
integer i;
always @(din) begin
dout = {2 ** DIN_WIDTH{1'b0}};
for (i = 0; i < din; i = i + 1) dout[i] = 1'b1;
end
endmodule
| 6.500458 |
module tx_checkTimeout_dev_mul_64ns_66ns_129_6_1_Multiplier_0 (
clk,
ce,
a,
b,
p
);
input clk;
input ce;
input [64 - 1 : 0] a;
input [66 - 1 : 0] b;
output [129 - 1 : 0] p;
reg [ 64 - 1 : 0] a_reg0;
reg [ 66 - 1 : 0] b_reg0;
wire [129 - 1 : 0] tmp_product;
reg [129 - 1 : 0] buf... | 6.500458 |
module tx_checkTimeout_dev_mul_64ns_66ns_129_6_1 (
clk,
reset,
ce,
din0,
din1,
dout
);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input [din0_WID... | 6.500458 |
module tx_checkTimeout_dev_mul_65s_67ns_131_6_1_Multiplier_1 (
clk,
ce,
a,
b,
p
);
input clk;
input ce;
input [65 - 1 : 0] a;
input [67 - 1 : 0] b;
output [131 - 1 : 0] p;
reg signed [65 - 1 : 0] a_reg0;
reg [67 - 1 : 0] b_reg0;
wire signed [131 - 1 : 0] tmp_product;
reg signed [1... | 6.500458 |
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