code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module inv_w_pu_g (
Y,
A,
gnd_node
);
output Y;
input A;
input gnd_node;
assign Y = !A;
endmodule
| 7.549095 |
module inv_w_pu_hvt (
Y,
A
);
output Y;
input A;
assign Y = !A;
endmodule
| 7.846323 |
module inv_w_pu_hvt_g (
Y,
A,
gnd_node
);
output Y;
input A;
input gnd_node;
assign Y = !A;
endmodule
| 8.042685 |
module mux2 (
out,
in0,
in1,
sel
);
output out;
input in0;
input in1;
input sel;
assign out = (sel) ? in1 : in0;
endmodule
| 6.762042 |
module mux2_g (
out,
in0,
in1,
sel,
gnd_node
);
output out;
input in0;
input in1;
input sel;
input gnd_node;
assign out = (sel) ? in1 : in0;
endmodule
| 6.866418 |
module mux2_hvt (
out,
in0,
in1,
sel
);
output out;
input in0;
input in1;
input sel;
assign out = (sel) ? in1 : in0;
endmodule
| 8.126877 |
module mux2_hvt_g (
out,
in0,
in1,
sel,
gnd_node
);
output out;
input in0;
input in1;
input sel;
input gnd_node;
assign out = (sel) ? in1 : in0;
endmodule
| 7.104145 |
module mux3_25 (
out,
in0,
in1,
in2,
sel
);
output out;
input in0;
input in1;
input in2;
input [3:0] sel;
reg out;
always @(sel or in0 or in1 or in2) begin
if (sel == 4'b1001) out = in0;
else if (sel == 4'b1010) out = in1;
else if (sel == 4'b1100) out = in2;
else out... | 6.64393 |
module mux3 (
out,
in0,
in1,
in2,
sel
);
output out;
input in0;
input in1;
input in2;
input [3:0] sel;
reg out;
always @(sel or in0 or in1 or in2) begin
if (sel == 4'b1001) out = in0;
else if (sel == 4'b1010) out = in1;
else if (sel == 4'b1100) out = in2;
else out = ... | 7.29964 |
module nand2_18 (
Y,
A,
B
);
output Y;
input A;
input B;
assign Y = ~(A & B);
endmodule
| 8.085373 |
module nand2_lvt (
Y,
A,
B
);
output Y;
input A;
input B;
assign Y = ~(A & B);
endmodule
| 9.305138 |
module nand2_18_g (
Y,
A,
B,
gnd_node
);
output Y;
input A;
input B;
input gnd_node;
initial begin
Y = 1;
end
reg Y;
always @(A or B or gnd_node)
if (gnd_node == 1'b0) Y = ~(A & B);
else Y = 1'bz;
endmodule
| 6.739653 |
module nand2_25_g (
Y,
A,
B,
gnd_node
);
output Y;
input A;
input B;
input gnd_node;
reg Y;
always @(A or B or gnd_node)
if (gnd_node == 1'b0) Y = ~(A & B);
else Y = 1'bz;
endmodule
| 6.963533 |
module nand2_33 (
Y,
A,
B
);
output Y;
input A;
input B;
assign Y = ~(A & B);
endmodule
| 8.526801 |
module nand2_33_g (
Y,
A,
B,
gnd_node
);
output Y;
input A;
input B;
input gnd_node;
reg Y;
always @(A or B or gnd_node)
if (gnd_node == 1'b0) Y = ~(A & B);
else Y = 1'bz;
endmodule
| 6.898864 |
module nand2_33_hv (
out,
in1,
in2,
vdd33
);
output out;
input vdd33;
input in1;
input in2;
assign out = ~(in1 & in2);
endmodule
| 8.652404 |
module nand2 (
Y,
A,
B
);
output Y;
input A;
input B;
assign Y = ~(A & B);
endmodule
| 9.113032 |
module nand2_g (
Y,
A,
B,
gnd_node
);
output Y;
input A;
input B;
input gnd_node;
reg Y;
always @(A or B or gnd_node)
if (gnd_node == 1'b0) Y = ~(A & B);
else Y = 1'bz;
endmodule
| 6.789204 |
module nand2_hvt (
Y,
A,
B
);
output Y;
input A;
input B;
assign Y = ~(A & B);
endmodule
| 9.392288 |
module nand2_hvt_g (
Y,
A,
B,
gnd_node
);
output Y;
input A;
input B;
input gnd_node;
reg Y;
always @(A or B or gnd_node)
if (gnd_node == 1'b0) Y = ~(A & B);
else Y = 1'bz;
endmodule
| 7.157983 |
module nand3_18 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
assign Y = ~(A & B & C);
endmodule
| 7.560604 |
module nand3_33 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
assign Y = ~(A & B & C);
endmodule
| 8.100182 |
module nand3_33_g (
Y,
A,
B,
C,
gnd_node
);
output Y;
input A;
input B;
input C;
input gnd_node;
reg Y;
always @(A or B or C or gnd_node)
if (gnd_node == 1'b0) Y = ~(A & B & C);
else Y = 1'bz;
endmodule
| 6.623985 |
module nand3 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
assign Y = ~(A & B & C);
endmodule
| 8.175282 |
module nand3_hvt (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
assign Y = ~(A & B & C);
endmodule
| 8.69723 |
module nand4_18 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
assign Y = ~(A & B & C & D);
endmodule
| 7.842592 |
module nand4_25_g (
Y,
A,
B,
C,
D,
gnd_node
);
output Y;
input A;
input B;
input C;
input D;
input gnd_node;
reg Y;
always @(A or B or C or D)
if (gnd_node == 1'b0) Y = ~(A & B & C & D);
else Y = 1'bz;
endmodule
| 6.961719 |
module nand4_33 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
assign Y = ~(A & B & C & D);
endmodule
| 8.403222 |
module nand4_33_g (
Y,
A,
B,
C,
D,
gnd_node
);
output Y;
input A;
input B;
input C;
input D;
input gnd_node;
reg Y;
always @(A or B or C or D)
if (gnd_node == 1'b0) Y = ~(A & B & C & D);
else Y = 1'bz;
endmodule
| 7.303227 |
module nand4 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
assign Y = ~(A & B & C & D);
endmodule
| 8.989501 |
module nand4_g (
Y,
A,
B,
C,
D,
gnd_node
);
output Y;
input A;
input B;
input C;
input D;
input gnd_node;
reg Y;
always @(A or B or C or D)
if (gnd_node == 1'b0) Y = ~(A & B & C & D);
else Y = 1'bz;
endmodule
| 6.877974 |
module nand4_hvt (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
assign Y = ~(A & B & C & D);
endmodule
| 8.931189 |
module nand4_hvt_g (
Y,
A,
B,
C,
D,
gnd_node
);
output Y;
input A;
input B;
input C;
input D;
input gnd_node;
reg Y;
always @(A or B or C or D)
if (gnd_node == 1'b0) Y = ~(A & B & C & D);
else Y = 1'bz;
endmodule
| 6.680195 |
module nor2_18 (
Y,
A,
B
);
output Y;
input A;
input B;
assign Y = ~(A | B);
endmodule
| 7.524882 |
module nor2_lvt (
Y,
A,
B
);
output Y;
input A;
input B;
assign Y = ~(A | B);
endmodule
| 8.594783 |
module nor2_18_g (
Y,
A,
B,
gnd_node
);
output Y;
input A;
input B;
input gnd_node;
reg Y;
always @(A or B or gnd_node)
if (gnd_node == 1'b0) Y = ~(A | B);
else Y = 1'bz;
endmodule
| 6.636566 |
module nor2_33 (
Y,
A,
B
);
output Y;
input A;
input B;
assign Y = ~(A | B);
endmodule
| 7.614976 |
module nor2_33_g (
Y,
A,
B,
gnd_node
);
output Y;
input A;
input B;
input gnd_node;
reg Y;
always @(A or B or gnd_node)
if (gnd_node == 1'b0) Y = ~(A | B);
else Y = 1'bz;
endmodule
| 6.718455 |
module nor2 (
Y,
A,
B
);
output Y;
input A;
input B;
assign Y = ~(A | B);
endmodule
| 8.297456 |
module nor2_g (
Y,
A,
B,
gnd_node
);
output Y;
input A;
input B;
input gnd_node;
reg Y;
always @(A or B or gnd_node)
if (gnd_node == 1'b0) Y = ~(A | B);
else Y = 1'bz;
endmodule
| 6.75369 |
module nor2_hvt (
Y,
A,
B
);
output Y;
input A;
input B;
assign Y = ~(A | B);
endmodule
| 8.725239 |
module nor2_hvt_g (
Y,
A,
B,
gnd_node
);
output Y;
input A;
input B;
input gnd_node;
reg Y;
always @(A or B or gnd_node)
if (gnd_node == 1'b0) Y = ~(A | B);
else Y = 1'bz;
endmodule
| 6.999871 |
module nor3_18 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
assign Y = ~(A | B | C);
endmodule
| 7.205138 |
module nor3_33 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
assign Y = ~(A | B | C);
endmodule
| 7.234638 |
module nor3 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
assign Y = ~(A | B | C);
endmodule
| 7.681855 |
module nor3_hvt (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
assign Y = ~(A | B | C);
endmodule
| 7.780348 |
module nor4_hvt (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
assign Y = ~(A | B | C | D);
endmodule
| 7.961286 |
module oai21x2_18_g (
Y,
A0,
A1,
B0,
gnd_node
);
output Y;
input A0;
input A1;
input B0;
input gnd_node;
reg Y;
always @(A0 or A1 or B0 or gnd_node)
if (gnd_node == 1'b0) begin
if (B0 == 1'b0) begin
Y = 1'b1;
end else begin
Y = !(A0 | A1);
end
... | 6.599237 |
module oai21x2_g (
Y,
A0,
A1,
B0,
gnd_node
);
output Y;
input A0;
input A1;
input B0;
input gnd_node;
reg Y;
always @(A0 or A1 or B0)
if (B0 == 1'b0) begin
Y = 1'b1;
end else begin
Y = !(A0 | A1);
end
endmodule
| 6.538832 |
module clkandnor22_hvt (
y,
a,
b,
c,
d
);
output y;
input a;
input b;
input c;
input d;
assign y = !((a & b) | (c & d));
endmodule
| 7.596161 |
module mux2_4lutx1_hvt_g (
out,
in0,
in1,
sel,
sel_b
);
output out;
input in0;
input in1;
input sel;
input sel_b;
assign out = (sel) ? in1 : in0;
endmodule
| 7.419326 |
module mux2x1_hvt (
out,
in0,
in1,
sel
);
output out;
input in0;
input in1;
input sel;
assign out = (sel) ? in1 : in0;
endmodule
| 8.134428 |
module clut4 (lut4, in0, in1, in2, in3, in0b, in1b, in2b, in3b, cbit);
//the output signal
output lut4;
//the input signals
input in0, in1, in2, in3, in0b, in1b, in2b, in3b;
input [15:0] cbit;
reg lut4;
`ifdef TIMINGCHECK
specify
// delay parameters
specparam
tplh$cbit0$lut4= 1.0,
tphl$c... | 7.764978 |
module cram_cell_3 (
q,
q_b,
bl,
r_gnd,
reset_b,
wl
);
output q;
output q_b;
inout bl;
input r_gnd;
input reset_b;
input wl;
reg q, blreg;
always @(bl or r_gnd or reset_b or wl)
if ((r_gnd == 1'b0) && (reset_b == 1'b0)) q = 1'b0;
else if ((wl == 1'b1) && (bl == 1'b0)) q =... | 6.620075 |
module mux2_defaultHigh (
Y,
A,
S0
);
output Y;
input A;
input S0;
reg Y;
always @(A or S0)
if (S0 == 1'b0) Y = 1'b1;
else Y = A;
endmodule
| 6.905997 |
module osc_logic (
clkin,
smc_oscen,
smc_osc_fsel,
sel_trim
);
input clkin;
input smc_oscen;
input [1:0] smc_osc_fsel;
output [3:0] sel_trim;
//Signal declaration
wire [2:0] in_sel;
wire clkin_buf_b;
wire reset_ff;
wire clkin_buf;
wire clkin_buf_delay;
reg i174q;
reg i238q;
r... | 6.74015 |
module carry_logic_nand (
cout,
carry_in,
a,
a_bar,
b,
b_bar,
vg_en
);
//the output signal
output cout;
//the input signals
input carry_in, a, a_bar, b, b_bar, vg_en;
`ifdef TIMINGCHECK
specify
// delay parameters
specparam
tplh$carry_in$cout= 1.0,
tphl$carry... | 6.500349 |
module nch_na25_macx (
D,
S,
G
);
inout D;
input G, S;
nmos (D, S, G); // D S G
//nmos (S, D, ~G); // D S G
endmodule
| 6.508578 |
module nand3_lvt (
A,
B,
C,
Y
);
input A, B, C;
output Y;
assign Y = ~(A & B & C);
endmodule
| 8.437168 |
module anor21_lvt (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
reg Y;
always @(A or B or C) Y = ~(C | (B * A));
endmodule
| 6.881661 |
module chiplib_mux4 (
input a,
input b,
input c,
input d,
input [1:0] s,
output y
);
`ifdef FPGA_SYNTH
assign y = (s == 2'b11) ? d : ((s == 2'b10) ? c : ((s == 2'b01) ? b : a));
`else
MX2_X4M_A9TH u_DONT_TOUCH_mux2_inst0 (
.A (a),
.B (b),
... | 7.053874 |
module dual_AsyncResetReg (
d,
q,
en,
clk,
rst
);
parameter RESET_VALUE = 0;
input wire d;
output reg q;
input wire en;
input wire clk;
input wire rst;
// There is a lot of initialization
// here you don't normally find in Verilog
// async registers because of scenarios in which ... | 6.946622 |
module dual_AsyncResetRegVec_w1_i0 (
input clock,
input reset,
input io_d,
output io_q,
input io_en
);
wire reg_0_d;
wire reg_0_q;
wire reg_0_en;
wire reg_0_clk;
wire reg_0_rst;
dual_AsyncResetReg #(
.RESET_VALUE(0)
) reg_0 (
.d (reg_0_d),
.q (reg_0_q),
.e... | 6.946622 |
module dual_AsyncResetRegVec_w4_i0 (
input clock,
input reset,
input [3:0] io_d,
output [3:0] io_q,
input io_en
);
wire reg_0_d;
wire reg_0_q;
wire reg_0_en;
wire reg_0_clk;
wire reg_0_rst;
wire reg_1_d;
wire reg_1_q;
wire reg_1_en;
wire reg_1_clk;
wire reg_... | 6.946622 |
module dual_AsyncResetSynchronizerShiftReg_w1_d1_i0 (
input clock,
input reset,
input io_d,
output io_q
);
wire sync_0_clock;
wire sync_0_reset;
wire sync_0_io_d;
wire sync_0_io_q;
wire sync_0_io_en;
dual_AsyncResetRegVec_w1_i0 sync_0 (
.clock(sync_0_clock),
.reset(sync_0_rese... | 6.946622 |
module dual_AsyncResetSynchronizerShiftReg_w1_d3_i0 (
input clock,
input reset,
input io_d,
output io_q
);
wire sync_0_clock;
wire sync_0_reset;
wire sync_0_io_d;
wire sync_0_io_q;
wire sync_0_io_en;
wire sync_1_clock;
wire sync_1_reset;
wire sync_1_io_d;
wire sync_1_io_q;
wire sy... | 6.946622 |
module dual_AsyncResetSynchronizerShiftReg_w1_d4_i0 (
input clock,
input reset,
input io_d,
output io_q
);
wire sync_0_clock;
wire sync_0_reset;
wire sync_0_io_d;
wire sync_0_io_q;
wire sync_0_io_en;
wire sync_1_clock;
wire sync_1_reset;
wire sync_1_io_d;
wire sync_1_io_q;
wire sy... | 6.946622 |
module dual_AsyncResetSynchronizerShiftReg_w4_d3_i0 (
input clock,
input reset,
input [3:0] io_d,
output [3:0] io_q
);
wire sync_0_clock;
wire sync_0_reset;
wire [3:0] sync_0_io_d;
wire [3:0] sync_0_io_q;
wire sync_0_io_en;
wire sync_1_clock;
wire sync_1_reset;
wire [3:0] ... | 6.946622 |
module dual_AsyncValidSync_1 (
input clock,
input reset,
input io_in,
output io_out
);
wire sink_extend_clock;
wire sink_extend_reset;
wire sink_extend_io_d;
wire sink_extend_io_q;
dual_AsyncResetSynchronizerShiftReg_w1_d1_i0 sink_extend (
.clock(sink_extend_clock),
.reset(sink_... | 6.952074 |
module dual_AsyncValidSync_2 (
input clock,
input reset,
input io_in,
output io_out
);
wire sink_valid_clock;
wire sink_valid_reset;
wire sink_valid_io_d;
wire sink_valid_io_q;
dual_AsyncResetSynchronizerShiftReg_w1_d3_i0 sink_valid (
.clock(sink_valid_clock),
.reset(sink_valid_... | 6.952074 |
module dual_AsyncValidSync (
input clock,
input reset,
input io_in,
output io_out
);
wire source_valid_clock;
wire source_valid_reset;
wire source_valid_io_d;
wire source_valid_io_q;
dual_AsyncResetSynchronizerShiftReg_w1_d4_i0 source_valid (
.clock(source_valid_clock),
.reset(s... | 6.952074 |
module dual_HellaQueue (
input clock,
input reset,
output io_enq_ready,
input io_enq_valid,
input [31:0] io_enq_bits,
input io_deq_ready,
output io_deq_valid,
output [31:0] io_deq_bits
);
wire fq_clock;
wire fq_reset;
wire fq_io_enq_re... | 7.271064 |
module dual_ParitalExtractor_1 (
input clock,
input reset,
input io_last,
output io_i_ready,
input io_i_valid,
input [2:0] io_i_bits_opcode,
output io_o_valid
);
reg [3:0] state;
reg [31:0] _RAND_0;
wire enable;
wire empty;
wire _GEN_1;
wi... | 6.934801 |
module dual_ParitalExtractor (
input clock,
input reset,
input io_last,
output io_i_ready,
input io_i_valid,
input [ 2:0] io_i_bits_opcode,
input [ 2:0] io_i_bits_param,
input [ 3:0] io_i_bits_size,
input [ 5:0] io_i_bits_source,
input ... | 6.934801 |
module dual_plusarg_reader #(
parameter FORMAT = "borked=%d",
DEFAULT = 0
) (
output [31:0] out
);
`ifdef SYNTHESIS
assign out = DEFAULT;
`else
reg [31:0] myplus;
assign out = myplus;
initial begin
if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;
end
`endif
endmodule
| 7.047631 |
module dual_ram_ext (
input W0_clk,
input [10:0] W0_addr,
input W0_en,
input [31:0] W0_data,
input R0_clk,
input [10:0] R0_addr,
input R0_en,
output [31:0] R0_data
);
reg reg_R0_ren;
reg [10:0] reg_R0_addr;
reg [31:0] dual_ram[2047:0];
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
... | 6.904976 |
module dual_ResetCatchAndSync_d3 (
input clock,
input reset,
output io_sync_reset
);
wire AsyncResetSynchronizerShiftReg_w1_d3_i0_clock;
wire AsyncResetSynchronizerShiftReg_w1_d3_i0_reset;
wire AsyncResetSynchronizerShiftReg_w1_d3_i0_io_d;
wire AsyncResetSynchronizerShiftReg_w1_d3_i0_io_q;
wire ... | 6.685157 |
module dual_SinkC(
input clock,
input reset,
input io_q_ready,
output io_q_valid,
output [31:0] io_q_bits_data,
output io_q_bits_last
);
reg [1:0] state;
reg [31:0] _RAND_0;
wire _T_21;
wire _T_22;
wire _T_23;
wire _T_24;
wire _T_26;
wi... | 6.713193 |
module dual_SinkE (
output [31:0] io_q_bits_data,
input [15:0] io_d_clSink
);
wire [22:0] _T_16;
assign _T_16 = {io_d_clSink, 3'h0, 4'h0};
assign io_q_bits_data = {_T_16, 9'h4};
endmodule
| 7.963865 |
module dual_SourceE (
input io_e_ready,
output io_e_valid,
output io_e_bits_sink,
output io_q_ready,
input io_q_valid,
input [31:0] io_q_bits
);
wire [15:0] q_sink;
assign q_sink = io_q_bits[31:16];
assign io_e_valid = io_q_valid;
assign io_e_bits_si... | 7.808107 |
module declaration
// This one is for driving shared ports and is asynchronous
//
//-------------------------------------------------------------------
module shared_vio
(
CONTROL,
ASYNC_IN,
ASYNC_OUT
);
input [35:0] CONTROL;
input [31:0] ASYNC_IN;
output [31:0] ASYNC_OUT;
endmodule
| 6.929638 |
module Module_FrequencyDivider (
clk_in,
period,
clk_out
);
input clk_in;
input [29:0] period;
output clk_out;
reg clk_out;
reg [29:0] counter;
always @(posedge clk_in) begin
if (counter >= (period - 1)) begin
counter <= 0;
clk_out <= ~clk_out;
end else counter <= count... | 6.759927 |
module Module_Ladder_8_bit_SR (
qzt_clk,
clk_in,
pulse_up,
pulse_down,
reset,
set,
presetValue,
limit,
out,
carry
);
input qzt_clk;
input clk_in;
input pulse_up;
input pulse_down;
input reset;
input set;
input [7:0] presetValue;
input [7:0] limit;
output [7:0... | 6.860549 |
module Module_Multiplexer_2_input_8_bit_sync (
clk_in,
address,
input_0,
input_1,
mux_output
);
input clk_in;
input address;
input [7:0] input_0;
input [7:0] input_1;
output [7:0] mux_output;
reg [7:0] mux_output;
always @(posedge clk_in) begin
mux_output <= (address) ? input_... | 6.514431 |
module Module_Monostable (
clk_in,
monostable_input,
N,
monostable_output
);
input clk_in;
input monostable_input;
input [27:0] N;
output monostable_output;
reg monostable_output;
reg monostable_input_old;
reg [27:0] counter;
always @(posedge clk_in) begin
if (counter == 0) beg... | 7.182172 |
module Module_Monostable_enforced (
clk_in,
monostable_input,
N,
monostable_output
);
input clk_in;
input monostable_input;
input [27:0] N;
output monostable_output;
reg monostable_output;
reg monostable_input_old;
reg [27:0] counter;
always @(posedge clk_in) begin
if (counter ... | 7.182172 |
module Module_Latch_16_bit (
clk_in,
holdFlag,
twoByteInput,
twoByteOuput
);
input clk_in;
input holdFlag;
input [15:0] twoByteInput;
output [15:0] twoByteOuput;
reg [15:0] twoByteOuput;
always @(posedge clk_in) begin
if (!holdFlag) twoByteOuput <= twoByteInput;
end
endmodule
| 6.620883 |
module ml_testdec_columns (
bl,
dec_det_even_25,
dec_det_odd_25
);
input dec_det_even_25, dec_det_odd_25;
inout [1:0] bl;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
supply1 VDD_;
nch_25 M5 (
.D(vdd_),
.B(gnd_),
.G(dec_det_even_... | 6.949738 |
module ml_ymux_bls_x8 (
bl,
bl_out,
vblinhi_pgm_25,
vblinhi_rde,
vblinhi_rdo,
vdd_tieh,
yp3_25,
yp3_b_25
);
inout bl_out, vblinhi_pgm_25, vblinhi_rde, vblinhi_rdo, vdd_tieh;
inout [7:0] bl;
input [7:0] yp3_b_25;
input [7:0] yp3_25;
supply1 vdd_;
supply0 gnd_;
//wire vddp... | 7.048968 |
module ml_ymux_bls_x64 (
bl,
bl_out,
vblinhi_pgm_25,
vblinhi_rde,
vblinhi_rdo,
vdd_tieh,
yp2,
yp2_b_25,
yp3_25,
yp3_b_25
);
inout bl_out, vblinhi_pgm_25, vblinhi_rde, vblinhi_rdo, vdd_tieh;
inout [63:0] bl;
input [7:0] yp2;
input [7:0] yp2_b_25;
input [7:0] yp3_25;
... | 7.048968 |
module out_logic_v3 (
dout,
sdo,
sp12,
bl,
bs_en,
ceb,
clk,
ddr0,
ddr1,
mode,
pgate,
prog,
reset,
rstio,
sdi,
shift,
slfop,
tclk,
ud,
vdd_cntl,
wl
);
output dout, sdo, sp12;
input bs_en, ceb, clk, ddr0, ddr1, mode, prog, rstio, sd... | 6.678151 |
module ioe_logic_v3 (
padeb,
sdo,
sp12,
bl,
bs_en,
ceb,
clk,
din,
hiz_b,
mode,
pgate,
prog,
reset,
rstio,
sdi,
shift,
slfop,
tclk,
ud,
vdd_cntl,
wl
);
output padeb, sdo, sp12;
input bs_en, ceb, clk, din, hiz_b, mode, prog, rstio, ... | 6.772624 |
module io_odrv4x5 (
cbit,
sp4_out,
bl,
pgate,
prog,
reset,
slfop,
vdd_cntl,
wl
);
input prog, slfop;
output [4:0] sp4_out;
output [7:5] cbit;
inout [3:0] bl;
input [1:0] vdd_cntl;
input [1:0] reset;
input [1:0] pgate;
input [1:0] wl;
supply0 gnd_;
supply1 vdd... | 7.043085 |
module io_col_odrv4_x40bare (
cf,
bl,
sp4_h_l,
sp4_v_b,
dout0,
dout1,
pgate,
prog,
reset,
vdd_cntl,
wl
);
input prog;
output [23:0] cf;
inout [3:0] bl;
inout [15:0] sp4_v_b;
inout [47:0] sp4_h_l;
input [0:1] dout0;
input [0:1] dout1;
input [15:0] pgate;
... | 7.038065 |
module cram2x2x6 (
q,
q_b,
bl,
pgate,
r_gnd,
reset_b,
wl
);
output [23:0] q;
output [23:0] q_b;
inout [11:0] bl;
input [1:0] reset_b;
input [1:0] wl;
input [1:0] pgate;
input [1:0] r_gnd;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply... | 6.651239 |
module span4_switchandmem (
b,
bl,
l,
r,
t,
pgate,
prog,
reset_b,
vdd_cntl,
wl
);
input prog;
inout [11:0] l;
inout [11:0] t;
inout [11:0] r;
inout [11:0] b;
inout [9:0] bl;
input [15:0] vdd_cntl;
input [15:0] wl;
input [15:0] reset_b;
input [15:0] pgate;
... | 7.107335 |
module odrv12_30 (
sp4_h_r,
sp4_r_v_b,
sp4_v_b,
sp12_h_r,
sp12_v_b,
cbitb,
prog,
slfop
);
output sp12_h_r;
input prog, slfop;
output [2:0] sp4_h_r;
output [2:0] sp4_v_b;
output [1:0] sp12_v_b;
output [2:0] sp4_r_v_b;
input [11:0] cbitb;
supply1 vdd_;
supply0 gnd_;
... | 6.657756 |
module ml_mux2_hvt_schematic (
out,
in0,
in1,
sel
);
output out;
input in0, in1, sel;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
supply1 VDD_;
txgate_hvt I31 (
.in (in1),
.out(out),
.pp (net25),
.nn (sel)
);
txgate... | 7.095052 |
module fabric_outbuf12p (
cout,
fabric_out
);
output cout;
input fabric_out;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
supply1 VDD_;
inv_hvt I24 (
.A(fabric_out),
.Y(net19)
);
inv_hvt I23 (
.A(net19),
.Y(cout)
);
endmo... | 6.604346 |
module nvcm_cell_2x8 (
bl,
wp,
wr
);
inout [1:0] bl;
input [7:0] wr;
input [7:0] wp;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
supply1 VDD_;
nvcm_cell_2x1 m7 (
.bl(bl[1:0]),
.wr(wr[7]),
.wp(wp[7])
);
nvcm_cell_2x1 m6 (
... | 6.933495 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.