code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module IntSyncAsyncCrossingSink (
input clock,
input auto_in_sync_0,
input auto_in_sync_1,
input auto_in_sync_2,
input auto_in_sync_3,
input auto_in_sync_4,
input auto_in_sync_5,
input auto_in_sync_6,
input auto_in_sync_7,
output auto_out_0,
output auto_out_1,
ou... | 6.70996 |
module FixedClockBroadcast (
input auto_in_clock,
input auto_in_reset,
output auto_out_2_clock,
output auto_out_2_reset,
output auto_out_1_clock,
output auto_out_1_reset,
output auto_out_0_clock,
output auto_out_0_reset
);
assign auto_out_2_clock = auto_in_clock; // @[Nodes.scala 12... | 6.914809 |
module TLWidthWidget (
output auto_in_a_ready,
input auto_in_a_valid,
input [ 2:0] auto_in_a_bits_opcode,
input [ 2:0] auto_in_a_bits_param,
input [ 3:0] auto_in_a_bits_size,
input [ 4:0] auto_in_a_bits_source,
input [27:0] auto_in_a_bits_address,
input [ 7:0] auto_i... | 6.593259 |
module TLBuffer_3 (
output auto_in_a_ready,
input auto_in_a_valid,
input [ 2:0] auto_in_a_bits_opcode,
input [ 2:0] auto_in_a_bits_size,
input [ 4:0] auto_in_a_bits_source,
input [20:0] auto_in_a_bits_address,
input [ 7:0] auto_in_a_bits_mask,
input [63:0] auto_in_a_... | 6.580493 |
module FixedClockBroadcast_2 (
input auto_in_clock,
input auto_in_reset,
output auto_out_1_clock,
output auto_out_1_reset,
output auto_out_0_clock,
output auto_out_0_reset
);
assign auto_out_1_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
assign auto_out_1_reset... | 6.914809 |
module FixedClockBroadcast_3 (
input auto_in_clock,
input auto_in_reset,
output auto_out_4_clock,
output auto_out_4_reset,
output auto_out_1_clock,
output auto_out_1_reset,
output auto_out_0_clock,
output auto_out_0_reset
);
assign auto_out_4_clock = auto_in_clock; // @[Nodes.scala ... | 6.914809 |
module TLWidthWidget_5 (
output auto_in_a_ready,
input auto_in_a_valid,
input [ 2:0] auto_in_a_bits_opcode,
input [ 2:0] auto_in_a_bits_param,
input [ 2:0] auto_in_a_bits_size,
input [ 4:0] auto_in_a_bits_source,
input [26:0] auto_in_a_bits_address,
input [ 7:0] auto... | 6.593259 |
module FixedClockBroadcast_5 (
input auto_in_clock,
input auto_in_reset,
output auto_out_clock,
output auto_out_reset
);
assign auto_out_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
assign auto_out_reset = auto_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:1... | 6.914809 |
module SourceE (
input clock,
input reset,
output io_req_ready,
input io_req_valid,
input [2:0] io_req_bits_sink,
output io_e_valid,
output [2:0] io_e_bits_sink
);
wire io_e_q_clock; // @[Decoupled.scala 296:21]
wire io_e_q_reset; // @[Decoupled.scala ... | 6.986119 |
module SourceX (
input clock,
input reset,
output io_req_ready,
input io_req_valid,
input io_x_ready,
output io_x_valid
);
wire io_x_q_clock; // @[Decoupled.scala 296:21]
wire io_x_q_reset; // @[Decoupled.scala 296:21]
wire io_x_q_io_enq_ready; // @[Decoupled.scala 296:21]
wire io... | 6.885755 |
module SinkE (
output io_resp_valid,
output [2:0] io_resp_bits_sink,
input io_e_valid,
input [2:0] io_e_bits_sink
);
assign io_resp_valid = io_e_valid; // @[SinkE.scala 44:19]
assign io_resp_bits_sink = io_e_bits_sink; // @[SinkE.scala 45:23]
endmodule
| 8.126739 |
module TLWidthWidget_9 (
output auto_in_a_ready,
input auto_in_a_valid,
input [ 2:0] auto_in_a_bits_opcode,
input [ 2:0] auto_in_a_bits_size,
input [ 3:0] auto_in_a_bits_source,
input [31:0] auto_in_a_bits_address,
input [ 7:0] auto_in_a_bits_mask,
input [63:0] auto_... | 6.593259 |
module BundleBridgeNexus_6 (
input auto_in,
output auto_out
);
assign auto_out = auto_in; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
| 6.861693 |
module BundleBridgeNexus_10 (
input auto_in_0_valid,
input [39:0] auto_in_0_iaddr,
input [31:0] auto_in_0_insn,
input [ 2:0] auto_in_0_priv,
input auto_in_0_exception,
input auto_in_0_interrupt,
input [63:0] auto_in_0_cause,
input [39:0] auto_in_0_tval,
o... | 6.861693 |
module OptimizationBarrier (
input [19:0] io_x_ppn,
input io_x_u,
input io_x_ae,
input io_x_sw,
input io_x_sx,
input io_x_sr,
input io_x_pw,
input io_x_px,
input io_x_pr,
input io_x_ppp,
input io... | 7.587549 |
module AMOALU (
input [ 7:0] io_mask,
input [ 4:0] io_cmd,
input [63:0] io_lhs,
input [63:0] io_rhs,
output [63:0] io_out
);
wire max = io_cmd == 5'hd | io_cmd == 5'hf; // @[AMOALU.scala 64:33]
wire min = io_cmd == 5'hc | io_cmd == 5'he; // @[AMOALU.scala 65:33]
wire add = io_cmd == 5'h8... | 8.467919 |
module RoundRawFNToRecFN (
input io_invalidExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [ 9:0] io_in_sExp,
input [26:0] io_in_sig,
input [ 2:0] io_roundingMode,
output [32:0] io_out,
output [ 4:0... | 6.992477 |
module CompareRecFN (
input [64:0] io_a,
input [64:0] io_b,
input io_signaling,
output io_lt,
output io_eq,
output [ 4:0] io_exceptionFlags
);
wire [11:0] rawA_exp = io_a[63:52]; // @[rawFloatFromRecFN.scala 50:21]
wire rawA_isZero = rawA_exp[11:9] == 3'h0; // @[raw... | 6.787862 |
module RecFNToRecFN (
input [64:0] io_in,
input [ 2:0] io_roundingMode,
output [32:0] io_out,
output [ 4:0] io_exceptionFlags
);
wire roundAnyRawFNToRecFN_io_invalidExc; // @[RecFNToRecFN.scala 72:19]
wire roundAnyRawFNToRecFN_io_in_isNaN; // @[RecFNToRecFN.scala 72:19]
wire roundAnyRawFNToRec... | 6.761906 |
module RoundRawFNToRecFN_1 (
input io_invalidExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [12:0] io_in_sExp,
input [55:0] io_in_sig,
input [ 2:0] io_roundingMode,
output [64:0] io_out,
output [ 4... | 6.992477 |
module RoundRawFNToRecFN_2 (
input io_invalidExc,
input io_infiniteExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [ 9:0] io_in_sExp,
input [26:0] io_in_sig,
input [ 2:0] io_roundingMode,
ou... | 6.992477 |
module RoundRawFNToRecFN_3 (
input io_invalidExc,
input io_infiniteExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [12:0] io_in_sExp,
input [55:0] io_in_sig,
input [ 2:0] io_roundingMode,
ou... | 6.992477 |
module OptimizationBarrier_117 (
input [2:0] io_x,
output [2:0] io_y
);
assign io_y = io_x; // @[package.scala 263:12]
endmodule
| 7.587549 |
module OptimizationBarrier_118 (
input [53:0] io_x_ppn,
input io_x_d,
input io_x_a,
input io_x_g,
input io_x_u,
input io_x_x,
input io_x_w,
input io_x_r,
input io_x_v,
output [53:0] io_y_ppn,
output io_y_... | 7.587549 |
module BreakpointUnit (
input io_status_debug,
input [ 1:0] io_status_prv,
input io_bp_0_control_action,
input [ 1:0] io_bp_0_control_tmatch,
input io_bp_0_control_m,
input io_bp_0_control_s,
input io_bp_0_control_u,
input io_bp_0_control... | 8.021329 |
module SynchronizerShiftReg_w1_d3 (
input clock,
input io_d,
output io_q
);
wire output_chain_clock; // @[ShiftReg.scala 45:23]
wire output_chain_io_d; // @[ShiftReg.scala 45:23]
wire output_chain_io_q; // @[ShiftReg.scala 45:23]
NonSyncResetSynchronizerPrimitiveShiftReg_d3 output_chain ( // @... | 6.820992 |
module IntSyncAsyncCrossingSink_1 (
input clock,
input auto_in_sync_0,
output auto_out_0
);
wire chain_clock; // @[ShiftReg.scala 45:23]
wire chain_io_d; // @[ShiftReg.scala 45:23]
wire chain_io_q; // @[ShiftReg.scala 45:23]
SynchronizerShiftReg_w1_d3 chain ( // @[ShiftReg.scala 45:23]
.... | 6.70996 |
module AsyncResetRegVec_w1_i0 (
input clock,
input reset,
input io_d,
output io_q
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg reg_; // @[AsyncResetReg.scala 64:50]
assign io_q = reg_; // @[AsyncResetReg.scala 68:8]
always @(posedge clock or posedge res... | 6.68936 |
module IntSyncCrossingSource_1 (
input clock,
input reset,
input auto_in_0,
output auto_out_sync_0
);
wire reg__clock; // @[AsyncResetReg.scala 89:21]
wire reg__reset; // @[AsyncResetReg.scala 89:21]
wire reg__io_d; // @[AsyncResetReg.scala 89:21]
wire reg__io_q; // @[AsyncResetReg.scala ... | 6.689384 |
module IntSyncCrossingSource_4 (
input auto_in_0,
output auto_out_sync_0
);
assign auto_out_sync_0 = auto_in_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
| 6.689384 |
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0 (
input clock,
input reset,
input io_d,
output io_q
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] _RAND_2;
`endif // RANDOMIZE_REG_INIT
reg sync_0; // @[SynchronizerReg.scala 51:87]
reg sync_1; // @[Sy... | 6.605499 |
module AsyncResetSynchronizerShiftReg_w1_d3_i0 (
input clock,
input reset,
input io_d,
output io_q
);
wire output_chain_clock; // @[ShiftReg.scala 45:23]
wire output_chain_reset; // @[ShiftReg.scala 45:23]
wire output_chain_io_d; // @[ShiftReg.scala 45:23]
wire output_chain_io_q; // @[Shi... | 6.605499 |
module AsyncResetSynchronizerShiftReg_w1_d3_i0_1 (
input clock,
input reset,
input io_d,
output io_q
);
wire output_chain_clock; // @[ShiftReg.scala 45:23]
wire output_chain_reset; // @[ShiftReg.scala 45:23]
wire output_chain_io_d; // @[ShiftReg.scala 45:23]
wire output_chain_io_q; // @[S... | 6.605499 |
module AsyncValidSync (
input io_in,
output io_out,
input clock,
input reset
);
wire io_out_source_valid_0_clock; // @[ShiftReg.scala 45:23]
wire io_out_source_valid_0_reset; // @[ShiftReg.scala 45:23]
wire io_out_source_valid_0_io_d; // @[ShiftReg.scala 45:23]
wire io_out_source_valid_0_i... | 6.70336 |
module BundleBridgeNexus_15 (
output auto_out
);
wire outputs_0 = 1'h0; // @[HasTiles.scala 162:32]
assign auto_out = outputs_0; // @[Nodes.scala 1207:84 BundleBridge.scala 151:67]
endmodule
| 6.861693 |
module AsyncResetRegVec_w2_i0 (
input clock,
input reset,
input [1:0] io_d,
output [1:0] io_q
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg [1:0] reg_; // @[AsyncResetReg.scala 64:50]
assign io_q = reg_; // @[AsyncResetReg.scala 68:8]
always ... | 6.68936 |
module IntSyncCrossingSource_5 (
input clock,
input reset,
input auto_in_0,
input auto_in_1,
output auto_out_sync_0,
output auto_out_sync_1
);
wire reg__clock; // @[AsyncResetReg.scala 89:21]
wire reg__reset; // @[AsyncResetReg.scala 89:21]
wire [1:0] reg__io_d; // @[AsyncResetReg.s... | 6.689384 |
module AsyncResetRegVec_w8_i0 (
input clock,
input reset,
input [7:0] io_d,
output [7:0] io_q
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg [7:0] reg_; // @[AsyncResetReg.scala 64:50]
assign io_q = reg_; // @[AsyncResetReg.scala 68:8]
always ... | 6.68936 |
module IntSyncCrossingSource_8 (
input clock,
input reset,
input auto_in_0,
input auto_in_1,
input auto_in_2,
input auto_in_3,
input auto_in_4,
input auto_in_5,
input auto_in_6,
input auto_in_7,
output auto_out_sync_0,
output auto_out_sync_1,
output auto_out... | 6.689384 |
module AsyncResetRegVec_w1_i0_6 (
input clock,
input reset,
input io_d,
output io_q,
input io_en
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg reg_; // @[AsyncResetReg.scala 64:50]
assign io_q = reg_; // @[AsyncResetReg.scala 68:8]
always @(posedge ... | 6.68936 |
module hi_us_ext (
input [6:0] W0_addr,
input W0_clk,
input [3:0] W0_data,
input W0_en,
input [3:0] W0_mask,
input [6:0] R0_addr,
input R0_clk,
output [3:0] R0_data,
input R0_en
);
wire [6:0] mem_0_0_W0_addr;
wire mem_0_0_W0_clk;
wire mem_0_0_W0_... | 7.054535 |
module hi_us_0_ext (
input [7:0] W0_addr,
input W0_clk,
input [3:0] W0_data,
input W0_en,
input [3:0] W0_mask,
input [7:0] R0_addr,
input R0_clk,
output [3:0] R0_data,
input R0_en
);
wire [7:0] mem_0_0_W0_addr;
wire mem_0_0_W0_clk;
wire mem_0_0_W... | 6.707874 |
module meta_ext (
input [ 4:0] W0_addr,
input W0_clk,
input [119:0] W0_data,
input W0_en,
input [ 4:0] R0_addr,
input R0_clk,
output [119:0] R0_data,
input R0_en
);
wire [4:0] mem_0_0_W0_addr;
wire mem_0_0_W0_clk;
wire [119:0] mem_0_0_W0_dat... | 6.502884 |
module IntXbar (
input auto_int_in_0,
output auto_int_out_0
);
assign auto_int_out_0 = auto_int_in_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
| 6.794458 |
module FixedClockBroadcast (
input auto_in_clock,
input auto_in_reset,
output auto_out_2_clock,
output auto_out_2_reset,
output auto_out_0_clock,
output auto_out_0_reset
);
assign auto_out_2_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
assign auto_out_2_reset =... | 6.914809 |
module TLWidthWidget (
output auto_in_a_ready,
input auto_in_a_valid,
input [ 2:0] auto_in_a_bits_opcode,
input [ 2:0] auto_in_a_bits_param,
input [ 3:0] auto_in_a_bits_size,
input [ 3:0] auto_in_a_bits_source,
input [30:0] auto_in_a_bits_address,
input [ 7:0] auto_i... | 6.593259 |
module TLWidthWidget_1 (
output auto_in_a_ready,
input auto_in_a_valid,
input [ 2:0] auto_in_a_bits_opcode,
input [ 2:0] auto_in_a_bits_param,
input [ 3:0] auto_in_a_bits_size,
input auto_in_a_bits_source,
input [31:0] auto_in_a_bits_address,
input [ 7:0] auto... | 6.593259 |
module FixedClockBroadcast_1 (
input auto_in_clock,
input auto_in_reset,
output auto_out_1_clock,
output auto_out_1_reset,
output auto_out_0_clock,
output auto_out_0_reset
);
assign auto_out_1_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
assign auto_out_1_reset... | 6.914809 |
module FixedClockBroadcast_3 (
input auto_in_clock,
input auto_in_reset,
output auto_out_5_clock,
output auto_out_5_reset,
output auto_out_4_clock,
output auto_out_4_reset,
output auto_out_3_clock,
output auto_out_3_reset,
output auto_out_1_clock,
output auto_out_1_reset,
o... | 6.914809 |
module TLWidthWidget_3 (
output auto_in_a_ready,
input auto_in_a_valid,
input [ 2:0] auto_in_a_bits_opcode,
input [ 2:0] auto_in_a_bits_param,
input [ 2:0] auto_in_a_bits_size,
input [ 4:0] auto_in_a_bits_source,
input [30:0] auto_in_a_bits_address,
input [ 7:0] auto... | 6.593259 |
module TLWidthWidget_6 (
output auto_in_a_ready,
input auto_in_a_valid,
input [ 2:0] auto_in_a_bits_opcode,
input [ 2:0] auto_in_a_bits_param,
input [ 2:0] auto_in_a_bits_size,
input [ 3:0] auto_in_a_bits_source,
input [31:0] auto_in_a_bits_address,
input [ 7:0] auto... | 6.593259 |
module TLWidthWidget_7 (
output auto_in_a_ready,
input auto_in_a_valid,
input [ 2:0] auto_in_a_bits_opcode,
input [ 2:0] auto_in_a_bits_param,
input [ 2:0] auto_in_a_bits_size,
input [ 3:0] auto_in_a_bits_source,
input [28:0] auto_in_a_bits_address,
input [ 7:0] auto... | 6.593259 |
module FixedClockBroadcast_5 (
input auto_in_clock,
input auto_in_reset,
output auto_out_clock,
output auto_out_reset
);
assign auto_out_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
assign auto_out_reset = auto_in_reset; // @[Nodes.scala 1210:84 LazyModule.scala 309:1... | 6.914809 |
module SourceE (
input clock,
input reset,
output io_req_ready,
input io_req_valid,
input [2:0] io_req_bits_sink,
output io_e_valid,
output [2:0] io_e_bits_sink
);
wire io_e_q_clock; // @[Decoupled.scala 361:21]
wire io_e_q_reset; // @[Decoupled.scala ... | 6.986119 |
module SourceX (
input clock,
input reset,
output io_req_ready,
input io_req_valid,
input io_x_ready,
output io_x_valid
);
wire io_x_q_clock; // @[Decoupled.scala 361:21]
wire io_x_q_reset; // @[Decoupled.scala 361:21]
wire io_x_q_io_enq_ready; // @[Decoupled.scala 361:21]
wire io... | 6.885755 |
module SinkE (
output io_resp_valid,
output [2:0] io_resp_bits_sink,
input io_e_valid,
input [2:0] io_e_bits_sink
);
assign io_resp_valid = io_e_valid; // @[SinkE.scala 44:19]
assign io_resp_bits_sink = io_e_bits_sink; // @[SinkE.scala 45:23]
endmodule
| 8.126739 |
module SinkX (
input clock,
input reset,
input io_req_ready,
output io_req_valid,
output [12:0] io_req_bits_tag,
output [ 9:0] io_req_bits_set,
output io_x_ready,
input io_x_valid,
input [31:0] io_x_bits_address
);
wire x_clock; // @[... | 6.564372 |
module BundleBridgeNexus_6 (
input auto_in,
output auto_out
);
assign auto_out = auto_in; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
| 6.861693 |
module Arbiter_14 (
output io_in_0_ready,
input io_in_0_valid,
input [31:0] io_in_0_bits_address,
output io_in_1_ready,
input io_in_1_valid,
input [31:0] io_in_1_bits_address,
input io_out_ready,
output io_out_valid,
output [31:0] io_out... | 7.080327 |
module AMOALU (
input [ 7:0] io_mask,
input [ 4:0] io_cmd,
input [63:0] io_lhs,
input [63:0] io_rhs,
output [63:0] io_out
);
wire max = io_cmd == 5'hd | io_cmd == 5'hf; // @[AMOALU.scala 64:33]
wire min = io_cmd == 5'hc | io_cmd == 5'he; // @[AMOALU.scala 65:33]
wire add = io_cmd == 5'h8... | 8.467919 |
module OptimizationBarrier (
input [19:0] io_x_ppn,
input io_x_u,
input io_x_ae_ptw,
input io_x_ae_final,
input io_x_gf,
input io_x_sx,
input io_x_px,
output [19:0] io_y_ppn,
output io_y_u,
output io_y_ae_ptw,
out... | 7.587549 |
module BranchDecode (
input [31:0] io_inst,
input [39:0] io_pc,
output io_out_is_ret,
output io_out_is_call,
output [39:0] io_out_target,
output [ 2:0] io_out_cfi_type,
output io_out_sfb_offset_valid,
output [ 5:0] io_out_sfb_offset_bits
);
wire [31:0] _bpd_csign... | 7.521911 |
module RoundRawFNToRecFN (
input io_invalidExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [12:0] io_in_sExp,
input [55:0] io_in_sig,
input [ 2:0] io_roundingMode,
output [64:0] io_out,
output [ 4:0... | 6.992477 |
module FMADecoder (
input [6:0] io_uopc,
output [1:0] io_cmd
);
wire [6:0] _decoder_T = io_uopc & 7'h27; // @[Decode.scala 14:65]
wire _decoder_T_1 = _decoder_T == 7'h0; // @[Decode.scala 14:121]
wire [6:0] _decoder_T_2 = io_uopc & 7'h12; // @[Decode.scala 14:65]
wire _decoder_T_3 = _decoder_T_2 == ... | 6.646488 |
module RoundRawFNToRecFN_1 (
input io_invalidExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [ 9:0] io_in_sExp,
input [26:0] io_in_sig,
input [ 2:0] io_roundingMode,
output [32:0] io_out,
output [ 4... | 6.992477 |
module CompareRecFN (
input [64:0] io_a,
input [64:0] io_b,
input io_signaling,
output io_lt,
output io_eq,
output [ 4:0] io_exceptionFlags
);
wire [11:0] rawA_exp = io_a[63:52]; // @[rawFloatFromRecFN.scala 50:21]
wire rawA_isZero = rawA_exp[11:9] == 3'h0; // @[raw... | 6.787862 |
module RecFNToRecFN (
input [64:0] io_in,
input [ 2:0] io_roundingMode,
input io_detectTininess,
output [32:0] io_out,
output [ 4:0] io_exceptionFlags
);
wire roundAnyRawFNToRecFN_io_invalidExc; // @[RecFNToRecFN.scala 72:19]
wire roundAnyRawFNToRecFN_io_in_isNaN; // @[RecFNToRecFN.s... | 6.761906 |
module UOPCodeFDivDecoder (
input [6:0] io_uopc,
output [1:0] io_sigs_typeTagIn,
output io_sigs_div,
output io_sigs_sqrt
);
wire [6:0] _decoder_T_2 = io_uopc & 7'ha; // @[Decode.scala 14:65]
wire _decoder_T_3 = _decoder_T_2 == 7'h0; // @[Decode.scala 14:121]
wire [6:0] _decoder_T_4 ... | 7.175893 |
module RoundAnyRawFNToRecFN_5 (
input io_invalidExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [ 9:0] io_in_sExp,
input [24:0] io_in_sig,
output [64:0] io_out
);
wire [11:0] _GEN_0 = {{2{io_in_sExp[9]}}, ... | 7.169444 |
module RoundRawFNToRecFN_2 (
input io_invalidExc,
input io_infiniteExc,
input io_in_isNaN,
input io_in_isInf,
input io_in_isZero,
input io_in_sign,
input [12:0] io_in_sExp,
input [55:0] io_in_sig,
input [ 2:0] io_roundingMode,
ou... | 6.992477 |
module OptimizationBarrier_14 (
input [19:0] io_x_ppn,
input io_x_u,
input io_x_ae,
input io_x_sw,
input io_x_sx,
input io_x_sr,
input io_x_pw,
input io_x_pr,
input io_x_pal,
input io_x_paa,
input ... | 7.587549 |
module OptimizationBarrier_35 (
input [2:0] io_x,
output [2:0] io_y
);
assign io_y = io_x; // @[package.scala 263:12]
endmodule
| 7.587549 |
module OptimizationBarrier_36 (
input [53:0] io_x_ppn,
input io_x_d,
input io_x_a,
input io_x_g,
input io_x_u,
input io_x_x,
input io_x_w,
input io_x_r,
input io_x_v,
output [53:0] io_y_ppn,
output io_y_d... | 7.587549 |
module HellaCacheArbiter (
output io_requestor_0_req_ready,
input io_requestor_0_req_valid,
input [39:0] io_requestor_0_req_bits_addr,
input io_requestor_0_s1_kill,
output io_requestor_0_s2_nack,
output io_requestor_0_resp_valid,
output [63:0] io_request... | 6.932065 |
module SynchronizerShiftReg_w1_d3 (
input clock,
input io_d,
output io_q
);
wire output_chain_clock; // @[ShiftReg.scala 45:23]
wire output_chain_io_d; // @[ShiftReg.scala 45:23]
wire output_chain_io_q; // @[ShiftReg.scala 45:23]
NonSyncResetSynchronizerPrimitiveShiftReg_d3 output_chain ( // @... | 6.820992 |
module IntSyncAsyncCrossingSink (
input clock,
input auto_in_sync_0,
output auto_out_0
);
wire chain_clock; // @[ShiftReg.scala 45:23]
wire chain_io_d; // @[ShiftReg.scala 45:23]
wire chain_io_q; // @[ShiftReg.scala 45:23]
SynchronizerShiftReg_w1_d3 chain ( // @[ShiftReg.scala 45:23]
.cl... | 6.70996 |
module AsyncResetRegVec_w1_i0 (
input clock,
input reset,
input io_d,
output io_q
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg reg_; // @[AsyncResetReg.scala 64:50]
assign io_q = reg_; // @[AsyncResetReg.scala 68:8]
always @(posedge clock or posedge res... | 6.68936 |
module IntSyncCrossingSource_1 (
input clock,
input reset,
input auto_in_0,
output auto_out_sync_0
);
wire reg__clock; // @[AsyncResetReg.scala 89:21]
wire reg__reset; // @[AsyncResetReg.scala 89:21]
wire reg__io_d; // @[AsyncResetReg.scala 89:21]
wire reg__io_q; // @[AsyncResetReg.scala ... | 6.689384 |
module PLICFanIn (
input io_prio_0,
input io_ip,
output io_dev,
output io_max
);
wire [1:0] effectivePriority_1 = {io_ip, io_prio_0}; // @[Cat.scala 31:58]
wire _T = 2'h2 >= effectivePriority_1; // @[Plic.scala 345:20]
wire [1:0] maxPri = _T ? 2'h2 : effectivePriority_1; // @[Misc.scala 34:9]... | 8.419901 |
module IntSyncCrossingSource_4 (
input auto_in_0,
output auto_out_sync_0
);
assign auto_out_sync_0 = auto_in_0; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
endmodule
| 6.689384 |
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0 (
input clock,
input reset,
input io_d,
output io_q
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] _RAND_2;
`endif // RANDOMIZE_REG_INIT
reg sync_0; // @[SynchronizerReg.scala 51:87]
reg sync_1; // @[Sy... | 6.605499 |
module AsyncResetSynchronizerShiftReg_w1_d3_i0 (
input clock,
input reset,
input io_d,
output io_q
);
wire output_chain_clock; // @[ShiftReg.scala 45:23]
wire output_chain_reset; // @[ShiftReg.scala 45:23]
wire output_chain_io_d; // @[ShiftReg.scala 45:23]
wire output_chain_io_q; // @[Shi... | 6.605499 |
module AsyncResetSynchronizerShiftReg_w1_d3_i0_1 (
input clock,
input reset,
input io_d,
output io_q
);
wire output_chain_clock; // @[ShiftReg.scala 45:23]
wire output_chain_reset; // @[ShiftReg.scala 45:23]
wire output_chain_io_d; // @[ShiftReg.scala 45:23]
wire output_chain_io_q; // @[S... | 6.605499 |
module AsyncValidSync (
input io_in,
output io_out,
input clock,
input reset
);
wire io_out_source_valid_0_clock; // @[ShiftReg.scala 45:23]
wire io_out_source_valid_0_reset; // @[ShiftReg.scala 45:23]
wire io_out_source_valid_0_io_d; // @[ShiftReg.scala 45:23]
wire io_out_source_valid_0_i... | 6.70336 |
module BundleBridgeNexus_16 (
output auto_out
);
wire outputs_0 = 1'h0; // @[HasTiles.scala 162:32]
assign auto_out = outputs_0; // @[Nodes.scala 1207:84 BundleBridge.scala 151:67]
endmodule
| 6.861693 |
module AsyncResetRegVec_w2_i0 (
input clock,
input reset,
input [1:0] io_d,
output [1:0] io_q
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg [1:0] reg_; // @[AsyncResetReg.scala 64:50]
assign io_q = reg_; // @[AsyncResetReg.scala 68:8]
always ... | 6.68936 |
module IntSyncCrossingSource_5 (
input clock,
input reset,
input auto_in_0,
input auto_in_1,
output auto_out_sync_0,
output auto_out_sync_1
);
wire reg__clock; // @[AsyncResetReg.scala 89:21]
wire reg__reset; // @[AsyncResetReg.scala 89:21]
wire [1:0] reg__io_d; // @[AsyncResetReg.s... | 6.689384 |
module GenericSerializer (
input clock,
input reset,
output io_in_ready,
input io_in_valid,
input [ 2:0] io_in_bits_chanId,
input [ 2:0] io_in_bits_opcode,
input [ 2:0] io_in_bits_param,
input [ 3:0] io_in_bits_size,
input [ 3:0] io_in_bits_source,... | 6.54933 |
module AsyncResetRegVec_w1_i1 (
input clock,
input reset,
input io_d,
output io_q,
input io_en
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg reg_; // @[AsyncResetReg.scala 64:50]
assign io_q = reg_; // @[AsyncResetReg.scala 68:8]
always @(posedge cl... | 6.68936 |
module AsyncResetRegVec_w1_i0_6 (
input clock,
input reset,
input io_d,
output io_q,
input io_en
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg reg_; // @[AsyncResetReg.scala 64:50]
assign io_q = reg_; // @[AsyncResetReg.scala 68:8]
always @(posedge ... | 6.68936 |
module ResetSynchronizerShiftReg_w1_d3_i0 (
input clock,
input reset,
input io_d,
output io_q
);
wire output_chain_clock; // @[ShiftReg.scala 45:23]
wire output_chain_reset; // @[ShiftReg.scala 45:23]
wire output_chain_io_d; // @[ShiftReg.scala 45:23]
wire output_chain_io_q; // @[ShiftReg... | 6.951709 |
module meta (
input [ 4:0] R0_addr,
input R0_clk,
output [119:0] R0_data_0,
input [ 4:0] W0_addr,
input W0_en,
input W0_clk,
input [119:0] W0_data_0
);
wire [4:0] meta_ext_R0_addr;
wire meta_ext_R0_en;
wire meta_ext_R0_clk;
wire [119:0] meta_ext_R0_dat... | 6.611905 |
module ghist_0 (
input [ 4:0] R0_addr,
input R0_clk,
output [63:0] R0_data_old_history,
output R0_data_current_saw_branch_not_taken,
output R0_data_new_saw_branch_not_taken,
output R0_data_new_saw_branch_taken,
output [ 4:0] R0_data_ras_idx,
input [ 4:0] W0... | 7.031635 |
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_inTestHarness (
input clock,
input reset,
input io_d,
output io_q
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] _RAND_2;
`endif // RANDOMIZE_REG_INIT
reg sync_0; // @[SynchronizerReg.scala 51:87]
reg sy... | 6.605499 |
module AsyncResetSynchronizerShiftReg_w1_d3_i0_inTestHarness (
input clock,
input reset,
output io_q
);
wire output_chain_clock; // @[ShiftReg.scala 45:23]
wire output_chain_reset; // @[ShiftReg.scala 45:23]
wire output_chain_io_d; // @[ShiftReg.scala 45:23]
wire output_chain_io_q; // @[ShiftR... | 6.605499 |
module FixedClockBroadcast_7_inTestHarness (
input auto_in_clock,
input auto_in_reset,
output auto_out_clock,
output auto_out_reset
);
assign auto_out_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
assign auto_out_reset = auto_in_reset; // @[Nodes.scala 1210:84 LazyModu... | 6.914809 |
module ResetSynchronizerShiftReg_w1_d3_i0_inTestHarness (
input clock,
input reset,
input io_d,
output io_q
);
wire output_chain_clock; // @[ShiftReg.scala 45:23]
wire output_chain_reset; // @[ShiftReg.scala 45:23]
wire output_chain_io_d; // @[ShiftReg.scala 45:23]
wire output_chain_io_q; ... | 6.951709 |
module hi_us_ext_boom (
input [6:0] W0_addr,
input W0_clk,
input [3:0] W0_data,
input W0_en,
input [3:0] W0_mask,
input [6:0] R0_addr,
input R0_clk,
output [3:0] R0_data,
input R0_en
);
wire [6:0] mem_0_0_W0_addr;
wire mem_0_0_W0_clk;
wire mem_0_... | 6.571339 |
module IntSyncAsyncCrossingSink_boom (
input clock,
input auto_in_sync_0,
input auto_in_sync_1,
input auto_in_sync_2,
input auto_in_sync_3,
input auto_in_sync_4,
input auto_in_sync_5,
input auto_in_sync_6,
input auto_in_sync_7,
output auto_out_0,
output auto_out_1,
... | 6.70996 |
module FixedClockBroadcast_boom (
input auto_in_clock,
input auto_in_reset,
output auto_out_2_clock,
output auto_out_2_reset,
output auto_out_1_clock,
output auto_out_1_reset,
output auto_out_0_clock,
output auto_out_0_reset
);
assign auto_out_2_clock = auto_in_clock; // @[Nodes.sca... | 6.914809 |
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