code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module nvcm_cell_1x8 (
bl,
wp,
wr
);
input wp, wr;
inout [7:0] bl;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
supply1 VDD_;
nvcm_cell_1 m0 (
.wp(wp),
.wr(wr),
.bl(bl[0])
);
nvcm_cell_1 m1 (
.wp(wp),
.wr(wr),
... | 7.009947 |
module nvcm_cell_8x8 (
bl,
wp,
wr
);
inout [7:0] bl;
input [7:0] wr;
input [7:0] wp;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
supply1 VDD_;
nvcm_cell_1x8 m0 (
.bl(bl[7:0]),
.wr(wr[0]),
.wp(wp[0])
);
nvcm_cell_1x8 m1 (
... | 7.497882 |
module nvcm_cell_16x8 (
bl,
wp,
wr
);
inout [15:0] bl;
input [7:0] wr;
input [7:0] wp;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
supply1 VDD_;
nvcm_cell_8x8 m0 (
.wr(wr[7:0]),
.wp(wp[7:0]),
.bl(bl[7:0])
);
nvcm_cell_8x8... | 7.518892 |
module nvcm_cell_336x8 (
bl,
bl_dummyl,
bl_dummyr,
bl_test,
wp,
wr
);
inout [1:0] bl_test;
inout [327:0] bl;
inout [1:0] bl_dummyl;
inout [5:0] bl_dummyr;
input [7:0] wp;
input [7:0] wr;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
... | 6.666213 |
module out_logic_v3 (
dout,
sdo,
sp12,
bl,
bs_en,
ceb,
clk,
ddr0,
ddr1,
mode,
pgate,
prog,
reset,
rstio,
sdi,
shift,
slfop,
tclk,
ud,
vdd_cntl,
wl
);
output dout, sdo, sp12;
input bs_en, ceb, clk, ddr0, ddr1, mode, prog, rstio, sd... | 6.678151 |
module ioe_logic_v3 (
padeb,
sdo,
sp12,
bl,
bs_en,
ceb,
clk,
din,
hiz_b,
mode,
pgate,
prog,
reset,
rstio,
sdi,
shift,
slfop,
tclk,
ud,
vdd_cntl,
wl
);
output padeb, sdo, sp12;
input bs_en, ceb, clk, din, hiz_b, mode, prog, rstio, ... | 6.772624 |
module ioe_col2_v3 (
dout,
padeb,
pado,
sdo,
sp12_h_l,
bl,
bs_en,
ceb,
hiz_b,
hold,
inclk,
mode,
outclk,
padin,
pgate,
prog,
reset,
rstio,
sdi,
shift,
tclk,
ti,
update,
vdd_cntl,
wl
);
output sdo;
input bs_en, ceb,... | 6.759959 |
module io_odrv4x5 (
cbit,
sp4_out,
bl,
pgate,
prog,
reset,
slfop,
vdd_cntl,
wl
);
input prog, slfop;
output [4:0] sp4_out;
output [7:5] cbit;
inout [3:0] bl;
input [1:0] vdd_cntl;
input [1:0] pgate;
input [1:0] reset;
input [1:0] wl;
supply1 vdd_;
supply0 gnd... | 7.043085 |
module io_col_odrv4_x40bare_v3 (
cf,
bl,
sp4_h_l,
sp4_v_b,
dout0,
dout1,
pgate,
prog,
reset,
vdd_cntl,
wl
);
input prog;
output [23:0] cf;
inout [3:0] bl;
inout [47:0] sp4_h_l;
inout [15:0] sp4_v_b;
input [0:1] dout1;
input [0:1] dout0;
input [15:0] wl;
... | 7.038065 |
module clkmux2buffer (
out,
in0,
in1,
sel
);
output out;
input in0, in1, sel;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
supply1 VDD_;
txgate Itg20 (
.in (in1),
.out(net16),
.pp (net10),
.nn (sel)
);
txgate I31 (
... | 6.698244 |
module ml_testdec_columns (
bl,
vdd_drv,
dec_det_even_25,
dec_det_odd_25
);
inout vdd_drv;
input dec_det_even_25, dec_det_odd_25;
inout [1:0] bl;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
supply1 VDD_;
nch_25 M5 (
.D(vdd_drv),
... | 6.949738 |
module nvcm_cell_2x8 (
bl,
wp,
wr
);
inout [1:0] bl;
input [7:0] wr;
input [7:0] wp;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
supply1 VDD_;
nvcm_cell_2x1 m7 (
.bl(bl[1:0]),
.wr(wr[7]),
.wp(wp[7])
);
nvcm_cell_2x1 m6 (
... | 6.933495 |
module nvcm_cell_1x8 (
bl,
wp,
wr
);
input wp, wr;
inout [7:0] bl;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
supply1 VDD_;
cell_1x1 m0 (
.wp(wp),
.wr(wr),
.bl(bl[0])
);
cell_1x1 m1 (
.wp(wp),
.wr(wr),
.bl... | 7.009947 |
module nvcm_cell_8x8 (
bl,
wp,
wr
);
inout [7:0] bl;
input [7:0] wp;
input [7:0] wr;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
supply1 VDD_;
nvcm_cell_1x8 m0 (
.bl(bl[7:0]),
.wr(wr[0]),
.wp(wp[0])
);
nvcm_cell_1x8 m1 (
... | 7.497882 |
module nvcm_cell_16x8 (
bl,
wp,
wr
);
inout [15:0] bl;
input [7:0] wp;
input [7:0] wr;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
supply1 VDD_;
nvcm_cell_8x8 m0 (
.wr(wr[7:0]),
.wp(wp[7:0]),
.bl(bl[7:0])
);
nvcm_cell_8x8... | 7.518892 |
module nvcm_cell_336x8 (
bl,
bl_dummyl,
bl_dummyr,
bl_test,
wp,
wr
);
inout [5:0] bl_dummyr;
inout [1:0] bl_dummyl;
inout [1:0] bl_test;
inout [327:0] bl;
input [7:0] wp;
input [7:0] wr;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
... | 6.666213 |
module ml_ymux_bls_x8 (
bl,
bl_out,
vblinhi_pgm_25,
vblinhi_rde,
vblinhi_rdo,
vdd_tieh,
yp3_25,
yp3_b_25
);
inout bl_out, vblinhi_pgm_25, vblinhi_rde, vblinhi_rdo, vdd_tieh;
inout [7:0] bl;
input [7:0] yp3_b_25;
input [7:0] yp3_25;
supply1 vdd_;
supply0 gnd_;
//wire vddp... | 7.048968 |
module ml_ymux_bls_x64 (
bl,
bl_out,
vblinhi_pgm_25,
vblinhi_rde,
vblinhi_rdo,
vdd_tieh,
yp2,
yp2_b_25,
yp3_25,
yp3_b_25
);
inout bl_out, vblinhi_pgm_25, vblinhi_rde, vblinhi_rdo, vdd_tieh;
inout [63:0] bl;
input [7:0] yp2;
input [7:0] yp2_b_25;
input [7:0] yp3_25;
... | 7.048968 |
module cram_2x2x2_ice8p (
q,
q_b,
bl,
pgate_l,
pgate_r,
r_gnd_l,
r_gnd_r,
reset_l,
reset_r,
wl_l,
wl_r
);
output [7:0] q_b;
output [7:0] q;
inout [3:0] bl;
input [1:0] r_gnd_r;
input [1:0] pgate_l;
input [1:0] reset_r;
input [1:0] wl_r;
input [1:0] reset_... | 6.609163 |
module sbox8to6_p2_v2 (
cbit,
cbitb,
b,
bl,
l,
r,
t,
pgate,
prog,
reset_b,
vdd_cntl,
wl
);
input prog;
output [19:0] cbit;
output [19:0] cbitb;
inout [11:0] b;
inout [11:0] l;
inout [11:0] r;
inout [11:0] t;
inout [9:0] bl;
input [1:0] vdd_cntl;
i... | 6.614683 |
module sbox5to3_p2_v2 (
cbit,
cbitb,
b,
bl,
l,
r,
t,
pgate,
prog,
reset_b,
vdd_cntl,
wl
);
input prog;
output [19:0] cbit;
output [19:0] cbitb;
inout [11:0] l;
inout [11:0] t;
inout [11:0] b;
inout [11:0] r;
inout [9:0] bl;
input [1:0] wl;
input [... | 6.508953 |
module span4_switchandmem_v3 (
c,
cc,
b,
bl,
l,
r,
t,
pgate,
prog,
reset_b,
vdd_cntl,
wl
);
input prog;
output [7:0] c;
output [15:8] cc;
inout [11:0] r;
inout [9:0] bl;
inout [11:0] t;
inout [11:0] l;
inout [11:0] b;
input [15:0] reset_b;
input [... | 7.107335 |
module cram2x2x6 (
q,
q_b,
bl,
pgate,
r_gnd,
reset_b,
wl
);
output [23:0] q;
output [23:0] q_b;
inout [11:0] bl;
input [1:0] r_gnd;
input [1:0] reset_b;
input [1:0] pgate;
input [1:0] wl;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply... | 6.651239 |
module odrv12_30 (
sp4_h_r,
sp4_r_v_b,
sp4_v_b,
sp12_h_r,
sp12_v_b,
cbitb,
prog,
slfop
);
output sp12_h_r;
input prog, slfop;
output [2:0] sp4_h_r;
output [2:0] sp4_v_b;
output [1:0] sp12_v_b;
output [2:0] sp4_r_v_b;
input [11:0] cbitb;
supply1 vdd_;
supply0 gnd_;
... | 6.657756 |
module ml_mux2_hvt_schematic (
out,
in0,
in1,
sel
);
output out;
input in0, in1, sel;
supply1 vdd_;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply0 GND_;
supply1 VDD_;
txgate I31 (
.in (in1),
.out(out),
.pp (net25),
.nn (sel)
);
txgate I32... | 7.095052 |
module nvcm_cell_2x8 (
bl,
wp,
wr
);
inout [1:0] bl;
input [7:0] wr;
input [7:0] wp;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply1 vdd_;
supply0 GND_;
supply1 VDD_;
nvcm_cell_2x1 m7 (
.bl(bl[1:0]),
.wr(wr[7]),
.wp(wp[7])
);
nvcm_cell_2x1 m6 (
... | 6.933495 |
module nvcm_cell_1x8 (
bl,
wp,
wr
);
input wp, wr;
inout [7:0] bl;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply1 vdd_;
supply0 GND_;
supply1 VDD_;
nvcm_cell_1 m0 (
.wp(wp),
.wr(wr),
.bl(bl[0])
);
nvcm_cell_1 m1 (
.wp(wp),
.wr(wr),
... | 7.009947 |
module nvcm_cell_8x8 (
bl,
wp,
wr
);
inout [7:0] bl;
input [7:0] wr;
input [7:0] wp;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply1 vdd_;
supply0 GND_;
supply1 VDD_;
nvcm_cell_1x8 m0 (
.bl(bl[7:0]),
.wr(wr[0]),
.wp(wp[0])
);
nvcm_cell_1x8 m1 (
... | 7.497882 |
module nvcm_cell_16x8 (
bl,
wp,
wr
);
inout [15:0] bl;
input [7:0] wr;
input [7:0] wp;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply1 vdd_;
supply0 GND_;
supply1 VDD_;
nvcm_cell_8x8 m0 (
.wr(wr[7:0]),
.wp(wp[7:0]),
.bl(bl[7:0])
);
nvcm_cell_8x8... | 7.518892 |
module nvcm_cell_336x8 (
bl,
bl_dummyl,
bl_dummyr,
bl_test,
wp,
wr
);
inout [1:0] bl_test;
inout [327:0] bl;
inout [1:0] bl_dummyl;
inout [5:0] bl_dummyr;
input [7:0] wp;
input [7:0] wr;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply1 vdd_;
supply0 GND_;
... | 6.666213 |
module ml_testdec_columns (
bl,
dec_det_even_25,
dec_det_odd_25
);
input dec_det_even_25, dec_det_odd_25;
inout [1:0] bl;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply1 vdd_;
supply0 GND_;
supply1 VDD_;
nch_25 M5 (
.D(vdd_),
.B(gnd_),
.G(dec_det_even_... | 6.949738 |
module ml_ymux_bls_x8 (
bl,
bl_out,
vblinhi_pgm_25,
vblinhi_rde,
vblinhi_rdo,
vdd_tieh,
yp3_25,
yp3_b_25
);
inout bl_out, vblinhi_pgm_25, vblinhi_rde, vblinhi_rdo, vdd_tieh;
inout [7:0] bl;
input [7:0] yp3_b_25;
input [7:0] yp3_25;
supply0 gnd_;
//wire vddp_ = test.cds_glo... | 7.048968 |
module ml_ymux_bls_x64 (
bl,
bl_out,
vblinhi_pgm_25,
vblinhi_rde,
vblinhi_rdo,
vdd_tieh,
yp2,
yp2_b_25,
yp3_25,
yp3_b_25
);
inout bl_out, vblinhi_pgm_25, vblinhi_rde, vblinhi_rdo, vdd_tieh;
inout [63:0] bl;
input [7:0] yp2;
input [7:0] yp2_b_25;
input [7:0] yp3_25;
... | 7.048968 |
module io_odrv4x5 (
cbit,
sp4_out,
bl,
pgate,
prog,
reset,
slfop,
vdd_cntl,
wl
);
input prog, slfop;
output [4:0] sp4_out;
output [7:5] cbit;
inout [3:0] bl;
input [1:0] vdd_cntl;
input [1:0] reset;
input [1:0] pgate;
input [1:0] wl;
supply0 gnd_;
supply1 vdd... | 7.043085 |
module io_col_odrv4_x40bare (
cf,
bl,
sp4_h_l,
sp4_v_b,
dout0,
dout1,
pgate,
prog,
reset,
vdd_cntl,
wl
);
input prog;
output [23:0] cf;
inout [3:0] bl;
inout [15:0] sp4_v_b;
inout [47:0] sp4_h_l;
input [0:1] dout0;
input [0:1] dout1;
input [15:0] pgate;
... | 7.038065 |
module out_logic_v3 (
dout,
sdo,
sp12,
bl,
bs_en,
ceb,
clk,
ddr0,
ddr1,
mode,
pgate,
prog,
reset,
rstio,
sdi,
shift,
slfop,
tclk,
ud,
vdd_cntl,
wl
);
output dout, sdo, sp12;
input bs_en, ceb, clk, ddr0, ddr1, mode, prog, rstio, sd... | 6.678151 |
module ioe_logic_v3 (
padeb,
sdo,
sp12,
bl,
bs_en,
ceb,
clk,
din,
hiz_b,
mode,
pgate,
prog,
reset,
rstio,
sdi,
shift,
slfop,
tclk,
ud,
vdd_cntl,
wl
);
output padeb, sdo, sp12;
input bs_en, ceb, clk, din, hiz_b, mode, prog, rstio, ... | 6.772624 |
module ml_mux2_hvt_schematic (
out,
in0,
in1,
sel
);
output out;
input in0, in1, sel;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply1 vdd_;
supply0 GND_;
supply1 VDD_;
txgate_hvt I31 (
.in (in1),
.out(out),
.pp (net25),
.nn (sel)
);
txgate... | 7.095052 |
module cram2x2x6 (
q,
q_b,
bl,
pgate,
r_gnd,
reset_b,
wl
);
output [23:0] q;
output [23:0] q_b;
inout [11:0] bl;
input [1:0] reset_b;
input [1:0] wl;
input [1:0] pgate;
input [1:0] r_gnd;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply1 vdd_;
supply... | 6.651239 |
module span4_switchandmem (
b,
bl,
l,
r,
t,
pgate,
prog,
reset_b,
vdd_cntl,
wl
);
input prog;
inout [9:0] bl;
inout [11:0] b;
inout [11:0] l;
inout [11:0] t;
inout [11:0] r;
input [15:0] wl;
input [15:0] reset_b;
input [15:0] vdd_cntl;
input [15:0] pgate;
... | 7.107335 |
module odrv12_30 (
sp4_h_r,
sp4_r_v_b,
sp4_v_b,
sp12_h_r,
sp12_v_b,
cbitb,
prog,
slfop
);
output sp12_h_r;
input prog, slfop;
output [2:0] sp4_h_r;
output [2:0] sp4_v_b;
output [1:0] sp12_v_b;
output [2:0] sp4_r_v_b;
input [11:0] cbitb;
supply0 gnd_;
//wire vddp_ = t... | 6.657756 |
module nvcm_cell_2x8 (
bl,
wp,
wr
);
inout [1:0] bl;
input [7:0] wr;
input [7:0] wp;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply1 vdd_;
supply0 GND_;
supply1 VDD_;
nvcm_cell_2x1 m7 (
.bl(bl[1:0]),
.wr(wr[7]),
.wp(wp[7])
);
nvcm_cell_2x1 m6 (
... | 6.933495 |
module nvcm_cell_1x8 (
bl,
wp,
wr
);
input wp, wr;
inout [7:0] bl;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply1 vdd_;
supply0 GND_;
supply1 VDD_;
nvcm_cell_1 m0 (
.wp(wp),
.wr(wr),
.bl(bl[0])
);
nvcm_cell_1 m1 (
.wp(wp),
.wr(wr),
... | 7.009947 |
module nvcm_cell_8x8 (
bl,
wp,
wr
);
inout [7:0] bl;
input [7:0] wr;
input [7:0] wp;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply1 vdd_;
supply0 GND_;
supply1 VDD_;
nvcm_cell_1x8 m0 (
.bl(bl[7:0]),
.wr(wr[0]),
.wp(wp[0])
);
nvcm_cell_1x8 m1 (
... | 7.497882 |
module nvcm_cell_16x8 (
bl,
wp,
wr
);
inout [15:0] bl;
input [7:0] wr;
input [7:0] wp;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply1 vdd_;
supply0 GND_;
supply1 VDD_;
nvcm_cell_8x8 m0 (
.wr(wr[7:0]),
.wp(wp[7:0]),
.bl(bl[7:0])
);
nvcm_cell_8x8... | 7.518892 |
module nvcm_cell_336x8 (
bl,
bl_dummyl,
bl_dummyr,
bl_test,
wp,
wr
);
inout [1:0] bl_test;
inout [327:0] bl;
inout [1:0] bl_dummyl;
inout [5:0] bl_dummyr;
input [7:0] wp;
input [7:0] wr;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply1 vdd_;
supply0 GND_;
... | 6.666213 |
module ml_testdec_columns (
bl,
dec_det_even_25,
dec_det_odd_25
);
input dec_det_even_25, dec_det_odd_25;
inout [1:0] bl;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply1 vdd_;
supply0 GND_;
supply1 VDD_;
nch_25 M5 (
.D(vdd_),
.B(gnd_),
.G(dec_det_even_... | 6.949738 |
module ml_ymux_bls_x8 (
bl,
bl_out,
vblinhi_pgm_25,
vblinhi_rde,
vblinhi_rdo,
vdd_tieh,
yp3_25,
yp3_b_25
);
inout bl_out, vblinhi_pgm_25, vblinhi_rde, vblinhi_rdo, vdd_tieh;
inout [7:0] bl;
input [7:0] yp3_b_25;
input [7:0] yp3_25;
supply0 gnd_;
//wire vddp_ = test.cds_glo... | 7.048968 |
module ml_ymux_bls_x64 (
bl,
bl_out,
vblinhi_pgm_25,
vblinhi_rde,
vblinhi_rdo,
vdd_tieh,
yp2,
yp2_b_25,
yp3_25,
yp3_b_25
);
inout bl_out, vblinhi_pgm_25, vblinhi_rde, vblinhi_rdo, vdd_tieh;
inout [63:0] bl;
input [7:0] yp2;
input [7:0] yp2_b_25;
input [7:0] yp3_25;
... | 7.048968 |
module io_odrv4x5 (
cbit,
sp4_out,
bl,
pgate,
prog,
reset,
slfop,
vdd_cntl,
wl
);
input prog, slfop;
output [4:0] sp4_out;
output [7:5] cbit;
inout [3:0] bl;
input [1:0] vdd_cntl;
input [1:0] reset;
input [1:0] pgate;
input [1:0] wl;
supply0 gnd_;
supply1 vdd... | 7.043085 |
module io_col_odrv4_x40bare (
cf,
bl,
sp4_h_l,
sp4_v_b,
dout0,
dout1,
pgate,
prog,
reset,
vdd_cntl,
wl
);
input prog;
output [23:0] cf;
inout [3:0] bl;
inout [15:0] sp4_v_b;
inout [47:0] sp4_h_l;
input [0:1] dout0;
input [0:1] dout1;
input [15:0] pgate;
... | 7.038065 |
module out_logic_v3 (
dout,
sdo,
sp12,
bl,
bs_en,
ceb,
clk,
ddr0,
ddr1,
mode,
pgate,
prog,
reset,
rstio,
sdi,
shift,
slfop,
tclk,
ud,
vdd_cntl,
wl
);
output dout, sdo, sp12;
input bs_en, ceb, clk, ddr0, ddr1, mode, prog, rstio, sd... | 6.678151 |
module ioe_logic_v3 (
padeb,
sdo,
sp12,
bl,
bs_en,
ceb,
clk,
din,
hiz_b,
mode,
pgate,
prog,
reset,
rstio,
sdi,
shift,
slfop,
tclk,
ud,
vdd_cntl,
wl
);
output padeb, sdo, sp12;
input bs_en, ceb, clk, din, hiz_b, mode, prog, rstio, ... | 6.772624 |
module ml_mux2_hvt_schematic (
out,
in0,
in1,
sel
);
output out;
input in0, in1, sel;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply1 vdd_;
supply0 GND_;
supply1 VDD_;
txgate_hvt I31 (
.in (in1),
.out(out),
.pp (net25),
.nn (sel)
);
txgate... | 7.095052 |
module cram2x2x6 (
q,
q_b,
bl,
pgate,
r_gnd,
reset_b,
wl
);
output [23:0] q;
output [23:0] q_b;
inout [11:0] bl;
input [1:0] reset_b;
input [1:0] wl;
input [1:0] pgate;
input [1:0] r_gnd;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply1 vdd_;
supply... | 6.651239 |
module span4_switchandmem (
b,
bl,
l,
r,
t,
pgate,
prog,
reset_b,
vdd_cntl,
wl
);
input prog;
inout [9:0] bl;
inout [11:0] b;
inout [11:0] l;
inout [11:0] t;
inout [11:0] r;
input [15:0] wl;
input [15:0] reset_b;
input [15:0] vdd_cntl;
input [15:0] pgate;
... | 7.107335 |
module odrv12_30 (
sp4_h_r,
sp4_r_v_b,
sp4_v_b,
sp12_h_r,
sp12_v_b,
cbitb,
prog,
slfop
);
output sp12_h_r;
input prog, slfop;
output [2:0] sp4_h_r;
output [2:0] sp4_v_b;
output [1:0] sp12_v_b;
output [2:0] sp4_r_v_b;
input [11:0] cbitb;
supply0 gnd_;
//wire vddp_ = t... | 6.657756 |
module ml_ymux_bls_x16 (
bl,
bl_out,
vblinhi_pgm_25,
vblinhi_rde,
vblinhi_rdo,
vdd_tieh,
yp2,
yp2_b_25,
yp3_25,
yp3_b_25
);
inout bl_out, vblinhi_pgm_25, vblinhi_rde, vblinhi_rdo, vdd_tieh;
inout [15:0] bl;
input [7:0] yp3_25;
input [7:0] yp3_b_25;
input [1:0] yp2;
... | 7.048968 |
module odrv12_30 (
sp4_h_r,
sp4_r_v_b,
sp4_v_b,
sp12_h_r,
sp12_v_b,
cbitb,
prog,
slfop
);
output sp12_h_r;
input prog, slfop;
output [2:0] sp4_h_r;
output [2:0] sp4_v_b;
output [1:0] sp12_v_b;
output [2:0] sp4_r_v_b;
input [11:0] cbitb;
supply0 gnd_;
//wire vddp_ = t... | 6.657756 |
module span4_switchandmem (
b,
bl,
l,
r,
t,
pgate,
prog,
reset_b,
vdd_cntl,
wl
);
input prog;
inout [9:0] bl;
inout [11:0] b;
inout [11:0] l;
inout [11:0] t;
inout [11:0] r;
input [15:0] wl;
input [15:0] reset_b;
input [15:0] vdd_cntl;
input [15:0] pgate;
... | 7.107335 |
module cram2x2x6 (
q,
q_b,
bl,
pgate,
r_gnd,
reset_b,
wl
);
output [23:0] q;
output [23:0] q_b;
inout [11:0] bl;
input [1:0] reset_b;
input [1:0] wl;
input [1:0] pgate;
input [1:0] r_gnd;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply1 vdd_;
supply... | 6.651239 |
module ml_mux2_hvt_schematic (
out,
in0,
in1,
sel
);
output out;
input in0, in1, sel;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply1 vdd_;
supply0 GND_;
supply1 VDD_;
txgate_hvt I31 (
.in (in1),
.out(out),
.pp (net25),
.nn (sel)
);
txgate... | 7.095052 |
module io_odrv4x5 (
cbit,
sp4_out,
bl,
pgate,
prog,
reset,
slfop,
vdd_cntl,
wl
);
input prog, slfop;
output [4:0] sp4_out;
output [7:5] cbit;
inout [3:0] bl;
input [1:0] vdd_cntl;
input [1:0] reset;
input [1:0] pgate;
input [1:0] wl;
supply1 vdd_;
supply0 gnd... | 7.043085 |
module io_col_odrv4_x40bare (
cf,
bl,
sp4_h_l,
sp4_v_b,
dout0,
dout1,
pgate,
prog,
reset,
vdd_cntl,
wl
);
input prog;
output [23:0] cf;
inout [3:0] bl;
inout [15:0] sp4_v_b;
inout [47:0] sp4_h_l;
input [0:1] dout0;
input [0:1] dout1;
input [15:0] pgate;
... | 7.038065 |
module out_logic_v3 (
dout,
sdo,
sp12,
bl,
bs_en,
ceb,
clk,
ddr0,
ddr1,
mode,
pgate,
prog,
reset,
rstio,
sdi,
shift,
slfop,
tclk,
ud,
vdd_cntl,
wl
);
output dout, sdo, sp12;
input bs_en, ceb, clk, ddr0, ddr1, mode, prog, rstio, sd... | 6.678151 |
module ioe_logic_v3 (
padeb,
sdo,
sp12,
bl,
bs_en,
ceb,
clk,
din,
hiz_b,
mode,
pgate,
prog,
reset,
rstio,
sdi,
shift,
slfop,
tclk,
ud,
vdd_cntl,
wl
);
output padeb, sdo, sp12;
input bs_en, ceb, clk, din, hiz_b, mode, prog, rstio, ... | 6.772624 |
module ml_testdec_columns (
bl,
dec_det_even_25,
dec_det_odd_25
);
input dec_det_even_25, dec_det_odd_25;
inout [1:0] bl;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply1 vdd_;
supply0 GND_;
supply1 VDD_;
nch_25 M5 (
.D(vdd_),
.B(gnd_),
.G(dec_det_even_... | 6.949738 |
module nvcm_cell_2x8 (
bl,
wp,
wr
);
inout [1:0] bl;
input [7:0] wr;
input [7:0] wp;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply1 vdd_;
supply0 GND_;
supply1 VDD_;
nvcm_cell_2x1 m7 (
.bl(bl[1:0]),
.wr(wr[7]),
.wp(wp[7])
);
nvcm_cell_2x1 m6 (
... | 6.933495 |
module nvcm_cell_1x8 (
bl,
wp,
wr
);
input wp, wr;
inout [7:0] bl;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply1 vdd_;
supply0 GND_;
supply1 VDD_;
nvcm_cell_1 m0 (
.wp(wp),
.wr(wr),
.bl(bl[0])
);
nvcm_cell_1 m1 (
.wp(wp),
.wr(wr),
... | 7.009947 |
module nvcm_cell_8x8 (
bl,
wp,
wr
);
inout [7:0] bl;
input [7:0] wr;
input [7:0] wp;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply1 vdd_;
supply0 GND_;
supply1 VDD_;
nvcm_cell_1x8 m0 (
.bl(bl[7:0]),
.wr(wr[0]),
.wp(wp[0])
);
nvcm_cell_1x8 m1 (
... | 7.497882 |
module nvcm_cell_16x8 (
bl,
wp,
wr
);
inout [15:0] bl;
input [7:0] wr;
input [7:0] wp;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply1 vdd_;
supply0 GND_;
supply1 VDD_;
nvcm_cell_8x8 m0 (
.wr(wr[7:0]),
.wp(wp[7:0]),
.bl(bl[7:0])
);
nvcm_cell_8x8... | 7.518892 |
module ml_ymux_bls_x64 (
bl,
bl_out,
vblinhi_pgm_25,
vblinhi_rde,
vblinhi_rdo,
vdd_tieh,
yp2,
yp2_b_25,
yp3_25,
yp3_b_25
);
inout bl_out, vblinhi_pgm_25, vblinhi_rde, vblinhi_rdo, vdd_tieh;
inout [63:0] bl;
input [7:0] yp2;
input [7:0] yp2_b_25;
input [7:0] yp3_25;
... | 7.048968 |
module ml_ymux_bls_x320 (
bl,
bl_dummyl,
bl_dummyr,
bl_out,
vblinhi_pgm_25,
vblinhi_rde,
vblinhi_rdo,
vdd_tieh,
pgminhi_dmmy_b_25,
yp1,
yp1_b_25,
yp2,
yp2_b_25,
yp3_25,
yp3_b_25
);
inout bl_out, vblinhi_pgm_25, vblinhi_rde, vblinhi_rdo, vdd_tieh;
input pg... | 7.048968 |
module nvcm_cell_336x8_8f (
bl,
bl_dummyl,
bl_dummyr,
wp,
wr
);
inout [1:0] bl_dummyr;
inout [337:0] bl;
inout [1:0] bl_dummyl;
input [7:0] wp;
input [7:0] wr;
supply0 gnd_;
//wire vddp_ = test.cds_globalsInst.vddp_;
supply1 vdd_;
supply0 GND_;
supply1 VDD_;
nvcm_cell_2x8... | 6.666213 |
module nvcm_cell_2x8 (
bl,
wp,
wr
);
inout [1:0] bl;
input [7:0] wr;
input [7:0] wp;
supply1 vdd_;
supply0 gnd_;
/* wire vddp_ = test.cds_globalsInst.vddp_; */supply1 vddp_;
supply0 GND_;
supply1 VDD_;
nvcm_cell_2x1 m7 (
.bl(bl[1:0]),
.wr(wr[7]),
.wp(wp[7])
);
n... | 6.933495 |
module nvcm_cell_1x8 (
bl,
wp,
wr
);
input wp, wr;
inout [7:0] bl;
supply1 vdd_;
supply0 gnd_;
/* wire vddp_ = test.cds_globalsInst.vddp_; */supply1 vddp_;
supply0 GND_;
supply1 VDD_;
cell_1x1 m0 (
.wp(wp),
.wr(wr),
.bl(bl[0])
);
cell_1x1 m1 (
.wp(wp),
... | 7.009947 |
module nvcm_cell_8x8 (
bl,
wp,
wr
);
inout [7:0] bl;
input [7:0] wp;
input [7:0] wr;
supply1 vdd_;
supply0 gnd_;
/* wire vddp_ = test.cds_globalsInst.vddp_; */supply1 vddp_;
supply0 GND_;
supply1 VDD_;
nvcm_cell_1x8 m0 (
.bl(bl[7:0]),
.wr(wr[0]),
.wp(wp[0])
);
n... | 7.497882 |
module nvcm_cell_16x8 (
bl,
wp,
wr
);
inout [15:0] bl;
input [7:0] wp;
input [7:0] wr;
supply1 vdd_;
supply0 gnd_;
/* wire vddp_ = test.cds_globalsInst.vddp_; */supply1 vddp_;
supply0 GND_;
supply1 VDD_;
nvcm_cell_8x8 m0 (
.wr(wr[7:0]),
.wp(wp[7:0]),
.bl(bl[7:0])
... | 7.518892 |
module nvcm_cell_336x8_8f (
bl,
bl_dummyl,
bl_dummyr,
bl_test,
wp,
wr
);
inout [1:0] bl_dummyl;
inout [335:0] bl;
inout [1:0] bl_test;
inout [1:0] bl_dummyr;
input [7:0] wp;
input [7:0] wr;
supply1 vdd_;
supply0 gnd_;
/* wire vddp_ = test.cds_globalsInst.vddp_; */supply1 vdd... | 6.666213 |
module ml_testdec_columns (
bl,
vdd_drv,
dec_det_even_25,
dec_det_odd_25
);
inout vdd_drv;
input dec_det_even_25, dec_det_odd_25;
inout [1:0] bl;
supply1 vdd_;
supply0 gnd_;
/* wire vddp_ = test.cds_globalsInst.vddp_; */supply1 vddp_;
supply0 GND_;
supply1 VDD_;
nch_25 M5 (
... | 6.949738 |
module ml_ymux_bls_x16 (
bl,
bl_out,
vblinhi_pgm_25,
vblinhi_rde,
vblinhi_rdo,
vdd_tieh,
yp2,
yp2_b_25,
yp3_25,
yp3_b_25
);
inout bl_out, vblinhi_pgm_25, vblinhi_rde, vblinhi_rdo, vdd_tieh;
inout [15:0] bl;
input [7:0] yp3_b_25;
input [7:0] yp3_25;
input [1:0] yp2_b_... | 7.048968 |
module ml_ymux_bls_x64 (
bl,
bl_out,
vblinhi_pgm_25,
vblinhi_rde,
vblinhi_rdo,
vdd_tieh,
yp2,
yp2_b_25,
yp3_25,
yp3_b_25
);
inout bl_out, vblinhi_pgm_25, vblinhi_rde, vblinhi_rdo, vdd_tieh;
inout [63:0] bl;
input [7:0] yp2;
input [7:0] yp2_b_25;
input [7:0] yp3_25;
... | 7.048968 |
module ml_ymux_bls_x320 (
bl,
bl_dummyl,
bl_dummyr,
bl_out,
vblinhi_pgm_25,
vblinhi_rde,
vblinhi_rdo,
vdd_tieh,
pgminhi_dmmy_b_25,
yp1,
yp1_b_25,
yp2,
yp2_b_25,
yp3_25,
yp3_b_25
);
inout bl_out, vblinhi_pgm_25, vblinhi_rde, vblinhi_rdo, vdd_tieh;
input pg... | 7.048968 |
module clkmux2buffer (
out,
in0,
in1,
sel
);
output out;
input in0, in1, sel;
supply1 vdd_;
supply0 gnd_;
/* wire vddp_ = test.cds_globalsInst.vddp_; */supply1 vddp_;
supply0 GND_;
supply1 VDD_;
txgate Itg20 (
.in (in1),
.out(net16),
.pp (net10),
.nn (sel)
)... | 6.698244 |
module cram_2x2x2_ice8p (
q,
q_b,
bl,
pgate_l,
pgate_r,
r_gnd_l,
r_gnd_r,
reset_l,
reset_r,
wl_l,
wl_r
);
output [7:0] q_b;
output [7:0] q;
inout [3:0] bl;
input [1:0] r_gnd_r;
input [1:0] pgate_l;
input [1:0] reset_r;
input [1:0] wl_r;
input [1:0] reset_... | 6.609163 |
module sbox8to6_p2_v2 (
cbit,
cbitb,
b,
bl,
l,
r,
t,
pgate,
prog,
reset_b,
vdd_cntl,
wl
);
input prog;
output [19:0] cbit;
output [19:0] cbitb;
inout [11:0] b;
inout [11:0] l;
inout [11:0] r;
inout [11:0] t;
inout [9:0] bl;
input [1:0] vdd_cntl;
i... | 6.614683 |
module sbox5to3_p2_v2 (
cbit,
cbitb,
b,
bl,
l,
r,
t,
pgate,
prog,
reset_b,
vdd_cntl,
wl
);
input prog;
output [19:0] cbit;
output [19:0] cbitb;
inout [11:0] l;
inout [11:0] t;
inout [11:0] b;
inout [11:0] r;
inout [9:0] bl;
input [1:0] wl;
input [... | 6.508953 |
module cram2x2x6 (
q,
q_b,
bl,
pgate,
r_gnd,
reset_b,
wl
);
output [23:0] q;
output [23:0] q_b;
inout [11:0] bl;
input [1:0] r_gnd;
input [1:0] reset_b;
input [1:0] pgate;
input [1:0] wl;
supply1 vdd_;
supply0 gnd_;
/* wire vddp_ = test.cds_globalsInst.vddp_; */suppl... | 6.651239 |
module odrv12_30 (
sp4_h_r,
sp4_r_v_b,
sp4_v_b,
sp12_h_r,
sp12_v_b,
cbitb,
prog,
slfop
);
output sp12_h_r;
input prog, slfop;
output [2:0] sp4_h_r;
output [2:0] sp4_v_b;
output [1:0] sp12_v_b;
output [2:0] sp4_r_v_b;
input [11:0] cbitb;
supply1 vdd_;
supply0 gnd_;
... | 6.657756 |
module ml_mux2_hvt_schematic (
out,
in0,
in1,
sel
);
output out;
input in0, in1, sel;
supply1 vdd_;
supply0 gnd_;
/* wire vddp_ = test.cds_globalsInst.vddp_; */supply1 vddp_;
supply0 GND_;
supply1 VDD_;
txgate I31 (
.in (in1),
.out(out),
.pp (net25),
.nn (sel)... | 7.095052 |
module io_odrv4x5 (
cbit,
sp4_out,
bl,
pgate,
prog,
reset,
slfop,
vdd_cntl,
wl
);
input prog, slfop;
output [4:0] sp4_out;
output [7:5] cbit;
inout [3:0] bl;
input [1:0] vdd_cntl;
input [1:0] pgate;
input [1:0] reset;
input [1:0] wl;
supply1 vdd_;
supply0 gnd... | 7.043085 |
module io_col_odrv4_x40bare_v3 (
cf,
bl,
sp4_h_l,
sp4_v_b,
dout0,
dout1,
pgate,
prog,
reset,
vdd_cntl,
wl
);
input prog;
output [23:0] cf;
inout [3:0] bl;
inout [47:0] sp4_h_l;
inout [15:0] sp4_v_b;
input [0:1] dout1;
input [0:1] dout0;
input [15:0] wl;
... | 7.038065 |
module out_logic_v3 (
dout,
sdo,
sp12,
bl,
bs_en,
ceb,
clk,
ddr0,
ddr1,
mode,
pgate,
prog,
reset,
rstio,
sdi,
shift,
slfop,
tclk,
ud,
vdd_cntl,
wl
);
output dout, sdo, sp12;
input bs_en, ceb, clk, ddr0, ddr1, mode, prog, rstio, sd... | 6.678151 |
module ioe_logic_v3 (
padeb,
sdo,
sp12,
bl,
bs_en,
ceb,
clk,
din,
hiz_b,
mode,
pgate,
prog,
reset,
rstio,
sdi,
shift,
slfop,
tclk,
ud,
vdd_cntl,
wl
);
output padeb, sdo, sp12;
input bs_en, ceb, clk, din, hiz_b, mode, prog, rstio, ... | 6.772624 |
module ioe_col2_v3 (
dout,
padeb,
pado,
sdo,
sp12_h_l,
bl,
bs_en,
ceb,
hiz_b,
hold,
inclk,
mode,
outclk,
padin,
pgate,
prog,
reset,
rstio,
sdi,
shift,
tclk,
ti,
update,
vdd_cntl,
wl
);
output sdo;
input bs_en, ceb,... | 6.759959 |
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_inTestHarness (
input clock,
input reset,
input io_d,
output io_q
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] _RAND_2;
`endif // RANDOMIZE_REG_INIT
reg sync_0; // @[SynchronizerReg.scala 51:87]
reg sy... | 6.605499 |
module AsyncResetSynchronizerShiftReg_w1_d3_i0_inTestHarness (
input clock,
input reset,
output io_q
);
wire output_chain_clock; // @[ShiftReg.scala 45:23]
wire output_chain_reset; // @[ShiftReg.scala 45:23]
wire output_chain_io_d; // @[ShiftReg.scala 45:23]
wire output_chain_io_q; // @[ShiftR... | 6.605499 |
module FixedClockBroadcast_7_inTestHarness (
input auto_in_clock,
input auto_in_reset,
output auto_out_clock,
output auto_out_reset
);
assign auto_out_clock = auto_in_clock; // @[Nodes.scala 1210:84 LazyModule.scala 309:16]
assign auto_out_reset = auto_in_reset; // @[Nodes.scala 1210:84 LazyModu... | 6.914809 |
module ResetSynchronizerShiftReg_w1_d3_i0_inTestHarness (
input clock,
input reset,
input io_d,
output io_q
);
wire output_chain_clock; // @[ShiftReg.scala 45:23]
wire output_chain_reset; // @[ShiftReg.scala 45:23]
wire output_chain_io_d; // @[ShiftReg.scala 45:23]
wire output_chain_io_q; ... | 6.951709 |
module IntXbar (
input auto_int_in_1_0,
input auto_int_in_0_0,
input auto_int_in_0_1,
input auto_int_in_0_2,
input auto_int_in_0_3,
input auto_int_in_0_4,
input auto_int_in_0_5,
input auto_int_in_0_6,
input auto_int_in_0_7,
output auto_int_out_0,
output auto_int_out_... | 6.794458 |
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