code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module ConfigRegA(CLK, RST, Q_OUT, D_IN, EN);
parameter width = 1;
parameter init = { width {1'b0}} ;
input CLK;
input RST;
input EN;
input [width - 1 : 0] D_IN;
output [width - 1 : 0] Q_OUT;
reg [width - 1 : 0] Q_OUT;
always@(posedge CLK or `BSV_RESET_EDGE RST) begin
... | 6.633049 |
module ConfigurationUnit (
clock,
request,
confirm,
key,
data,
inputData,
dataP,
dataQ
);
input clock;
input request;
input confirm;
input [7:0] inputData;
input [7:0] key;
input [7:0] data;
output [6:0] dataP;
output [6:0] dataQ;
wire writeRegP;
wire writeRegQ;
... | 8.386409 |
module ConfigurationUnitTest;
// Inputs
reg clock;
reg request;
reg confirm;
reg [7:0] key;
reg [7:0] inputData;
// Outputs
wire [6:0] dataP;
wire [6:0] dataQ;
// Instantiate the Unit Under Test (UUT)jjj
ConfigurationUnit uut (
.clock(clock),
.request(request),
.confirm(confir... | 8.386409 |
module configuration_manager (
input clk_in,
output prog_reset,
output prog_clk,
output ccff_head,
output configuration_done
);
parameter START_CYCLE = 3; // Start configuration on cycle 3 of prog_clk
parameter CONFIGURATION_CLK_DIV_SIZE = 12; // Divide clk_in (50MHz) by 4096 (2^12) times
... | 7.163412 |
module configuration_register (
input RST,
input CLK,
input WREN,
input [2:0] ABUS,
input [15:0] DBUS,
output [15:0] FWLEN,
output [15:0] SWLEN,
output [15:0] RST_LMT,
output WDSRVC,
output INIT,
output [2:0] FLSTAT,
output [19:0] BOD_thresh1,
output [19:0] BOD_thresh... | 7.163412 |
module configuration_register_tb ();
localparam T = 20;
reg [15:0] dbus;
reg [ 1:0] abus;
reg clk, rst;
wire wren;
wire [15:0] swlen, fwlen, rst_lmt;
wire wdsrvc;
wire init;
wire [2:0] flstat;
pattern_comparator PAT (
.DBUS(dbus),
.CLK (clk),
.RST (rst),
.WREN(wren)
);
... | 7.163412 |
module configuration_tb (
reset,
//----------------------------------------------------------------
// Host Interface: host_clk is always required
//----------------------------------------------------------------
host_clk,
//----------------------------------------------------------------
... | 7.163412 |
module Config_access (
C_bit0,
C_bit1,
C_bit2,
C_bit3,
ConfigBits
);
parameter NoConfigBits = 4;// has to be adjusted manually (we don't use an arithmetic parser for the value)
// Pin0
output C_bit0; // EXTERNAL
output C_bit1; // EXTERNAL
output C_bit2; // EXTERNAL
output C_bit3; // ... | 8.742914 |
module config_camera (
input clk,
input rstn,
output scl,
inout sda,
output config_done,
output reg [7:0] chip_version_h,
output reg [7:0] chip_version_l,
output reg [7:0] revision_number,
output reg [7:0] manufacturer_id,
output reg [7:0] smia_version,
output reg [7:0] f... | 6.86403 |
module config_controller #(
parameter WIDTH = 40,
parameter STAGES = 16,
parameter LUTSIZE = 6
) (
clk,
reset,
wren_in,
wren_out,
addr_in,
addr_out,
progress,
done
);
input clk;
input reset;
input wren_in;
output [STAGES-1:0] wren_out;
output [LUTSIZE-1:0] add... | 7.434386 |
module config_controller_simple #(
parameter WIDTH = 40,
parameter STAGES = 16,
parameter LUTSIZE = 6
) (
clk,
reset,
wren_in,
wren_out,
addr_in,
addr_out,
progress,
done
);
input clk;
input reset;
input wren_in;
output [STAGES-1:0] wren_out;
output [LUTSIZE-1... | 7.434386 |
module config_guass (
input CMOS_oCLK,
input iRST_N,
input [7:0] DATA,
input CMOS_VSYNC,
//input pclk,
output [7:0] reg1,
output [7:0] reg2,
output guass_clk
//output pp_ram_write_clk
);
//2bit counter
reg byte_state;
always @(posedge CMOS_oCLK or negedge iRST_N) begin
if... | 6.607796 |
module.
//
// Output that cycles ~1Hz (e.g., for LED indicator).
//
//////////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ns
module config_ind #(parameter P_CLK_FREQ_HZ = 100000000)
(
input clk, // system clk
input rst_n, // system reset, ac... | 7.909788 |
module config_parser_flow_control_loop_pipe_sequential_init (
ap_clk,
ap_rst,
ap_start,
ap_ready,
ap_done,
ap_start_int,
ap_ready_int,
ap_done_int,
ap_continue_int,
ap_loop_init,
ap_loop_exit_ready,
ap_loop_exit_done
);
input ap_clk;
input ap_rst;
//Block level ha... | 7.17314 |
module config_parser_regslice_both #(
parameter DataWidth = 32
) (
input ap_clk,
input ap_rst,
input [DataWidth-1:0] data_in,
input vld_in,
output ack_in,
output [DataWidth-1:0] data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wir... | 7.17314 |
module config_parser_regslice_both_w1 #(
parameter DataWidth = 1
) (
input ap_clk,
input ap_rst,
input data_in,
input vld_in,
output ack_in,
output data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire B_V_data_1_data_in;
... | 7.17314 |
module config_parser_v1_buffer_V (
address0,
ce0,
d0,
we0,
q0,
reset,
clk
);
parameter DataWidth = 64;
parameter AddressWidth = 8;
parameter AddressRange = 256;
input [AddressWidth-1:0] address0;
input ce0;
input [DataWidth-1:0] d0;
input we0;
output reg [DataWidth-1:0] q0;... | 7.17314 |
module config_passer (
CLK,
RSTn,
Empty,
Data,
D7_D0,
RINC,
WrEn,
RegAddr
);
/***************************************************************
*1.addr code empty
*7 6 5 4 3 2 1 0
*0 0|reg addr|op cnt|
*2.addr code write
*7 6 5 4 3 2 1 0
*1 0|reg addr|op cnt|
*******************... | 8.984925 |
module config_regs #(
parameter CH0_REG_ADDR = 2'h0,
parameter CH1_REG_ADDR = 2'h1,
parameter CH2_REG_ADDR = 2'h2,
parameter CRC_EN_REG_ADDR = 2'h3
) (
input clk,
input rst_n,
input [1:0] config_addr,
input [1:0] config_data,
input config_en,
output [1:0] ch0_addr,
output [1:... | 6.819559 |
module config_reg_mux (
`ifdef USE_POWER_PINS
inout vccd1, // User area 1 1.8V supply
inout vssd1, // User area 1 digital ground
`endif
input rst_n_i,
input reg_wr_i,
input [1:0] reg_adr_i,
input [15:0] reg_dat_i,
output reg [15:0] reg0_o,
output reg [15:0] reg1_o,
output ... | 6.908333 |
module config_retriever (
input wire clk,
output tri [20:0] sram_addr,
input wire [7:0] sram_data,
output tri sram_we_n,
output wire pwon_reset_n,
output wire vga_on,
output wire scanlines_on
);
reg [ 7:0] videoconfig = 8'h00;
reg [63:0] shift_master_reset = 64'd0;
always @(posedge c... | 6.979124 |
module config_tb;
//reg and wire definition
reg Empty;
reg iRCLK;
reg RSTn;
reg [7:0] Data;
wire [7:0] D7_D0;
wire RINC;
wire WrEn;
wire [2:0] RegAddr;
//inst for this module
config_passer config_passer_inst (
.CLK(iRCLK),
.RSTn(RSTn),
.Empty(Empty),
.Data(Data),
.... | 7.305113 |
module config_top (
clk,
rst,
CMOS_PCLK,
CMOS_VSYNC,
CMOS_HREF,
CMOS_iDATA,
I2C_SDAT,
I2C_SCLK,
xclk,
data,
CMOS_oCLK,
con
);
input clk;
input rst;
//cmos camera
input CMOS_PCLK;
input CMOS_VSYNC;
input CMOS_HREF;
input [7:0] CMOS_iDATA;
output I2C_SCLK;
... | 6.913884 |
module conflict_block #(
parameter ADDR_WIDTH = 13,
lower_addr = 0,
upper_addr = 4
) (
input clk,
input [ADDR_WIDTH-1:0] addrA,
input [ADDR_WIDTH-1:0] addrB,
output reg conflict //
);
always @(*) begin
if (addrA >= lower_addr && addrA <= upper_addr && addrB >= lower_addr && addrB <=... | 8.154134 |
module Conflict_Control_Unit (
input [31:0] ID_ir,
input [31:0] EX_ir,
input [31:0] MEM_ir,
input [31:0] WB_ir,
output IF_pc_enable,
output IF_ID_enable,
output ID_EX_enable,
output [1:0] EX_mux1_select_enable,
output [1:0] EX_mux2_select_enable
);
parameter [5:0] ALU = 6'b000001;... | 7.530942 |
module ConfMux (
input clock,
input reset,
input io_selector,
input [1:0] io_mux_input,
output io_mux_output
);
wire inputs_0 = io_mux_input[0]; // @[ConfMux.scala 32:34]
wire inputs_1 = io_mux_input[1]; // @[ConfMux.scala 32:34]
assign io_mux_output = io_selector... | 6.758398 |
module BufferCC_3 (
input [31:0] io_dataIn,
output [31:0] io_dataOut,
input timer_clk,
input aresetn
);
(* async_reg = "true" *)reg [31:0] buffers_0;
(* async_reg = "true" *)reg [31:0] buffers_1;
assign io_dataOut = buffers_1;
always @(posedge timer_clk) begin
buffers_0 <=... | 6.792516 |
module BufferCC_1 (
input [31:0] io_dataIn,
output [31:0] io_dataOut,
input aclk,
input aresetn
);
(* async_reg = "true" *)reg [31:0] buffers_0;
(* async_reg = "true" *)reg [31:0] buffers_1;
assign io_dataOut = buffers_1;
always @(posedge aclk) begin
buffers_0 <= io_dataIn... | 6.574801 |
module BufferCC (
input io_dataIn,
output io_dataOut,
input aclk,
input aresetn
);
(* async_reg = "true" *)reg buffers_0;
(* async_reg = "true" *)reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge aclk) begin
buffers_0 <= io_dataIn;
buffers_1 <= buffers_0;
end
endmod... | 6.712921 |
module confrontatore_1bit (
z,
x,
y
);
output wire z;
input wire x;
input wire y;
wire termine1;
wire termine2;
wire notx;
wire noty;
not (notx, x);
not (noty, y);
and_tp and1 (
termine1,
notx,
y
);
and_tp and2 (
termine2,
x,
noty
);
or_tp... | 7.155375 |
module confrontatore_nbit (
r,
x,
y
);
parameter N = 20;
input [N-1:0] x;
input [N-1:0] y;
output r;
wire [N-1:0] z;
genvar i;
generate
for (i = 0; i < N; i = i + 1) begin : testo_utile_a_togliere_il_warning
confrontatore_1bit t (
z[i],
x[i],
y[i]
... | 7.155375 |
module conf_read (
input clk,
input rst,
input start,
input [32-1:0] num_conf,
input available_read,
input [512-1:0] rd_data,
output reg req_rd_data,
output reg wr_conf,
output reg [352-1:0] conf_out,
output reg [10-1:0] conf_addr_out,
output reg [512-1:0] initial_conf,
o... | 7.439087 |
modules for supporting adaptive routing
**
**************************************************************/
/*****************************
port_presel
... | 9.070948 |
module port_presel_based_dst_ports_credit #(
parameter PPSw = 4,
parameter P = 5,
parameter V = 4,
parameter B = 4
) (
credit_decreased_all,
credit_increased_all,
port_pre_sel,
clk,
reset
);
function integer log2;
input integer number;
begin
log2 = (number <= 1) ? 1... | 7.654903 |
module mesh_torus_port_presel_based_dst_routers_vc #(
parameter PPSw = 4,
parameter P = 5,
parameter CONGw = 2 //congestion width per port
) (
port_pre_sel,
congestion_in_all,
reset,
clk
);
localparam CONG_ALw = CONGw * P; // congestion width per router;
localparam XDIR = 1'b0;
l... | 7.421465 |
module port_presel_based_dst_routers_ovc #(
parameter PPSw = 4,
parameter P = 5,
parameter V = 4,
parameter CONGw = 2 //congestion width per port
) (
port_pre_sel,
congestion_in_all
);
localparam P_1 = P - 1, CONG_ALw = CONGw * P; // congestion width per router;
input [CONG_ALw-1 : 0]... | 7.654903 |
module port_pre_sel_gen #(
parameter PPSw = 4,
parameter P = 5,
parameter V = 4,
parameter B = 4,
parameter CONGESTION_INDEX = 2,
parameter CONGw = 2,
parameter ROUTE_TYPE = "ADAPTIVE",
parameter [V-1 : 0] ESCAP_VC_MASK = 4'b0001
) (
port_pre_sel,
ovc_status,
ovc_avalable_al... | 7.27179 |
module congestion_out_based_ivc_req #(
parameter P = 5,
parameter V = 4,
parameter CONGw = 2 //congestion width per port
) (
ivc_request_all,
congestion_out_all
);
localparam PV = (V * P), CONG_ALw = (CONGw * P); // congestion width per router;
input [PV-1 : 0] ivc_request_all;
outp... | 7.985184 |
module congestion_out_based_ivc_notgrant #(
parameter P = 5,
parameter V = 4,
parameter CONGw = 2 //congestion width per port
) (
ivc_request_all,
congestion_out_all,
ivc_num_getting_sw_grant,
clk,
reset
);
function integer log2;
input integer number;
begin
log2 = (nu... | 7.985184 |
module congestion_out_based_3port_avb_ovc #(
parameter P = 5,
parameter V = 4,
parameter CONGw = 2 //congestion width per port
) (
ovc_avalable_all,
congestion_out_all
);
localparam P_1 = P - 1, PV = (V * P), CONG_ALw = CONGw * P;
localparam EAST = 0, NORTH = 1, WEST = 2, SOUTH = 3;
lo... | 7.985184 |
module congestion_out_based_avb_ovc_w2 #(
parameter P = 5,
parameter V = 4
) (
ovc_avalable_all,
congestion_out_all
);
localparam CONGw = 2; //congestion width per port
localparam P_1 = P - 1, PV = (V * P), CONG_ALw = CONGw * P, CNT_Iw = 2 * V;
input [PV-1 : 0] ovc_avalable_all;
output... | 7.985184 |
module congestion_out_based_avb_ovc_w3 #(
parameter P = 5,
parameter V = 4
) (
ovc_avalable_all,
congestion_out_all
);
localparam CONGw = 3; //congestion width per port
localparam P_1 = P - 1, PV = (V * P), CONG_ALw = CONGw * P;
localparam EAST = 0, NORTH = 1, WEST = 2, SOUTH = 3;
inpu... | 7.985184 |
module congestion_out_based_avb_ovc_w4 #(
parameter P = 5,
parameter V = 4
) (
ovc_avalable_all,
congestion_out_all
);
localparam CONGw = 4; //congestion width per port
localparam P_1 = P - 1, PV = (V * P), CONG_ALw = CONGw * P, CNT_Iw = 2 * V;
input [PV-1 : 0] ovc_avalable_all;
output ... | 7.985184 |
module cong_32bit (
s,
cout,
x,
y,
cin
);
parameter WID_DATA = 32;
input [WID_DATA-1:0] x, y;
input cin;
output [WID_DATA-1:0] s;
output cout;
wire net[0:WID_DATA-1];
genvar i;
FullAdder FA0 (
.s(s[0]),
.c(net[0]),
.x(x[0]),
.y(y[0]),
.z(cin)
);
gene... | 7.393933 |
module half_adder (
a,
b,
c,
s
);
input a, b;
output s, c;
wire a, b, c, s;
assign s = a ^ b;
assign c = a & b;
endmodule
| 6.966406 |
module chia_4bit (
input [3:0] a,
output [3:0] b,
output c
);
wire [3:0] a1;
assign a1 = 4'b0101;
FA FA[3:0] (
.a(a[3:0]),
.b(a1[3:0]),
.cin(1'b1),
.s(b),
.cout(c)
);
endmodule
| 7.155376 |
module adder_8bit (
in1,
in2,
S,
Cout
); //bo cong 8 bit
input [7:0] in1, in2;
output [7:0] S;
output Cout;
wire [7:1] temp;
FA FA_0 (
.a(in1[0]),
.b(in2[0]),
.cin(1'b0),
.S(S[0]),
.cout(temp[1])
);
FA FA_1 (
.a(in1[1]),
.b(in2[1]),
.cin(t... | 6.892153 |
module adder_9bit (
in1,
in2,
S,
Cout
); //bo cong 9bit
input [8:0] in1, in2;
output [8:0] S;
output Cout;
wire [8:1] temp;
FA FA_0 (
.a(in1[0]),
.b(in2[0]),
.cin(1'b0),
.S(S[0]),
.cout(temp[1])
);
FA FA_1 (
.a(in1[1]),
.b(in2[1]),
.cin(te... | 6.905269 |
module adder_10bit (
in1,
in2,
S,
Cout
); //bo cong 10bit
input [9:0] in1, in2;
output [9:0] S;
output Cout;
wire [9:1] temp;
FA FA_10 (
.a(in1[0]),
.b(in2[0]),
.cin(1'b0),
.S(S[0]),
.cout(temp[1])
);
FA FA_11 (
.a(in1[1]),
.b(in2[1]),
.ci... | 6.732604 |
module adder_26bit (
in1,
in2,
S,
Cout
); //bo cong 26bit
input [25:0] in1, in2;
output [25:0] S;
output Cout;
wire [25:1] temp;
FA FA_50 (
.a(in1[0]),
.b(in2[0]),
.cin(1'b0),
.S(S[0]),
.cout(temp[1])
);
FA FA_51 (
.a(in1[1]),
.b(in2[1]),
... | 6.609881 |
module shift_left16 (
in,
out,
sel
);
input [24:0] in;
input sel;
output [24:0] out;
assign out = sel ? {in[8:0], 16'b0} : in;
endmodule
| 7.715312 |
module shift_left8 (
in,
out,
sel
);
input [24:0] in;
input sel;
output [24:0] out;
assign out = sel ? {in[16:0], 8'b0} : in;
endmodule
| 6.882675 |
module shift_left4 (
in,
out,
sel
);
input [24:0] in;
input sel;
output [24:0] out;
assign out = sel ? {in[20:0], 4'b0} : in;
endmodule
| 6.688751 |
module shift_left2 (
in,
out,
sel
);
input [24:0] in;
input sel;
output [24:0] out;
assign out = sel ? {in[22:0], 2'b0} : in;
endmodule
| 7.131814 |
module shift_right (
in,
out,
shift
);
input [24:0] in;
input [4:0] shift;
output [24:0] out;
wire [23:0] tmp1, tmp2, tmp3, tmp4;
shift_right16 shift_1 (
.in (in[23:0]),
.sel(shift[4]),
.out(tmp1)
);
shift_right8 shift_2 (
.in (tmp1),
.sel(shift[3]),
.ou... | 6.706335 |
module shift_right16 (
in,
out,
sel
);
input [23:0] in;
input sel;
output [23:0] out;
assign out = sel ? {16'b0, in[23:16]} : in;
endmodule
| 7.507891 |
module shift_right8 (
in,
out,
sel
);
input [23:0] in;
input sel;
output [23:0] out;
assign out = sel ? {8'b0, in[23:8]} : in;
endmodule
| 6.617153 |
module shift_right2 (
in,
out,
sel
);
input [23:0] in;
input sel;
output [23:0] out;
assign out = sel ? {2'b0, in[23:2]} : in;
endmodule
| 7.02062 |
module bu2_8bit (
in,
out
);
input [7:0] in;
output [7:0] out;
wire [7:0] not_in;
assign not_in = ~in;
adder_8bit add1 (
.in1(not_in),
.in2(8'd1),
.S(out),
.Cout()
);
endmodule
| 7.916666 |
module bu2_9bit (
in,
out
);
input [8:0] in;
output [8:0] out;
wire [8:0] not_in;
assign not_in = ~in;
adder_9bit add1 (
.in1(not_in),
.in2(9'd1),
.S(out),
.Cout()
);
endmodule
| 8.173614 |
module bu2_10bit (
in,
out
);
input [9:0] in;
output [9:0] out;
wire [9:0] not_in;
assign not_in = ~in;
adder_10bit add1 (
.in1(not_in),
.in2(10'd1),
.S(out),
.Cout()
);
endmodule
| 8.350981 |
module bu2_25bit (
in,
out
);
input [24:0] in;
output [24:0] out;
wire [24:0] not_in;
assign not_in = ~in;
adder_25bit add1 (
.in1(not_in),
.in2(25'd1),
.S(out),
.Cout()
);
endmodule
| 7.570944 |
module mux8 (
in1,
in2,
sel,
out
);
input [7:0] in1, in2;
input sel;
output [7:0] out;
assign out = sel ? in2 : in1;
endmodule
| 7.606032 |
module mux25 (
in1,
in2,
sel,
out
);
input [24:0] in1, in2;
input sel;
output [24:0] out;
assign out = sel ? in2 : in1;
endmodule
| 8.296164 |
module Conical (
input [6:0] X,
input [5:0] Y,
input [6:0] leftX,
input [5:0] topY,
input [15:0] BACKGROUND,
output reg [15:0] oled_data = 16'b0,
input selected
);
parameter [15:0] WHITE = 16'b11111_111111_11111;
parameter [15:0] LIGHTGREY = 16'b10100_101001_10100;
parameter [15:0] DAR... | 6.639579 |
module conj #(
parameter WIDTH = 16
) (
input clk,
input reset,
input clear,
input [2*WIDTH-1:0] i_tdata,
input i_tlast,
input i_tvalid,
output i_tready,
output [2*WIDTH-1:0] o_tdata,
output o_tlast,
output o_tvalid,
input o_tready
);
assign o_tdata = {i_tdata[2*WIDTH... | 7.175338 |
module conjugate_Op #(
parameter MULT_WIDTH = 18
) (
input [MULT_WIDTH-1:0] iReal,
input [MULT_WIDTH-1:0] iImag,
output [MULT_WIDTH-1:0] oReal,
output [MULT_WIDTH-1:0] oImag
);
// `include "fft_inc.h"
assign oReal = iReal;
assign oImag = -iImag;
endmodule
| 8.040029 |
module : connect6
// top module :
// author : vipin k
// description : top most module
// revision :
// 18-8-2011 : Initial draft
//--------------------------------------------------------------------------------------------
module connect6(
input wire i_clk,
input wi... | 7.05814 |
module connected #(
parameter EDGE_W = 64
) (
input wire clk,
input wire rst,
input wire start,
input wire [EDGE_W-1:0] RData,
input wire RDataV,
input wire r_en0,
input wire w_en0,
output wire WDataV0,
input wire r_en1,
input wire w_en1,
output wire WDataV1,
input wi... | 6.559914 |
module combine_unit (
input wire clk,
input wire [31:0] update_A,
input wire [31:0] update_B,
output reg [31:0] combined_update
);
always @(posedge clk) begin
combined_update <= (update_A > update_B) ? update_B : update_A;
end
endmodule
| 7.696525 |
module PP #(
parameter PIPE_DEPTH = 5,
parameter URAM_DATA_W = 32,
parameter PAR_SIZE_W = 18,
parameter EDGE_W = 64
) (
input wire clk,
input wire rst,
input wire [ 1:0] control,
input wire [ URAM_DATA_... | 6.701393 |
module wcc_gather_pipe #(
parameter PIPE_DEPTH = 1,
parameter PAR_SIZE_W = 18,
parameter URAM_DATA_W = 32
) (
input wire clk,
input wire rst,
input wire [ 31:0] update_value,
input wire [ 31:0] update_dest,
input wire [URAM_D... | 7.202247 |
module wcc_scatter_pipe #(
parameter PIPE_DEPTH = 3,
parameter URAM_DATA_W = 32
) (
input wire clk,
input wire rst,
input wire [ 15:0] edge_weight,
input wire [URAM_DATA_W-1:0] src_attr,
input wire [ 31:0] edge_dest,
input wi... | 7.522624 |
module seout (
input wire clk,
input wire rst,
input wire [63:0] input_update0,
input wire [63:0] input_update1,
input wire [63:0] input_update2,
input wire [63:0] input_update3,
input wire [63:0] input_update4,
input wire [63:0] input_update5,
input wire [63:0] input_update6,
in... | 7.596749 |
module scheduler #(
parameter PAR_NUM = 32,
parameter PAR_NUM_W = 5
) (
input wire clk,
input wire rst,
input wire [ 1:0] control,
input wire par_complete_sig,
input wire par_active,
output reg [31:0] Raddr,
output reg [31:0] work_size,
output... | 6.930344 |
module bram #(
parameter DATA = 1,
parameter ADDR = 16
) (
// Port A
input wire clk,
input wire a_wr,
input wire [ADDR-1:0] a_addr,
input wire [DATA-1:0] a_din,
output reg [DATA-1:0] a_dout,
// Port B
//input wire b_clk,
input wir... | 7.645509 |
module URAM (
Data_in, // W
R_Addr, // R
W_Addr, // W
W_En, // W
En,
clk,
Data_out // R
);
parameter DATA_W = 256;
parameter ADDR_W = 10;
localparam DEPTH = (2 ** ADDR_W);
input [DATA_W-1:0] Data_in;
input [ADDR_W-1:0] R_Addr, W_Addr;
input W_En;
input En;
input clk;
... | 6.958095 |
module URAM (
Data_in, // W
R_Addr, // R
W_Addr, // W
W_En, // W
En,
clk,
Data_out // R
);
parameter DATA_W = 256;
parameter ADDR_W = 10;
localparam DEPTH = (2 ** ADDR_W);
input [DATA_W-1:0] Data_in;
input [ADDR_W-1:0] R_Addr, W_Addr;
input W_En;
input En;
input clk;
... | 6.958095 |
module get_around (
input clk,
input rst_n,
input fs,
input hs,
input [DATA_WIDH-1:00] data,
output [DATA_WIDH-1:00] middle,
output [DATA_WIDH-1:00] left,
output [DATA_WIDH-1:00] up_right1,
output [DATA_WIDH-1:00] ... | 6.923827 |
module connect_mailbox_v1_0 #(
// Users to add parameters here
parameter integer C_FLIT_WIDTH = 39,
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00... | 7.488335 |
module consecutive_instructions_tb ();
reg clk;
reg reset;
SoC mut (
.clk (clk),
.reset(reset)
);
initial begin
clk = 0;
end
always begin
#5;
clk = ~clk;
end
initial begin
$info("Unit testing consecutive instructions");
$dumpfile("multiple_instructions_out.vcd");
... | 6.738805 |
module const
#(parameter WIDTH=32)
(input clk, input reset,
input [WIDTH-1:0] config_tdata, input config_tlast, input config_tvalid, output config_tready,
output [WIDTH-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready);
reg [WIDTH-1:0] const_val;
always @(posedge clk)
if(reset... | 7.000163 |
module const32 (
cons
);
output signed [31:0] cons;
parameter signed [31:0] VALUE = 0;
assign cons = VALUE;
endmodule
| 8.377249 |
module std_const #(
parameter WIDTH = 32,
parameter VALUE = 0
) (
output logic [WIDTH - 1:0] out
);
assign out = VALUE;
endmodule
| 8.794277 |
module std_wire #(
parameter WIDTH = 32
) (
input wire logic [WIDTH - 1:0] in,
output logic [WIDTH - 1:0] out
);
assign out = in;
endmodule
| 8.485736 |
module std_slice #(
parameter IN_WIDTH = 32,
parameter OUT_WIDTH = 32
) (
input wire logic [ IN_WIDTH-1:0] in,
output logic [OUT_WIDTH-1:0] out
);
assign out = in[OUT_WIDTH-1:0];
`ifdef VERILATOR
always_comb begin
if (IN_WIDTH < OUT_WIDTH)
$error(
"std_slice: Input width ... | 8.248138 |
module std_pad #(
parameter IN_WIDTH = 32,
parameter OUT_WIDTH = 32
) (
input wire logic [ IN_WIDTH-1:0] in,
output logic [OUT_WIDTH-1:0] out
);
localparam EXTEND = OUT_WIDTH - IN_WIDTH;
assign out = {{EXTEND{1'b0}}, in};
`ifdef VERILATOR
always_comb begin
if (IN_WIDTH > OUT_WIDTH)
... | 8.450332 |
module std_not #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] in,
output logic [WIDTH-1:0] out
);
if (WIDTH == 1) begin
lakeroad_xilinx_ultrascale_plus_not1_1 _impl (
in,
out
);
end else if (WIDTH == 8) begin
lakeroad_xilinx_ultrascale_plus_not8_1 _impl (
... | 8.707194 |
module std_and #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
if (WIDTH == 1) begin
lakeroad_xilinx_ultrascale_plus_and1_2 _impl (
left,
right,
out
);
end else if (WIDTH == 32) ... | 8.159461 |
module std_or #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
if (WIDTH == 1) begin
lakeroad_xilinx_ultrascale_plus_or1_2 _impl (
left,
right,
out
);
end else begin
$error("U... | 8.160076 |
module std_xor #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
// if (WIDTH == x) begin
// lakeroad_xilinx_ultrascale_plus_op _impl(in, out);
// end
// //else begin
$error("Unsupported bitwidth %0d", WI... | 8.185133 |
module std_add #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
if (WIDTH == 2) begin
lakeroad_xilinx_ultrascale_plus_add2_2 _impl (
left,
right,
out
);
end else if (WIDTH == 3) ... | 7.105468 |
module std_sub #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
if (WIDTH == 5) begin
lakeroad_xilinx_ultrascale_plus_sub5_2 _impl (
left,
right,
out
);
end else if (WIDTH == 6) b... | 7.29825 |
module std_gt #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
if (WIDTH == 5) begin
lakeroad_xilinx_ultrascale_plus_ugt5_2 _impl (
left,
right,
out
);
end else begin
$error("Unsupported bitwidt... | 7.445889 |
module std_lt #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
if (WIDTH == 3) begin
lakeroad_xilinx_ultrascale_plus_ult3_2 _impl (
left,
right,
out
);
end else if (WIDTH == 4) begin
lakeroad_xi... | 7.925865 |
module std_eq #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
if (WIDTH == 1) begin
lakeroad_xilinx_ultrascale_plus_eq1_2 _impl (
left,
right,
out
);
end else if (WIDTH == 5) begin
lakeroad_xil... | 8.155468 |
module std_neq #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
if (0 == 1) begin
end else begin
$error("Unsupported bitwidth %0d", WIDTH);
end
endmodule
| 7.624981 |
module std_ge #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
if (0 == 1) begin
end else begin
$error("Unsupported bitwidth %0d", WIDTH);
end
endmodule
| 6.896227 |
module std_le #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
if (WIDTH == 4) begin
lakeroad_xilinx_ultrascale_plus_ule4_2 _impl (
left,
right,
out
);
end else begin
$error("Unsupported bitwidt... | 8.161124 |
module std_lsh #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left << right;
endmodule
| 8.684363 |
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