code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module ReduceParallel_n3_unq1 (
input [7:0] I_0_0,
input [7:0] I_1_0,
input [7:0] I_2_0,
output [7:0] O_0
);
wire [7:0] renamedForReduce_inst0_out_0;
wire [7:0] renamedForReduce_inst1_out_0;
renamedForReduce_unq1 renamedForReduce_inst0 (
.in0_0(I_2_0),
.in1_0(renamedForReduce_inst1_... | 7.174445 |
module Reduce_S_n3_unq1 (
input clk,
input [7:0] I_0_0,
input [7:0] I_1_0,
input [7:0] I_2_0,
output [7:0] O_0_0,
output valid_down,
input valid_up
);
wire [7:0] ReduceParallel_n3_inst0_O_0;
wire [7:0] Register_Array_1_Array_1_Array_8_Bit___t_0init_FalseCE_FalseRESET_inst0_O_0_0;
wire ... | 7.107378 |
module NativeMapParallel_n2_unq7 (
input clk,
input [7:0] I_0_0_0,
input [7:0] I_0_0_1,
input [7:0] I_0_0_2,
input [7:0] I_0_1_0,
input [7:0] I_0_1_1,
input [7:0] I_0_1_2,
input [7:0] I_0_2_0,
input [7:0] I_0_2_1,
input [7:0] I_0_2_2,
input [7:0] I_1_0_0,
input [7:0] I_1_... | 7.274395 |
module Map_T_n8_i0_unq8 (
input clk,
input [7:0] I_0_0_0,
input [7:0] I_0_0_1,
input [7:0] I_0_0_2,
input [7:0] I_0_1_0,
input [7:0] I_0_1_1,
input [7:0] I_0_1_2,
input [7:0] I_0_2_0,
input [7:0] I_0_2_1,
input [7:0] I_0_2_2,
input [7:0] I_1_0_0,
input [7:0] I_1_0_1,
... | 7.240773 |
module Conv2d (
input clk,
input [7:0] I_0,
input [7:0] I_1,
output [7:0] O_0,
output [7:0] O_1
);
top t (
.clk(clk),
.valid_up(1'd1),
.valid_down(),
.I_0(I_0),
.I_1(I_1),
.O_0(O_0),
.O_1(O_1)
);
endmodule
| 7.302381 |
module conv2D_opt #(
parameter AWIDTH = 32,
parameter DWIDTH = 32,
parameter WT_DIM = 3
) (
input clk,
input rst,
// Control/Status signals
input start,
output idle,
output done,
// Scalar signals
input [31:0] fm_dim,
input [31:0] wt_offset,
input [31:0] ifm_offset... | 7.3386 |
module conv2d_top #(
parameter IFMAP_DATA_WIDTH = 8,
parameter OFMAP_DATA_WIDTH = 32,
parameter KERNEL_SIZE = 3
) (
input clk,
input rst_n,
input en,
input clear,
input ifmap_fifo_wr_en_i,
input [IFMAP_DATA_WIDTH-1:0] ifmap_fifo_data_i,
input [KERNEL_SIZE*KERNEL_SIZE*IFMAP_DATA_... | 7.331374 |
module conv2(
input [12 * 12 * 8 - 1:0] tensor_in,
input [25 * 8 - 1:0] filter_in,
input [7:0] bias_in,
output [8 * 8 * 8 - 1:0] tensor_out,
output overflow
);
wire [8 * 8 * 2 - 1:0] overflows;
wire [8 * 8 * 8 - 1:0] conv_out;
genvar rowCnt,colCnt;
generate
for (rowCnt = 0... | 6.526784 |
module Conv2_Full_tb;
// Inputs
reg [7:0] pattern;
reg [7:0] image;
reg rst;
reg clk;
reg enable;
// Outputs
wire [21:0] convSum;
wire packetRead;
Conv2_Full dut (
.clk(clk),
.rst(rst),
.enable(enable),
.packetRead(packetRead),
.image(image),
.pattern(pattern),... | 6.742799 |
module Conv2_weight_rom_group (
input work_clk,
input rst_n,
input [ 3:0] AER_channel,
input [`A_weight_rom_width_conv2] addra, // 8bit address width
output reg [`D_weight_rom_width_conv2] douta... | 7.615754 |
module kernel_pixel_2 (
input clk,
input signed [15:0] pixel,
output reg signed [32*3*3-1:0] weighted_pixel
);
wire signed [15:0] weight[0:2][0:2];
assign weight[0][0] = -16'd6887;
assign weight[0][1] = -16'd4375;
assign weight[0][2] = 16'd1520;
assign weight[1][0] = -16'd422;
assign weight[1][... | 6.500467 |
module conv3D_sw #(
parameter IFM_DIM = 28,
parameter IFM_DEPTH = 2,
parameter OFM_DIM = 24,
parameter OFM_DEPTH = 2,
parameter WT_DIM = 5
) ();
integer ifm_data[IFM_DEPTH*IFM_DIM*IFM_DIM-1:0];
integer wt_data[OFM_DEPTH*IFM_DEPTH * WT_DIM*WT_DIM-1:0];
integer ofm_sw_data[OFM_DEPTH*OFM_... | 7.664168 |
module conv3x3_2D #(
parameter DATA_WIDTH = 32,
parameter IMAGE_WIDTH = 5
) (
clk,
rst_n,
i_valid,
i_data,
i_kernel,
o_data,
o_valid
);
//----------input and output port----------//
input clk;
input rst_n;
input i_valid;
input [DATA_WIDTH-1:0] i_data;
input [DATA_WIDTH*... | 7.278256 |
module conv553 #(
parameter BIT_WIDTH = 8,
OUT_WIDTH = 32
) (
input clk, //rst,
input en, // whether to latch or not
input signed [BIT_WIDTH-1:0] in01,
in02,
in03,
in04,
in05,
input signed [BIT_WIDTH-1:0] in11,
in12,
in13,
in14,
in15,
input signed [BIT_WIDTH... | 6.830941 |
module conv554 #(
parameter BIT_WIDTH = 8,
OUT_WIDTH = 32
) (
input clk, //rst,
input en, // whether to latch or not
input signed [BIT_WIDTH-1:0] in01,
in02,
in03,
in04,
in05,
input signed [BIT_WIDTH-1:0] in11,
in12,
in13,
in14,
in15,
input signed [BIT_WIDTH... | 6.892072 |
module conv556 #(
parameter BIT_WIDTH = 8,
OUT_WIDTH = 32
) (
input clk, //rst,
input en, // whether to latch or not
input signed [BIT_WIDTH-1:0] in01,
in02,
in03,
in04,
in05,
input signed [BIT_WIDTH-1:0] in11,
in12,
in13,
in14,
in15,
input signed [BIT_WIDTH... | 7.282924 |
module conv5x5 (
input clock,
input reset,
input [DWIDTH-1:0] data_in,
input data_valid,
output [DWIDTH-1:0] data_out,
output data_valid_out
);
parameter DWIDTH = 8;
///
///
endmodule
| 7.186648 |
module conva1_DP #(
parameter
///////////advanced parameters//////////
DATA_WIDTH = 32,
ADDRESS_BITS = 15,
/////////////////////////////////////
IFM_SIZE = 34,
IFM_DEPTH = 1,
KERNAL_SIZE = 5,
NUMBER_OF_FILTERS = 8,
NUMBER_OF_UNITS = 3,
ARITH_TYPE = 0,
////////////////////... | 7.441781 |
module convenc (
input wire clk,
input wire rst,
input wire enc_en,
input wire bit_in,
output wire [1:0] bits_out
);
reg [5:0] state;
always @(posedge clk)
if (rst) begin
state <= 0;
end else if (enc_en) begin
state <= {state[4:0], bit_in};
end
assign bits_out[0] = bi... | 6.965801 |
module load_shift_control (
Qin,
QMin,
CshiftQ,
CshiftQM,
Qkplusone
);
input [1:0] Qkplusone; // Qkplusone[0] is the q- bit, Qkplusone[1] is the q+ bit
output Qin;
output CshiftQ;
output QMin;
output CshiftQM;
not i1 (CshiftQ, Qkplusone[0]);
not i2 (CshiftQM, Qkplusone[1]);
or o1... | 6.926719 |
module register8 (
Q,
D,
Clk,
Load,
Reset
);
input [7:0] D;
input Clk;
input Load;
input Reset;
output [7:0] Q;
reg [7:0] Q;
always @(posedge Clk or posedge Reset)
if (Reset) Q <= 8'h00;
else if (Load) Q <= D;
else Q <= Q;
endmodule
| 6.951061 |
module dff (
output q,
output qnot,
input d,
input clk,
input clear,
input preset
);
reg q, qnot;
always @(posedge clk)
if (clear) begin
q <= 0;
qnot <= ~q;
end else if (preset) begin
q <= 1;
qnot <= ~q;
end else begin
q <= d;
qnot <= ~q;
... | 7.02102 |
module Conversor_BCD_7seg (
input wire [3:0] Valor_Decimal,
output reg [7:0] Code_7seg
);
//Descripcin combinacional del valor decimal a cdigo para el 7 segmentos
always @* begin
case (Valor_Decimal)
4'h0: Code_7seg = 8'b00000011; //0
4'h1: Code_7seg = 8'b10011111; //1
4'h2: Co... | 7.742803 |
module conversor_RegNbits_RegBCD (
reg_binario,
reg_BCD
); //convierte un registro binario en un registro de cifras BCD
//module conversor_RegNbits_RegBCD(reg_binario, habilitado,reg_BCD);//convierte un registro binario en un registro de cifras BCD
parameter TAM_REG_BIN = `BUS_DAT;
input reg_binario;
... | 7.60515 |
module Convert12 (
ALUout,
ALUout12bit
);
input [31:0] ALUout;
output [11:0] ALUout12bit;
assign ALUout12bit = ALUout[11:0];
endmodule
| 7.547308 |
module ConvertBinaryToMantissa (
en,
isFloat,
isExponentOdd,
in,
mantissa,
isDone
);
parameter DOUBLE_PRECISION_ODD = 11'd52,
SINGLE_PRECISION_ODD = 8'd23,
DOUBLE_PRECISION_EVEN = 11'd53,
SINGLE_PRECISION_EVEN = 8'd24,
MANTISSA_SIZE = 6... | 8.273659 |
module dma_converter (
input clk,
input reset,
output last,
output reg [3:0] keep,
input [31:0] dout,
input valid,
input ready,
output reg [31:0] OutCnt
);
always @(posedge clk /* or negedge reset*/) begin
if (reset) OutCnt <= 0;
else begin
if (valid && ready) begin... | 6.682236 |
module b2g (
b,
g
);
input [3:0] b;
output [3:0] g;
xor (g[0], b[0], b[1]), (g[1], b[1], b[2]), (g[2], b[2], b[3]);
assign g[3] = b[3];
endmodule
| 6.834884 |
module ConvertFromZ (
IN,
OUT
);
parameter width = 1;
input [width - 1 : 0] IN;
output [width - 1 : 0] OUT;
tri [width - 1 : 0] BUS;
assign BUS = IN;
assign OUT = BUS;
endmodule
| 7.862828 |
module convertidor (
PCLK,
in,
out_8,
ENB,
CLK
);
input wire [1:0] PCLK;
input wire CLK;
input wire ENB;
input wire [31:0] in;
output reg [7:0] out_8;
reg [1:0] bits;
always @(*) begin
case (PCLK[1:0])
2'b00: bits = 2'b11;
2'b01: bits = 2'b01;
2'b10: bits = 2'b00... | 7.1666 |
module ConvertMantissaToBinary (
en,
isFloat,
isExponentOdd,
mantissa,
out
);
parameter DOUBLE_PRECISION_ODD = 11'd52,
SINGLE_PRECISION_ODD = 8'd23,
DOUBLE_PRECISION_EVEN = 11'd53,
SINGLE_PRECISION_EVEN = 8'd24,
MANTISSA_SIZE = 6'd52,
... | 7.730979 |
module Convertor #(
parameter BUS_WIDTH = 8,
parameter REGISTER_QUANTITY = 4
) (
Register0,
Register1,
Register2,
Register3,
ReadNextByte,
Enable,
ByteReady,
McuBus
);
input [BUS_WIDTH-1:0] Register0, Register1, Register2, Register3;
input ReadNextByte, Enable;
output Byte... | 8.26616 |
module CONVERTOR_CKT (
input wire [3 : 0] hours_cur,
wire [5 : 0] mins_cur,
output reg [13 : 0] hours_disp,
mins_disp
);
// digital number display
parameter [6 : 0] zero = 7'b1111110;
parameter [6 : 0] one = 7'b0110000;
parameter [6 : 0] two = 7'b1101101;
parameter [6 : 0] three = 7'b1111001;... | 6.767745 |
module ConvertToZ (
IN,
CTL,
OUT
);
parameter width = 1;
input [width - 1 : 0] IN;
input CTL;
output [width - 1 : 0] OUT;
tri [width - 1 : 0] BUS;
assign BUS = CTL ? IN : 'bz;
assign OUT = BUS;
endmodule
| 6.70819 |
module Convert_32to8 (
clk,
data_in,
data_out,
t_done,
start,
t_signal,
s_empty
);
input clk;
input [31:0] data_in;
input t_done;
input start;
output reg [7:0] data_out;
output reg t_signal;
output reg s_empty;
reg state;
reg [31:0] data_temp;
reg [5:0] counter;
parame... | 6.83763 |
module convert_444_422 (
//input signal
input clk,
input [7:0] r_in, // R
input [7:0] g_in, // G
input [7:0] b_in, // B
input hsync_in,
input vsync_in,
input de_in,
//output signal
output [8:0] r1_out,
output [8:0] g1_out,
output... | 6.718317 |
module CONVERT_AND_SCALE (
clk,
reset_x,
clk_enable,
In1,
In2,
ce_out,
PID_OUT
);
input clk;
input reset_x;
input clk_enable;
input [4:0] In1; // ufix5
input [63:0] In2; // ufix64
output ce_out;
output signed [35:0] PID_OUT; // sfix36_En14
wire signed [35:0] RECIPROCAL... | 6.811419 |
module Convert_Ascii_to_Music (
key_ascii,
music_note
); //将ascii码转化为对应的音符位置
input [7:0] key_ascii;
output reg [4:0] music_note;
always @(*) begin
case (key_ascii)
0: music_note = 0;
8'h51: music_note = 5'd1;
8'h57: music_note = 5'd2;
8'h45: music_note = 5'd3;
8'h52: m... | 7.790228 |
module convert_clk (
clk_j83,
clk,
rst,
sc_i_d,
sc_i_dval,
sc_i_sop,
sc_i_eop,
sc_o_d,
sc_o_dval,
sc_o_sop,
sc_o_eop
);
input clk_j83;
input clk;
input rst;
input [31:0] sc_i_d;
input sc_i_dval;
input sc_i_sop;
input sc_i_eop;
output [31:0] sc_o_d;
output s... | 6.82409 |
module convert_encoder (
input clk,
input [15:0] data_in,
output reg [15:0] data_out
);
initial begin
data_out = 0;
end
always @(posedge clk) begin
if (data_in[11]) begin
data_out <= (data_in - 2048) * (-1);
end else begin
data_out <= data_in;
end
end
endmodule
| 7.043024 |
module Convert_Float_To_Fixed (
input wire CLK, //CLOCK
input wire [31:0] FLOAT, //VALOR DEL NUMERO EN PUNTO FLOTANTE
input wire EN_REG1, // ENABLE PARA EL REGISTRO 1 QUE GUARDA EL NUMERO EN PUNTO FLOTANTE
input wire LOAD, // SELECCION CARGA REGISTRO DE DESPLZAMIENTOS
input wire MS_1, //SE... | 7.010957 |
module Convert_Float_To_Fixed_V (
input wire CLK, //CLOCK
input wire [31:0] FLOAT, //VALOR DEL NUMERO EN PUNTO FLOTANTE
input wire EN_REG1, // ENABLE PARA EL REGISTRO 1 QUE GUARDA EL NUMERO EN PUNTO FLOTANTE
input wire LOAD, // SELECCION CARGA REGISTRO DE DESPLZAMIENTOS
input wire MS_1, //... | 7.010957 |
module is bit-sliced. Instantiate once for each GPIO pad.
* (Caravel has only one GPIO pad, so bit-slicing is irrelevant.)
*/
module convert_gpio_sigs (
input gpio_out,
input gpio_outenb,
input gpio_pu,
input gpio_pd,
output gpio_out_pad,
output gpio_o... | 7.949666 |
module convert_k (
in,
k
);
parameter DWIDTH = 32;
parameter IWIDTH = 64;
input [0:0] in;
output [DWIDTH-1:0] k;
assign k = in ? 32'b00000000100000000000000000000000 : 32'b00000000000000000000000000000000;
endmodule
| 7.569058 |
module Convert_to_EightBit (
input [3:0] in,
output reg [7:0] out
);
always @(in) begin
case (in)
4'd0: out = 8'd0;
4'd1: out = 8'd1;
4'd2: out = 8'd2;
4'd3: out = 8'd3;
4'd4: out = 8'd4;
4'd5: out = 8'd5;
4'd6: out = 8'd6;
4'd7: out = 8'd7;
4... | 6.596888 |
module ConvKernel
//----------------------------------------------------------------
// Params
//----------------------------------------------------------------
#(
parameter integer BITWIDTH = 8,
parameter integer DATACHANNEL = 1,
parameter integer FILTERHEIGHT = 5,
parameter integer FILTERWIDTH = 5
... | 7.908537 |
module convolution3x3_dilation (
input clk,
input rst_n,
input i_pixel,
input i_pixel_valid,
output tap0,
output tap1,
output o_pixel,
output pixel0_check,
output pixel1_check,
output pixel2_check,
output pixel3_check,
output pixel4_check,
output pixel5_check,
out... | 7.920011 |
module convolution3x3_erosion (
input clk,
input rst_n,
input i_pixel,
input i_pixel_valid,
output tap0,
output tap1,
output o_pixel,
output pixel0_check,
output pixel1_check,
output pixel2_check,
output pixel3_check,
output pixel4_check,
output pixel5_check,
outp... | 7.920011 |
module convolution3x3_median (
input clk,
input rst_n,
input [DATA_WIDTH - 1:0] i_pixel,
input i_pixel_valid,
output [DATA_WIDTH - 1:0] tap0,
output [DATA_WIDTH - 1:0] tap1,
output [DATA_WIDTH - 1:0] o_pixel,
output [DATA_WIDTH - 1:0] pixel0_check,
output [DATA_WIDTH - 1:0] pixel1_ch... | 7.920011 |
module Convolutional_Encoder_V1 (
in,
parities,
CLK
);
input wire in;
input wire CLK;
output reg [1:0] parities;
reg [1:0] state = 2'b00;
always @(posedge CLK) begin
if (in == 1'b0 && state == 2'b00) begin
parities = 2'b00;
state = 2'b00;
end else if (in == 1'b1 && state == 2... | 6.764084 |
module ConvolutionInputGenerator1D_0_ConvolutionInputGbkb_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 8;
parameter AWIDTH = 10;
parameter MEM_SIZE = 784;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
... | 7.617353 |
module ConvolutionInputGenerator1D_0_ConvolutionInputGbkb (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd784;
parameter AddressWidth = 32'd10;
input reset;
input clk;
input [AddressWidth - 1:0] address... | 7.617353 |
module ConvolutionInputGenerator1D_1_ConvolutionInputGbkb_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 8;
parameter MEM_SIZE = 194;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
... | 7.617353 |
module ConvolutionInputGenerator1D_1_ConvolutionInputGbkb (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd194;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input [AddressWidth - 1:0] address... | 7.617353 |
module ConvolutionInputGenerator1D_2_ConvolutionInputGbkb_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 40;
parameter AWIDTH = 6;
parameter MEM_SIZE = 37;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
i... | 7.617353 |
module ConvolutionInputGenerator1D_2_ConvolutionInputGbkb (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd40;
parameter AddressRange = 32'd37;
parameter AddressWidth = 32'd6;
input reset;
input clk;
input [AddressWidth - 1:0] address0... | 7.617353 |
module ConvolutionInputGenerator_0_ConvolutionInputGbkb_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 8;
parameter AWIDTH = 5;
parameter MEM_SIZE = 30;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
inpu... | 7.617353 |
module ConvolutionInputGenerator_0_ConvolutionInputGbkb (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd30;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
... | 7.617353 |
module ConvolutionInputGenerator_0_ConvolutionInputGenerator_3u_3u_8u_258u_256u_1u_1u_ap_resource_lutram_s_inputbkb_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 8;
parameter AWIDTH = 10;
parameter MEM_SIZE = 774;
input [AWIDTH-1:0] addr0;
input ce0;
... | 7.617353 |
module ConvolutionInputGenerator_0_ConvolutionInputGenerator_3u_3u_8u_258u_256u_1u_1u_ap_resource_lutram_s_inputbkb(
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd774;
parameter AddressWidth = 32'd10;
input... | 7.617353 |
module ConvolutionInputGenerator_0_ConvolutionInputGfYi #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
dout_WIDTH = 32
) (
input [... | 7.617353 |
module ConvolutionInputGenerator_0_mux_42_8_1_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
dout_WIDTH = 32
) (
input [7 : 0] d... | 7.617353 |
module ConvolutionInputGenerator_0_regslice_both #(
parameter DataWidth = 32
) (
input ap_clk,
input ap_rst,
input [DataWidth-1:0] data_in,
input vld_in,
output ack_in,
output [DataWidth-1:0] data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_... | 7.617353 |
module ConvolutionInputGenerator_0_regslice_both_w1 #(
parameter DataWidth = 1
) (
input ap_clk,
input ap_rst,
input data_in,
input vld_in,
output ack_in,
output data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire B_V_dat... | 7.617353 |
module ConvolutionInputGenerator_1_ConvolutionInputGbkb_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 4;
parameter MEM_SIZE = 14;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
inp... | 7.617353 |
module ConvolutionInputGenerator_1_ConvolutionInputGbkb (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd14;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
... | 7.617353 |
module ConvolutionInputGenerator_1_ConvolutionInputGenerator_3u_64u_2u_130u_128u_4u_1u_ap_resource_lutram_s_inpubkb_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 8;
parameter AWIDTH = 12;
parameter MEM_SIZE = 2080;
input [AWIDTH-1:0] addr0;
input ce0;
... | 7.617353 |
module ConvolutionInputGenerator_1_ConvolutionInputGenerator_3u_64u_2u_130u_128u_4u_1u_ap_resource_lutram_s_inpubkb(
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd2080;
parameter AddressWidth = 32'd12;
inpu... | 7.617353 |
module ConvolutionInputGenerator_1_ConvolutionInputGfYi #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
dout_WIDTH = 32
) (
input [... | 7.617353 |
module ConvolutionInputGenerator_1_mux_42_8_1_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
dout_WIDTH = 32
) (
input [7 : 0] d... | 7.617353 |
module ConvolutionInputGenerator_1_regslice_both #(
parameter DataWidth = 32
) (
input ap_clk,
input ap_rst,
input [DataWidth-1:0] data_in,
input vld_in,
output ack_in,
output [DataWidth-1:0] data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_... | 7.617353 |
module ConvolutionInputGenerator_1_regslice_both_w1 #(
parameter DataWidth = 1
) (
input ap_clk,
input ap_rst,
input data_in,
input vld_in,
output ack_in,
output data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire B_V_dat... | 7.617353 |
module ConvolutionInputGenerator_2_ConvolutionInputGbkb_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 40;
parameter AWIDTH = 3;
parameter MEM_SIZE = 6;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
inpu... | 7.617353 |
module ConvolutionInputGenerator_2_ConvolutionInputGbkb (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd40;
parameter AddressRange = 32'd6;
parameter AddressWidth = 32'd3;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
... | 7.617353 |
module ConvolutionInputGenerator_2_ConvolutionInputGenerator_3u_64u_2u_66u_64u_1u_1u_ap_resource_lutram_s_inputBbkb_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 2;
parameter AWIDTH = 13;
parameter MEM_SIZE = 4224;
input [AWIDTH-1:0] addr0;
input ce0;
... | 7.617353 |
module ConvolutionInputGenerator_2_ConvolutionInputGenerator_3u_64u_2u_66u_64u_1u_1u_ap_resource_lutram_s_inputBbkb(
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd2;
parameter AddressRange = 32'd4224;
parameter AddressWidth = 32'd13;
inpu... | 7.617353 |
module ConvolutionInputGenerator_2_ConvolutionInputGfYi #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
dout_WIDTH = 32
) (
input [... | 7.617353 |
module ConvolutionInputGenerator_2_mux_42_2_1_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
dout_WIDTH = 32
) (
input [1 : 0] d... | 7.617353 |
module ConvolutionInputGenerator_2_regslice_both #(
parameter DataWidth = 32
) (
input ap_clk,
input ap_rst,
input [DataWidth-1:0] data_in,
input vld_in,
output ack_in,
output [DataWidth-1:0] data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_... | 7.617353 |
module ConvolutionInputGenerator_2_regslice_both_w1 #(
parameter DataWidth = 1
) (
input ap_clk,
input ap_rst,
input data_in,
input vld_in,
output ack_in,
output data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire B_V_dat... | 7.617353 |
module ConvolutionInputGenerator_3_ConvolutionInputGenerator_3u_128u_2u_34u_32u_1u_1u_ap_resource_lutram_s_inputbkb_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 2;
parameter AWIDTH = 13;
parameter MEM_SIZE = 4352;
input [AWIDTH-1:0] addr0;
input ce0;
... | 7.617353 |
module ConvolutionInputGenerator_3_ConvolutionInputGenerator_3u_128u_2u_34u_32u_1u_1u_ap_resource_lutram_s_inputbkb(
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd2;
parameter AddressRange = 32'd4352;
parameter AddressWidth = 32'd13;
inpu... | 7.617353 |
module ConvolutionInputGenerator_3_mux_42_2_1_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
dout_WIDTH = 32
) (
input [1 : 0] d... | 7.617353 |
module ConvolutionInputGenerator_3_regslice_both #(
parameter DataWidth = 32
) (
input ap_clk,
input ap_rst,
input [DataWidth-1:0] data_in,
input vld_in,
output ack_in,
output [DataWidth-1:0] data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_... | 7.617353 |
module ConvolutionInputGenerator_3_regslice_both_w1 #(
parameter DataWidth = 1
) (
input ap_clk,
input ap_rst,
input data_in,
input vld_in,
output ack_in,
output data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire B_V_dat... | 7.617353 |
module ConvolutionInputGenerator_4_ConvolutionInputGenerator_3u_128u_2u_18u_16u_1u_1u_ap_resource_lutram_s_inputbkb_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 2;
parameter AWIDTH = 12;
parameter MEM_SIZE = 2304;
input [AWIDTH-1:0] addr0;
input ce0;
... | 7.617353 |
module ConvolutionInputGenerator_4_ConvolutionInputGenerator_3u_128u_2u_18u_16u_1u_1u_ap_resource_lutram_s_inputbkb(
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd2;
parameter AddressRange = 32'd2304;
parameter AddressWidth = 32'd12;
inpu... | 7.617353 |
module ConvolutionInputGenerator_4_mux_42_2_1_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
dout_WIDTH = 32
) (
input [1 : 0] d... | 7.617353 |
module ConvolutionInputGenerator_4_regslice_both #(
parameter DataWidth = 32
) (
input ap_clk,
input ap_rst,
input [DataWidth-1:0] data_in,
input vld_in,
output ack_in,
output [DataWidth-1:0] data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_... | 7.617353 |
module ConvolutionInputGenerator_4_regslice_both_w1 #(
parameter DataWidth = 1
) (
input ap_clk,
input ap_rst,
input data_in,
input vld_in,
output ack_in,
output data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire B_V_dat... | 7.617353 |
module ConvolutionInputGenerator_5_ConvolutionInputGenerator_3u_256u_2u_10u_8u_1u_1u_ap_resource_lutram_s_inputBbkb_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 2;
parameter AWIDTH = 12;
parameter MEM_SIZE = 2560;
input [AWIDTH-1:0] addr0;
input ce0;
... | 7.617353 |
module ConvolutionInputGenerator_5_ConvolutionInputGenerator_3u_256u_2u_10u_8u_1u_1u_ap_resource_lutram_s_inputBbkb(
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd2;
parameter AddressRange = 32'd2560;
parameter AddressWidth = 32'd12;
inpu... | 7.617353 |
module ConvolutionInputGenerator_5_mux_42_2_1_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
dout_WIDTH = 32
) (
input [1 : 0] d... | 7.617353 |
module ConvolutionInputGenerator_5_regslice_both #(
parameter DataWidth = 32
) (
input ap_clk,
input ap_rst,
input [DataWidth-1:0] data_in,
input vld_in,
output ack_in,
output [DataWidth-1:0] data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_... | 7.617353 |
module ConvolutionInputGenerator_5_regslice_both_w1 #(
parameter DataWidth = 1
) (
input ap_clk,
input ap_rst,
input data_in,
input vld_in,
output ack_in,
output data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire B_V_dat... | 7.617353 |
module ConvolutionInputGenerator_6_ConvolutionInputGenerator_3u_256u_2u_6u_4u_1u_1u_ap_resource_lutram_s_inputBubkb_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 2;
parameter AWIDTH = 11;
parameter MEM_SIZE = 1536;
input [AWIDTH-1:0] addr0;
input ce0;
... | 7.617353 |
module ConvolutionInputGenerator_6_ConvolutionInputGenerator_3u_256u_2u_6u_4u_1u_1u_ap_resource_lutram_s_inputBubkb(
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd2;
parameter AddressRange = 32'd1536;
parameter AddressWidth = 32'd11;
inpu... | 7.617353 |
module ConvolutionInputGenerator_6_mux_42_2_1_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
dout_WIDTH = 32
) (
input [1 : 0] d... | 7.617353 |
module ConvolutionInputGenerator_6_regslice_both #(
parameter DataWidth = 32
) (
input ap_clk,
input ap_rst,
input [DataWidth-1:0] data_in,
input vld_in,
output ack_in,
output [DataWidth-1:0] data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_... | 7.617353 |
module ConvolutionInputGenerator_6_regslice_both_w1 #(
parameter DataWidth = 1
) (
input ap_clk,
input ap_rst,
input data_in,
input vld_in,
output ack_in,
output data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire B_V_dat... | 7.617353 |
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