code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module CELL_TYPE_ANDR #(
parameter PARAM_WIDTH = 1
) (
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN,
output [0 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = &PORT_ID_IN;
endmodule
| 7.368723 |
module CELL_TYPE_PORT #(
parameter PARAM_PORT_TYPE = 0,
parameter PARAM_OUT_WIDTH = 1
) (
input [PARAM_OUT_WIDTH - 1 : 0] PORT_ID_IN,
output [PARAM_OUT_WIDTH - 1 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = PORT_ID_IN;
endmodule
| 7.188365 |
module CELL_TYPE_ZEXT #(
parameter PARAM_IN_WIDTH = 1,
parameter PARAM_OUT_WIDTH = 1
) (
input [ PARAM_IN_WIDTH - 1 : 0] PORT_ID_IN,
output [PARAM_OUT_WIDTH - 1 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = {{(PARAM_OUT_WIDTH - PARAM_IN_WIDTH) {1'b0}}, PORT_ID_IN};
endmodule
| 8.169785 |
module CELL_TYPE_SLICE #(
parameter PARAM_WIDTH = 1,
parameter PARAM_LOW = 1,
parameter PARAM_HIGH = 1
) (
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN,
output [PARAM_HIGH - PARAM_LOW - 1 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = PORT_ID_IN[PARAM_HIGH:PARAM_LOW];
endmodule
| 7.958967 |
module CELL_TYPE_PASSTHROUGH #(
parameter PARAM_WIDTH = 1
) (
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN,
output [PARAM_WIDTH - 1 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = PORT_ID_IN;
endmodule
| 7.047345 |
module conv_code (
input conv_clk, //编码时钟, 50MHz
input out_clk, //数据输出时钟, 100MHz
input reset,
input data_in,
input conv_en, //置高开始编码
output reg data_out,
output reg conv_out_valid
);
reg [2:1] shift_reg; //编码移位寄存器
reg [1:0] enc_reg; //编码输出寄... | 6.553052 |
module conv_controller (
input rst,
input clk,
// IO memory map
input [3:0] conv_we_i,
input [`WORD_BUS] cont_data_i,
input [`WORD_BUS] cont_addr_i,
output [`WORD_BUS] cont_data_o,
output conv_active_o,
// Interact with conv2D
// Control/Status signals
input conv_idle_i,
... | 7.117335 |
module Conv_F16_F32 (
input [15:0] Fin,
output [31:0] Fout
);
reg [ 7:0] Exp_tmp;
reg [22:0] Man_tmp;
// este bloco resolve concatenação dos bits incluindo subnormal
always @(Fin) begin
if (Fin[14:10] == 5'd31) // se exp==31 +- inf
begin
Exp_tmp = 8'd255;
Man_tmp = 23'... | 8.90295 |
module Conv_F32_F16 (
input [31:0] Fin,
output [15:0] Fout
);
reg [4:0] Exp_tmp;
reg [9:0] Man_tmp;
always @(Fin) begin
if (Fin[30:23]>8'd142) // se exp32 > 142, mostra infinity F16
begin
Exp_tmp = 5'b11111; // exp = max (rep +- INF)
Man_tmp = 10'b0000000000; // man... | 7.259865 |
module conv_filt (
input clk,
input rst,
input [7:0] sw,
input [7:0] rx_red,
input [7:0] rx_green,
input [7:0] rx_blue,
input rx_dv,
input rx_hs,
input rx_vs,
output [7:0] tx_red,
output [7:0] tx_green,
output [7:0] tx_blue,
output ... | 6.794911 |
module conv_img #(
parameter AW = 14, //address width
parameter BW = 8, //bit width
parameter CH = 3, //channel nums
parameter DW = 64, //data width
parameter DH = 64, //data height
parameter WW = 3, //weight width
parameter WH = 3, //weight height
parameter SW = 1, //stride... | 6.66453 |
module conv_input_reg (
input clk,
enable,
input [7:0] data_in,
output reg [71:0] data_out
);
always @(posedge clk) begin
if (enable) begin
data_out <= data_out >> 8;
data_out[71:64] <= data_in;
end
end
endmodule
| 7.269203 |
module conv_kernel(
clk,
rst_n,
clear,
i_pixel,
i_weight,
o_pixel
);
parameter WIDTH = 32;
input clk;
input rst_n;
input clear;
input [WIDTH-1:0] i_pixel;
input [WIDTH-1:0] i_weight;
output [WIDTH-1:0] o_pixel;
reg [WIDTH-1:0] o_pixel;
//reg [WIDTH-1:0] o_pixel_reg;
reg [WIDTH-1:0] mult... | 7.633349 |
module ram (
addr0,
d0,
we0,
q0,
addr1,
d1,
we1,
q1,
clk
);
input [`AWIDTH-1:0] addr0;
input [`AWIDTH-1:0] addr1;
input [`MAT_MUL_SIZE*`DWIDTH-1:0] d0;
input [`MAT_MUL_SIZE*`DWIDTH-1:0] d1;
input [`MAT_MUL_SIZE-1:0] we0;
input [`MAT_MUL_SIZE-1:0] we1;
output [`MAT_MUL_... | 6.838627 |
module processing_element (
reset,
clk,
op,
ready_for_eltwise_op,
in_a,
in_b,
out_a,
out_b,
out_c,
flags
);
input reset;
input clk;
input [1:0] op;
input ready_for_eltwise_op;
input [`DWIDTH-1:0] in_a;
input [`DWIDTH-1:0] in_b;
output [`DWIDTH-1:0] out_a;
output ... | 6.504296 |
module Conv_layer_1 (
input work_clk,
input rst_n,
input [15:0] Conv1_AER_i,
output reg Conv1_AER_req_flag, // when a input AER operation conpleted it changes to zero
output wire [17:0] Conv1_AER_spike_o,
output wire spike_emit_flag
);
// Conv layer
reg [15:0] conv1_AER_buf;
... | 6.631085 |
module dpram (
clk,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
out_a,
out_b
);
parameter AWIDTH = 10;
parameter NUM_WORDS = 1024;
parameter DWIDTH = 32;
input clk;
input [(AWIDTH-1):0] address_a;
input [(AWIDTH-1):0] address_b;
input wren_a;
... | 7.511306 |
module td_fused_top_Block_entry_proc_proc505 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
outp... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP49028_accum1_out_0_memcore_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 3;
parameter MEM_SIZE = 8;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
inpu... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP49028_accum1_out_0_memcore (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd8;
parameter AddressWidth = 32'd3;
input reset;
input clk;
input... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP49028_ifmap_vec_0_0_memcore_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
in... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP49028_ifmap_vec_0_0_memcore (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
inp... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP49028_products_0_memcore_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
o... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP49028_products_0_memcore (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
q1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressW... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP49028_weight_vecs_0_0_0_memcore_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
d1,
we1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 6;
parameter MEM_SIZE = 64;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1... | 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP49028_weight_vecs_0_0_0_memcore (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1,
q1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd64;
parameter AddressWidth = 32'd6;
input reset;
inpu... | 6.827284 |
module td_fused_top_fifo_w12_d6_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd6;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output reg [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0... | 6.827284 |
module td_fused_top_fifo_w12_d6_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd6;
input clk;
input... | 6.827284 |
module td_fused_top_fifo_w16_d2_S_x0_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd16;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output reg [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-... | 6.827284 |
module td_fused_top_fifo_w16_d2_S_x0 (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd16;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
in... | 6.827284 |
module td_fused_top_fifo_w4_d2_S_x_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd4;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output reg [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0... | 6.827284 |
module td_fused_top_fifo_w4_d2_S_x (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd4;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input... | 6.827284 |
module td_fused_top_fifo_w6_d6_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd6;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd6;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output reg [DATA_WIDTH-1:0] q;
//reg[DATA_WIDTH-1:0]... | 6.827284 |
module td_fused_top_fifo_w6_d6_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd6;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd6;
input clk;
input r... | 6.827284 |
module td_fused_top_ap_hadd_0_full_dsp_16 (
input wire s_axis_a_tvalid,
input wire [15:0] s_axis_a_tdata,
input wire s_axis_b_tvalid,
input wire [15:0] s_axis_b_tdata,
output wire m_axis_result_tvalid,
output wire [15:0] m_axis_result_tdata
);
`ifdef complex_dsp
adde... | 6.827284 |
module td_fused_top_hadd_16ns_16ns_16_2_full_dsp_1 #(
parameter ID = 45,
NUM_STAGE = 2,
din0_WIDTH = 16,
din1_WIDTH = 16,
dout_WIDTH = 16
) (
input wire clk,
input wire reset,
input wire ... | 6.827284 |
module td_fused_top_ap_hmul_0_max_dsp_16 (
input wire s_axis_a_tvalid,
input wire [15:0] s_axis_a_tdata,
input wire s_axis_b_tvalid,
input wire [15:0] s_axis_b_tdata,
output wire m_axis_result_tvalid,
output wire [15:0] m_axis_result_tdata
);
`ifdef complex_dsp
multip... | 6.827284 |
module td_fused_top_hmul_16ns_16ns_16_2_max_dsp_1 #(
parameter ID = 31,
NUM_STAGE = 2,
din0_WIDTH = 16,
din1_WIDTH = 16,
dout_WIDTH = 16
) (
input wire clk,
input wire reset,
input wire ... | 6.827284 |
module FPMult_PrepModule (
clk,
rst,
a,
b,
Sa,
Sb,
Ea,
Eb,
Mp,
InputExc
);
// Input ports
input clk;
input rst;
input [`DWIDTH-1:0] a; // Input A, a 32-bit floating point number
input [`DWIDTH-1:0] b; // Input B, a 32-bit floating point number
// Output ports
ou... | 7.427166 |
module FPMult_NormalizeModule (
NormM,
NormE,
RoundE,
RoundEP,
RoundM,
RoundMP
);
// Input Ports
input [`MANTISSA-1:0] NormM; // Normalized mantissa
input [`EXPONENT:0] NormE; // Normalized exponent
// Output Ports
output [`EXPONENT:0] RoundE;
output [`EXPONENT:0] RoundEP;
outp... | 7.947312 |
module FPMult_RoundModule (
RoundM,
RoundMP,
RoundE,
RoundEP,
Sp,
GRS,
InputExc,
Z,
Flags
);
// Input Ports
input [`MANTISSA:0] RoundM; // Normalized mantissa
input [`MANTISSA:0] RoundMP; // Normalized exponent
input [`EXPONENT:0] RoundE; // Normalized mantissa + 1
inpu... | 7.570448 |
module is responsible for taking the inputs
// apart and checking the parts for exceptions.
// The exponent difference is also calculated in this module.
module FPAddSub_PrealignModule(
A,
B,
operation,
Sa,
Sb,
ShiftDet,
InputExc,
Aout,
Bout,
Opout
);
// Input ports
input [`DWIDTH-1... | 7.391888 |
module determines the larger input operand and
// sets the mantissas, shift and common exponent accordingly.
module FPAddSub_AlignModule (
A,
B,
ShiftDet,
CExp,
MaxAB,
Shift,
Mmin,
Mmax
);
// Input ports
input [`DWIDTH-2:0] A ; // Input A, a 32-bit floating point number
input [`DWIDTH... | 6.986217 |
module FPAddSub_AlignShift1 (
MminP,
Shift,
Mmin
);
// Input ports
input [`MANTISSA-1:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [2:0] Shift; // Shift amount
// Output ports
output [`MANTISSA:0] Mmin; // The smaller mantissa
// Internal signals
reg [ `MANTISSA:0] Lv... | 6.969233 |
module FPAddSub_AlignShift2 (
MminP,
Shift,
Mmin
);
// Input ports
input [`MANTISSA:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [1:0] Shift; // Shift amount
// Output ports
output [`MANTISSA:0] Mmin; // The smaller mantissa
// Internal Signal
reg [ `MANTISSA:0] Lvl3;... | 6.969233 |
module FPAddSub_ExecutionModule (
Mmax,
Mmin,
Sa,
Sb,
MaxAB,
OpMode,
Sum,
PSgn,
Opr
);
// Input ports
input [`MANTISSA-1:0] Mmax; // The larger mantissa
input [`MANTISSA:0] Mmin; // The smaller mantissa
input Sa; // Sign bit of larger number
input Sb; // Sign bit of sm... | 6.632792 |
module FPAddSub_NormalizeModule (
Sum,
Mmin,
Shift
);
// Input ports
input [`DWIDTH:0] Sum; // Mantissa sum including hidden 1 and GRS
// Output ports
output [`DWIDTH:0] Mmin; // Mantissa after 16|0 shift
output [4:0] Shift; // Shift amount
// Determine normalization shift amount by findin... | 6.905513 |
module FPAddSub_NormalizeShift1 (
MminP,
Shift,
Mmin
);
// Input ports
input [`DWIDTH:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [3:0] Shift; // Shift amount
// Output ports
output [`DWIDTH:0] Mmin; // The smaller mantissa
reg [ `DWIDTH:0] Lvl2;
wire [2*`DWIDTH+1... | 6.905513 |
module FPAddSub_NormalizeShift2 (
PSSum,
CExp,
Shift,
NormM,
NormE,
ZeroSum,
NegE,
R,
S,
FG
);
// Input ports
input [`DWIDTH:0] PSSum; // The Pre-Shift-Sum
input [`EXPONENT-1:0] CExp;
input [4:0] Shift; // Amount to be shifted
// Output ports
output [`MANTISSA-1:0... | 6.905513 |
module FPAddSub_RoundModule (
ZeroSum,
NormE,
NormM,
R,
S,
G,
Sa,
Sb,
Ctrl,
MaxAB,
Z,
EOF
);
// Input ports
input ZeroSum; // Sum is zero
input [`EXPONENT:0] NormE; // Normalized exponent
input [`MANTISSA-1:0] NormM; // Normalized mantissa
input R; // Round... | 7.753919 |
module FPAddSub_ExceptionModule (
Z,
NegE,
R,
S,
InputExc,
EOF,
P,
Flags
);
// Input ports
input [`DWIDTH-1:0] Z; // Final product
input NegE; // Negative exponent?
input R; // Round bit
input S; // Sticky bit
input [4:0] InputExc; // Exceptions in inputs A and B
inpu... | 7.326377 |
module
----------------------------------------------*/
module conv_op_sim
#(
parameter EW = 8,
parameter MW = 23,
parameter FW = 32
)
(
input clk_i,
input rstn_i,
input conv_en_i,
output reg conv_finish_o
);
localparam IDLE = 4'd0;
localparam CONV_STAG = 4'd1;
reg [ 4-1:0 ] STATE;
reg [ 8-1:0 ... | 8.593552 |
module with shift register
//
module conv_pe_sr#(parameter WIDTH = 9)
(
input clk,
input rst_n,
input [WIDTH-1:0] data_in,
input [WIDTH-1:0] weight_in,
output [2*WIDTH-1:0] data_out
);
reg [3:0] weight_counter;
reg [WIDTH-1:0] weight_buffer0;
reg [WIDTH-1:0] weight_buffer1;
reg [WIDTH-1:0] weight... | 7.567043 |
module conv_pe_sr_tb #(
parameter WIDTH = 9
);
reg clk;
reg rst_n;
reg [WIDTH-1:0] data_in;
reg [WIDTH-1:0] weight_in;
wire [2*WIDTH-1:0] data_out;
reg [6:0] clk_counter;
initial begin
clk = 1'b0;
rst_n = 1'b0;
#10 rst_n = 1'b1;
clk_counter = 6'b0;
end
always @(*) begin
... | 6.567531 |
module Conv_ReLu_MaxPool #(
parameter ConvKernel = 1
) (
input [71:0] inputData,
input inputValid,
input clk,
output [15:0] MP_Out,
output MPOut_valid
);
wire out_data_valid;
wire [71:0] out_data;
wire data_conv_valid;
wire [23:0] conv_data;
wire relu_data_valid_Out;
wire [15:0] relu... | 6.863812 |
module conv_top_tb ();
reg clk;
reg rst_n;
reg start;
reg [31:0] i_data;
reg i_valid;
reg d_type; // 0 for Input or 1 for Weight
wire [31:0] o_data;
wire o_valid;
wire finish;
reg [10:0] count;
initial begin
clk = 1;
rst_n =... | 7.005789 |
module conv_unit_testbench #(
parameter WIDTH = 9
);
reg clk;
reg rst_n;
reg [WIDTH-1:0] a0;
reg [WIDTH-1:0] a1;
reg [WIDTH-1:0] a2;
reg [WIDTH-1:0] a3;
reg [WIDTH-1:0] a4;
reg [WIDTH-1:0] a5;
reg [WIDTH-1:0] a6;
reg [WIDTH-1:0] a7;
reg [WIDTH-1:0] a8;
reg [WIDTH-1:0] b0;
reg [WIDTH-1:0]... | 6.727483 |
module Conv_unsign_sign #(
parameter bits = 16,
parameter filter_size = 25,
parameter filter_size_2 = 5
) (
//system clock
input clk_in,
input rst_n,
//feature map input & bias & weight
input sign... | 7.201648 |
module conv_weight_cache (
//--input
clk,
rst_n,
current_state,
// a signal to indicate the send state, eg. stop, hold or change the rom_addr
//--output
o_weight
);
parameter WIDTH = 32;
parameter KERNEL_SIZE = 3; //3x3
parameter IMAGE_SIZE = 8;
parameter ARRAY_SIZE = 6;
//para... | 8.626371 |
module CONV (
input clk,
input reset,
output reg busy,
input ready,
output wire [11:0] iaddr,
input [19:0] idata,
output reg cwr,
output wire [11:0] caddr_wr,
output reg [19:0] cdata_wr,
output reg crd,
output wire [11:0] caddr_rd,
input [19:0] cd... | 6.982921 |
module top_module (
input clk,
input load,
input [255:0] data,
output [255:0] q
);
reg [255:0] temp;
wire [287:0] map = {temp[15:0], temp, temp[255:240]};
int count;
always @(posedge clk) begin
if (load) begin
q <= data;
end else begin
for (int i = 16; i < 272; i = i + 1) b... | 7.203305 |
module conway (
clk,
rst,
addr_rd,
we_rd,
din,
addr_wr,
we_wr,
dout
);
input clk, rst;
input din;
output wire [11:0] addr_rd, addr_wr;
output wire we_rd, we_wr;
output reg dout;
/* States. At RD0, we read 0. At CK0 we check 0 and read 1. ...
* At CK7, we read the X positi... | 7.487445 |
module top_module (
input clk,
input load,
input [255:0] data,
output [255:0] q
);
reg [255:0] sreg;
assign q = sreg;
integer i, sum;
always @(posedge clk) begin
if (load) sreg <= data;
else begin
for (i = 0; i < 256; i++) begin
if (i == 0)
sum = sreg[1] + sreg... | 7.203305 |
module top_module (
input clk,
input load,
input [255:0] data,
output [255:0] q
);
wire [3:0] sum;
wire [15:0][0:15] mayukh;
wire [15:0][0:15] temp;
always @(*) begin
mayukh = q;
temp = q;
for (int i = 0; i < 16; i++) begin
for (int j = 0; j < 16; j++) begin
sum=( ma... | 7.203305 |
module top;
bus_master b1 (); //instantiate module unconditionally
`ifdef ADD_B2
bus_master b2 (); //b2 is instantiated conditionally if flag ADD_B2
//is set
`endif
endmodule
| 8.214046 |
module with delays
module bus_master;
initial
$display("Module %m instantiated");
endmodule
| 7.362331 |
module con_ff_logic (
input [1:0] in_condition,
input [31:0] in_bus,
input in_con_write,
input clk,
output out_branch
);
wire w_eq_zero;
wire w_neq_zero;
wire w_gte_zero;
wire w_lt_zero;
wire w_bus_reduce;
wire w_con_ff_d;
wire [31:0] w_con_ff_q; // This is just here so we dont get... | 7.459756 |
module con_signal (
input movea,
moveb,
movec,
input add,
sub,
and1,
not1,
rsr,
rsl,
input jmp,
jz,
zf,
jc,
cf,
in1,
out1,
nop,
halt,
input [7:0] ir,
input sm,
output reg [1:0] reg_ra,
reg_wa,
madd,
output reg [3:0] alu_s,
... | 7.523506 |
module Con_Synch_tb();
reg rst, clk;
reg cyc_i;
reg [31:0] dat_in;
wire ack_o;
reg [3:0] SNR;
wire [31:0] dat_out;
wire we_o, stb_o, cyc_o;
reg ack_i;
wire stb_i = cyc_i;
Con_Synch UUT(
.CLK_I(clk), .RST_I(rst),
.DAT_I(dat_in),
.CYC_I(cyc_i),
.STB_I(stb_i),
.ACK_O(ack_o),
.DAT_O(dat_out),
.WE_O... | 6.952556 |
module booth_2_unit (
A,
B,
PP
);
input [2:0] A;
input signed [15:0] B;
output reg signed [15:0] PP;
wire signed [15:0] B_not;
wire signed [15:0] B_shift;
wire signed [15:0] B_shift_not;
assign B_not = ~B;
assign B_shift = {B[14:0], 1'b0}; // left shift after adding signed-bit
assign B_... | 8.533561 |
module compressor_3to2_4 (
A_1,
A_2,
A_3,
Sum,
Carry
);
input [3:0] A_1, A_2, A_3;
output [3:0] Sum, Carry;
compressor_3to2 c3to2_0 (
A_1[0],
A_2[0],
A_3[0],
Sum[0],
Carry[0]
);
compressor_3to2 c3to2_1 (
A_1[1],
A_2[1],
A_3[1],
Sum[1],
... | 6.73183 |
module compressor_3to2_20 (
A_1,
A_2,
A_3,
Sum,
Carry
);
input [19:0] A_1, A_2, A_3;
output [19:0] Sum, Carry;
compressor_3to2_4 c3to2_4_0 (
A_1[3:0],
A_2[3:0],
A_3[3:0],
Sum[3:0],
Carry[3:0]
);
compressor_3to2_4 c3to2_4_1 (
A_1[7:4],
A_2[7:4],
... | 6.73183 |
module compressor_3to2 (
a,
b,
cin,
sum,
cout
);
input a, b, cin;
output sum, cout;
//assign s = a ^ b ^ c;
assign sum = a + b + cin;
assign cout = (a & b) + (a & cin) + (b & cin);
endmodule
| 6.73183 |
module booth_2_unit (
A,
B,
PP
);
input [2:0] A;
input signed [15:0] B;
output reg signed [15:0] PP;
wire signed [15:0] B_not;
wire signed [15:0] B_shift;
wire signed [15:0] B_shift_not;
assign B_not = ~B;
assign B_shift = {B[14:0], 1'b0}; // left shift after adding signed-bit
assign B_... | 8.533561 |
module compressor_3to2_4 (
A_1,
A_2,
A_3,
Sum,
Carry
);
input [3:0] A_1, A_2, A_3;
output [3:0] Sum, Carry;
compressor_3to2 c3to2_0 (
A_1[0],
A_2[0],
A_3[0],
Sum[0],
Carry[0]
);
compressor_3to2 c3to2_1 (
A_1[1],
A_2[1],
A_3[1],
Sum[1],
... | 6.73183 |
module compressor_3to2_20 (
A_1,
A_2,
A_3,
Sum,
Carry
);
input [19:0] A_1, A_2, A_3;
output [19:0] Sum, Carry;
compressor_3to2_4 c3to2_4_0 (
A_1[3:0],
A_2[3:0],
A_3[3:0],
Sum[3:0],
Carry[3:0]
);
compressor_3to2_4 c3to2_4_1 (
A_1[7:4],
A_2[7:4],
... | 6.73183 |
module compressor_3to2 (
a,
b,
cin,
sum,
cout
);
input a, b, cin;
output sum, cout;
//assign s = a ^ b ^ c;
assign sum = a + b + cin;
assign cout = (a & b) + (a & cin) + (b & cin);
endmodule
| 6.73183 |
module Add32_head(
// input [31:0]A,
// input [31:0]B,
// input C_in,
// output [31:0]Result,
// output C_out
// );
// wire [3:0]G;wire [3:0]P;
// assign G[3:2]=2'b00;
// assign P[3:2]=2'b00;
// Add16_head add16_low(
// .A(A[15:0]),
// .B(B[15:0]),
// .C_in(C_in),
// .F(Result[15:0]),
// .Gm(G[0]),
... | 7.044201 |
module Add16_head(
// input [15:0]A,
// input [15:0]B,
// input C_in,
// output [15:0] F,
// output Gm,
// output Pm,
// output C_out
// );
// wire [3:0]G;
// wire [3:0]P;
// wire [4:1]C;
// Add4_head A0(
// .A(A[3:0]),
// .B(B[3:0]),
// .C_in(C_in),
// .F(F[3:0]),
// .Gm(G[0]),
// .Pm(P[0])
//... | 6.685667 |
module Add4_head(
// input [3:0]A,
// input [3:0]B,
// input C_in,
// output [3:0]F,
// output Gm,
// output Pm,
// output C_out
// );
// wire [3:0] G;
// wire [3:0] P;
// wire [4:1] C;
// Add1 u1(
// .a(A[0]),
// .b(B[0]),
// .C_in(C_in),
// .f(F[0]),
// .g(G[0]),
// .p(P[0])
// );
// Add... | 7.809321 |
module CLA_4(
// input [3:0]P,
// input [3:0]G,
// input C_in,
// output [4:1]Ci,
// output Gm,
// output Pm
// );
// assign Ci[1]=G[0]|P[0]&C_in;
// assign Ci[2]=G[1]|P[1]&G[0]|P[1]&P[0]&C_in;
// assign Ci[3]=G[2]|P[2]&G[1]|P[2]&P[1]&G[0]|P[2]&P[1]&P[0]&C_in;
// assign Ci[4]=G[3]|P[3]&G[2]|P[3]&P[2]&G[1]|P... | 6.668406 |
module cookie #(
parameter COOKIE_LEN = 32
) (
input clk,
input rst_n,
input [95:0] time_stamp,
output reg [31:0] cookie_val
);
localparam COOKIE_BASE = 32'hf1ec234d;
wire [31:0] time_lsb;
reg [31:0] cycle_cnt;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
... | 7.834039 |
module CoolHeatSystem (
input arst, // reset [asynch]
input clk, // clock [posedge]
input [7:0] speed, // speed [duty-cycle]
input [7:0] chs_conf, // degree [temprature]
output [3:0] chs_power, // power [cooler/heater]
output chs_mode, // model [heat=1/cool=0]
outp... | 6.62859 |
module cooling(
//////////// ADC //////////
output ADC_CONVST,
output ADC_SCK,
output ADC_SDI,
input ADC_SDO,
//////////// CLOCK //////////
input FPGA_CLK1_50,
input FPGA_CLK2_50,
input FPGA_CLK3_50,
////////////... | 6.509779 |
module that counts the pixel coordinats as sample_pixel events occur.
*/
module coordinate_decoder(clk, sending_pixels, sample_pixel, x, y);
parameter Width = 96;
parameter Height = 64;
input clk, sending_pixels, sample_pixel;
output reg [$clog2(Width-1)-1:0] x;
output reg [$clog2(Height-1)-1:0] y;
always @(negedge ... | 6.764035 |
module Coordinator (
input RESET,
input EN,
input ISCL,
input DSCL,
inout DSDA,
inout ISDA,
output CACK,
output ENC,
output clkA,
output clkB,
input [7:0] PC,
output [15:0] INST,
output [7:0] DI,
input [7:0] DO,
input GCLK,
input IICING
);
wire c... | 7.432614 |
module CoordTrans (
cruiserx,
cruisery,
absquarex,
absquarey,
squarex,
squarey
);
input [6:0] cruiserx, cruisery, absquarex, absquarey;
output [8:0] squarex, squarey;
assign squarex = absquarex - cruiserx + 9'd64;
assign squarey = absquarey - cruisery + 9'd32;
endmodule
| 6.555543 |
module coord_gen (
input clk_i,
input rst_i,
input [ `ROW_SZ-1:0] start_row_i,
input coord_en_i,
output [`COORD_SZ-1:0] coord_o
);
reg next_row;
reg [`X_COORD_SZ-1:0] x_coord;
reg [`Y_COORD_SZ-1:0] y_coord; // x_coord and y_coor are 4 bits... | 6.655226 |
module coord_pl #(
parameter IP_BIT_WIDTH = 31
) (
input clk,
input rst,
input [IP_BIT_WIDTH-1:0] rand_num,
input rand_valid,
output reg op_lt_1_out,
output reg coord_valid_out
);
wire next_coord_sel;
wire... | 6.836235 |
module coord_to_ram #(
parameter NO_BANKS = 2,
COORDW = 16,
RAM_ADDR_WIDTH = 12,
NO_FFTS = 50,
FFT_SIZE = 256
) (
input wire clk,
input wire [COORDW-1:0] x, // 0 - 512
input wire [COORDW-1:0] y, // 0 -
input wire signed [$clog2(NO_FFTS)-1:0] OLDEST_FFT_IDX,
output reg [NO_BAN... | 6.890153 |
module transform #(
parameter HEIGHT = 525,
WIDTH = 525
) (
clk,
start,
t_height,
t_width,
x,
y,
cv_x,
cv_y
);
input clk, start;
input [10:0] t_width, x;
input [9:0] t_height, y;
output reg [12:0] cv_x;
output reg [12:0] cv_y;
reg [10:0] w_x_diff;
reg [ 9:0] h_y_di... | 6.883404 |
module runs through each x,y screen pixel (640 x 480) and calculates
// the associated values in x + iy mandelbrot space.
// It then passes these values to any calculating engine that is available to run the
// algorithm.
`include "mandel_constants.vh"
module Coor_gen
#( parameter C_ADDR_WIDTH )
(
input cclk,
... | 6.658559 |
module coor_trans_forward #(
parameter IMAGE_W = 1024,
parameter IMAGE_H = 768
) (
input clk,
input rst_n,
input signed [31:0] x_in,
input signed [31:0] y_in,
output signed [31:0] x_out,
output signed [31:0] y_out
);
assign x_out = x_in - IMAGE_W / 2;
assign y_out = IMAGE_H / 2 ... | 7.617622 |
module coor_trans_reverse #(
parameter IMAGE_W = 1024,
parameter IMAGE_H = 768
) (
input clk,
input rst_n,
input signed [31:0] x_in,
input signed [31:0] y_in,
output signed [31:0] x_out,
output signed [31:0] y_out
);
assign x_out = x_in + IMAGE_W / 2;
assign y_out = IMAGE_H / 2... | 7.280101 |
module coor_warper #(
parameter ROW = 4,
parameter COL = 6
) (
input start,
// Ports of Axi Master Bus Interface M_AXIS
input wire m_axis_aclk,
input wire m_axis_aresetn,
output reg m_axis_tvalid,
output reg [31 : 0] m_axis_tdata,
output reg m_axis_tlast,
input wire m_axis_tready... | 7.750545 |
module cop0 (
clk,
resetn,
stalled,
instr,
exception,
read_addr,
dest_addr,
fromcpu,
fromcpu_en,
tocpu,
tocpu_en,
epc_in,
ext_cause_in,
int_cause_in_stage1, //very weak - implement OR in SPREE instead
int_cause_in_stage2,
status,
badvaddr_in,
... | 6.731171 |
module cop2 (
clk,
resetn,
stalled,
fromcpu,
fromcpu_en,
tocpu,
tocpu_en,
//Global I/O
tocop2,
tocop2_en,
tocop2_wait,
fromcop2,
fromcop2_en,
fromcop2_wait
);
input clk;
input resetn;
output stalled;
input [31:0] fromcpu;
input fromcpu_en;
output [... | 7.323016 |
module Copier #(parameter addrBits = `ADDRESS_BITS, parameter dataBits = `DATA_BITS) (
// Section: operational I/Os
input wire clk,
input wire reset,
output wire finished,
// Section: memory I/Os
output wire [addrBits-1:0] readAddress,
output wi... | 6.844043 |
module copierDataMemory (
// This is the 64W x 32 data memory for the block copier.
//signals common to all local I/O devices:
input clock,
input [ 5:0] aq, //the CPU address queue output.
input read, //request in AQ is a read
input [31:0] wq, //the CPU wri... | 7.744478 |
module Copier_tb ();
parameter srcFile = "../programs/hexes/resume_untested.hex";
parameter dstFile = "zeroes.hex";
reg clk;
always #1 clk = clk !== 1'b1;
localparam addrBits = `ADDRESS_BITS;
localparam dataBits = `DATA_BITS;
wire [addrBits-1:0] readAddress;
wire [dataBits-1:0] readDataIn;
wire [da... | 7.137685 |
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