code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module convolutionTop #(
parameter filter_rows = 3,
parameter filter_cols = 3,
parameter image_rows = 32,
parameter image_cols = 32,
parameter depth = 16,
parameter image_addressWidth = 16,
parameter filterAddressWidth = 16,
parameter dataWidth = 16,
parameter imageFile = "G:\\RA\\BN... | 6.698582 |
module addr1 (
input clk,
input enable,
input signed [7:0] in2,
input signed [7:0] in4,
input signed [7:0] in5,
input signed [7:0] in6,
input signed [7:0] in8,
output reg signed [7:0] sum1,
output reg finished
);
//Remove Inputs that are 0 since adding them wont make a difference
... | 6.549846 |
module addr2 (
input clk,
input enable,
input signed [15:0] in1,
input signed [15:0] in2,
input signed [15:0] in3,
input signed [15:0] in4,
input signed [15:0] in5,
input signed [15:0] in6,
input signed [15:0] in7,
input signed [15:0] in8,
input signed [15:0] in9,
output ... | 6.70247 |
module MULTB (
input clk,
reset,
start,
input [7:0] A,
B,
output reg [15:0] result,
output reg done
);
always @(posedge clk) begin
if (reset || ~start) begin
done <= 0;
result <= 0;
end else if (start) begin
result <= A * B;
done <= 1;
end
end
endm... | 7.418018 |
module Convolution_example (
//Input Port
clk,
rst_n,
in_valid,
In_IFM_1,
In_IFM_2,
In_IFM_3,
In_IFM_4,
In_Weight_1,
In_Weight_2,
In_Weight_3,
In_Weight_4,
//Output Port
out_valid,
Out_OFM
);
//---------------------------------------------------------------... | 7.255272 |
module SRAM #(
parameter ADDR_WIDTH = 8,
DEPTH = 256
) (
input wire i_clk,
input wire [ADDR_WIDTH-1:0] i_addr,
input wire i_write,
input wire [31:0] i_data,
output reg [31:0] o_data
);
reg [31:0] memory_array[0:DEPTH-1];
always @(posedge i_clk) begin
if (i_write) begin
memory... | 7.897187 |
module conv_1x1_buffer (
clk,
reset,
valid_in,
in,
stride2,
out_buffer,
valid_out,
load_weights
);
/////////////////////////////////////////////////////////////////////////
// Parameter Declarations
parameter DATA_WIDTH = 32;
// Localparam TOP
parameter IMAGE_SIZE = 36; //... | 7.480355 |
module conv_1x1_buffer_weights_01 (
clk,
reset,
valid_in,
in,
load_weights,
out_buffer_weight,
valid_out
);
/////////////////////////////////////////////////////////////////////////
// Parameter Declarations
parameter DATA_WIDTH = 32;
//////////////////////////////////////////////... | 7.480355 |
module conv_1x1_buffer_weights_02 (
clk,
reset,
valid_in,
in,
load_weights,
out_buffer_weight,
valid_out
);
/////////////////////////////////////////////////////////////////////////
// Parameter Declarations
parameter DATA_WIDTH = 32;
//////////////////////////////////////////////... | 7.480355 |
module conv_1x1_buffer_weights_03 (
clk,
reset,
valid_in,
in,
load_weights,
out_buffer_weight,
valid_out
);
/////////////////////////////////////////////////////////////////////////
// Parameter Declarations
parameter DATA_WIDTH = 32;
//////////////////////////////////////////////... | 7.480355 |
module conv_1x1_buffer_weights_04_05_06_07_08 (
clk,
reset,
valid_in,
in,
load_weights,
out_buffer_weight,
valid_out
);
/////////////////////////////////////////////////////////////////////////
// Parameter Declarations
parameter DATA_WIDTH = 32;
//////////////////////////////////... | 7.480355 |
module conv_1x1_buffer_weights_09 (
clk,
reset,
valid_in,
in,
load_weights,
out_buffer_weight,
valid_out
);
/////////////////////////////////////////////////////////////////////////
// Parameter Declarations
parameter DATA_WIDTH = 32;
//////////////////////////////////////////////... | 7.480355 |
module conv_1x1_buffer_weights_10 (
clk,
reset,
valid_in,
in,
load_weights,
out_buffer_weight,
valid_out
);
/////////////////////////////////////////////////////////////////////////
// Parameter Declarations
parameter DATA_WIDTH = 32;
//////////////////////////////////////////////... | 7.480355 |
module conv_1x1_buffer_weights_11 (
clk,
reset,
valid_in,
in,
load_weights,
out_buffer_weight,
valid_out
);
/////////////////////////////////////////////////////////////////////////
// Parameter Declarations
parameter DATA_WIDTH = 32;
//////////////////////////////////////////////... | 7.480355 |
module conv_1x1_buffer_weights_12 (
clk,
reset,
valid_in,
in,
load_weights,
out_buffer_weight,
valid_out
);
/////////////////////////////////////////////////////////////////////////
// Parameter Declarations
parameter DATA_WIDTH = 32;
//////////////////////////////////////////////... | 7.480355 |
module conv_1x1_buffer_weights_13 (
clk,
reset,
valid_in,
in,
load_weights,
out_buffer_weight,
valid_out
);
/////////////////////////////////////////////////////////////////////////
// Parameter Declarations
parameter DATA_WIDTH = 32;
//////////////////////////////////////////////... | 7.480355 |
module conv_1x1_top_01 (
clk,
reset,
valid_in,
pxl_in,
valid_weight_in,
weight_in,
pxl_out,
valid_out
);
/////////////////////////////////////////////////////////////////////////
// Parameter Declarations
// General
parameter IMAGE_WIDTH = 64; //Width
parameter IMAGE_HEIGHT ... | 7.724608 |
module conv_1x1_top_02 (
clk,
reset,
valid_in,
pxl_in,
valid_weight_in,
weight_in,
pxl_out,
valid_out
);
/////////////////////////////////////////////////////////////////////////
// Parameter Declarations
// General
parameter IMAGE_WIDTH = 32; //Width
parameter IMAGE_HEIGHT ... | 7.724608 |
module conv_1x1_top_03 (
clk,
reset,
valid_in,
pxl_in,
valid_weight_in,
weight_in,
pxl_out,
valid_out
);
/////////////////////////////////////////////////////////////////////////
// Parameter Declarations
// General
parameter IMAGE_WIDTH = 16; //Width
parameter IMAGE_HEIGHT ... | 7.724608 |
module conv_1x1_top_04_05_06_07_08 (
clk,
reset,
valid_in,
pxl_in,
valid_weight_in,
weight_in,
pxl_out,
valid_out
);
/////////////////////////////////////////////////////////////////////////
// Parameter Declarations
// General
parameter IMAGE_WIDTH = 16; //Width
parameter I... | 7.724608 |
module conv_1x1_top_09 (
clk,
reset,
valid_in,
pxl_in,
valid_weight_in,
weight_in,
pxl_out,
valid_out
);
/////////////////////////////////////////////////////////////////////////
// Parameter Declarations
// General
parameter IMAGE_WIDTH = 16; //Width
parameter IMAGE_HEIGHT ... | 7.724608 |
module conv_1x1_top_10 (
clk,
reset,
valid_in,
pxl_in,
valid_weight_in,
weight_in,
pxl_out,
valid_out
);
/////////////////////////////////////////////////////////////////////////
// Parameter Declarations
// General
parameter IMAGE_WIDTH = 64; //Width
parameter IMAGE_HEIGHT ... | 7.724608 |
module conv_1x1_top_11 (
clk,
reset,
valid_in,
pxl_in,
valid_weight_in,
weight_in,
pxl_out,
valid_out
);
/////////////////////////////////////////////////////////////////////////
// Parameter Declarations
// General
parameter IMAGE_WIDTH = 64; //Width
parameter IMAGE_HEIGHT ... | 7.724608 |
module conv_1x1_top_12 (
clk,
reset,
valid_in,
pxl_in,
valid_weight_in,
weight_in,
pxl_out,
valid_out
);
/////////////////////////////////////////////////////////////////////////
// Parameter Declarations
// General
parameter IMAGE_WIDTH = 64; //Width
parameter IMAGE_HEIGHT ... | 7.724608 |
module conv_1x1_top_13 (
clk,
reset,
valid_in,
pxl_in,
valid_weight_in,
weight_in,
pxl_out,
valid_out
);
/////////////////////////////////////////////////////////////////////////
// Parameter Declarations
// General
parameter IMAGE_WIDTH = 64; //Width
parameter IMAGE_HEIGHT ... | 7.724608 |
module conv_217 #(
parameter m = 2,
parameter n = 7
) (
input clk,
rst_n,
ena,
input din, // bit 0 is to be sent first
output [m-1:0] cout
);
wire [n-1:0] g[m-1:0]; //should inverse bit for multiply
assign g[0][n-1:0] = 7'b110_110_1; //7'b1_011_011;
assign g[1][n-1:0] = 7'b100_111_... | 6.51548 |
module conv_2d #(
parameter CORE3X3_0 = 2'b01,
parameter CORE3X3_1 = 2'b10,
parameter CORE3X3_2 = 2'b11,
parameter CORE3X3_3 = 2'b01,
parameter CORE3X3_4 = 2'b10,
parameter CORE3X3_5 = 2'b11,
parameter CORE3X3_6 = 2'b01,
parameter CORE3X3_7 = 2'b10,
parameter CORE3X3_8 = 2'b11
) (
... | 7.876071 |
module conv_2d_tb ();
reg CLK;
reg RSTn;
reg read;
wire [7:0] CONV_OUT;
initial begin
CLK = 0;
forever #100 CLK = ~CLK;
end
initial begin
RSTn = 0;
#50 RSTn = 1;
read = 1;
end
conv_2d CONV (
.CLK(CLK),
.RSTn(RSTn),
.read(read),
.CONV_OUT(CONV_OUT)
);
... | 7.08213 |
module CELL_TYPE_CONST #(
parameter PARAM_WIDTH = 1,
parameter PARAM_INIT_VALUE = 0
) (
output [PARAM_WIDTH - 1 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = PARAM_INIT_VALUE;
endmodule
| 7.01637 |
module CELL_TYPE_MUL #(
parameter PARAM_WIDTH = 1
) (
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN0,
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN1,
output [PARAM_WIDTH - 1 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = PORT_ID_IN0 * PORT_ID_IN1;
endmodule
| 6.950653 |
module CELL_TYPE_NOT #(
parameter PARAM_WIDTH = 1
) (
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN,
output [PARAM_WIDTH - 1 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = ~PORT_ID_IN;
endmodule
| 7.229703 |
module CELL_TYPE_ADD #(
parameter PARAM_WIDTH = 1
) (
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN0,
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN1,
output [PARAM_WIDTH - 1 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = PORT_ID_IN0 + PORT_ID_IN1;
endmodule
| 6.940592 |
module CELL_TYPE_SUB #(
parameter PARAM_WIDTH = 1
) (
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN0,
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN1,
output [PARAM_WIDTH - 1 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = PORT_ID_IN0 - PORT_ID_IN1;
endmodule
| 6.840102 |
module CELL_TYPE_AND #(
parameter PARAM_WIDTH = 1
) (
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN0,
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN1,
output [PARAM_WIDTH - 1 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = PORT_ID_IN0 & PORT_ID_IN1;
endmodule
| 7.368723 |
module CELL_TYPE_LSHR #(
parameter PARAM_WIDTH = 1
) (
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN0,
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN1,
output [PARAM_WIDTH - 1 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = PORT_ID_IN0 >> PORT_ID_IN1;
endmodule
| 7.383756 |
module CELL_TYPE_ASHR #(
parameter PARAM_WIDTH = 1
) (
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN0,
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN1,
output [PARAM_WIDTH - 1 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = PORT_ID_IN0 >>> PORT_ID_IN1;
endmodule
| 7.452926 |
module CELL_TYPE_XOR #(
parameter PARAM_WIDTH = 1
) (
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN0,
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN1,
output [PARAM_WIDTH - 1 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = PORT_ID_IN0 ^ PORT_ID_IN1;
endmodule
| 6.893784 |
module CELL_TYPE_OR #(
parameter PARAM_WIDTH = 1
) (
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN0,
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN1,
output [PARAM_WIDTH - 1 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = PORT_ID_IN0 | PORT_ID_IN1;
endmodule
| 6.829625 |
module CELL_TYPE_EQ #(
parameter PARAM_WIDTH = 1
) (
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN0,
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN1,
output [0 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = PORT_ID_IN0 == PORT_ID_IN1;
endmodule
| 7.166867 |
module CELL_TYPE_NEQ #(
parameter PARAM_WIDTH = 1
) (
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN0,
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN1,
output [0 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = PORT_ID_IN0 != PORT_ID_IN1;
endmodule
| 6.879083 |
module CELL_TYPE_ULT #(
parameter PARAM_WIDTH = 1
) (
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN0,
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN1,
output [0 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = PORT_ID_IN0 < PORT_ID_IN1;
endmodule
| 6.579566 |
module CELL_TYPE_UGE #(
parameter PARAM_WIDTH = 1
) (
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN0,
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN1,
output [0 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = PORT_ID_IN0 >= PORT_ID_IN1;
endmodule
| 6.511793 |
module CELL_TYPE_REG #(
parameter PARAM_CLK_POSEDGE = 1,
parameter PARAM_INIT_VALUE = 0,
parameter PARAM_WIDTH = 1
) (
input PORT_ID_CLK,
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN,
output [PARAM_WIDTH - 1 : 0] PORT_ID_OUT
);
reg [PARAM_WIDTH - 1 : 0] data;
initial begin
data = PARAM_INIT_VA... | 7.94098 |
module CELL_TYPE_REG_ARST #(
parameter PARAM_CLK_POSEDGE = 1,
parameter PARAM_ARST_POSEDGE = 1,
parameter PARAM_INIT_VALUE = 0,
parameter PARAM_WIDTH = 1
) (
input PORT_ID_ARST,
input PORT_ID_CLK,
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN,
output [PARAM_WIDTH - 1 : 0] PORT_ID_OUT
);
reg [... | 7.94098 |
module CELL_TYPE_MEM #(
parameter PARAM_HAS_INIT = 0,
parameter PARAM_MEM_DEPTH = 2,
parameter PARAM_MEM_WIDTH = 2
) (
input PORT_ID_CLK,
input PORT_ID_WEN,
input [$clog2(PARAM_MEM_DEPTH) - 1 : 0] PORT_ID_RADDR,
input [$clog2(PARAM_MEM_DEPTH) - 1 : 0] PORT_ID_WADDR,
input [PARAM_MEM_WID... | 6.695867 |
module CELL_TYPE_MUX #(
parameter PARAM_WIDTH = 1
) (
input PORT_ID_SEL,
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN0,
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN1,
output [PARAM_WIDTH - 1 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = PORT_ID_SEL ? PORT_ID_IN1 : PORT_ID_IN0;
endmodule
| 7.597812 |
module CELL_TYPE_ORR #(
parameter PARAM_WIDTH = 1
) (
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN,
output [0 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = |PORT_ID_IN;
endmodule
| 6.754358 |
module CELL_TYPE_ANDR #(
parameter PARAM_WIDTH = 1
) (
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN,
output [0 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = &PORT_ID_IN;
endmodule
| 7.368723 |
module CELL_TYPE_PORT #(
parameter PARAM_PORT_TYPE = 0,
parameter PARAM_OUT_WIDTH = 1
) (
input [PARAM_OUT_WIDTH - 1 : 0] PORT_ID_IN,
output [PARAM_OUT_WIDTH - 1 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = PORT_ID_IN;
endmodule
| 7.188365 |
module CELL_TYPE_ZEXT #(
parameter PARAM_IN_WIDTH = 1,
parameter PARAM_OUT_WIDTH = 1
) (
input [ PARAM_IN_WIDTH - 1 : 0] PORT_ID_IN,
output [PARAM_OUT_WIDTH - 1 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = {{(PARAM_OUT_WIDTH - PARAM_IN_WIDTH) {1'b0}}, PORT_ID_IN};
endmodule
| 8.169785 |
module CELL_TYPE_SLICE #(
parameter PARAM_WIDTH = 1,
parameter PARAM_LOW = 1,
parameter PARAM_HIGH = 1
) (
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN,
output [PARAM_HIGH - PARAM_LOW - 1 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = PORT_ID_IN[PARAM_HIGH:PARAM_LOW];
endmodule
| 7.958967 |
module CELL_TYPE_PASSTHROUGH #(
parameter PARAM_WIDTH = 1
) (
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN,
output [PARAM_WIDTH - 1 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = PORT_ID_IN;
endmodule
| 7.047345 |
module CELL_TYPE_CONST #(
parameter PARAM_WIDTH = 1,
parameter PARAM_INIT_VALUE = 0
) (
output [PARAM_WIDTH - 1 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = PARAM_INIT_VALUE;
endmodule
| 7.01637 |
module CELL_TYPE_MUL #(
parameter PARAM_WIDTH = 1
) (
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN0,
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN1,
output [PARAM_WIDTH - 1 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = PORT_ID_IN0 * PORT_ID_IN1;
endmodule
| 6.950653 |
module CELL_TYPE_NOT #(
parameter PARAM_WIDTH = 1
) (
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN,
output [PARAM_WIDTH - 1 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = ~PORT_ID_IN;
endmodule
| 7.229703 |
module CELL_TYPE_ADD #(
parameter PARAM_WIDTH = 1
) (
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN0,
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN1,
output [PARAM_WIDTH - 1 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = PORT_ID_IN0 + PORT_ID_IN1;
endmodule
| 6.940592 |
module CELL_TYPE_SUB #(
parameter PARAM_WIDTH = 1
) (
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN0,
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN1,
output [PARAM_WIDTH - 1 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = PORT_ID_IN0 - PORT_ID_IN1;
endmodule
| 6.840102 |
module CELL_TYPE_AND #(
parameter PARAM_WIDTH = 1
) (
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN0,
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN1,
output [PARAM_WIDTH - 1 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = PORT_ID_IN0 & PORT_ID_IN1;
endmodule
| 7.368723 |
module CELL_TYPE_LSHR #(
parameter PARAM_WIDTH = 1
) (
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN0,
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN1,
output [PARAM_WIDTH - 1 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = PORT_ID_IN0 >> PORT_ID_IN1;
endmodule
| 7.383756 |
module CELL_TYPE_ASHR #(
parameter PARAM_WIDTH = 1
) (
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN0,
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN1,
output [PARAM_WIDTH - 1 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = PORT_ID_IN0 >>> PORT_ID_IN1;
endmodule
| 7.452926 |
module CELL_TYPE_XOR #(
parameter PARAM_WIDTH = 1
) (
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN0,
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN1,
output [PARAM_WIDTH - 1 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = PORT_ID_IN0 ^ PORT_ID_IN1;
endmodule
| 6.893784 |
module CELL_TYPE_OR #(
parameter PARAM_WIDTH = 1
) (
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN0,
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN1,
output [PARAM_WIDTH - 1 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = PORT_ID_IN0 | PORT_ID_IN1;
endmodule
| 6.829625 |
module CELL_TYPE_EQ #(
parameter PARAM_WIDTH = 1
) (
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN0,
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN1,
output [0 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = PORT_ID_IN0 == PORT_ID_IN1;
endmodule
| 7.166867 |
module CELL_TYPE_NEQ #(
parameter PARAM_WIDTH = 1
) (
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN0,
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN1,
output [0 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = PORT_ID_IN0 != PORT_ID_IN1;
endmodule
| 6.879083 |
module CELL_TYPE_ULT #(
parameter PARAM_WIDTH = 1
) (
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN0,
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN1,
output [0 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = PORT_ID_IN0 < PORT_ID_IN1;
endmodule
| 6.579566 |
module CELL_TYPE_UGE #(
parameter PARAM_WIDTH = 1
) (
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN0,
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN1,
output [0 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = PORT_ID_IN0 >= PORT_ID_IN1;
endmodule
| 6.511793 |
module CELL_TYPE_REG #(
parameter PARAM_CLK_POSEDGE = 1,
parameter PARAM_INIT_VALUE = 0,
parameter PARAM_WIDTH = 1
) (
input PORT_ID_CLK,
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN,
output [PARAM_WIDTH - 1 : 0] PORT_ID_OUT
);
reg [PARAM_WIDTH - 1 : 0] data;
initial begin
data = PARAM_INIT_VA... | 7.94098 |
module CELL_TYPE_REG_ARST #(
parameter PARAM_CLK_POSEDGE = 1,
parameter PARAM_ARST_POSEDGE = 1,
parameter PARAM_INIT_VALUE = 0,
parameter PARAM_WIDTH = 1
) (
input PORT_ID_ARST,
input PORT_ID_CLK,
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN,
output [PARAM_WIDTH - 1 : 0] PORT_ID_OUT
);
reg [... | 7.94098 |
module CELL_TYPE_MEM #(
parameter PARAM_HAS_INIT = 0,
parameter PARAM_MEM_DEPTH = 2,
parameter PARAM_MEM_WIDTH = 2
) (
input PORT_ID_CLK,
input PORT_ID_WEN,
input [$clog2(PARAM_MEM_DEPTH) - 1 : 0] PORT_ID_RADDR,
input [$clog2(PARAM_MEM_DEPTH) - 1 : 0] PORT_ID_WADDR,
input [PARAM_MEM_WID... | 6.695867 |
module CELL_TYPE_MUX #(
parameter PARAM_WIDTH = 1
) (
input PORT_ID_SEL,
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN0,
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN1,
output [PARAM_WIDTH - 1 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = PORT_ID_SEL ? PORT_ID_IN1 : PORT_ID_IN0;
endmodule
| 7.597812 |
module CELL_TYPE_ORR #(
parameter PARAM_WIDTH = 1
) (
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN,
output [0 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = |PORT_ID_IN;
endmodule
| 6.754358 |
module CELL_TYPE_ANDR #(
parameter PARAM_WIDTH = 1
) (
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN,
output [0 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = &PORT_ID_IN;
endmodule
| 7.368723 |
module CELL_TYPE_PORT #(
parameter PARAM_PORT_TYPE = 0,
parameter PARAM_OUT_WIDTH = 1
) (
input [PARAM_OUT_WIDTH - 1 : 0] PORT_ID_IN,
output [PARAM_OUT_WIDTH - 1 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = PORT_ID_IN;
endmodule
| 7.188365 |
module CELL_TYPE_ZEXT #(
parameter PARAM_IN_WIDTH = 1,
parameter PARAM_OUT_WIDTH = 1
) (
input [ PARAM_IN_WIDTH - 1 : 0] PORT_ID_IN,
output [PARAM_OUT_WIDTH - 1 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = {{(PARAM_OUT_WIDTH - PARAM_IN_WIDTH) {1'b0}}, PORT_ID_IN};
endmodule
| 8.169785 |
module CELL_TYPE_SLICE #(
parameter PARAM_WIDTH = 1,
parameter PARAM_LOW = 1,
parameter PARAM_HIGH = 1
) (
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN,
output [PARAM_HIGH - PARAM_LOW - 1 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = PORT_ID_IN[PARAM_HIGH:PARAM_LOW];
endmodule
| 7.958967 |
module CELL_TYPE_PASSTHROUGH #(
parameter PARAM_WIDTH = 1
) (
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN,
output [PARAM_WIDTH - 1 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = PORT_ID_IN;
endmodule
| 7.047345 |
module conv_adder #(
parameter GROUP_CHANNEL = 16,
parameter BW_CONV1x1 = 2 * `BITWIDTH + 4,
parameter BW_BIAS = BW_CONV1x1 + 4 + 1
) (
input signed [9*BW_CONV1x1-1:0] add_in,
input signed [`BITWIDTH-1:0] bias,
input [`BW_FL-1:0] ftr_fl, // input feature map fractional length (fl)
input [`B... | 7.603986 |
module: conv_adic
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module conv_adic_tb;
// Inputs
reg CLK;
reg RST;
reg [9:0] deci1;
reg [9:0] deci2;
reg [9:0] decp1;
reg [9:0] decp2... | 6.830073 |
module conv_apb (
input wire PCLK, // APB clock
input wire PRESETB, // APB asynchronous reset (0: reset, 1: normal)
input wire [31:0] PADDR, // APB address
input wire PSEL, // APB select
input wire PENABLE, // APB enable
input wire PWRITE, ... | 6.804277 |
module conv_blk_tb #(
parameter KERNEL_SIZE = 3,
parameter FM_SIZE = 252,
parameter PADDING = 0,
parameter STRIDE = 1,
parameter MAXPOOL = 0,
localparam OUT_SIZE = ((FM_SIZE - KERNEL_SIZE + 2 * PADDING) / STRIDE) + 1
) ();
reg i_clk, i_rst, i_go, weight_en;
wire w_o_en;
wire signed [48-1:... | 7.158575 |
module conv_block #
(
parameter integer
kernel_size = 2,
data_width = 4,
data_height = 4,
point_width = 8
)
(
input wire clock,
input wire reset,
input wire start,
input wire [0:point_width*data_width*data_height-1] data,
input wire [0:point_width*k... | 7.211961 |
module CELL_TYPE_CONST #(
parameter PARAM_WIDTH = 1,
parameter PARAM_INIT_VALUE = 0
) (
output [PARAM_WIDTH - 1 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = PARAM_INIT_VALUE;
endmodule
| 7.01637 |
module CELL_TYPE_MUL #(
parameter PARAM_WIDTH = 1
) (
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN0,
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN1,
output [PARAM_WIDTH - 1 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = PORT_ID_IN0 * PORT_ID_IN1;
endmodule
| 6.950653 |
module CELL_TYPE_NOT #(
parameter PARAM_WIDTH = 1
) (
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN,
output [PARAM_WIDTH - 1 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = ~PORT_ID_IN;
endmodule
| 7.229703 |
module CELL_TYPE_ADD #(
parameter PARAM_WIDTH = 1
) (
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN0,
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN1,
output [PARAM_WIDTH - 1 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = PORT_ID_IN0 + PORT_ID_IN1;
endmodule
| 6.940592 |
module CELL_TYPE_SUB #(
parameter PARAM_WIDTH = 1
) (
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN0,
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN1,
output [PARAM_WIDTH - 1 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = PORT_ID_IN0 - PORT_ID_IN1;
endmodule
| 6.840102 |
module CELL_TYPE_AND #(
parameter PARAM_WIDTH = 1
) (
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN0,
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN1,
output [PARAM_WIDTH - 1 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = PORT_ID_IN0 & PORT_ID_IN1;
endmodule
| 7.368723 |
module CELL_TYPE_LSHR #(
parameter PARAM_WIDTH = 1
) (
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN0,
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN1,
output [PARAM_WIDTH - 1 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = PORT_ID_IN0 >> PORT_ID_IN1;
endmodule
| 7.383756 |
module CELL_TYPE_ASHR #(
parameter PARAM_WIDTH = 1
) (
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN0,
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN1,
output [PARAM_WIDTH - 1 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = PORT_ID_IN0 >>> PORT_ID_IN1;
endmodule
| 7.452926 |
module CELL_TYPE_XOR #(
parameter PARAM_WIDTH = 1
) (
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN0,
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN1,
output [PARAM_WIDTH - 1 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = PORT_ID_IN0 ^ PORT_ID_IN1;
endmodule
| 6.893784 |
module CELL_TYPE_OR #(
parameter PARAM_WIDTH = 1
) (
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN0,
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN1,
output [PARAM_WIDTH - 1 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = PORT_ID_IN0 | PORT_ID_IN1;
endmodule
| 6.829625 |
module CELL_TYPE_EQ #(
parameter PARAM_WIDTH = 1
) (
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN0,
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN1,
output [0 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = PORT_ID_IN0 == PORT_ID_IN1;
endmodule
| 7.166867 |
module CELL_TYPE_NEQ #(
parameter PARAM_WIDTH = 1
) (
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN0,
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN1,
output [0 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = PORT_ID_IN0 != PORT_ID_IN1;
endmodule
| 6.879083 |
module CELL_TYPE_ULT #(
parameter PARAM_WIDTH = 1
) (
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN0,
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN1,
output [0 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = PORT_ID_IN0 < PORT_ID_IN1;
endmodule
| 6.579566 |
module CELL_TYPE_UGE #(
parameter PARAM_WIDTH = 1
) (
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN0,
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN1,
output [0 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = PORT_ID_IN0 >= PORT_ID_IN1;
endmodule
| 6.511793 |
module CELL_TYPE_REG #(
parameter PARAM_CLK_POSEDGE = 1,
parameter PARAM_INIT_VALUE = 0,
parameter PARAM_WIDTH = 1
) (
input PORT_ID_CLK,
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN,
output [PARAM_WIDTH - 1 : 0] PORT_ID_OUT
);
reg [PARAM_WIDTH - 1 : 0] data;
initial begin
data = PARAM_INIT_VA... | 7.94098 |
module CELL_TYPE_REG_ARST #(
parameter PARAM_CLK_POSEDGE = 1,
parameter PARAM_ARST_POSEDGE = 1,
parameter PARAM_INIT_VALUE = 0,
parameter PARAM_WIDTH = 1
) (
input PORT_ID_ARST,
input PORT_ID_CLK,
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN,
output [PARAM_WIDTH - 1 : 0] PORT_ID_OUT
);
reg [... | 7.94098 |
module CELL_TYPE_MEM #(
parameter PARAM_HAS_INIT = 0,
parameter PARAM_MEM_DEPTH = 2,
parameter PARAM_MEM_WIDTH = 2
) (
input PORT_ID_CLK,
input PORT_ID_WEN,
input [$clog2(PARAM_MEM_DEPTH) - 1 : 0] PORT_ID_RADDR,
input [$clog2(PARAM_MEM_DEPTH) - 1 : 0] PORT_ID_WADDR,
input [PARAM_MEM_WID... | 6.695867 |
module CELL_TYPE_MUX #(
parameter PARAM_WIDTH = 1
) (
input PORT_ID_SEL,
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN0,
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN1,
output [PARAM_WIDTH - 1 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = PORT_ID_SEL ? PORT_ID_IN1 : PORT_ID_IN0;
endmodule
| 7.597812 |
module CELL_TYPE_ORR #(
parameter PARAM_WIDTH = 1
) (
input [PARAM_WIDTH - 1 : 0] PORT_ID_IN,
output [0 : 0] PORT_ID_OUT
);
assign PORT_ID_OUT = |PORT_ID_IN;
endmodule
| 6.754358 |
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