code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module COMP4to2_3 (
X1,
X2,
X3,
X4,
Sum,
Carry,
Cin_BAR,
Cout_BAR
);
input X1, X2, X3, X4, Cin_BAR;
output Sum, Carry, Cout_BAR;
wire Cin, n2, n3, n4, n5;
assign Cin = Cin_BAR;
XOR2_X1 U1 (
.A1(X1),
.A2(X2),
.Z (n2)
);
AOI22_X1 U2 (
.A1(X1),
.... | 7.447748 |
module COMP4to2_4 (
X1,
X2,
X3,
X4,
Sum,
Carry,
Cin_BAR,
Cout_BAR
);
input X1, X2, X3, X4, Cin_BAR;
output Sum, Carry, Cout_BAR;
wire Cin, n2, n3, n4, n5;
assign Cin = Cin_BAR;
XOR2_X1 U1 (
.A1(X1),
.A2(X2),
.Z (n2)
);
AOI22_X1 U2 (
.A1(X1),
.... | 7.469665 |
module COMP4to2_5 (
X1,
X2,
X3,
X4,
Sum,
Carry,
Cin_BAR,
Cout_BAR
);
input X1, X2, X3, X4, Cin_BAR;
output Sum, Carry, Cout_BAR;
wire Cin, n2, n3, n4, n5;
assign Cin = Cin_BAR;
XOR2_X1 U1 (
.A1(X1),
.A2(X2),
.Z (n2)
);
AOI22_X1 U2 (
.A1(X1),
.... | 7.299536 |
module COMP4to2_7 (
X1,
X2,
X3,
X4,
Cout,
Sum,
Carry,
Cin_BAR
);
input X1, X2, X3, X4, Cin_BAR;
output Cout, Sum, Carry;
wire Cin, n1, n2, n3, n4, n5;
assign Cin = Cin_BAR;
XOR2_X1 U1 (
.A1(X1),
.A2(X2),
.Z (n2)
);
AOI22_X1 U2 (
.A1(X1),
.A2(X... | 6.968554 |
module COMP4to2_9 (
X1,
X2,
X3,
X4,
Cout,
Sum,
Carry,
Cin_BAR
);
input X1, X2, X3, X4, Cin_BAR;
output Cout, Sum, Carry;
wire Cin, n1, n2, n3, n4, n5;
assign Cin = Cin_BAR;
XOR2_X1 U1 (
.A1(X1),
.A2(X2),
.Z (n2)
);
AOI22_X1 U2 (
.A1(X1),
.A2(X... | 6.530048 |
module FA_4 (
A,
B,
CI,
CO,
S
);
input A, B, CI;
output CO, S;
wire n1, n2;
XOR2_X1 U1 (
.A1(A),
.A2(B),
.Z (n2)
);
AOI22_X1 U2 (
.A1(A),
.A2(B),
.B1(n2),
.B2(CI),
.ZN(n1)
);
INV_X1 U3 (
.I (n1),
.ZN(CO)
);
XOR2_X1 U4 (... | 6.626139 |
module AND2_0 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.420626 |
module AND2_1 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.595903 |
module AND2_2 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.948015 |
module AND2_3 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.570512 |
module AND2_4 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.779641 |
module AND2_5 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.939218 |
module AND2_6 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.701088 |
module AND2_7 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.456289 |
module AND2_8 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.811418 |
module AND2_9 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.884729 |
module AND2_10 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.486296 |
module AND2_11 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.443228 |
module AND2_12 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.990184 |
module AND2_13 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.522602 |
module AND2_14 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.558896 |
module AND2_15 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.821494 |
module AND2_16 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.975484 |
module AND2_17 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.742214 |
module AND2_18 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.602137 |
module AND2_19 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.685614 |
module AND2_20 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.950668 |
module AND2_21 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.110455 |
module AND2_22 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.778983 |
module AND2_24 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.619801 |
module AND2_25 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 8.053899 |
module AND2_26 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.038308 |
module AND2_27 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.477153 |
module AND2_28 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.161566 |
module AND2_29 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.096193 |
module AND2_32 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.707741 |
module AND2_33 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.67428 |
module AND2_34 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.072859 |
module AND2_35 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.434487 |
module AND2_36 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.353443 |
module AND2_40 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.663086 |
module AND2_41 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.253745 |
module AND2_42 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.866662 |
module AND2_43 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.733255 |
module AND2_48 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.984819 |
module AND2_49 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.820852 |
module AND2_50 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.527647 |
module AND2_56 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.93103 |
module AND2_48 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.984819 |
module COMP4to2_7 (
X1,
X2,
X3,
X4,
Cin,
Sum,
Carry,
Cout_BAR
);
input X1, X2, X3, X4, Cin;
output Sum, Carry, Cout_BAR;
wire N9, n3, n4;
assign Carry = N9;
XOR2_X1 U1 (
.A1(X1),
.A2(X2),
.Z (n3)
);
AOI22_X1 U2 (
.A1(X1),
.A2(X2),
.B1(n3... | 6.968554 |
module COMP4to2_6 (
X1,
X2,
X3,
X4,
Cout,
Sum,
Carry,
Cin_BAR
);
input X1, X2, X3, X4, Cin_BAR;
output Cout, Sum, Carry;
wire Cin, n1, n2, n3, n4, n5;
assign Cin = Cin_BAR;
XOR2_X1 U1 (
.A1(X1),
.A2(X2),
.Z (n2)
);
AOI22_X1 U2 (
.A1(X1),
.A2(X... | 7.196782 |
module COMP4to2_5 (
X1,
X2,
X3,
X4,
Cin,
Cout,
Sum,
Carry
);
input X1, X2, X3, X4, Cin;
output Cout, Sum, Carry;
wire N7, n2, n3, n4;
assign Carry = N7;
XOR2_X1 U1 (
.A1(X1),
.A2(X2),
.Z (n3)
);
AOI22_X1 U2 (
.A1(X1),
.A2(X2),
.B1(n3),
... | 7.299536 |
module COMP4to2_0 (
X1,
X2,
X3,
X4,
Cout,
Sum,
Carry,
Cin_BAR
);
input X1, X2, X3, X4, Cin_BAR;
output Cout, Sum, Carry;
wire Cin, n1, n2, n3, n4, n5;
assign Cin = Cin_BAR;
XOR2_X1 U1 (
.A1(X1),
.A2(X2),
.Z (n2)
);
AOI22_X1 U2 (
.A1(X1),
.A2(X... | 7.327846 |
module COMP4to2_1 (
X1,
X2,
X3,
X4,
Sum,
Carry,
Cin_BAR,
Cout_BAR
);
input X1, X2, X3, X4, Cin_BAR;
output Sum, Carry, Cout_BAR;
wire Cin, n2, n3, n4, n5;
assign Cin = Cin_BAR;
XOR2_X1 U1 (
.A1(X1),
.A2(X2),
.Z (n2)
);
AOI22_X1 U2 (
.A1(X1),
.... | 7.480044 |
module COMP4to2_2 (
X1,
X2,
X3,
X4,
Sum,
Carry,
Cin_BAR,
Cout_BAR
);
input X1, X2, X3, X4, Cin_BAR;
output Sum, Carry, Cout_BAR;
wire Cin, n2, n3, n4, n5;
assign Cin = Cin_BAR;
XOR2_X1 U1 (
.A1(X1),
.A2(X2),
.Z (n2)
);
AOI22_X1 U2 (
.A1(X1),
.... | 7.455477 |
module COMP4to2_3 (
X1,
X2,
X3,
X4,
Cin,
Sum,
Carry_BAR,
Cout_BAR
);
input X1, X2, X3, X4, Cin;
output Sum, Carry_BAR, Cout_BAR;
wire n2, n3, n4;
XOR2_X1 U1 (
.A1(X1),
.A2(X2),
.Z (n2)
);
AOI22_X1 U2 (
.A1(X1),
.A2(X2),
.B1(n2),
.B2(... | 7.447748 |
module COMP4to2_4 (
X1,
X2,
X3,
X4,
Cin,
Cout,
Sum,
Carry
);
input X1, X2, X3, X4, Cin;
output Cout, Sum, Carry;
wire N9, n2, n3, n4;
assign Carry = N9;
XOR2_X1 U1 (
.A1(X1),
.A2(X2),
.Z (n3)
);
AOI22_X1 U2 (
.A1(X1),
.A2(X2),
.B1(n3),
... | 7.469665 |
module AND2_0 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.420626 |
module AND2_1 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.595903 |
module AND2_2 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.948015 |
module AND2_3 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.570512 |
module AND2_4 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.779641 |
module AND2_5 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.939218 |
module AND2_6 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.701088 |
module AND2_8 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.811418 |
module AND2_9 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.884729 |
module AND2_10 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.486296 |
module AND2_11 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.443228 |
module AND2_12 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.990184 |
module AND2_13 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.522602 |
module AND2_16 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.975484 |
module AND2_17 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.742214 |
module AND2_18 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.602137 |
module AND2_19 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.685614 |
module AND2_20 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.950668 |
module AND2_24 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.619801 |
module AND2_25 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 8.053899 |
module AND2_26 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.038308 |
module AND2_27 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.477153 |
module AND2_32 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.707741 |
module AND2_33 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.67428 |
module AND2_34 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.072859 |
module AND2_40 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.663086 |
module AND2_41 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.253745 |
module dadda8_CLA (
input [ 7:0] A,
input [ 7:0] B,
input [15:0] M,
output [16:0] RES
);
genvar i;
wire [7:0][ 7:0] P;
wire [1:0][15:0] PRE;
gen_part_products U1 (
A,
B,
P
);
dadda_processing_block_8 U2 (
P,
M,
PRE
);
CLA16 adder16_CLA (
.sum... | 7.403718 |
module dadda8_RCA (
input [ 7:0] A,
input [ 7:0] B,
input [15:0] M,
output [16:0] RES
);
genvar i;
wire [7:0][ 7:0] P;
wire [1:0][15:0] PRE;
gen_part_products U1 (
A,
B,
P
);
dadda_processing_block_8 U2 (
P,
M,
PRE
);
RCA16 adder16_CLA (
.sum... | 7.167701 |
module dadda8_CSelA (
input [ 7:0] A,
input [ 7:0] B,
input [15:0] M,
output [16:0] RES
);
genvar i;
wire [7:0][ 7:0] P;
wire [1:0][15:0] PRE;
gen_part_products U1 (
A,
B,
P
);
dadda_processing_block_8 U2 (
P,
M,
PRE
);
CSelA16 adder16_CLA (
... | 6.795344 |
module dadda8_CSkipA (
input [ 7:0] A,
input [ 7:0] B,
input [15:0] M,
output [16:0] RES
);
genvar i;
wire [7:0][ 7:0] P;
wire [1:0][15:0] PRE;
gen_part_products U1 (
A,
B,
P
);
dadda_processing_block_8 U2 (
P,
M,
PRE
);
CSkipA16 adder16_CLA (
... | 6.707236 |
module dadda8_KSA (
input [ 7:0] A,
input [ 7:0] B,
input [15:0] M,
output [16:0] RES
);
genvar i;
wire [7:0][ 7:0] P;
wire [1:0][15:0] PRE;
gen_part_products U1 (
A,
B,
P
);
dadda_processing_block_8 U2 (
P,
M,
PRE
);
KSA16 adder16_CLA (
.sum... | 7.156138 |
module dadda16_RCA (
input [15:0] A,
B,
output [32:0] prod
);
wire pp[15:0][15:0];
wire [31:0] to_FA[1:0];
generate_partial_products_16 pp1 (
.x(A),
.y(B),
.p(pp)
);
dadda_processing_block_16 mul1 (
.pp(pp),
.to_FA(to_FA)
);
RCA32 cla1 (
.sum(prod[31:0]),
... | 6.747092 |
module dadda_multiplier_32_tb;
reg [15:0] in0;
reg [15:0] in1;
output [31:0] product;
output [31:0] chk_product;
dadda_multiplier_32 dadda0 (
in0,
in1,
product
);
assign chk_product = in0 * in1;
initial begin
in0 = 3;
in1 = 2;
#5 in0 = 15;
#5 in1 = 5;
#5 in0 = 10;
... | 6.503721 |
module AND2_63 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 6.991603 |
module HA_5 (
A,
B,
CO,
S
);
input A, B;
output CO, S;
AND2_X1 U1 (
.A1(B),
.A2(A),
.Z (CO)
);
XOR2_X1 U2 (
.A1(B),
.A2(A),
.Z (S)
);
endmodule
| 7.160208 |
module COMP4to2_6 (
X1,
X2,
X3,
X4,
Cin,
Sum,
Carry,
Cout_BAR
);
input X1, X2, X3, X4, Cin;
output Sum, Carry, Cout_BAR;
wire n2, n3, n4, n5, n6;
XOR2_X1 U1 (
.A1(X1),
.A2(X2),
.Z (n2)
);
AOI22_X1 U2 (
.A1(X1),
.A2(X2),
.B1(n2),
.B2(... | 7.196782 |
module COMP4to2_0 (
X1,
X2,
X3,
X4,
Cout,
Sum,
Carry,
Cin_BAR
);
input X1, X2, X3, X4, Cin_BAR;
output Cout, Sum, Carry;
wire Cin, n1, n2, n3, n4, n5;
assign Cin = Cin_BAR;
XOR2_X1 U1 (
.A1(X1),
.A2(X2),
.Z (n2)
);
AOI22_X1 U2 (
.A1(X1),
.A2(X... | 7.327846 |
module COMP4to2_1 (
X1,
X2,
X3,
X4,
Sum,
Carry,
Cin_BAR,
Cout_BAR
);
input X1, X2, X3, X4, Cin_BAR;
output Sum, Carry, Cout_BAR;
wire Cin, n2, n3, n4, n5;
assign Cin = Cin_BAR;
XOR2_X1 U1 (
.A1(X1),
.A2(X2),
.Z (n2)
);
AOI22_X1 U2 (
.A1(X1),
.... | 7.480044 |
module COMP4to2_2 (
X1,
X2,
X3,
X4,
Sum,
Carry,
Cin_BAR,
Cout_BAR
);
input X1, X2, X3, X4, Cin_BAR;
output Sum, Carry, Cout_BAR;
wire Cin, n2, n3, n4, n5;
assign Cin = Cin_BAR;
XOR2_X1 U1 (
.A1(X1),
.A2(X2),
.Z (n2)
);
AOI22_X1 U2 (
.A1(X1),
.... | 7.455477 |
module COMP4to2_3 (
X1,
X2,
X3,
X4,
Sum,
Carry,
Cin_BAR,
Cout_BAR
);
input X1, X2, X3, X4, Cin_BAR;
output Sum, Carry, Cout_BAR;
wire Cin, n2, n3, n4, n5;
assign Cin = Cin_BAR;
XOR2_X1 U1 (
.A1(X1),
.A2(X2),
.Z (n2)
);
AOI22_X1 U2 (
.A1(X1),
.... | 7.447748 |
module COMP4to2_4 (
X1,
X2,
X3,
X4,
Sum,
Carry,
Cin_BAR,
Cout_BAR
);
input X1, X2, X3, X4, Cin_BAR;
output Sum, Carry, Cout_BAR;
wire Cin, n2, n3, n4, n5;
assign Cin = Cin_BAR;
XOR2_X1 U1 (
.A1(X1),
.A2(X2),
.Z (n2)
);
AOI22_X1 U2 (
.A1(X1),
.... | 7.469665 |
module COMP4to2_5 (
X1,
X2,
X3,
X4,
Sum,
Carry,
Cin_BAR,
Cout_BAR
);
input X1, X2, X3, X4, Cin_BAR;
output Sum, Carry, Cout_BAR;
wire Cin, n2, n3, n4, n5;
assign Cin = Cin_BAR;
XOR2_X1 U1 (
.A1(X1),
.A2(X2),
.Z (n2)
);
AOI22_X1 U2 (
.A1(X1),
.... | 7.299536 |
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