code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module is originally from this repo:
// https://github.com/emard/ulx3s-misc/tree/master/examples/audio/hdl
// combines resistor DAC and PWM
// upper bits using DAC, lower bit using PWM
module dacpwm
#(
parameter C_pcm_bits = 12, // input: how many bits PCM (including sign bit)
parameter C_dac_bits = 4 // output:... | 7.798353 |
module DACSimple (
Clk,
loaddac,
resdac,
sel_dac,
DACout,
dac_val
); //, restest);
input Clk;
input resdac;
input loaddac;
input sel_dac;
output DACout;
output [7:0] dac_val;
reg [7:0] Accum; // for optimum performance, ensure that this ff is in IOB
wire [8:0] Sum;
reg ... | 7.069138 |
module dacspi_tb ();
reg rst_n, clk;
reg [15:0] wr_data;
reg wr;
wire spi_cs_n, spi_sclk, spi_sdout;
initial begin
rst_n = 1;
clk = 0;
wr_data = 16'b1010_0110_1100_1101;
wr = 0;
end
always #1 clk <= ~clk;
initial begin
#4 rst_n = 0;
#4 rst_n = 1;
#4 wr = 1;
#4... | 6.860371 |
module mux_16x4 (
in,
sel,
out
);
input wire [15:0] in;
input wire [1:0] sel;
output wire [3:0] out;
wire [3:0] w0 = {in[15], in[11], in[7], in[3]};
mux_4x1 m0 (
.in (w0[3:0]),
.sel(sel[1:0]),
.out(out[3])
);
wire [3:0] w1 = {in[14], in[10], in[6], in[2]};
mux_4x1 m1 (
... | 7.032216 |
module mux_8x1 (
in,
sel,
out
);
input wire [7:0] in;
input wire [2:0] sel;
output wire out;
wire [1:0] bus;
mux_4x1 m1 (
.in (in[7:4]),
.sel(sel[1:0]),
.out(bus[1])
);
mux_4x1 m2 (
.in (in[3:0]),
.sel(sel[1:0]),
.out(bus[0])
);
//the input wires must ... | 7.358788 |
module mux_4x1 (
in,
sel,
out
);
input wire [3:0] in;
input wire [1:0] sel;
output reg out;
always @(in or sel)
case (sel)
2'b00: out <= in[3]; //the input wires must be parsed backwards
2'b01: out <= in[2];
2'b10: out <= in[1];
2'b11: out <= in[0];
default... | 8.288733 |
module dac_5390 (
output wire ready_o,
output wire [4:0] dac_spi_o,
//output wire [63:0] check_o,
//output wire [7:0] id,
input wire busy_i,
input wire clk_i,
input wire reset_i,
input wire dac_reset_i,
input wire [23:0] data_i,
//input wire [3:0] cmd_i,
input wire cmdtrig_i,... | 6.86843 |
module dactest;
// Inputs
reg clock;
reg clockenable;
reg [0:11] datos;
// Outputs
wire mosi;
wire daccs;
wire sck;
wire dacclr;
// Instantiate the Unit Under Test (UUT)
dac uut (
.clock(clock),
.clockenable(clockenable),
.datos(datos),
.mosi(mosi),
.daccs(daccs),
... | 6.68398 |
module DAC_8BIT (
`ifdef USE_POWER_PINS
input wire vdd, // User area 1 1.8V supply
input wire gnd, // User area 1 digital ground
`endif
input wire d0,
input wire d1,
input wire d2,
input wire d3,
input wire d4,
input wire d5,
input wire d6,
input wire d7,
input wire inp1,
... | 8.333302 |
module: DAC_AD5668_Interface
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module dac_ad5668_interface_tb;
// Inputs
reg CLK;
reg [15:0] v_dac_a;
reg [15:0] v_dac_b;
reg [15:0] v_da... | 6.638411 |
module dac_cells #(
parameter width = 16
) (
input clk,
input [width-1:0] data0,
input [width-1:0] data1,
output [width-1:0] dac
);
wire rst = 0;
wire set = 0;
wire ce = 1;
genvar ix;
generate
for (ix = 0; ix < width; ix = ix + 1) begin : out_cell
// Xilinx XST 12.1 tells me SRT... | 8.714182 |
module dac_cells_5d (
input clk,
input [13:0] data0,
input [13:0] data1,
output [13:0] dacp,
output [13:0] dacn
);
wire rst = 0;
wire set = 0;
wire ce = 1;
wire [13:0] dac_se;
genvar ix;
generate
for (ix = 0; ix < 14; ix = ix + 1) begin : out_cell
// Use the SAME_EDGE feature ... | 7.114776 |
module dac_clk_src (
clk,
rst,
nck,
pck
);
input wire clk, rst;
output reg pck, nck;
always @(posedge clk, negedge rst) begin
if (!rst) begin
pck <= 1'b0;
nck <= 1'b0;
end else begin
pck <= ~pck;
nck <= pck;
end
end
endmodule
| 7.93397 |
module DAC_CONTROL (
input [15:0] data_in,
input clk,
input rst,
output reg data_out,
output reg cs
);
//bit counter
reg [4:0] bit_counter;
//to help with shifting
reg [15:0] shifter;
reg [15:0] shifter_hold;
//to add extra clock cycle
reg read_in;
//to prevent from over counting... | 7.427834 |
module dac_conver_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull
);
input aclr;
input [23:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [23:0] q;
output rdempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys trans... | 7.228298 |
module dac_ctrl_fsm ();
reg [15:0] dac0_pdin, dac1_pdin, dac2_pdin, dac3_pdin;
always @(negedge reset or posedge sclk)
if (~reset) begin
bitcnt <= 8'h0;
state <= st_IDLE;
end else
case (state)
st_IDLE: begin
bitcnt <= 8'h0;
if (ap_start) state <= st_UPDATE;... | 6.771963 |
module dac_data_coding (
reset,
reg_addr,
clk,
data_out
);
input reset;
input [2:0] reg_addr;
input clk;
//input [9:0] data_in;
output [3:0] data_out;
wire reset;
wire [2:0] reg_addr;
wire clk;
//wire [9:0] data_in;
reg [3:0] data_out;
always @(negedge reset or posedge clk) begin... | 7.237517 |
module dac_delay (
input clkcomm,
input clk200,
input RST,
output [5:0] DA1,
output [5:0] DA2,
input [5:0] da1_nd,
input [5:0] da2_nd
);
generate
genvar g;
for (g = 0; g < 6; g = g + 1) begin : GENERATE_DAC_DELAY
IODELAY #(
.REFCLK_FREQUENCY(200.0),
.O... | 6.82255 |
module
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module dac_driver_module(reset, clk, hv_start, dac_dout, ... | 7.088073 |
module: DAC_drive
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module DAC_drive_tb;
// Inputs
reg clk;
reg [11:0] x_in;
reg [11:0] y_in;
reg start;
reg laser_rgb;
// Outputs
wi... | 6.502157 |
module dac_fifo #(
parameter ADDR_WIDTH = "mandatory",
parameter DATA_WIDTH = "mandatory",
parameter EMPTY_CONSTANT = (2 ** ADDR_WIDTH) / 4
) (
input clk,
input resetn,
// write port a
input write_enable,
output reg ... | 8.986117 |
module dac_fm (
m_clk,
b_clk,
dac_lr_clk,
dacdat
);
input m_clk, b_clk, dac_lr_clk, dacdat;
task measuresclk;
real frequency_m, frequency_b, frequency_lr;
begin
fork
begin
mesura_m_clk(frequency_m);
mesura_b_clk(frequency_b);
mesura_dac_lr_clk(f... | 7.427658 |
module dac_fsm #(
parameter DATA_WIDTH = "mandatory",
parameter SAMP_DAC = "mandatory"
) (
input clk,
input resetn,
input empty,
input ready,
input [DATA_WIDTH-1:0] bit_frame_number,
//Output C... | 7.911409 |
module DAC_interface_APB (
CLK,
RST,
PWRITE,
PSEL,
PENABLE,
PREADY,
PADDR,
PWDATA,
PSTRB,
DATA,
PRDATA
);
//----general--input----
input CLK, RST, PWRITE, PSEL, PENABLE;
//----general--output----
output wire PREADY;
//----write--input----
input [31:0] PADDR, PWDA... | 7.805746 |
module dac_phy (
input wire clk,
input wire reset,
input wire [11:0] data_i,
input wire [11:0] data_q,
output wire [11:0] dac_data,
output wire dac_clk
);
ODDR #(
.DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE"
.INIT (1'b0), // Initi... | 7.150042 |
module DAC_PWM (
input clk_in,
input RST,
input signed [31:0] data_in,
output DAC_PWM
);
parameter MAIN_FRE = 500;
localparam FRE_WORD = 32'd2147483648 / MAIN_FRE;
reg [31:0] addr_r = 0;
always @(posedge clk_in) begin
if (RST) begin
addr_r... | 7.202563 |
module dac_seq_crt (
clk,
rst,
cmd,
pck,
nck,
sync,
scl,
sdo,
ldac,
drst
);
input wire clk, rst, pck, nck;
input wire [23:0] cmd;
output reg sync, scl, sdo, ldac, drst;
reg [1:0] st;
parameter [1:0] s0 = 2'd0, s1 = 2'd1, s2 = 2'd2;
always @(posedge clk, negedge rst... | 7.663872 |
module dac_source_register (
input clk,
input rst,
input we,
input source_in,
output reg source_out
);
always @(posedge clk) begin
if (rst) source_out <= 1'b0;
else if (we) source_out <= source_in;
end
endmodule
| 6.807755 |
module dac_source_sel (
input select,
input [11:0] rv,
input [11:0] wg,
output [11:0] pwm
);
assign pwm = select ? wg : rv;
endmodule
| 7.033228 |
module DAC_SPI_Out #(
parameter CLOCK_COUNT = 4'd5
) // number of internal clock events between each SPI clock transition
(
input wire i_Clock,
input wire i_Reset,
input wire [23:0] i_Data,
input wire i_Send,
output reg o_SPI_CS,
output wire o_SPI_Clock,
output reg o_SPI_Data,
outpu... | 8.463166 |
module DAC_SRAM (
clka,
wea,
addra,
dina,
douta,
clkb,
web,
addrb,
dinb,
doutb
);
input clka;
input [0 : 0] wea;
input [9 : 0] addra;
input [7 : 0] dina;
output [7 : 0] douta;
input clkb;
input [0 : 0] web;
input [7 : 0] addrb;
input [31 : 0] dinb;
output [31... | 7.226951 |
module DAC_SRAM (
address_a,
address_b,
clock_a,
clock_b,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b
);
input [9:0] address_a;
input [7:0] address_b;
input clock_a;
input clock_b;
input [7:0] data_a;
input [31:0] data_b;
input wren_a;
input wren_b;
output [7:0] q... | 7.226951 |
module dac_start_generator (
input clk, //dac clock expected
input reset, //dac reset expected
input start, //the start signal synced to dac clock expected
input trigger, //the trigger synced to dac clock to look for before setting dac_start high, usually the reset pulse (ie when integrator reset ... | 6.794679 |
module: dac_start_generator
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module dac_start_generator_tb;
// Inputs
reg clk;
reg reset;
reg start;
reg trigger;
// Outputs
wire dac... | 7.764017 |
module DAC_test (
input CLK_24M,
output [7:0] VGA_R,
output [7:0] VGA_G,
output [7:0] VGA_B
);
// VGA DAC tester
reg [23:0] TEMP;
reg [ 2:0] TEST_COLOR;
always @(posedge CLK_24M) begin
TEMP <= TEMP + 1'b1;
if (TEMP >= 24'd12000000) begin
TEMP <= 24'd0;
TEST_COLOR <= TEST_COL... | 7.3912 |
module dac_tester (
SCK,
SDI,
CS_,
SDO
); //Width of SPI Peripheral
input SCK;
input SDI;
input CS_;
output SDO;
reg SDO;
integer i, j;
reg [ 7:0] ControlReg;
reg [15:0] DataReg;
reg [15:0] ChanAData, ChanBData;
initial begin
SDO = 0;
ControlReg = 0;
ChanAData = 0;
... | 6.73196 |
module dadda4 (
Z,
A,
B
);
input [3:0] B;
input [3:0] A;
output [7:0] Z;
wire [7:0] S;
wire [7:0] C;
wire [6:0] carry;
// generate the partial products.
and pp1 (N0_0_0, A[0], B[0]);
and pp2 (N0_0_1, A[1], B[0]);
and pp3 (N0_0_2, A[2], B[0]);
and pp4 (N0_0_3, A[3], B[0]);
and pp5 ... | 6.65369 |
module AND2_61 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.067643 |
module HA_2 (
A,
B,
CO,
S
);
input A, B;
output CO, S;
AND2_X1 U1 (
.A1(B),
.A2(A),
.Z (CO)
);
XOR2_X1 U2 (
.A1(B),
.A2(A),
.Z (S)
);
endmodule
| 7.228961 |
module COMP4to2_17 (
X1,
X2,
X3,
X4,
Cin,
Sum,
Carry,
Cout_BAR
);
input X1, X2, X3, X4, Cin;
output Sum, Carry, Cout_BAR;
wire N7, n3, n4;
assign Carry = N7;
XOR2_X1 U1 (
.A1(X1),
.A2(X2),
.Z (n3)
);
AOI22_X1 U2 (
.A1(X1),
.A2(X2),
.B1(n... | 7.282062 |
module COMP4to2_16 (
X1,
X2,
X3,
X4,
Sum,
Carry,
Cin_BAR,
Cout_BAR
);
input X1, X2, X3, X4, Cin_BAR;
output Sum, Carry, Cout_BAR;
wire Cin, n2, n3, n4, n5;
assign Cin = Cin_BAR;
XOR2_X1 U1 (
.A1(X1),
.A2(X2),
.Z (n2)
);
AOI22_X1 U2 (
.A1(X1),
... | 7.125313 |
module COMP4to2_0 (
X1,
X2,
X3,
X4,
Cout,
Sum,
Carry,
Cin_BAR
);
input X1, X2, X3, X4, Cin_BAR;
output Cout, Sum, Carry;
wire Cin, n1, n2, n3, n4, n5;
assign Cin = Cin_BAR;
XOR2_X1 U1 (
.A1(X1),
.A2(X2),
.Z (n2)
);
AOI22_X1 U2 (
.A1(X1),
.A2(X... | 7.327846 |
module COMP4to2_1 (
X1,
X2,
X3,
X4,
Sum,
Carry,
Cin_BAR,
Cout_BAR
);
input X1, X2, X3, X4, Cin_BAR;
output Sum, Carry, Cout_BAR;
wire Cin, n2, n3, n4, n5;
assign Cin = Cin_BAR;
XOR2_X1 U1 (
.A1(X1),
.A2(X2),
.Z (n2)
);
AOI22_X1 U2 (
.A1(X1),
.... | 7.480044 |
module COMP4to2_2 (
X1,
X2,
X3,
X4,
Sum,
Carry,
Cin_BAR,
Cout_BAR
);
input X1, X2, X3, X4, Cin_BAR;
output Sum, Carry, Cout_BAR;
wire Cin, n2, n3, n4, n5;
assign Cin = Cin_BAR;
XOR2_X1 U1 (
.A1(X1),
.A2(X2),
.Z (n2)
);
AOI22_X1 U2 (
.A1(X1),
.... | 7.455477 |
module COMP4to2_3 (
X1,
X2,
X3,
X4,
Sum,
Carry,
Cin_BAR,
Cout_BAR
);
input X1, X2, X3, X4, Cin_BAR;
output Sum, Carry, Cout_BAR;
wire Cin, n2, n3, n4, n5;
assign Cin = Cin_BAR;
XOR2_X1 U1 (
.A1(X1),
.A2(X2),
.Z (n2)
);
AOI22_X1 U2 (
.A1(X1),
.... | 7.447748 |
module COMP4to2_4 (
X1,
X2,
X3,
X4,
Sum,
Carry,
Cin_BAR,
Cout_BAR
);
input X1, X2, X3, X4, Cin_BAR;
output Sum, Carry, Cout_BAR;
wire Cin, n2, n3, n4, n5;
assign Cin = Cin_BAR;
XOR2_X1 U1 (
.A1(X1),
.A2(X2),
.Z (n2)
);
AOI22_X1 U2 (
.A1(X1),
.... | 7.469665 |
module COMP4to2_5 (
X1,
X2,
X3,
X4,
Sum,
Carry,
Cin_BAR,
Cout_BAR
);
input X1, X2, X3, X4, Cin_BAR;
output Sum, Carry, Cout_BAR;
wire Cin, n2, n3, n4, n5;
assign Cin = Cin_BAR;
XOR2_X1 U1 (
.A1(X1),
.A2(X2),
.Z (n2)
);
AOI22_X1 U2 (
.A1(X1),
.... | 7.299536 |
module COMP4to2_6 (
X1,
X2,
X3,
X4,
Sum,
Carry,
Cin_BAR,
Cout_BAR
);
input X1, X2, X3, X4, Cin_BAR;
output Sum, Carry, Cout_BAR;
wire Cin, n2, n3, n4, n5;
assign Cin = Cin_BAR;
XOR2_X1 U1 (
.A1(X1),
.A2(X2),
.Z (n2)
);
AOI22_X1 U2 (
.A1(X1),
.... | 7.196782 |
module COMP4to2_7 (
X1,
X2,
X3,
X4,
Sum,
Carry,
Cin_BAR,
Cout_BAR
);
input X1, X2, X3, X4, Cin_BAR;
output Sum, Carry, Cout_BAR;
wire Cin, n2, n3, n4, n5;
assign Cin = Cin_BAR;
XOR2_X1 U1 (
.A1(X1),
.A2(X2),
.Z (n2)
);
AOI22_X1 U2 (
.A1(X1),
.... | 6.968554 |
module COMP4to2_8 (
X1,
X2,
X3,
X4,
Sum,
Carry,
Cin_BAR,
Cout_BAR
);
input X1, X2, X3, X4, Cin_BAR;
output Sum, Carry, Cout_BAR;
wire Cin, n2, n3, n4, n5;
assign Cin = Cin_BAR;
XOR2_X1 U1 (
.A1(X1),
.A2(X2),
.Z (n2)
);
AOI22_X1 U2 (
.A1(X1),
.... | 6.68837 |
module COMP4to2_9 (
X1,
X2,
X3,
X4,
Cin,
Sum,
Carry,
Cout_BAR
);
input X1, X2, X3, X4, Cin;
output Sum, Carry, Cout_BAR;
wire n2, n3, n4, n5, n6;
XOR2_X1 U1 (
.A1(X1),
.A2(X2),
.Z (n2)
);
AOI22_X1 U2 (
.A1(X1),
.A2(X2),
.B1(n2),
.B2(... | 6.530048 |
module COMP4to2_10 (
X1,
X2,
X3,
X4,
Cout,
Sum,
Carry,
Cin_BAR
);
input X1, X2, X3, X4, Cin_BAR;
output Cout, Sum, Carry;
wire Cin, n1, n2, n3, n4, n5;
assign Cin = Cin_BAR;
XOR2_X1 U1 (
.A1(X1),
.A2(X2),
.Z (n2)
);
AOI22_X1 U2 (
.A1(X1),
.A2(... | 7.310682 |
module COMP4to2_11 (
X1,
X2,
X3,
X4,
Sum,
Carry,
Cin_BAR,
Cout_BAR
);
input X1, X2, X3, X4, Cin_BAR;
output Sum, Carry, Cout_BAR;
wire Cin, n2, n3, n4, n5;
assign Cin = Cin_BAR;
XOR2_X1 U1 (
.A1(X1),
.A2(X2),
.Z (n2)
);
AOI22_X1 U2 (
.A1(X1),
... | 6.530062 |
module COMP4to2_13 (
X1,
X2,
X3,
X4,
Sum,
Carry,
Cin_BAR,
Cout_BAR
);
input X1, X2, X3, X4, Cin_BAR;
output Sum, Carry, Cout_BAR;
wire Cin, n2, n3, n4, n5;
assign Cin = Cin_BAR;
XOR2_X1 U1 (
.A1(X1),
.A2(X2),
.Z (n2)
);
AOI22_X1 U2 (
.A1(X1),
... | 6.703995 |
module COMP4to2_15 (
X1,
X2,
X3,
X4,
Sum,
Carry,
Cin_BAR,
Cout_BAR
);
input X1, X2, X3, X4, Cin_BAR;
output Sum, Carry, Cout_BAR;
wire Cin, n2, n3, n4, n5;
assign Cin = Cin_BAR;
XOR2_X1 U1 (
.A1(X1),
.A2(X2),
.Z (n2)
);
AOI22_X1 U2 (
.A1(X1),
... | 7.470939 |
module COMP4to2_12 (
X1,
X2,
X3,
X4,
Cin,
Cout,
Sum,
Carry
);
input X1, X2, X3, X4, Cin;
output Cout, Sum, Carry;
wire N7, n2, n3, n4;
assign Carry = N7;
XOR2_X1 U1 (
.A1(X1),
.A2(X2),
.Z (n3)
);
AOI22_X1 U2 (
.A1(X1),
.A2(X2),
.B1(n3),
... | 7.291934 |
module COMP4to2_14 (
X1,
X2,
X3,
X4,
Cin,
Cout,
Sum,
Carry
);
input X1, X2, X3, X4, Cin;
output Cout, Sum, Carry;
wire N7, n2, n3, n4;
assign Carry = N7;
XOR2_X1 U1 (
.A1(X1),
.A2(X2),
.Z (n3)
);
AOI22_X1 U2 (
.A1(X1),
.A2(X2),
.B1(n3),
... | 7.437358 |
module HA_0 (
A,
B,
CO,
S
);
input A, B;
output CO, S;
AND2_X1 U1 (
.A1(B),
.A2(A),
.Z (CO)
);
XOR2_X1 U2 (
.A1(B),
.A2(A),
.Z (S)
);
endmodule
| 6.608558 |
module HA_1 (
A,
B,
CO,
S
);
input A, B;
output CO, S;
AND2_X1 U1 (
.A1(B),
.A2(A),
.Z (CO)
);
XOR2_X1 U2 (
.A1(B),
.A2(A),
.Z (S)
);
endmodule
| 7.223383 |
module AND2_0 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.420626 |
module AND2_1 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.595903 |
module AND2_2 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.948015 |
module AND2_3 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.570512 |
module AND2_4 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.779641 |
module AND2_5 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.939218 |
module AND2_6 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.701088 |
module AND2_7 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.456289 |
module AND2_8 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.811418 |
module AND2_9 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.884729 |
module AND2_10 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.486296 |
module AND2_11 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.443228 |
module AND2_12 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.990184 |
module AND2_13 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.522602 |
module AND2_14 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.558896 |
module AND2_15 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.821494 |
module AND2_16 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.975484 |
module AND2_17 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.742214 |
module AND2_18 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.602137 |
module AND2_19 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.685614 |
module AND2_20 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.950668 |
module AND2_21 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.110455 |
module AND2_22 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.778983 |
module AND2_23 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.5039 |
module AND2_24 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.619801 |
module AND2_25 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 8.053899 |
module AND2_26 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.038308 |
module AND2_27 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.477153 |
module AND2_28 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.161566 |
module AND2_29 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.096193 |
module AND2_30 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.021831 |
module AND2_31 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 6.896828 |
module AND2_32 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.707741 |
module AND2_33 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.67428 |
module AND2_34 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.072859 |
module AND2_35 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.434487 |
module AND2_36 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.353443 |
module AND2_37 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.945882 |
module AND2_38 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.695829 |
module AND2_39 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.243499 |
module AND2_40 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.663086 |
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