code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module AND2_57 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.8828 |
module AND2_58 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.766942 |
module AND2_59 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.027072 |
module AND2_60 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.361265 |
module AND2_61 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.067643 |
module AND2_62 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.60295 |
module fa_df (
input a,
b,
cin,
output sum,
cout
);
assign sum = a ^ b ^ cin;
assign cout = (a & b) | (cin & (a ^ b));
endmodule
| 6.889194 |
module ha_df (
input a,
b,
output sum,
cout
);
assign sum = a ^ b;
assign cout = a & b;
endmodule
| 8.302286 |
module Half_Adder (
input wire in1,
input wire in2,
output wire sum,
output wire cout
);
xor (sum, in1, in2);
and (cout, in1, in2);
endmodule
| 7.558237 |
module Half_Adder (
input wire in1,
input wire in2,
output wire sum,
output wire cout
);
xor (sum, in1, in2);
and (cout, in1, in2);
endmodule
| 7.558237 |
module half_adder (
output wire sum,
output wire cout,
input wire in1,
input wire in2
);
xor (sum, in1, in2);
and (cout, in1, in2);
endmodule
| 6.966406 |
module CLA_25 (
output [24:0] sum,
output cout,
input [24:0] in1,
input [24:0] in2
);
wire [24:0] G;
wire [24:0] C;
wire [24:0] P;
assign G[0] = in1[24] & in2[24];
assign P[0] = in1[24] ^ in2[24];
assign G[1] = in1[23] & in2[23];
assign P[1] = in1[23] ^ in2[23];
assign G[2] = in1[... | 6.529114 |
module CLA_24 (
output [23:0] sum,
output cout,
input [23:0] in1,
input [23:0] in2
);
wire [23:0] G;
wire [23:0] C;
wire [23:0] P;
assign G[0] = in1[23] & in2[23];
assign P[0] = in1[23] ^ in2[23];
assign G[1] = in1[22] & in2[22];
assign P[1] = in1[22] ^ in2[22];
assign G[2] = in1[... | 6.530348 |
module CLA_23 (
output [22:0] sum,
output cout,
input [22:0] in1,
input [22:0] in2
);
wire [22:0] G;
wire [22:0] C;
wire [22:0] P;
assign G[0] = in1[22] & in2[22];
assign P[0] = in1[22] ^ in2[22];
assign G[1] = in1[21] & in2[21];
assign P[1] = in1[21] ^ in2[21];
assign G[2] = in1[... | 6.702242 |
module CLA_22 (
output [21:0] sum,
output cout,
input [21:0] in1,
input [21:0] in2
);
wire [21:0] G;
wire [21:0] C;
wire [21:0] P;
assign G[0] = in1[21] & in2[21];
assign P[0] = in1[21] ^ in2[21];
assign G[1] = in1[20] & in2[20];
assign P[1] = in1[20] ^ in2[20];
assign G[2] = in1[... | 6.674363 |
module CLA_20 (
output [19:0] sum,
output cout,
input [19:0] in1,
input [19:0] in2
);
wire [19:0] G;
wire [19:0] C;
wire [19:0] P;
assign G[0] = in1[19] & in2[19];
assign P[0] = in1[19] ^ in2[19];
assign G[1] = in1[18] & in2[18];
assign P[1] = in1[18] ^ in2[18];
assign G[2] = in1[... | 6.880941 |
module CLA_18 (
output [17:0] sum,
output cout,
input [17:0] in1,
input [17:0] in2
);
wire [17:0] G;
wire [17:0] C;
wire [17:0] P;
assign G[0] = in1[17] & in2[17];
assign P[0] = in1[17] ^ in2[17];
assign G[1] = in1[16] & in2[16];
assign P[1] = in1[16] ^ in2[16];
assign G[2] = in1[... | 6.528946 |
module CLA_17 (
output [16:0] sum,
output cout,
input [16:0] in1,
input [16:0] in2
);
wire [16:0] G;
wire [16:0] C;
wire [16:0] P;
assign G[0] = in1[16] & in2[16];
assign P[0] = in1[16] ^ in2[16];
assign G[1] = in1[15] & in2[15];
assign P[1] = in1[15] ^ in2[15];
assign G[2] = in1[... | 6.575661 |
module CLA_16 (
output [15:0] sum,
output cout,
input [15:0] in1,
input [15:0] in2
);
wire [15:0] G;
wire [15:0] C;
wire [15:0] P;
assign G[0] = in1[15] & in2[15];
assign P[0] = in1[15] ^ in2[15];
assign G[1] = in1[14] & in2[14];
assign P[1] = in1[14] ^ in2[14];
assign G[2] = in1[... | 6.903294 |
module CLA_15 (
output [14:0] sum,
output cout,
input [14:0] in1,
input [14:0] in2
);
wire [14:0] G;
wire [14:0] C;
wire [14:0] P;
assign G[0] = in1[14] & in2[14];
assign P[0] = in1[14] ^ in2[14];
assign G[1] = in1[13] & in2[13];
assign P[1] = in1[13] ^ in2[13];
assign G[2] = in1[... | 6.959698 |
module CLA_14 (
output [13:0] sum,
output cout,
input [13:0] in1,
input [13:0] in2
);
wire [13:0] G;
wire [13:0] C;
wire [13:0] P;
assign G[0] = in1[13] & in2[13];
assign P[0] = in1[13] ^ in2[13];
assign G[1] = in1[12] & in2[12];
assign P[1] = in1[12] ^ in2[12];
assign G[2] = in1[... | 6.986577 |
module CLA_13 (
output [12:0] sum,
output cout,
input [12:0] in1,
input [12:0] in2
);
wire [12:0] G;
wire [12:0] C;
wire [12:0] P;
assign G[0] = in1[12] & in2[12];
assign P[0] = in1[12] ^ in2[12];
assign G[1] = in1[11] & in2[11];
assign P[1] = in1[11] ^ in2[11];
assign G[2] = in1[... | 6.891116 |
module CLA_12 (
output [11:0] sum,
output cout,
input [11:0] in1,
input [11:0] in2
);
wire [11:0] G;
wire [11:0] C;
wire [11:0] P;
assign G[0] = in1[11] & in2[11];
assign P[0] = in1[11] ^ in2[11];
assign G[1] = in1[10] & in2[10];
assign P[1] = in1[10] ^ in2[10];
assign G[2] = in1[... | 7.264929 |
module CLA_11 (
output [10:0] sum,
output cout,
input [10:0] in1,
input [10:0] in2
);
wire [10:0] G;
wire [10:0] C;
wire [10:0] P;
assign G[0] = in1[10] & in2[10];
assign P[0] = in1[10] ^ in2[10];
assign G[1] = in1[9] & in2[9];
assign P[1] = in1[9] ^ in2[9];
assign G[2] = in1[8] &... | 7.191184 |
module CLA_10 (
output [9:0] sum,
output cout,
input [9:0] in1,
input [9:0] in2
);
wire [9:0] G;
wire [9:0] C;
wire [9:0] P;
assign G[0] = in1[9] & in2[9];
assign P[0] = in1[9] ^ in2[9];
assign G[1] = in1[8] & in2[8];
assign P[1] = in1[8] ^ in2[8];
assign G[2] = in1[7] & in2[7];
assi... | 7.307011 |
module CLA_9 (
output [8:0] sum,
output cout,
input [8:0] in1,
input [8:0] in2
);
wire [8:0] G;
wire [8:0] C;
wire [8:0] P;
assign G[0] = in1[8] & in2[8];
assign P[0] = in1[8] ^ in2[8];
assign G[1] = in1[7] & in2[7];
assign P[1] = in1[7] ^ in2[7];
assign G[2] = in1[6] & in2[6];
assig... | 7.485644 |
module CLA_8 (
output [7:0] sum,
output cout,
input [7:0] in1,
input [7:0] in2
);
wire [7:0] G;
wire [7:0] C;
wire [7:0] P;
assign G[0] = in1[7] & in2[7];
assign P[0] = in1[7] ^ in2[7];
assign G[1] = in1[6] & in2[6];
assign P[1] = in1[6] ^ in2[6];
assign G[2] = in1[5] & in2[5];
assig... | 7.55691 |
module CLA_7 (
output [6:0] sum,
output cout,
input [6:0] in1,
input [6:0] in2
);
wire [6:0] G;
wire [6:0] C;
wire [6:0] P;
assign G[0] = in1[6] & in2[6];
assign P[0] = in1[6] ^ in2[6];
assign G[1] = in1[5] & in2[5];
assign P[1] = in1[5] ^ in2[5];
assign G[2] = in1[4] & in2[4];
assig... | 7.045431 |
module CLA_6 (
output [5:0] sum,
output cout,
input [5:0] in1,
input [5:0] in2
);
wire [5:0] G;
wire [5:0] C;
wire [5:0] P;
assign G[0] = in1[5] & in2[5];
assign P[0] = in1[5] ^ in2[5];
assign G[1] = in1[4] & in2[4];
assign P[1] = in1[4] ^ in2[4];
assign G[2] = in1[3] & in2[3];
assig... | 7.213409 |
module CLA_5 (
output [4:0] sum,
output cout,
input [4:0] in1,
input [4:0] in2
);
wire [4:0] G;
wire [4:0] C;
wire [4:0] P;
assign G[0] = in1[4] & in2[4];
assign P[0] = in1[4] ^ in2[4];
assign G[1] = in1[3] & in2[3];
assign P[1] = in1[3] ^ in2[3];
assign G[2] = in1[2] & in2[2];
assig... | 7.366825 |
module CLA_4 (
output [3:0] sum,
output cout,
input [3:0] in1,
input [3:0] in2
);
wire [3:0] G;
wire [3:0] C;
wire [3:0] P;
assign G[0] = in1[3] & in2[3];
assign P[0] = in1[3] ^ in2[3];
assign G[1] = in1[2] & in2[2];
assign P[1] = in1[2] ^ in2[2];
assign G[2] = in1[1] & in2[1];
assig... | 7.250167 |
module CLA_3 (
output [2:0] sum,
output cout,
input [2:0] in1,
input [2:0] in2
);
wire [2:0] G;
wire [2:0] C;
wire [2:0] P;
assign G[0] = in1[2] & in2[2];
assign P[0] = in1[2] ^ in2[2];
assign G[1] = in1[1] & in2[1];
assign P[1] = in1[1] ^ in2[1];
assign G[2] = in1[0] & in2[0];
assig... | 7.186081 |
module CLA_2 (
output [1:0] sum,
output cout,
input [1:0] in1,
input [1:0] in2
);
wire [1:0] G;
wire [1:0] C;
wire [1:0] P;
assign G[0] = in1[1] & in2[1];
assign P[0] = in1[1] ^ in2[1];
assign G[1] = in1[0] & in2[0];
assign P[1] = in1[0] ^ in2[0];
assign C[0] = 0; /* Carry_out = Ci+... | 7.600036 |
module Half_Adder (
input wire in1,
input wire in2,
output wire sum,
output wire cout
);
xor (sum, in1, in2);
and (cout, in1, in2);
endmodule
| 7.558237 |
module half_adder (
output wire sum,
output wire cout,
input wire in1,
input wire in2
);
xor (sum, in1, in2);
and (cout, in1, in2);
endmodule
| 6.966406 |
module CLA4 (
output [3:0] sum,
output cout,
input [3:0] in1,
in2
);
wire [3:0] G; /* Generate */
wire [3:0] P; /* Propagate */
wire [3:0] C; /* Carry */
assign G[0] = in1[3] & in2[3]; /*Generate Gi = Ai * Bi */
assign G[1] = in1[2] & in2[2];
assign G[2] = in1[1] & in2[1];
assign ... | 7.204138 |
module CLA3 (
output [2:0] sum,
output cout,
input [2:0] in1,
in2
);
wire [2:0] G; /* Generate */
wire [2:0] P; /* Propagate */
wire [2:0] C; /* Carry */
assign G[0] = in1[2] & in2[2]; /*Generate Gi = Ai * Bi */
assign G[1] = in1[1] & in2[1];
assign G[2] = in1[0] & in2[0];
assign... | 7.070041 |
module CLA4_c (
output [3:0] sum,
output cout,
input [3:0] in1,
in2,
input cin
);
wire [3:0] G; /* Generate */
wire [3:0] P; /* Propagate */
wire [3:0] C; /* Carry */
assign G[0] = in1[3] & in2[3]; /*Generate Gi = Ai * Bi */
assign G[1] = in1[2] & in2[2];
assign G[2] = in1[1] & ... | 6.996581 |
module half_adder (
output wire sum,
output wire cout,
input wire in1,
input wire in2
);
xor (sum, in1, in2);
and (cout, in1, in2);
endmodule
| 6.966406 |
module half_adder (
output wire sum,
output wire cout,
input wire in1,
input wire in2
);
xor (sum, in1, in2);
and (cout, in1, in2);
endmodule
| 6.966406 |
module CLA4 (
output [3:0] sum,
output cout,
input [3:0] in1,
in2,
input cin
);
wire [3:0] G; /* Generate */
wire [3:0] P; /* Propagate */
wire [3:0] C; /* Carry */
assign G[0] = in1[3] & in2[3]; /*Generate Gi = Ai * Bi */
assign G[1] = in1[2] & in2[2];
assign G[2] = in1[1] & in... | 7.204138 |
module half_adder (
output wire sum,
output wire cout,
input wire in1,
input wire in2
);
xor (sum, in1, in2);
and (cout, in1, in2);
endmodule
| 6.966406 |
module half_adder (
output wire sum,
output wire cout,
input wire in1,
input wire in2
);
xor (sum, in1, in2);
and (cout, in1, in2);
endmodule
| 6.966406 |
module kogge_stone_6 (
sum,
cout,
in1,
in2
);
input [5:0] in1, in2; //input
output [5:0] sum; //output
output cout; //carry-out
wire [5:0] G_Z, P_Z, //wires
G_A, P_A, G_B, P_B, G_C, P_C, G_D, P_D;
assign P_Z[0] = in1[5] ^ in2[5];
assign P_Z[1] = in1[4] ^ in2[4];
assign P_Z[2] = in1[... | 7.097274 |
module black_cell (
Gk_j,
Pi_k,
Gi_k,
Pk_j,
G,
P
);
input Gk_j, Pi_k, Gi_k, Pk_j;
output G, P;
wire Y;
and (Y, Gk_j, Pi_k);
or (G, Gi_k, Y);
and (P, Pk_j, Pi_k);
endmodule
| 6.786907 |
module Half_Adder (
input wire in1,
input wire in2,
output wire sum,
output wire cout
);
xor (sum, in1, in2);
and (cout, in1, in2);
endmodule
| 7.558237 |
module Half_Adder (
input wire in1,
input wire in2,
output wire sum,
output wire cout
);
xor (sum, in1, in2);
and (cout, in1, in2);
endmodule
| 7.558237 |
module half_adder (
output wire sum,
output wire cout,
input wire in1,
input wire in2
);
xor (sum, in1, in2);
and (cout, in1, in2);
endmodule
| 6.966406 |
module Half_Adder (
input wire in1,
input wire in2,
output wire sum,
output wire cout
);
xor (sum, in1, in2);
and (cout, in1, in2);
endmodule
| 7.558237 |
module half_adder (
output wire sum,
output wire cout,
input wire in1,
input wire in2
);
xor (sum, in1, in2);
and (cout, in1, in2);
endmodule
| 6.966406 |
module Half_Adder (
input wire in1,
input wire in2,
output wire sum,
output wire cout
);
xor (sum, in1, in2);
and (cout, in1, in2);
endmodule
| 7.558237 |
module dadz (
in,
out
);
parameter DWIDTH = 32;
parameter AWIDTH = 10;
parameter IWIDTH = 64;
parameter HiddenNeuron = 16;
parameter x = 4;
parameter Layer = 3;
input signed [DWIDTH-1:0] in;
output signed [DWIDTH-1:0] out;
wire signed [DWIDTH-1:0] temp;
substract substract (
.a(in),
... | 6.861734 |
module that generates differential of activation function
//dadz = (1-a)*a where a is sigmoid function
module dadz_module (
clk, rst, step, controller, a, dadz
);
input clk, rst;
input [3:0] step, controller;
input signed [15:0] a;
output signed [15:0] dadz;
reg signed [31:0] temp;
paramet... | 6.649759 |
module dafsm //--> Interface
(
input clk,
reset,
input [2:0] x_in0,
x_in1,
x_in2,
output [2:0] lut,
output reg [5:0] y
);
reg [2:0] x0, x1, x2;
wire [2:0] table_in, table_out;
reg [5:0] p; // temporary register
assign table_in[0] = x0[0];
assign table_in[1]... | 7.520981 |
module dag (
input clk,
input re, // Read-enable
input [ 2:0] cbs, // Circular Buffer Select
input we, // Write-enable
input [15:0] base, // These four inputs add to 32-bits.
input [11:0] len,
input sign,
input ... | 7.331505 |
module dali_clock (
// input
input wire CLK_IN, // 24.0MHz
input wire RST_N, // reset
// LCD
output wire [0:7] R,
output wire [0:7] G,
output wire [0:7] B,
output wire LCD_CLK,
output wire LCD_DEN,
output wire LCD_PWM // backlight,set to hi... | 7.643683 |
module bidirec_dallas_ds1821 (
input clk,
input en_in,
input data_in,
input en_out,
output data_out,
inout bidir
);
reg reg_in;
reg reg_out;
assign bidir = (en_in) ? reg_in : 1'bZ;
assign data_out = reg_out;
always @(posedge clk) begin
if (en_out) reg_out <= bidir;
else... | 6.870005 |
module daq #(
parameter NDAQ = 0,
parameter MAC_PACKET_BITS = 0
) (
input wire clk,
input wire [31:0] systime,
input wire [(32 * NDAQ) - 1:0] daq_data_in,
input wire [NDAQ-1:0] daq_end,
input wire [NDAQ-1:0] daq_valid,
input wire [NDAQ-1:0] daq_req,
output reg [NDAQ-1:0] daq_grant =... | 7.167789 |
module daq1_spi (
spi_csn,
spi_clk,
spi_mosi,
spi_miso,
spi_sdio
);
// 4 wire
input [2:0] spi_csn;
input spi_clk;
input spi_mosi;
output spi_miso;
// 3 wire
inout spi_sdio;
// internal registers
reg [5:0] spi_count = 'd0;
reg spi_rd_wr_n = 'd0;
reg spi_en... | 6.670247 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
module daqcon (
clk_i,
en_o,
os_o,
data_i
);
input wire clk_i;
output reg en_o;
output reg [2:0] os_o;
input wire [7:0] data_i;
endmodule
| 6.840783 |
module daqtriggerctrl (
clk_i,
busy_i,
conv_clk_o,
reset_i,
en_i
);
parameter IDLE = 2'b00;
parameter WAIT_FOR_BUSY = 2'b01;
parameter TRIGGER = 2'b10;
parameter PAUSE = 2'b11;
//TODO: Calculate these in Hertz using macro
parameter CYCLES_TIL_TRIGGER_ON = 990;
parameter CYCLES_TIL_TR... | 6.862627 |
module dAreg (
clk,
aluOut,
dAregCtl,
dAddr
);
input clk;
input [15:0] aluOut;
input dAregCtl;
output [15:0] dAddr;
reg [15:0] dAddr;
always @(clk or dAregCtl or aluOut) begin
if (dAregCtl == 1'b1 && clk == 1'b1) // transparent latch
dAddr = aluOut;
end
endmodule
| 6.942274 |
module Darken (
input clock,
input reset,
input [7:0] io_in,
output [7:0] io_out
);
wire [8:0] _T = {io_in, 1'h0}; // @[Darken.scala 12:19]
assign io_out = _T[7:0]; // @[Darken.scala 12:10]
endmodule
| 7.357135 |
module darkroom (
clk_clk,
darkroom_0_conduit_end_mosi_o,
darkroom_0_conduit_end_sck_o,
darkroom_0_conduit_end_ss_n_o,
darkroom_0_conduit_end_sync_o,
darkroom_0_conduit_end_d_io,
darkroom_0_conduit_end_e_io,
darkroom_0_conduit_end_led,
darkroom_0_conduit_end_trigger_me,
reset_res... | 6.944103 |
module darom //--> Interface
(
input clk,
reset,
input [2:0] x_in0,
x_in1,
x_in2,
output [2:0] lut,
output reg [5:0] y
);
reg [2:0] x0, x1, x2;
wire [2:0] table_in, table_out;
reg [5:0] p; // Temporary register
wire ena;
assign ena = 1;
assign table_in[0... | 8.177353 |
module dartport #(
parameter WIDTH = 16,
BAUD_RATE = 9600
) (
input clock,
input reset,
input enable,
output rx_error,
output tx_error,
input RS232_RX_DATA,
output RS232_TX_DATA,
output [WIDTH-1:0] rx_data,
output rx_valid,
input [WIDTH-1:0] tx_data,
... | 9.062689 |
module segmentDisplay (
score,
out
);
input [9:0] score;
output [23:0] out;
wire [3:0] num_hun, num_ten, num_one;
reg [7:0] hun, ten, one;
assign num_hun = score / 100;
assign num_ten = score / 10 % 10;
assign num_one = score % 10;
assign out = {hun, ten, one};
always @(*) begin
case (n... | 7.675339 |
module clk_div #(
parameter n = (10 ** 7 - 1)
) (
clk,
rst,
new_clk
);
input clk, rst;
output new_clk;
reg [32-1:0] cnt;
wire [32-1:0] next_cnt;
always @(posedge clk) begin
if (rst) begin
cnt <= 0;
end else begin
cnt <= next_cnt;
end
end
assign next_cnt = (cnt ==... | 7.516677 |
module onepulse (
clk,
clk_op,
btn_debounced,
btn_onepulse
);
input clk, clk_op, btn_debounced;
output reg btn_onepulse;
reg debounced_delay;
always @(posedge clk) begin
if (clk_op) begin
btn_onepulse <= btn_debounced & (!debounced_delay);
debounced_delay <= btn_debounced;
e... | 7.208433 |
module dart_shoot (
input clk_32,
input rst,
input switch,
input acc_pulse,
input acc,
output valid,
output [15:0] led,
output reg [4:0] str
);
reg valid = 1'b1;
reg [15:0] led = 15'd0;
reg m;
always @(led) begin
if (led == 16'b1111_1111_1111_1111) m <= 1'b1;
else if (led... | 7.293624 |
module dasign //-> Interface
(
input clk, // System clock
input reset, // Asynchron reset
input signed [3:0] x0_in, // First system input
input signed [3:0] x1_in, // Second system input
input signed [3:0] x2_in, // Third system input
ou... | 7.557681 |
module dasresetcounter #(
parameter RESETLEN = 65536
) (
input wire clk_i,
output wire reset_o,
input wire reset_i,
input wire en_i
);
reg [32:0] clkcount = 0;
reg reset_r;
// Generate pulses for read clock
// Expect 200MHz Clockin
always @(posedge clk_i, posedge reset_i) begin
... | 7.633415 |
module inv (
y,
a
);
output y;
input a;
assign y = ~(a);
endmodule
| 7.293204 |
module nand2 (
y,
a,
b
);
output y;
input a, b;
wire d;
assign d = a & b;
assign y = ~(d);
endmodule
| 7.981307 |
module nor2 (
y,
a,
b
);
output y;
input a, b;
wire d;
assign d = a | b;
assign y = ~(d);
endmodule
| 8.014792 |
module dassign1_1 (
pdec0,
pdec3,
pdec12,
pdec15,
nando,
addr
);
output pdec0, pdec3, pdec12, pdec15;
output [3:0] nando; //the output of the 4 nand gates that you should be using
input [5:0] addr;
//
// vvv - Declare your wires here - vvv
//
wire a = addr[5];
wire b = addr[4]... | 8.10689 |
module dassign1_2 (
y1,
y2,
a,
b,
c,
d
);
output y1, y2;
input a, b, c, d;
//
// vvv - Declare your wires here - vvv
//
wire notA;
wire notB;
wire notD;
wire CDnor;
wire BDnor;
wire nAnBnor;
wire t1nor;
wire t2nand;
//
// vvv - Your structural verilog code here - ... | 7.09814 |
module mux21 (
y,
i0,
i1,
sel
);
output y;
input i0, i1, sel;
//sel = 1 choose a, otherwise b)
assign y = (sel) ? i1 : i0;
endmodule
| 7.781482 |
module dassign1_3 (
pos,
pos3,
ascii
);
input [6:0] ascii;
output [4:0] pos;
output pos3;
//
// vvv - Declare your reg and wires here - vvv
//
reg [4:0] pos;
wire pos3;
//
// vvv - Your procedural verilog (case) code here - vvv
//
always @(ascii) begin
case (ascii)
7'b... | 6.929819 |
modules provided for your use
//
module inv(y,a);
output y;
input a;
assign y=~(a);
endmodule
| 6.677313 |
module and2 (
y,
a,
b
);
output y;
input a, b;
assign y = a & b;
endmodule
| 7.643233 |
module or2 (
y,
a,
b
);
output y;
input a, b;
assign y = a | b;
endmodule
| 8.14099 |
module xor2 (
y,
a,
b
);
output y;
input a, b;
assign y = a ^ b;
endmodule
| 8.661623 |
module mux21 (
y,
i0,
i1,
sel
);
output y;
input i0, i1, sel;
//sel = 1 choose i1, otherwise i0)
assign y = (sel) ? i1 : i0;
endmodule
| 7.781482 |
module sbs (
d,
bout,
x,
y,
bin
);
output d, bout;
input x, y, bin;
// d Logic
wire exor;
xor2 un (
exor,
x,
y
);
xor2 to (
d,
bin,
exor
);
// bout Logic
wire xinv;
wire and1;
wire and2;
wire and3;
wire ortmp;
inv won (
... | 6.567055 |
module subtract8 (
d,
bout,
x,
y
);
output [7:0] d;
output bout;
input [7:0] x, y;
wire bin;
wire [7:0] b;
assign bin = 1'b0;
assign bout = b[7];
//
// Implement the 8-bit subtract function here
//
sbs sbs0 (
d[0],
b[0],
x[0],
y[0],
bin
);
s... | 6.803169 |
module dassign2_1 (
q,
rout,
rin,
din
);
output q;
output [7:0] rout;
input [7:0] rin, din;
//
// Instantiate the subtract module
//
wire bout;
wire [7:0] dout;
subtract8 sub8 (
dout,
bout,
rin,
din
);
//
// Implement the rest of the SCS function here
... | 7.439557 |
module ascii2pos (
pos,
ascii
);
output [4:0] pos;
reg [4:0] pos;
input [6:0] ascii;
always @(ascii) begin
case (ascii)
7'b010_0000: pos[4:0] = 5'b00000;
7'b110_0001: pos[4:0] = 5'b00001;
7'b110_0010: pos[4:0] = 5'b00010;
7'b110_0011: pos[4:0] = 5'b00011;
7'b110_0100... | 6.911598 |
modules you need below---vvv
//
module stepper(step, state, forward, pos, stateReg, forwardReg, reset, req);
output [7:0] step;
output [4:0] state;
output forward;
input [4:0] pos;
input [4:0] stateReg;
input forwardReg;
input reset;
input req;
reg [7:0] step;
reg [4:0] state;
reg [4:0] counter... | 6.777168 |
module dassign3 (
ready,
motor_drv,
req,
ascii_in,
sys_clk,
reset
);
output ready;
output [3:0] motor_drv;
input req;
input [6:0] ascii_in;
input sys_clk, reset;
//
// Instantiate the motor clock divider
//
wire motor_clk;
motor_clk_div mclkdiv (
motor_clk,
sys_... | 7.189034 |
modules as necessary
// Do not delete or modify any of the modules provided
// ****************
// Blocks to design
// ****************
// 3.1a) Rectified linear unit
// out = max(0, in/4)
// 16 bit signed input
// 8 bit unsigned output
module relu(in, out);
input [15:0] in;
output [7:0] out;
assign out =... | 6.550427 |
modules as necessary
// Do not delete or modify any of the modules provided
// ****************
// Blocks to design
// ****************
// 3.2a) Inter-layer module
// four sets of inputs: 8 bit value, 1 bit input ready
// one 1 bit input new (from input layer of neurons)
// four sets of 8 bits output
// one 1 bit out... | 6.550427 |
module dasync (
input d,
clk,
reset,
output reg q
);
always @(posedge clk, posedge reset) begin
if (reset) q = 1'b0;
else q = d;
end
endmodule
| 6.563637 |
module DAS_RF (
clock,
data,
rdaddress,
wraddress,
wren,
q
);
input clock;
input [15:0] data;
input [13:0] rdaddress;
input [13:0] wraddress;
input wren;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 wren;
`ifndef ALTERA_RESERVED_QIS
// syn... | 7.083766 |
module dat23_line (
rst,
clk,
clkn,
//high_speed,
crc_rst,
//interrupt,
//interrupt_disable,
oe,
data_sel,
crc_check_en,
dat_phase,
xmit_data,
rcv_data,
crc_error,
dat
);
input rst;
input clk;
input clkn;
//input high_speed;
input crc_rst;
//... | 6.699416 |
module data_mem (
input clk,
input mem_WE,
input [31:0] mem_WD,
input [31:0] mem_Address,
input reset,
output [31:0] mem_RD,
output [15:0] test_value
);
integer i;
reg [31:0] mem_RAM[0:99];
initial begin
for (i = 0; i < 100; i = i + 1) mem_RAM[i] <= 32'b0;
end
always @(pose... | 7.214114 |
module data_path #(
parameter data_width1 = 5,
data_width2 = 32,
data_width3 = 28
) (
input clk,
input reset,
input [31:0] instr,
input [31:0] data,
input mem_reg,
input mem_write,
input reg_dest,
input reg_write,
input ALU_SRC,
input jump,
input [2:0] ALU_control... | 7.155626 |
module ram_memory (
clk,
rst,
din,
dout
);
parameter dt_depth = 88;
paraeter dt_height = 90;
endmodule
| 6.79609 |
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