code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module Encoder4 (
input [3:0] I,
output [1:0] O
);
wire Or2_inst0_O;
wire Or2_inst1_O;
Or2 Or2_inst0 (
.I({I[3], I[1]}),
.O(Or2_inst0_O)
);
Or2 Or2_inst1 (
.I({I[3], I[2]}),
.O(Or2_inst1_O)
);
assign O = {Or2_inst1_O, Or2_inst0_O};
endmodule
| 7.323619 |
module Or2 (
input [1:0] I,
output O
);
wire LUT2_inst0_O;
LUT2 #(
.INIT(4'h1)
) LUT2_inst0 (
.I0(I[0]),
.I1(I[1]),
.O (LUT2_inst0_O)
);
assign O = LUT2_inst0_O;
endmodule
| 7.624303 |
module Encoder4 (
input [3:0] I,
output [1:0] O
);
wire Or2_inst0_O;
wire Or2_inst1_O;
Or2 Or2_inst0 (
.I({I[3], I[1]}),
.O(Or2_inst0_O)
);
Or2 Or2_inst1 (
.I({I[3], I[2]}),
.O(Or2_inst1_O)
);
assign O = {Or2_inst1_O, Or2_inst0_O};
endmodule
| 7.323619 |
module Or2 (
input [1:0] I,
output O
);
wire LUT2_inst0_O;
LUT2 #(
.INIT(4'h1)
) LUT2_inst0 (
.I0(I[0]),
.I1(I[1]),
.O (LUT2_inst0_O)
);
assign O = LUT2_inst0_O;
endmodule
| 7.624303 |
module Encoder4 (
input [3:0] I,
output [1:0] O
);
wire Or2_inst0_O;
wire Or2_inst1_O;
Or2 Or2_inst0 (
.I({I[3], I[1]}),
.O(Or2_inst0_O)
);
Or2 Or2_inst1 (
.I({I[3], I[2]}),
.O(Or2_inst1_O)
);
assign O = {Or2_inst1_O, Or2_inst0_O};
endmodule
| 7.323619 |
module Or4xNone (
input I0,
input I1,
input I2,
input I3,
output O
);
assign O = |({I3, I2, I1, I0});
endmodule
| 8.172074 |
module Encoder8 (
input [7:0] I,
output [2:0] O
);
wire Or4xNone_inst0_O;
wire Or4xNone_inst1_O;
wire Or4xNone_inst2_O;
Or4xNone Or4xNone_inst0 (
.I0(I[1]),
.I1(I[3]),
.I2(I[5]),
.I3(I[7]),
.O (Or4xNone_inst0_O)
);
Or4xNone Or4xNone_inst1 (
.I0(I[2]),
.I1(I... | 7.555278 |
module coreir_orr #(
parameter width = 1
) (
input [width-1:0] in,
output out
);
assign out = |in;
endmodule
| 8.413586 |
module Or4xNone (
input I0,
input I1,
input I2,
input I3,
output O
);
wire orr_inst0_out;
wire [3:0] orr_inst0_in;
assign orr_inst0_in = {I3, I2, I1, I0};
coreir_orr #(
.width(4)
) orr_inst0 (
.in (orr_inst0_in),
.out(orr_inst0_out)
);
assign O = orr_inst0_out;
en... | 8.172074 |
module Encoder8 (
input [7:0] I,
output [2:0] O
);
wire Or4xNone_inst0_O;
wire Or4xNone_inst1_O;
wire Or4xNone_inst2_O;
Or4xNone Or4xNone_inst0 (
.I0(I[1]),
.I1(I[3]),
.I2(I[5]),
.I3(I[7]),
.O (Or4xNone_inst0_O)
);
Or4xNone Or4xNone_inst1 (
.I0(I[2]),
.I1(I... | 7.555278 |
module Or4 (
input [3:0] I,
output O
);
wire SB_LUT4_inst0_O;
SB_LUT4 #(
.LUT_INIT(16'hFFFE)
) SB_LUT4_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(I[2]),
.I3(I[3]),
.O (SB_LUT4_inst0_O)
);
assign O = SB_LUT4_inst0_O;
endmodule
| 6.96089 |
module Encoder8 (
input [7:0] I,
output [2:0] O
);
wire Or4_inst0_O;
wire Or4_inst1_O;
wire Or4_inst2_O;
Or4 Or4_inst0 (
.I({I[7], I[5], I[3], I[1]}),
.O(Or4_inst0_O)
);
Or4 Or4_inst1 (
.I({I[7], I[6], I[3], I[2]}),
.O(Or4_inst1_O)
);
Or4 Or4_inst2 (
.I({I[7], I[6]... | 7.555278 |
module Or4 (
input [3:0] I,
output O
);
wire LUT4_inst0_O;
LUT4 #(
.INIT(16'h0001)
) LUT4_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(I[2]),
.I3(I[3]),
.O (LUT4_inst0_O)
);
assign O = LUT4_inst0_O;
endmodule
| 6.96089 |
module Encoder8 (
input [7:0] I,
output [2:0] O
);
wire Or4_inst0_O;
wire Or4_inst1_O;
wire Or4_inst2_O;
Or4 Or4_inst0 (
.I({I[7], I[5], I[3], I[1]}),
.O(Or4_inst0_O)
);
Or4 Or4_inst1 (
.I({I[7], I[6], I[3], I[2]}),
.O(Or4_inst1_O)
);
Or4 Or4_inst2 (
.I({I[7], I[6]... | 7.555278 |
module Or4 (
input [3:0] I,
output O
);
wire LUT4_inst0_O;
LUT4 #(
.INIT(16'h0001)
) LUT4_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(I[2]),
.I3(I[3]),
.O (LUT4_inst0_O)
);
assign O = LUT4_inst0_O;
endmodule
| 6.96089 |
module Encoder8 (
input [7:0] I,
output [2:0] O
);
wire Or4_inst0_O;
wire Or4_inst1_O;
wire Or4_inst2_O;
Or4 Or4_inst0 (
.I({I[7], I[5], I[3], I[1]}),
.O(Or4_inst0_O)
);
Or4 Or4_inst1 (
.I({I[7], I[6], I[3], I[2]}),
.O(Or4_inst1_O)
);
Or4 Or4_inst2 (
.I({I[7], I[6]... | 7.555278 |
module coreir_eq_2_wrapped (
input [1:0] I0,
input [1:0] I1,
output O
);
assign O = I0 == I1;
endmodule
| 7.330287 |
module coreir_eq #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output out
);
assign out = in0 == in1;
endmodule
| 7.939296 |
module coreir_eq_2_wrapped (
input [1:0] I0,
input [1:0] I1,
output O
);
wire coreir_eq_2_inst0_out;
coreir_eq #(
.width(2)
) coreir_eq_2_inst0 (
.in0(I0),
.in1(I1),
.out(coreir_eq_2_inst0_out)
);
assign O = coreir_eq_2_inst0_out;
endmodule
| 7.330287 |
module EQ2 (
input [1:0] I0,
input [1:0] I1,
output O
);
wire SB_LUT4_inst0_O;
wire SB_LUT4_inst1_O;
SB_LUT4 #(
.LUT_INIT(16'h8282)
) SB_LUT4_inst0 (
.I0(1'b1),
.I1(I0[0]),
.I2(I1[0]),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
SB_LUT4 #(
.LUT_INIT(16'h8282)
)... | 6.852235 |
module EQ2 (
input [1:0] I0,
input [1:0] I1,
output O
);
wire LUT4_inst0_O;
wire MUXCY_inst0_O;
LUT4 #(
.INIT(16'h9009)
) LUT4_inst0 (
.I0(I0[0]),
.I1(I1[0]),
.I2(I0[1]),
.I3(I1[1]),
.O (LUT4_inst0_O)
);
MUXCY MUXCY_inst0 (
.DI(1'b0),
.CI(1'b1),
... | 6.852235 |
module EQ2 (
input [1:0] I0,
input [1:0] I1,
output O
);
wire LUT6_2_inst0_O5;
wire LUT6_2_inst0_O6;
wire MUXCY_inst0_O;
LUT6_2 #(
.INIT(64'h9009900900000000)
) LUT6_2_inst0 (
.I0(I0[0]),
.I1(I1[0]),
.I2(I0[1]),
.I3(I1[1]),
.I4(1'b0),
.I5(1'b1),
.O5(... | 6.852235 |
module coreir_eq_4_wrapped (
input [3:0] I0,
input [3:0] I1,
output O
);
assign O = I0 == I1;
endmodule
| 7.393511 |
module coreir_eq #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output out
);
assign out = in0 == in1;
endmodule
| 7.939296 |
module coreir_eq_4_wrapped (
input [3:0] I0,
input [3:0] I1,
output O
);
wire coreir_eq_4_inst0_out;
coreir_eq #(
.width(4)
) coreir_eq_4_inst0 (
.in0(I0),
.in1(I1),
.out(coreir_eq_4_inst0_out)
);
assign O = coreir_eq_4_inst0_out;
endmodule
| 7.393511 |
module EQ4 (
input [3:0] I0,
input [3:0] I1,
output O
);
wire SB_LUT4_inst0_O;
wire SB_LUT4_inst1_O;
wire SB_LUT4_inst2_O;
wire SB_LUT4_inst3_O;
SB_LUT4 #(
.LUT_INIT(16'h8282)
) SB_LUT4_inst0 (
.I0(1'b1),
.I1(I0[0]),
.I2(I1[0]),
.I3(1'b0),
.O (SB_LUT4_inst0_O)... | 6.717664 |
module EQ4 (
input [3:0] I0,
input [3:0] I1,
output O
);
wire LUT4_inst0_O;
wire MUXCY_inst0_O;
wire LUT4_inst1_O;
wire MUXCY_inst1_O;
LUT4 #(
.INIT(16'h9009)
) LUT4_inst0 (
.I0(I0[0]),
.I1(I1[0]),
.I2(I0[1]),
.I3(I1[1]),
.O (LUT4_inst0_O)
);
MUXCY MUXCY_i... | 6.717664 |
module EQ4 (
input [3:0] I0,
input [3:0] I1,
output O
);
wire LUT6_2_inst0_O5;
wire LUT6_2_inst0_O6;
wire MUXCY_inst0_O;
wire LUT6_2_inst1_O5;
wire LUT6_2_inst1_O6;
wire MUXCY_inst1_O;
LUT6_2 #(
.INIT(64'h9009900900000000)
) LUT6_2_inst0 (
.I0(I0[0]),
.I1(I1[0]),
.I2(... | 6.717664 |
module coreir_eq_8_wrapped (
input [7:0] I0,
input [7:0] I1,
output O
);
assign O = I0 == I1;
endmodule
| 7.167719 |
module coreir_eq #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output out
);
assign out = in0 == in1;
endmodule
| 7.939296 |
module coreir_eq_8_wrapped (
input [7:0] I0,
input [7:0] I1,
output O
);
wire coreir_eq_8_inst0_out;
coreir_eq #(
.width(8)
) coreir_eq_8_inst0 (
.in0(I0),
.in1(I1),
.out(coreir_eq_8_inst0_out)
);
assign O = coreir_eq_8_inst0_out;
endmodule
| 7.167719 |
module EQ8 (
input [7:0] I0,
input [7:0] I1,
output O
);
wire SB_LUT4_inst0_O;
wire SB_LUT4_inst1_O;
wire SB_LUT4_inst2_O;
wire SB_LUT4_inst3_O;
wire SB_LUT4_inst4_O;
wire SB_LUT4_inst5_O;
wire SB_LUT4_inst6_O;
wire SB_LUT4_inst7_O;
SB_LUT4 #(
.LUT_INIT(16'h8282)
) SB_LUT4_inst0 (
... | 6.605022 |
module EQ8 (
input [7:0] I0,
input [7:0] I1,
output O
);
wire LUT4_inst0_O;
wire MUXCY_inst0_O;
wire LUT4_inst1_O;
wire MUXCY_inst1_O;
wire LUT4_inst2_O;
wire MUXCY_inst2_O;
wire LUT4_inst3_O;
wire MUXCY_inst3_O;
LUT4 #(
.INIT(16'h9009)
) LUT4_inst0 (
.I0(I0[0]),
.I1(I1... | 6.605022 |
module EQ8 (
input [7:0] I0,
input [7:0] I1,
output O
);
wire LUT6_2_inst0_O5;
wire LUT6_2_inst0_O6;
wire MUXCY_inst0_O;
wire LUT6_2_inst1_O5;
wire LUT6_2_inst1_O6;
wire MUXCY_inst1_O;
wire LUT6_2_inst2_O5;
wire LUT6_2_inst2_O6;
wire MUXCY_inst2_O;
wire LUT6_2_inst3_O5;
wire LUT6_2_ins... | 6.605022 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= ... | 7.868877 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= ... | 7.868877 |
module corebit_not (
input in,
output out
);
assign out = ~in;
endmodule
| 8.318293 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= ... | 7.868877 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= ... | 7.868877 |
module corebit_not (
input in,
output out
);
assign out = ~in;
endmodule
| 8.318293 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= ... | 7.868877 |
module Johnson8 (
output [7:0] O,
input CLK
);
wire DFF_init0_has_ceFalse_has_resetFalse_has_async_resetFalse_inst0_O;
wire DFF_init0_has_ceFalse_has_resetFalse_has_async_resetFalse_inst1_O;
wire DFF_init0_has_ceFalse_has_resetFalse_has_async_resetFalse_inst2_O;
wire DFF_init0_has_ceFalse_has_resetFalse... | 6.698855 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= ... | 7.868877 |
module corebit_not (
input in,
output out
);
assign out = ~in;
endmodule
| 8.318293 |
module Johnson8 (
output [7:0] O,
input CLK
);
wire DFF_init0_has_ceFalse_has_resetFalse_has_async_resetFalse_inst0_O;
wire DFF_init0_has_ceFalse_has_resetFalse_has_async_resetFalse_inst1_O;
wire DFF_init0_has_ceFalse_has_resetFalse_has_async_resetFalse_inst2_O;
wire DFF_init0_has_ceFalse_has_resetFalse... | 6.698855 |
module Johnson8 (
output [7:0] O,
input CLK
);
wire SB_DFF_inst0_Q;
wire SB_DFF_inst1_Q;
wire SB_DFF_inst2_Q;
wire SB_DFF_inst3_Q;
wire SB_DFF_inst4_Q;
wire SB_DFF_inst5_Q;
wire SB_DFF_inst6_Q;
wire SB_DFF_inst7_Q;
wire SB_LUT4_inst0_O;
SB_DFF SB_DFF_inst0 (
.C(CLK),
.D(SB_LUT4_i... | 6.698855 |
module Johnson8 (
output [7:0] O,
input CLK
);
wire FDRSE_inst0_Q;
wire FDRSE_inst1_Q;
wire FDRSE_inst2_Q;
wire FDRSE_inst3_Q;
wire FDRSE_inst4_Q;
wire FDRSE_inst5_Q;
wire FDRSE_inst6_Q;
wire FDRSE_inst7_Q;
wire LUT1_inst0_O;
FDRSE #(
.INIT(1'h0)
) FDRSE_inst0 (
.C (CLK),
... | 6.698855 |
module Johnson8 (
output [7:0] O,
input CLK
);
wire FDRSE_inst0_Q;
wire FDRSE_inst1_Q;
wire FDRSE_inst2_Q;
wire FDRSE_inst3_Q;
wire FDRSE_inst4_Q;
wire FDRSE_inst5_Q;
wire FDRSE_inst6_Q;
wire FDRSE_inst7_Q;
wire LUT1_inst0_O;
FDRSE #(
.INIT(1'h0)
) FDRSE_inst0 (
.C (CLK),
... | 6.698855 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire SB_LUT4_inst0_O;
SB_LUT4 #(
.LUT_INIT(16'hCACA)
) SB_LUT4_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
assign O = SB_LUT4_inst0_O;
endmodule
| 7.615389 |
module LSL2_1 (
input [1:0] I,
input S,
output [1:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
Mux2 Mux2_inst0 (
.I({1'b0, I[0]}),
.S(S),
.O(Mux2_inst0_O)
);
Mux2 Mux2_inst1 (
.I({I[0], I[1]}),
.S(S),
.O(Mux2_inst1_O)
);
assign O = {Mux2_inst1_O, Mux2_inst0... | 6.585607 |
module LSL2 (
input [1:0] I,
input [0:0] S,
output [1:0] O
);
wire [1:0] LSL2_1_inst0_O;
LSL2_1 LSL2_1_inst0 (
.I(I),
.S(S[0]),
.O(LSL2_1_inst0_O)
);
assign O = LSL2_1_inst0_O;
endmodule
| 7.259144 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire LUT3_inst0_O;
LUT3 #(
.INIT(8'hCA)
) LUT3_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.O (LUT3_inst0_O)
);
assign O = LUT3_inst0_O;
endmodule
| 7.615389 |
module LSL2_1 (
input [1:0] I,
input S,
output [1:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
Mux2 Mux2_inst0 (
.I({1'b0, I[0]}),
.S(S),
.O(Mux2_inst0_O)
);
Mux2 Mux2_inst1 (
.I({I[0], I[1]}),
.S(S),
.O(Mux2_inst1_O)
);
assign O = {Mux2_inst1_O, Mux2_inst0... | 6.585607 |
module LSL2 (
input [1:0] I,
input [0:0] S,
output [1:0] O
);
wire [1:0] LSL2_1_inst0_O;
LSL2_1 LSL2_1_inst0 (
.I(I),
.S(S[0]),
.O(LSL2_1_inst0_O)
);
assign O = LSL2_1_inst0_O;
endmodule
| 7.259144 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire LUT3_inst0_O;
LUT3 #(
.INIT(8'hCA)
) LUT3_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.O (LUT3_inst0_O)
);
assign O = LUT3_inst0_O;
endmodule
| 7.615389 |
module LSL2_1 (
input [1:0] I,
input S,
output [1:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
Mux2 Mux2_inst0 (
.I({1'b0, I[0]}),
.S(S),
.O(Mux2_inst0_O)
);
Mux2 Mux2_inst1 (
.I({I[0], I[1]}),
.S(S),
.O(Mux2_inst1_O)
);
assign O = {Mux2_inst1_O, Mux2_inst0... | 6.585607 |
module LSL2 (
input [1:0] I,
input [0:0] S,
output [1:0] O
);
wire [1:0] LSL2_1_inst0_O;
LSL2_1 LSL2_1_inst0 (
.I(I),
.S(S[0]),
.O(LSL2_1_inst0_O)
);
assign O = LSL2_1_inst0_O;
endmodule
| 7.259144 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire SB_LUT4_inst0_O;
SB_LUT4 #(
.LUT_INIT(16'hCACA)
) SB_LUT4_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
assign O = SB_LUT4_inst0_O;
endmodule
| 7.615389 |
module LSL4_1 (
input [3:0] I,
input S,
output [3:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
wire Mux2_inst2_O;
wire Mux2_inst3_O;
Mux2 Mux2_inst0 (
.I({1'b0, I[0]}),
.S(S),
.O(Mux2_inst0_O)
);
Mux2 Mux2_inst1 (
.I({I[0], I[1]}),
.S(S),
.O(Mux2_inst1_O)
... | 6.552521 |
module LSL4 (
input [3:0] I,
input [1:0] S,
output [3:0] O
);
wire [3:0] LSL4_1_inst0_O;
wire [3:0] LSL4_2_inst0_O;
LSL4_1 LSL4_1_inst0 (
.I(I),
.S(S[0]),
.O(LSL4_1_inst0_O)
);
LSL4_2 LSL4_2_inst0 (
.I(LSL4_1_inst0_O),
.S(S[1]),
.O(LSL4_2_inst0_O)
);
assig... | 7.139865 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire LUT3_inst0_O;
LUT3 #(
.INIT(8'hCA)
) LUT3_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.O (LUT3_inst0_O)
);
assign O = LUT3_inst0_O;
endmodule
| 7.615389 |
module LSL4_1 (
input [3:0] I,
input S,
output [3:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
wire Mux2_inst2_O;
wire Mux2_inst3_O;
Mux2 Mux2_inst0 (
.I({1'b0, I[0]}),
.S(S),
.O(Mux2_inst0_O)
);
Mux2 Mux2_inst1 (
.I({I[0], I[1]}),
.S(S),
.O(Mux2_inst1_O)
... | 6.552521 |
module LSL4 (
input [3:0] I,
input [1:0] S,
output [3:0] O
);
wire [3:0] LSL4_1_inst0_O;
wire [3:0] LSL4_2_inst0_O;
LSL4_1 LSL4_1_inst0 (
.I(I),
.S(S[0]),
.O(LSL4_1_inst0_O)
);
LSL4_2 LSL4_2_inst0 (
.I(LSL4_1_inst0_O),
.S(S[1]),
.O(LSL4_2_inst0_O)
);
assig... | 7.139865 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire LUT3_inst0_O;
LUT3 #(
.INIT(8'hCA)
) LUT3_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.O (LUT3_inst0_O)
);
assign O = LUT3_inst0_O;
endmodule
| 7.615389 |
module LSL4_1 (
input [3:0] I,
input S,
output [3:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
wire Mux2_inst2_O;
wire Mux2_inst3_O;
Mux2 Mux2_inst0 (
.I({1'b0, I[0]}),
.S(S),
.O(Mux2_inst0_O)
);
Mux2 Mux2_inst1 (
.I({I[0], I[1]}),
.S(S),
.O(Mux2_inst1_O)
... | 6.552521 |
module LSL4 (
input [3:0] I,
input [1:0] S,
output [3:0] O
);
wire [3:0] LSL4_1_inst0_O;
wire [3:0] LSL4_2_inst0_O;
LSL4_1 LSL4_1_inst0 (
.I(I),
.S(S[0]),
.O(LSL4_1_inst0_O)
);
LSL4_2 LSL4_2_inst0 (
.I(LSL4_1_inst0_O),
.S(S[1]),
.O(LSL4_2_inst0_O)
);
assig... | 7.139865 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire SB_LUT4_inst0_O;
SB_LUT4 #(
.LUT_INIT(16'hCACA)
) SB_LUT4_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
assign O = SB_LUT4_inst0_O;
endmodule
| 7.615389 |
module LSL8_1 (
input [7:0] I,
input S,
output [7:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
wire Mux2_inst2_O;
wire Mux2_inst3_O;
wire Mux2_inst4_O;
wire Mux2_inst5_O;
wire Mux2_inst6_O;
wire Mux2_inst7_O;
Mux2 Mux2_inst0 (
.I({1'b0, I[0]}),
.S(S),
.O(Mux2_inst0_O)
... | 6.738525 |
module LSL8_4 (
input [7:0] I,
input S,
output [7:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
wire Mux2_inst2_O;
wire Mux2_inst3_O;
wire Mux2_inst4_O;
wire Mux2_inst5_O;
wire Mux2_inst6_O;
wire Mux2_inst7_O;
Mux2 Mux2_inst0 (
.I({1'b0, I[0]}),
.S(S),
.O(Mux2_inst0_O)
... | 6.988531 |
module LSL8 (
input [7:0] I,
input [2:0] S,
output [7:0] O
);
wire [7:0] LSL8_1_inst0_O;
wire [7:0] LSL8_2_inst0_O;
wire [7:0] LSL8_4_inst0_O;
LSL8_1 LSL8_1_inst0 (
.I(I),
.S(S[0]),
.O(LSL8_1_inst0_O)
);
LSL8_2 LSL8_2_inst0 (
.I(LSL8_1_inst0_O),
.S(S[1]),
.O... | 7.159438 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire LUT3_inst0_O;
LUT3 #(
.INIT(8'hCA)
) LUT3_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.O (LUT3_inst0_O)
);
assign O = LUT3_inst0_O;
endmodule
| 7.615389 |
module LSL8_1 (
input [7:0] I,
input S,
output [7:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
wire Mux2_inst2_O;
wire Mux2_inst3_O;
wire Mux2_inst4_O;
wire Mux2_inst5_O;
wire Mux2_inst6_O;
wire Mux2_inst7_O;
Mux2 Mux2_inst0 (
.I({1'b0, I[0]}),
.S(S),
.O(Mux2_inst0_O)
... | 6.738525 |
module LSL8_4 (
input [7:0] I,
input S,
output [7:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
wire Mux2_inst2_O;
wire Mux2_inst3_O;
wire Mux2_inst4_O;
wire Mux2_inst5_O;
wire Mux2_inst6_O;
wire Mux2_inst7_O;
Mux2 Mux2_inst0 (
.I({1'b0, I[0]}),
.S(S),
.O(Mux2_inst0_O)
... | 6.988531 |
module LSL8 (
input [7:0] I,
input [2:0] S,
output [7:0] O
);
wire [7:0] LSL8_1_inst0_O;
wire [7:0] LSL8_2_inst0_O;
wire [7:0] LSL8_4_inst0_O;
LSL8_1 LSL8_1_inst0 (
.I(I),
.S(S[0]),
.O(LSL8_1_inst0_O)
);
LSL8_2 LSL8_2_inst0 (
.I(LSL8_1_inst0_O),
.S(S[1]),
.O... | 7.159438 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire LUT3_inst0_O;
LUT3 #(
.INIT(8'hCA)
) LUT3_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.O (LUT3_inst0_O)
);
assign O = LUT3_inst0_O;
endmodule
| 7.615389 |
module LSL8_1 (
input [7:0] I,
input S,
output [7:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
wire Mux2_inst2_O;
wire Mux2_inst3_O;
wire Mux2_inst4_O;
wire Mux2_inst5_O;
wire Mux2_inst6_O;
wire Mux2_inst7_O;
Mux2 Mux2_inst0 (
.I({1'b0, I[0]}),
.S(S),
.O(Mux2_inst0_O)
... | 6.738525 |
module LSL8_4 (
input [7:0] I,
input S,
output [7:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
wire Mux2_inst2_O;
wire Mux2_inst3_O;
wire Mux2_inst4_O;
wire Mux2_inst5_O;
wire Mux2_inst6_O;
wire Mux2_inst7_O;
Mux2 Mux2_inst0 (
.I({1'b0, I[0]}),
.S(S),
.O(Mux2_inst0_O)
... | 6.988531 |
module LSL8 (
input [7:0] I,
input [2:0] S,
output [7:0] O
);
wire [7:0] LSL8_1_inst0_O;
wire [7:0] LSL8_2_inst0_O;
wire [7:0] LSL8_4_inst0_O;
LSL8_1 LSL8_1_inst0 (
.I(I),
.S(S[0]),
.O(LSL8_1_inst0_O)
);
LSL8_2 LSL8_2_inst0 (
.I(LSL8_1_inst0_O),
.S(S[1]),
.O... | 7.159438 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire SB_LUT4_inst0_O;
SB_LUT4 #(
.LUT_INIT(16'hCACA)
) SB_LUT4_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
assign O = SB_LUT4_inst0_O;
endmodule
| 7.615389 |
module LSR2_1 (
input [1:0] I,
input S,
output [1:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
Mux2 Mux2_inst0 (
.I(I),
.S(S),
.O(Mux2_inst0_O)
);
Mux2 Mux2_inst1 (
.I({1'b0, I[1]}),
.S(S),
.O(Mux2_inst1_O)
);
assign O = {Mux2_inst1_O, Mux2_inst0_O};
endmod... | 7.261613 |
module LSR2 (
input [1:0] I,
input [0:0] S,
output [1:0] O
);
wire [1:0] LSR2_1_inst0_O;
LSR2_1 LSR2_1_inst0 (
.I(I),
.S(S[0]),
.O(LSR2_1_inst0_O)
);
assign O = LSR2_1_inst0_O;
endmodule
| 7.712614 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire LUT3_inst0_O;
LUT3 #(
.INIT(8'hCA)
) LUT3_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.O (LUT3_inst0_O)
);
assign O = LUT3_inst0_O;
endmodule
| 7.615389 |
module LSR2_1 (
input [1:0] I,
input S,
output [1:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
Mux2 Mux2_inst0 (
.I(I),
.S(S),
.O(Mux2_inst0_O)
);
Mux2 Mux2_inst1 (
.I({1'b0, I[1]}),
.S(S),
.O(Mux2_inst1_O)
);
assign O = {Mux2_inst1_O, Mux2_inst0_O};
endmod... | 7.261613 |
module LSR2 (
input [1:0] I,
input [0:0] S,
output [1:0] O
);
wire [1:0] LSR2_1_inst0_O;
LSR2_1 LSR2_1_inst0 (
.I(I),
.S(S[0]),
.O(LSR2_1_inst0_O)
);
assign O = LSR2_1_inst0_O;
endmodule
| 7.712614 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire LUT3_inst0_O;
LUT3 #(
.INIT(8'hCA)
) LUT3_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.O (LUT3_inst0_O)
);
assign O = LUT3_inst0_O;
endmodule
| 7.615389 |
module LSR2_1 (
input [1:0] I,
input S,
output [1:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
Mux2 Mux2_inst0 (
.I(I),
.S(S),
.O(Mux2_inst0_O)
);
Mux2 Mux2_inst1 (
.I({1'b0, I[1]}),
.S(S),
.O(Mux2_inst1_O)
);
assign O = {Mux2_inst1_O, Mux2_inst0_O};
endmod... | 7.261613 |
module LSR2 (
input [1:0] I,
input [0:0] S,
output [1:0] O
);
wire [1:0] LSR2_1_inst0_O;
LSR2_1 LSR2_1_inst0 (
.I(I),
.S(S[0]),
.O(LSR2_1_inst0_O)
);
assign O = LSR2_1_inst0_O;
endmodule
| 7.712614 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire SB_LUT4_inst0_O;
SB_LUT4 #(
.LUT_INIT(16'hCACA)
) SB_LUT4_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
assign O = SB_LUT4_inst0_O;
endmodule
| 7.615389 |
module LSR4_1 (
input [3:0] I,
input S,
output [3:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
wire Mux2_inst2_O;
wire Mux2_inst3_O;
Mux2 Mux2_inst0 (
.I({I[1], I[0]}),
.S(S),
.O(Mux2_inst0_O)
);
Mux2 Mux2_inst1 (
.I({I[2], I[1]}),
.S(S),
.O(Mux2_inst1_O)
... | 6.97918 |
module LSR4_2 (
input [3:0] I,
input S,
output [3:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
wire Mux2_inst2_O;
wire Mux2_inst3_O;
Mux2 Mux2_inst0 (
.I({I[2], I[0]}),
.S(S),
.O(Mux2_inst0_O)
);
Mux2 Mux2_inst1 (
.I({I[3], I[1]}),
.S(S),
.O(Mux2_inst1_O)
... | 6.782375 |
module LSR4 (
input [3:0] I,
input [1:0] S,
output [3:0] O
);
wire [3:0] LSR4_1_inst0_O;
wire [3:0] LSR4_2_inst0_O;
LSR4_1 LSR4_1_inst0 (
.I(I),
.S(S[0]),
.O(LSR4_1_inst0_O)
);
LSR4_2 LSR4_2_inst0 (
.I(LSR4_1_inst0_O),
.S(S[1]),
.O(LSR4_2_inst0_O)
);
assig... | 7.556119 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire LUT3_inst0_O;
LUT3 #(
.INIT(8'hCA)
) LUT3_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.O (LUT3_inst0_O)
);
assign O = LUT3_inst0_O;
endmodule
| 7.615389 |
module LSR4_1 (
input [3:0] I,
input S,
output [3:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
wire Mux2_inst2_O;
wire Mux2_inst3_O;
Mux2 Mux2_inst0 (
.I({I[1], I[0]}),
.S(S),
.O(Mux2_inst0_O)
);
Mux2 Mux2_inst1 (
.I({I[2], I[1]}),
.S(S),
.O(Mux2_inst1_O)
... | 6.97918 |
module LSR4_2 (
input [3:0] I,
input S,
output [3:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
wire Mux2_inst2_O;
wire Mux2_inst3_O;
Mux2 Mux2_inst0 (
.I({I[2], I[0]}),
.S(S),
.O(Mux2_inst0_O)
);
Mux2 Mux2_inst1 (
.I({I[3], I[1]}),
.S(S),
.O(Mux2_inst1_O)
... | 6.782375 |
module LSR4 (
input [3:0] I,
input [1:0] S,
output [3:0] O
);
wire [3:0] LSR4_1_inst0_O;
wire [3:0] LSR4_2_inst0_O;
LSR4_1 LSR4_1_inst0 (
.I(I),
.S(S[0]),
.O(LSR4_1_inst0_O)
);
LSR4_2 LSR4_2_inst0 (
.I(LSR4_1_inst0_O),
.S(S[1]),
.O(LSR4_2_inst0_O)
);
assig... | 7.556119 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire LUT3_inst0_O;
LUT3 #(
.INIT(8'hCA)
) LUT3_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.O (LUT3_inst0_O)
);
assign O = LUT3_inst0_O;
endmodule
| 7.615389 |
module LSR4_1 (
input [3:0] I,
input S,
output [3:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
wire Mux2_inst2_O;
wire Mux2_inst3_O;
Mux2 Mux2_inst0 (
.I({I[1], I[0]}),
.S(S),
.O(Mux2_inst0_O)
);
Mux2 Mux2_inst1 (
.I({I[2], I[1]}),
.S(S),
.O(Mux2_inst1_O)
... | 6.97918 |
module LSR4_2 (
input [3:0] I,
input S,
output [3:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
wire Mux2_inst2_O;
wire Mux2_inst3_O;
Mux2 Mux2_inst0 (
.I({I[2], I[0]}),
.S(S),
.O(Mux2_inst0_O)
);
Mux2 Mux2_inst1 (
.I({I[3], I[1]}),
.S(S),
.O(Mux2_inst1_O)
... | 6.782375 |
module LSR4 (
input [3:0] I,
input [1:0] S,
output [3:0] O
);
wire [3:0] LSR4_1_inst0_O;
wire [3:0] LSR4_2_inst0_O;
LSR4_1 LSR4_1_inst0 (
.I(I),
.S(S[0]),
.O(LSR4_1_inst0_O)
);
LSR4_2 LSR4_2_inst0 (
.I(LSR4_1_inst0_O),
.S(S[1]),
.O(LSR4_2_inst0_O)
);
assig... | 7.556119 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire SB_LUT4_inst0_O;
SB_LUT4 #(
.LUT_INIT(16'hCACA)
) SB_LUT4_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
assign O = SB_LUT4_inst0_O;
endmodule
| 7.615389 |
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