code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module LSR8_1 (
input [7:0] I,
input S,
output [7:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
wire Mux2_inst2_O;
wire Mux2_inst3_O;
wire Mux2_inst4_O;
wire Mux2_inst5_O;
wire Mux2_inst6_O;
wire Mux2_inst7_O;
Mux2 Mux2_inst0 (
.I({I[1], I[0]}),
.S(S),
.O(Mux2_inst0_O)
... | 7.121647 |
module LSR8_2 (
input [7:0] I,
input S,
output [7:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
wire Mux2_inst2_O;
wire Mux2_inst3_O;
wire Mux2_inst4_O;
wire Mux2_inst5_O;
wire Mux2_inst6_O;
wire Mux2_inst7_O;
Mux2 Mux2_inst0 (
.I({I[2], I[0]}),
.S(S),
.O(Mux2_inst0_O)
... | 6.715162 |
module LSR8_4 (
input [7:0] I,
input S,
output [7:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
wire Mux2_inst2_O;
wire Mux2_inst3_O;
wire Mux2_inst4_O;
wire Mux2_inst5_O;
wire Mux2_inst6_O;
wire Mux2_inst7_O;
Mux2 Mux2_inst0 (
.I({I[4], I[0]}),
.S(S),
.O(Mux2_inst0_O)
... | 7.245229 |
module LSR8 (
input [7:0] I,
input [2:0] S,
output [7:0] O
);
wire [7:0] LSR8_1_inst0_O;
wire [7:0] LSR8_2_inst0_O;
wire [7:0] LSR8_4_inst0_O;
LSR8_1 LSR8_1_inst0 (
.I(I),
.S(S[0]),
.O(LSR8_1_inst0_O)
);
LSR8_2 LSR8_2_inst0 (
.I(LSR8_1_inst0_O),
.S(S[1]),
.O... | 7.649467 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire LUT3_inst0_O;
LUT3 #(
.INIT(8'hCA)
) LUT3_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.O (LUT3_inst0_O)
);
assign O = LUT3_inst0_O;
endmodule
| 7.615389 |
module LSR8_1 (
input [7:0] I,
input S,
output [7:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
wire Mux2_inst2_O;
wire Mux2_inst3_O;
wire Mux2_inst4_O;
wire Mux2_inst5_O;
wire Mux2_inst6_O;
wire Mux2_inst7_O;
Mux2 Mux2_inst0 (
.I({I[1], I[0]}),
.S(S),
.O(Mux2_inst0_O)
... | 7.121647 |
module LSR8_2 (
input [7:0] I,
input S,
output [7:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
wire Mux2_inst2_O;
wire Mux2_inst3_O;
wire Mux2_inst4_O;
wire Mux2_inst5_O;
wire Mux2_inst6_O;
wire Mux2_inst7_O;
Mux2 Mux2_inst0 (
.I({I[2], I[0]}),
.S(S),
.O(Mux2_inst0_O)
... | 6.715162 |
module LSR8_4 (
input [7:0] I,
input S,
output [7:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
wire Mux2_inst2_O;
wire Mux2_inst3_O;
wire Mux2_inst4_O;
wire Mux2_inst5_O;
wire Mux2_inst6_O;
wire Mux2_inst7_O;
Mux2 Mux2_inst0 (
.I({I[4], I[0]}),
.S(S),
.O(Mux2_inst0_O)
... | 7.245229 |
module LSR8 (
input [7:0] I,
input [2:0] S,
output [7:0] O
);
wire [7:0] LSR8_1_inst0_O;
wire [7:0] LSR8_2_inst0_O;
wire [7:0] LSR8_4_inst0_O;
LSR8_1 LSR8_1_inst0 (
.I(I),
.S(S[0]),
.O(LSR8_1_inst0_O)
);
LSR8_2 LSR8_2_inst0 (
.I(LSR8_1_inst0_O),
.S(S[1]),
.O... | 7.649467 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire LUT3_inst0_O;
LUT3 #(
.INIT(8'hCA)
) LUT3_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.O (LUT3_inst0_O)
);
assign O = LUT3_inst0_O;
endmodule
| 7.615389 |
module LSR8_1 (
input [7:0] I,
input S,
output [7:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
wire Mux2_inst2_O;
wire Mux2_inst3_O;
wire Mux2_inst4_O;
wire Mux2_inst5_O;
wire Mux2_inst6_O;
wire Mux2_inst7_O;
Mux2 Mux2_inst0 (
.I({I[1], I[0]}),
.S(S),
.O(Mux2_inst0_O)
... | 7.121647 |
module LSR8_2 (
input [7:0] I,
input S,
output [7:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
wire Mux2_inst2_O;
wire Mux2_inst3_O;
wire Mux2_inst4_O;
wire Mux2_inst5_O;
wire Mux2_inst6_O;
wire Mux2_inst7_O;
Mux2 Mux2_inst0 (
.I({I[2], I[0]}),
.S(S),
.O(Mux2_inst0_O)
... | 6.715162 |
module LSR8_4 (
input [7:0] I,
input S,
output [7:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
wire Mux2_inst2_O;
wire Mux2_inst3_O;
wire Mux2_inst4_O;
wire Mux2_inst5_O;
wire Mux2_inst6_O;
wire Mux2_inst7_O;
Mux2 Mux2_inst0 (
.I({I[4], I[0]}),
.S(S),
.O(Mux2_inst0_O)
... | 7.245229 |
module LSR8 (
input [7:0] I,
input [2:0] S,
output [7:0] O
);
wire [7:0] LSR8_1_inst0_O;
wire [7:0] LSR8_2_inst0_O;
wire [7:0] LSR8_4_inst0_O;
LSR8_1 LSR8_1_inst0 (
.I(I),
.S(S[0]),
.O(LSR8_1_inst0_O)
);
LSR8_2 LSR8_2_inst0 (
.I(LSR8_1_inst0_O),
.S(S[1]),
.O... | 7.649467 |
module NE2 (
input [1:0] I0,
input [1:0] I1,
output O
);
assign O = ~(I0 == I1);
endmodule
| 6.651985 |
module coreir_eq #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output out
);
assign out = in0 == in1;
endmodule
| 7.939296 |
module corebit_not (
input in,
output out
);
assign out = ~in;
endmodule
| 8.318293 |
module NE2 (
input [1:0] I0,
input [1:0] I1,
output O
);
wire coreir_eq_2_inst0_out;
wire not_inst0_out;
coreir_eq #(
.width(2)
) coreir_eq_2_inst0 (
.in0(I0),
.in1(I1),
.out(coreir_eq_2_inst0_out)
);
corebit_not not_inst0 (
.in (coreir_eq_2_inst0_out),
.out(n... | 6.651985 |
module NE2 (
input [1:0] I0,
input [1:0] I1,
output O
);
wire SB_LUT4_inst0_O;
wire SB_LUT4_inst1_O;
SB_LUT4 #(
.LUT_INIT(16'hBEBE)
) SB_LUT4_inst0 (
.I0(1'b0),
.I1(I0[0]),
.I2(I1[0]),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
SB_LUT4 #(
.LUT_INIT(16'hBEBE)
)... | 6.651985 |
module NE2 (
input [1:0] I0,
input [1:0] I1,
output O
);
wire LUT4_inst0_O;
wire MUXCY_inst0_O;
LUT4 #(
.INIT(16'h6FF6)
) LUT4_inst0 (
.I0(I0[0]),
.I1(I1[0]),
.I2(I0[1]),
.I3(I1[1]),
.O (LUT4_inst0_O)
);
MUXCY MUXCY_inst0 (
.DI(1'b0),
.CI(1'b1),
... | 6.651985 |
module NE2 (
input [1:0] I0,
input [1:0] I1,
output O
);
wire LUT6_2_inst0_O5;
wire LUT6_2_inst0_O6;
wire MUXCY_inst0_O;
LUT6_2 #(
.INIT(64'h6FF66FF600000000)
) LUT6_2_inst0 (
.I0(I0[0]),
.I1(I1[0]),
.I2(I0[1]),
.I3(I1[1]),
.I4(1'b0),
.I5(1'b1),
.O5(... | 6.651985 |
module NE4 (
input [3:0] I0,
input [3:0] I1,
output O
);
assign O = ~(I0 == I1);
endmodule
| 7.333423 |
module coreir_eq #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output out
);
assign out = in0 == in1;
endmodule
| 7.939296 |
module corebit_not (
input in,
output out
);
assign out = ~in;
endmodule
| 8.318293 |
module NE4 (
input [3:0] I0,
input [3:0] I1,
output O
);
wire coreir_eq_4_inst0_out;
wire not_inst0_out;
coreir_eq #(
.width(4)
) coreir_eq_4_inst0 (
.in0(I0),
.in1(I1),
.out(coreir_eq_4_inst0_out)
);
corebit_not not_inst0 (
.in (coreir_eq_4_inst0_out),
.out(n... | 7.333423 |
module NE4 (
input [3:0] I0,
input [3:0] I1,
output O
);
wire SB_LUT4_inst0_O;
wire SB_LUT4_inst1_O;
wire SB_LUT4_inst2_O;
wire SB_LUT4_inst3_O;
SB_LUT4 #(
.LUT_INIT(16'hBEBE)
) SB_LUT4_inst0 (
.I0(1'b0),
.I1(I0[0]),
.I2(I1[0]),
.I3(1'b0),
.O (SB_LUT4_inst0_O)... | 7.333423 |
module NE4 (
input [3:0] I0,
input [3:0] I1,
output O
);
wire LUT4_inst0_O;
wire MUXCY_inst0_O;
wire LUT4_inst1_O;
wire MUXCY_inst1_O;
LUT4 #(
.INIT(16'h6FF6)
) LUT4_inst0 (
.I0(I0[0]),
.I1(I1[0]),
.I2(I0[1]),
.I3(I1[1]),
.O (LUT4_inst0_O)
);
MUXCY MUXCY_i... | 7.333423 |
module NE4 (
input [3:0] I0,
input [3:0] I1,
output O
);
wire LUT6_2_inst0_O5;
wire LUT6_2_inst0_O6;
wire MUXCY_inst0_O;
wire LUT6_2_inst1_O5;
wire LUT6_2_inst1_O6;
wire MUXCY_inst1_O;
LUT6_2 #(
.INIT(64'h6FF66FF600000000)
) LUT6_2_inst0 (
.I0(I0[0]),
.I1(I1[0]),
.I2(... | 7.333423 |
module NE8 (
input [7:0] I0,
input [7:0] I1,
output O
);
assign O = ~(I0 == I1);
endmodule
| 7.080079 |
module coreir_eq #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output out
);
assign out = in0 == in1;
endmodule
| 7.939296 |
module corebit_not (
input in,
output out
);
assign out = ~in;
endmodule
| 8.318293 |
module NE8 (
input [7:0] I0,
input [7:0] I1,
output O
);
wire coreir_eq_8_inst0_out;
wire not_inst0_out;
coreir_eq #(
.width(8)
) coreir_eq_8_inst0 (
.in0(I0),
.in1(I1),
.out(coreir_eq_8_inst0_out)
);
corebit_not not_inst0 (
.in (coreir_eq_8_inst0_out),
.out(n... | 7.080079 |
module NE8 (
input [7:0] I0,
input [7:0] I1,
output O
);
wire SB_LUT4_inst0_O;
wire SB_LUT4_inst1_O;
wire SB_LUT4_inst2_O;
wire SB_LUT4_inst3_O;
wire SB_LUT4_inst4_O;
wire SB_LUT4_inst5_O;
wire SB_LUT4_inst6_O;
wire SB_LUT4_inst7_O;
SB_LUT4 #(
.LUT_INIT(16'hBEBE)
) SB_LUT4_inst0 (
... | 7.080079 |
module NE8 (
input [7:0] I0,
input [7:0] I1,
output O
);
wire LUT4_inst0_O;
wire MUXCY_inst0_O;
wire LUT4_inst1_O;
wire MUXCY_inst1_O;
wire LUT4_inst2_O;
wire MUXCY_inst2_O;
wire LUT4_inst3_O;
wire MUXCY_inst3_O;
LUT4 #(
.INIT(16'h6FF6)
) LUT4_inst0 (
.I0(I0[0]),
.I1(I1... | 7.080079 |
module NE8 (
input [7:0] I0,
input [7:0] I1,
output O
);
wire LUT6_2_inst0_O5;
wire LUT6_2_inst0_O6;
wire MUXCY_inst0_O;
wire LUT6_2_inst1_O5;
wire LUT6_2_inst1_O6;
wire MUXCY_inst1_O;
wire LUT6_2_inst2_O5;
wire LUT6_2_inst2_O6;
wire MUXCY_inst2_O;
wire LUT6_2_inst3_O5;
wire LUT6_2_ins... | 7.080079 |
module or2_wrapped (
input [1:0] I0,
input [1:0] I1,
output [1:0] O
);
assign O = I0 | I1;
endmodule
| 8.416424 |
module coreir_or #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output [width-1:0] out
);
assign out = in0 | in1;
endmodule
| 8.25836 |
module or2_wrapped (
input [1:0] I0,
input [1:0] I1,
output [1:0] O
);
wire [1:0] or2_inst0_out;
coreir_or #(
.width(2)
) or2_inst0 (
.in0(I0),
.in1(I1),
.out(or2_inst0_out)
);
assign O = or2_inst0_out;
endmodule
| 8.416424 |
module Or2 (
input [1:0] I,
output O
);
wire SB_LUT4_inst0_O;
SB_LUT4 #(
.LUT_INIT(16'hEEEE)
) SB_LUT4_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(1'b0),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
assign O = SB_LUT4_inst0_O;
endmodule
| 7.624303 |
module Or2x2 (
input [1:0] I0,
input [1:0] I1,
output [1:0] O
);
wire Or2_inst0_O;
wire Or2_inst1_O;
Or2 Or2_inst0 (
.I({I1[0], I0[0]}),
.O(Or2_inst0_O)
);
Or2 Or2_inst1 (
.I({I1[1], I0[1]}),
.O(Or2_inst1_O)
);
assign O = {Or2_inst1_O, Or2_inst0_O};
endmodule
| 7.870093 |
module Or2 (
input [1:0] I,
output O
);
wire LUT2_inst0_O;
LUT2 #(
.INIT(4'h1)
) LUT2_inst0 (
.I0(I[0]),
.I1(I[1]),
.O (LUT2_inst0_O)
);
assign O = LUT2_inst0_O;
endmodule
| 7.624303 |
module Or2x2 (
input [1:0] I0,
input [1:0] I1,
output [1:0] O
);
wire Or2_inst0_O;
wire Or2_inst1_O;
Or2 Or2_inst0 (
.I({I1[0], I0[0]}),
.O(Or2_inst0_O)
);
Or2 Or2_inst1 (
.I({I1[1], I0[1]}),
.O(Or2_inst1_O)
);
assign O = {Or2_inst1_O, Or2_inst0_O};
endmodule
| 7.870093 |
module Or2 (
input [1:0] I,
output O
);
wire LUT2_inst0_O;
LUT2 #(
.INIT(4'h1)
) LUT2_inst0 (
.I0(I[0]),
.I1(I[1]),
.O (LUT2_inst0_O)
);
assign O = LUT2_inst0_O;
endmodule
| 7.624303 |
module Or2x2 (
input [1:0] I0,
input [1:0] I1,
output [1:0] O
);
wire Or2_inst0_O;
wire Or2_inst1_O;
Or2 Or2_inst0 (
.I({I1[0], I0[0]}),
.O(Or2_inst0_O)
);
Or2 Or2_inst1 (
.I({I1[1], I0[1]}),
.O(Or2_inst1_O)
);
assign O = {Or2_inst1_O, Or2_inst0_O};
endmodule
| 7.870093 |
module or4_wrapped (
input [3:0] I0,
input [3:0] I1,
output [3:0] O
);
assign O = I0 | I1;
endmodule
| 8.263764 |
module coreir_or #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output [width-1:0] out
);
assign out = in0 | in1;
endmodule
| 8.25836 |
module or4_wrapped (
input [3:0] I0,
input [3:0] I1,
output [3:0] O
);
wire [3:0] or4_inst0_out;
coreir_or #(
.width(4)
) or4_inst0 (
.in0(I0),
.in1(I1),
.out(or4_inst0_out)
);
assign O = or4_inst0_out;
endmodule
| 8.263764 |
module Or2 (
input [1:0] I,
output O
);
wire SB_LUT4_inst0_O;
SB_LUT4 #(
.LUT_INIT(16'hEEEE)
) SB_LUT4_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(1'b0),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
assign O = SB_LUT4_inst0_O;
endmodule
| 7.624303 |
module Or2x4 (
input [3:0] I0,
input [3:0] I1,
output [3:0] O
);
wire Or2_inst0_O;
wire Or2_inst1_O;
wire Or2_inst2_O;
wire Or2_inst3_O;
Or2 Or2_inst0 (
.I({I1[0], I0[0]}),
.O(Or2_inst0_O)
);
Or2 Or2_inst1 (
.I({I1[1], I0[1]}),
.O(Or2_inst1_O)
);
Or2 Or2_inst2 (
... | 7.242632 |
module Or2 (
input [1:0] I,
output O
);
wire LUT2_inst0_O;
LUT2 #(
.INIT(4'h1)
) LUT2_inst0 (
.I0(I[0]),
.I1(I[1]),
.O (LUT2_inst0_O)
);
assign O = LUT2_inst0_O;
endmodule
| 7.624303 |
module Or2x4 (
input [3:0] I0,
input [3:0] I1,
output [3:0] O
);
wire Or2_inst0_O;
wire Or2_inst1_O;
wire Or2_inst2_O;
wire Or2_inst3_O;
Or2 Or2_inst0 (
.I({I1[0], I0[0]}),
.O(Or2_inst0_O)
);
Or2 Or2_inst1 (
.I({I1[1], I0[1]}),
.O(Or2_inst1_O)
);
Or2 Or2_inst2 (
... | 7.242632 |
module Or2 (
input [1:0] I,
output O
);
wire LUT2_inst0_O;
LUT2 #(
.INIT(4'h1)
) LUT2_inst0 (
.I0(I[0]),
.I1(I[1]),
.O (LUT2_inst0_O)
);
assign O = LUT2_inst0_O;
endmodule
| 7.624303 |
module Or2x4 (
input [3:0] I0,
input [3:0] I1,
output [3:0] O
);
wire Or2_inst0_O;
wire Or2_inst1_O;
wire Or2_inst2_O;
wire Or2_inst3_O;
Or2 Or2_inst0 (
.I({I1[0], I0[0]}),
.O(Or2_inst0_O)
);
Or2 Or2_inst1 (
.I({I1[1], I0[1]}),
.O(Or2_inst1_O)
);
Or2 Or2_inst2 (
... | 7.242632 |
module or8_wrapped (
input [7:0] I0,
input [7:0] I1,
output [7:0] O
);
assign O = I0 | I1;
endmodule
| 8.217435 |
module coreir_or #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output [width-1:0] out
);
assign out = in0 | in1;
endmodule
| 8.25836 |
module or8_wrapped (
input [7:0] I0,
input [7:0] I1,
output [7:0] O
);
wire [7:0] or8_inst0_out;
coreir_or #(
.width(8)
) or8_inst0 (
.in0(I0),
.in1(I1),
.out(or8_inst0_out)
);
assign O = or8_inst0_out;
endmodule
| 8.217435 |
module Or2 (
input [1:0] I,
output O
);
wire SB_LUT4_inst0_O;
SB_LUT4 #(
.LUT_INIT(16'hEEEE)
) SB_LUT4_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(1'b0),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
assign O = SB_LUT4_inst0_O;
endmodule
| 7.624303 |
module Or2x8 (
input [7:0] I0,
input [7:0] I1,
output [7:0] O
);
wire Or2_inst0_O;
wire Or2_inst1_O;
wire Or2_inst2_O;
wire Or2_inst3_O;
wire Or2_inst4_O;
wire Or2_inst5_O;
wire Or2_inst6_O;
wire Or2_inst7_O;
Or2 Or2_inst0 (
.I({I1[0], I0[0]}),
.O(Or2_inst0_O)
);
Or2 Or2_... | 6.972293 |
module Or2 (
input [1:0] I,
output O
);
wire LUT2_inst0_O;
LUT2 #(
.INIT(4'h1)
) LUT2_inst0 (
.I0(I[0]),
.I1(I[1]),
.O (LUT2_inst0_O)
);
assign O = LUT2_inst0_O;
endmodule
| 7.624303 |
module Or2x8 (
input [7:0] I0,
input [7:0] I1,
output [7:0] O
);
wire Or2_inst0_O;
wire Or2_inst1_O;
wire Or2_inst2_O;
wire Or2_inst3_O;
wire Or2_inst4_O;
wire Or2_inst5_O;
wire Or2_inst6_O;
wire Or2_inst7_O;
Or2 Or2_inst0 (
.I({I1[0], I0[0]}),
.O(Or2_inst0_O)
);
Or2 Or2_... | 6.972293 |
module Or2 (
input [1:0] I,
output O
);
wire LUT2_inst0_O;
LUT2 #(
.INIT(4'h1)
) LUT2_inst0 (
.I0(I[0]),
.I1(I[1]),
.O (LUT2_inst0_O)
);
assign O = LUT2_inst0_O;
endmodule
| 7.624303 |
module Or2x8 (
input [7:0] I0,
input [7:0] I1,
output [7:0] O
);
wire Or2_inst0_O;
wire Or2_inst1_O;
wire Or2_inst2_O;
wire Or2_inst3_O;
wire Or2_inst4_O;
wire Or2_inst5_O;
wire Or2_inst6_O;
wire Or2_inst7_O;
Or2 Or2_inst0 (
.I({I1[0], I0[0]}),
.O(Or2_inst0_O)
);
Or2 Or2_... | 6.972293 |
module Or4x2 (
input [1:0] I0,
input [1:0] I1,
input [1:0] I2,
input [1:0] I3,
output [1:0] O
);
assign O = {|({I3[1], I2[1], I1[1], I0[1]}), |({I3[0], I2[0], I1[0], I0[0]})};
endmodule
| 7.266415 |
module coreir_orr #(
parameter width = 1
) (
input [width-1:0] in,
output out
);
assign out = |in;
endmodule
| 8.413586 |
module Or4x2 (
input [1:0] I0,
input [1:0] I1,
input [1:0] I2,
input [1:0] I3,
output [1:0] O
);
wire orr_inst0_out;
wire orr_inst1_out;
wire [3:0] orr_inst0_in;
assign orr_inst0_in = {I3[0], I2[0], I1[0], I0[0]};
coreir_orr #(
.width(4)
) orr_inst0 (
.in (orr_inst0_in),
... | 7.266415 |
module Or4 (
input [3:0] I,
output O
);
wire SB_LUT4_inst0_O;
SB_LUT4 #(
.LUT_INIT(16'hFFFE)
) SB_LUT4_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(I[2]),
.I3(I[3]),
.O (SB_LUT4_inst0_O)
);
assign O = SB_LUT4_inst0_O;
endmodule
| 6.96089 |
module Or4x2 (
input [1:0] I0,
input [1:0] I1,
input [1:0] I2,
input [1:0] I3,
output [1:0] O
);
wire Or4_inst0_O;
wire Or4_inst1_O;
Or4 Or4_inst0 (
.I({I3[0], I2[0], I1[0], I0[0]}),
.O(Or4_inst0_O)
);
Or4 Or4_inst1 (
.I({I3[1], I2[1], I1[1], I0[1]}),
.O(Or4_ins... | 7.266415 |
module Or4 (
input [3:0] I,
output O
);
wire LUT4_inst0_O;
LUT4 #(
.INIT(16'h0001)
) LUT4_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(I[2]),
.I3(I[3]),
.O (LUT4_inst0_O)
);
assign O = LUT4_inst0_O;
endmodule
| 6.96089 |
module Or4x2 (
input [1:0] I0,
input [1:0] I1,
input [1:0] I2,
input [1:0] I3,
output [1:0] O
);
wire Or4_inst0_O;
wire Or4_inst1_O;
Or4 Or4_inst0 (
.I({I3[0], I2[0], I1[0], I0[0]}),
.O(Or4_inst0_O)
);
Or4 Or4_inst1 (
.I({I3[1], I2[1], I1[1], I0[1]}),
.O(Or4_ins... | 7.266415 |
module Or4 (
input [3:0] I,
output O
);
wire LUT4_inst0_O;
LUT4 #(
.INIT(16'h0001)
) LUT4_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(I[2]),
.I3(I[3]),
.O (LUT4_inst0_O)
);
assign O = LUT4_inst0_O;
endmodule
| 6.96089 |
module Or4x2 (
input [1:0] I0,
input [1:0] I1,
input [1:0] I2,
input [1:0] I3,
output [1:0] O
);
wire Or4_inst0_O;
wire Or4_inst1_O;
Or4 Or4_inst0 (
.I({I3[0], I2[0], I1[0], I0[0]}),
.O(Or4_inst0_O)
);
Or4 Or4_inst1 (
.I({I3[1], I2[1], I1[1], I0[1]}),
.O(Or4_ins... | 7.266415 |
module Or4x4 (
input [3:0] I0,
input [3:0] I1,
input [3:0] I2,
input [3:0] I3,
output [3:0] O
);
assign O = {
|({I3[3], I2[3], I1[3], I0[3]}),
|({I3[2], I2[2], I1[2], I0[2]}),
|({I3[1], I2[1], I1[1], I0[1]}),
|({I3[0], I2[0], I1[0], I0[0]})
};
endmodule
| 7.273789 |
module coreir_orr #(
parameter width = 1
) (
input [width-1:0] in,
output out
);
assign out = |in;
endmodule
| 8.413586 |
module Or4x4 (
input [3:0] I0,
input [3:0] I1,
input [3:0] I2,
input [3:0] I3,
output [3:0] O
);
wire orr_inst0_out;
wire orr_inst1_out;
wire orr_inst2_out;
wire orr_inst3_out;
wire [3:0] orr_inst0_in;
assign orr_inst0_in = {I3[0], I2[0], I1[0], I0[0]};
coreir_orr #(
.width(4... | 7.273789 |
module Or4 (
input [3:0] I,
output O
);
wire SB_LUT4_inst0_O;
SB_LUT4 #(
.LUT_INIT(16'hFFFE)
) SB_LUT4_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(I[2]),
.I3(I[3]),
.O (SB_LUT4_inst0_O)
);
assign O = SB_LUT4_inst0_O;
endmodule
| 6.96089 |
module Or4x4 (
input [3:0] I0,
input [3:0] I1,
input [3:0] I2,
input [3:0] I3,
output [3:0] O
);
wire Or4_inst0_O;
wire Or4_inst1_O;
wire Or4_inst2_O;
wire Or4_inst3_O;
Or4 Or4_inst0 (
.I({I3[0], I2[0], I1[0], I0[0]}),
.O(Or4_inst0_O)
);
Or4 Or4_inst1 (
.I({I3[1],... | 7.273789 |
module Or4 (
input [3:0] I,
output O
);
wire LUT4_inst0_O;
LUT4 #(
.INIT(16'h0001)
) LUT4_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(I[2]),
.I3(I[3]),
.O (LUT4_inst0_O)
);
assign O = LUT4_inst0_O;
endmodule
| 6.96089 |
module Or4x4 (
input [3:0] I0,
input [3:0] I1,
input [3:0] I2,
input [3:0] I3,
output [3:0] O
);
wire Or4_inst0_O;
wire Or4_inst1_O;
wire Or4_inst2_O;
wire Or4_inst3_O;
Or4 Or4_inst0 (
.I({I3[0], I2[0], I1[0], I0[0]}),
.O(Or4_inst0_O)
);
Or4 Or4_inst1 (
.I({I3[1],... | 7.273789 |
module Or4 (
input [3:0] I,
output O
);
wire LUT4_inst0_O;
LUT4 #(
.INIT(16'h0001)
) LUT4_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(I[2]),
.I3(I[3]),
.O (LUT4_inst0_O)
);
assign O = LUT4_inst0_O;
endmodule
| 6.96089 |
module Or4x4 (
input [3:0] I0,
input [3:0] I1,
input [3:0] I2,
input [3:0] I3,
output [3:0] O
);
wire Or4_inst0_O;
wire Or4_inst1_O;
wire Or4_inst2_O;
wire Or4_inst3_O;
Or4 Or4_inst0 (
.I({I3[0], I2[0], I1[0], I0[0]}),
.O(Or4_inst0_O)
);
Or4 Or4_inst1 (
.I({I3[1],... | 7.273789 |
module Or4x8 (
input [7:0] I0,
input [7:0] I1,
input [7:0] I2,
input [7:0] I3,
output [7:0] O
);
assign O = {
|({I3[7], I2[7], I1[7], I0[7]}),
|({I3[6], I2[6], I1[6], I0[6]}),
|({I3[5], I2[5], I1[5], I0[5]}),
|({I3[4], I2[4], I1[4], I0[4]}),
|({I3[3], I2[3], I1[3], I0[3]}),... | 7.017397 |
module coreir_orr #(
parameter width = 1
) (
input [width-1:0] in,
output out
);
assign out = |in;
endmodule
| 8.413586 |
module Or4x8 (
input [7:0] I0,
input [7:0] I1,
input [7:0] I2,
input [7:0] I3,
output [7:0] O
);
wire orr_inst0_out;
wire orr_inst1_out;
wire orr_inst2_out;
wire orr_inst3_out;
wire orr_inst4_out;
wire orr_inst5_out;
wire orr_inst6_out;
wire orr_inst7_out;
wire [3:0] orr_inst0_... | 7.017397 |
module Or4 (
input [3:0] I,
output O
);
wire SB_LUT4_inst0_O;
SB_LUT4 #(
.LUT_INIT(16'hFFFE)
) SB_LUT4_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(I[2]),
.I3(I[3]),
.O (SB_LUT4_inst0_O)
);
assign O = SB_LUT4_inst0_O;
endmodule
| 6.96089 |
module Or4x8 (
input [7:0] I0,
input [7:0] I1,
input [7:0] I2,
input [7:0] I3,
output [7:0] O
);
wire Or4_inst0_O;
wire Or4_inst1_O;
wire Or4_inst2_O;
wire Or4_inst3_O;
wire Or4_inst4_O;
wire Or4_inst5_O;
wire Or4_inst6_O;
wire Or4_inst7_O;
Or4 Or4_inst0 (
.I({I3[0], I2[0... | 7.017397 |
module Or4 (
input [3:0] I,
output O
);
wire LUT4_inst0_O;
LUT4 #(
.INIT(16'h0001)
) LUT4_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(I[2]),
.I3(I[3]),
.O (LUT4_inst0_O)
);
assign O = LUT4_inst0_O;
endmodule
| 6.96089 |
module Or4x8 (
input [7:0] I0,
input [7:0] I1,
input [7:0] I2,
input [7:0] I3,
output [7:0] O
);
wire Or4_inst0_O;
wire Or4_inst1_O;
wire Or4_inst2_O;
wire Or4_inst3_O;
wire Or4_inst4_O;
wire Or4_inst5_O;
wire Or4_inst6_O;
wire Or4_inst7_O;
Or4 Or4_inst0 (
.I({I3[0], I2[0... | 7.017397 |
module Or4 (
input [3:0] I,
output O
);
wire LUT4_inst0_O;
LUT4 #(
.INIT(16'h0001)
) LUT4_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(I[2]),
.I3(I[3]),
.O (LUT4_inst0_O)
);
assign O = LUT4_inst0_O;
endmodule
| 6.96089 |
module Or4x8 (
input [7:0] I0,
input [7:0] I1,
input [7:0] I2,
input [7:0] I3,
output [7:0] O
);
wire Or4_inst0_O;
wire Or4_inst1_O;
wire Or4_inst2_O;
wire Or4_inst3_O;
wire Or4_inst4_O;
wire Or4_inst5_O;
wire Or4_inst6_O;
wire Or4_inst7_O;
Or4 Or4_inst0 (
.I({I3[0], I2[0... | 7.017397 |
module Or8x2 (
input [1:0] I0,
input [1:0] I1,
input [1:0] I2,
input [1:0] I3,
input [1:0] I4,
input [1:0] I5,
input [1:0] I6,
input [1:0] I7,
output [1:0] O
);
assign O = {
|({I7[1], I6[1], I5[1], I4[1], I3[1], I2[1], I1[1], I0[1]}),
|({I7[0], I6[0], I5[0], I4[0], ... | 7.823943 |
module coreir_orr #(
parameter width = 1
) (
input [width-1:0] in,
output out
);
assign out = |in;
endmodule
| 8.413586 |
module Or8x2 (
input [1:0] I0,
input [1:0] I1,
input [1:0] I2,
input [1:0] I3,
input [1:0] I4,
input [1:0] I5,
input [1:0] I6,
input [1:0] I7,
output [1:0] O
);
wire orr_inst0_out;
wire orr_inst1_out;
wire [7:0] orr_inst0_in;
assign orr_inst0_in = {I7[0], I6[0], I5[0]... | 7.823943 |
module Or8x2 (
input [1:0] I0,
input [1:0] I1,
input [1:0] I2,
input [1:0] I3,
input [1:0] I4,
input [1:0] I5,
input [1:0] I6,
input [1:0] I7,
output [1:0] O
);
wire Or8_inst0_O;
wire Or8_inst1_O;
Or8 Or8_inst0 (
.I({I7[0], I6[0], I5[0], I4[0], I3[0], I2[0], I1[0]... | 7.823943 |
module Or8x2 (
input [1:0] I0,
input [1:0] I1,
input [1:0] I2,
input [1:0] I3,
input [1:0] I4,
input [1:0] I5,
input [1:0] I6,
input [1:0] I7,
output [1:0] O
);
wire Or8_inst0_O;
wire Or8_inst1_O;
Or8 Or8_inst0 (
.I({I7[0], I6[0], I5[0], I4[0], I3[0], I2[0], I1[0]... | 7.823943 |
module Or8x2 (
input [1:0] I0,
input [1:0] I1,
input [1:0] I2,
input [1:0] I3,
input [1:0] I4,
input [1:0] I5,
input [1:0] I6,
input [1:0] I7,
output [1:0] O
);
wire Or8_inst0_O;
wire Or8_inst1_O;
Or8 Or8_inst0 (
.I({I7[0], I6[0], I5[0], I4[0], I3[0], I2[0], I1[0]... | 7.823943 |
module Or8x4 (
input [3:0] I0,
input [3:0] I1,
input [3:0] I2,
input [3:0] I3,
input [3:0] I4,
input [3:0] I5,
input [3:0] I6,
input [3:0] I7,
output [3:0] O
);
assign O = {
|({I7[3], I6[3], I5[3], I4[3], I3[3], I2[3], I1[3], I0[3]}),
|({I7[2], I6[2], I5[2], I4[2], ... | 7.289546 |
module coreir_orr #(
parameter width = 1
) (
input [width-1:0] in,
output out
);
assign out = |in;
endmodule
| 8.413586 |
module Or8x4 (
input [3:0] I0,
input [3:0] I1,
input [3:0] I2,
input [3:0] I3,
input [3:0] I4,
input [3:0] I5,
input [3:0] I6,
input [3:0] I7,
output [3:0] O
);
wire orr_inst0_out;
wire orr_inst1_out;
wire orr_inst2_out;
wire orr_inst3_out;
wire [7:0] orr_inst0_in;
... | 7.289546 |
module Or8x4 (
input [3:0] I0,
input [3:0] I1,
input [3:0] I2,
input [3:0] I3,
input [3:0] I4,
input [3:0] I5,
input [3:0] I6,
input [3:0] I7,
output [3:0] O
);
wire Or8_inst0_O;
wire Or8_inst1_O;
wire Or8_inst2_O;
wire Or8_inst3_O;
Or8 Or8_inst0 (
.I({I7[0], ... | 7.289546 |
module Or8x4 (
input [3:0] I0,
input [3:0] I1,
input [3:0] I2,
input [3:0] I3,
input [3:0] I4,
input [3:0] I5,
input [3:0] I6,
input [3:0] I7,
output [3:0] O
);
wire Or8_inst0_O;
wire Or8_inst1_O;
wire Or8_inst2_O;
wire Or8_inst3_O;
Or8 Or8_inst0 (
.I({I7[0], ... | 7.289546 |
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