code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module Or8x4 (
input [3:0] I0,
input [3:0] I1,
input [3:0] I2,
input [3:0] I3,
input [3:0] I4,
input [3:0] I5,
input [3:0] I6,
input [3:0] I7,
output [3:0] O
);
wire Or8_inst0_O;
wire Or8_inst1_O;
wire Or8_inst2_O;
wire Or8_inst3_O;
Or8 Or8_inst0 (
.I({I7[0], ... | 7.289546 |
module Or8x8 (
input [7:0] I0,
input [7:0] I1,
input [7:0] I2,
input [7:0] I3,
input [7:0] I4,
input [7:0] I5,
input [7:0] I6,
input [7:0] I7,
output [7:0] O
);
assign O = {
|({I7[7], I6[7], I5[7], I4[7], I3[7], I2[7], I1[7], I0[7]}),
|({I7[6], I6[6], I5[6], I4[6], ... | 7.05471 |
module coreir_orr #(
parameter width = 1
) (
input [width-1:0] in,
output out
);
assign out = |in;
endmodule
| 8.413586 |
module Or8x8 (
input [7:0] I0,
input [7:0] I1,
input [7:0] I2,
input [7:0] I3,
input [7:0] I4,
input [7:0] I5,
input [7:0] I6,
input [7:0] I7,
output [7:0] O
);
wire orr_inst0_out;
wire orr_inst1_out;
wire orr_inst2_out;
wire orr_inst3_out;
wire orr_inst4_out;
wir... | 7.05471 |
module Or8x8 (
input [7:0] I0,
input [7:0] I1,
input [7:0] I2,
input [7:0] I3,
input [7:0] I4,
input [7:0] I5,
input [7:0] I6,
input [7:0] I7,
output [7:0] O
);
wire Or8_inst0_O;
wire Or8_inst1_O;
wire Or8_inst2_O;
wire Or8_inst3_O;
wire Or8_inst4_O;
wire Or8_inst... | 7.05471 |
module Or8x8 (
input [7:0] I0,
input [7:0] I1,
input [7:0] I2,
input [7:0] I3,
input [7:0] I4,
input [7:0] I5,
input [7:0] I6,
input [7:0] I7,
output [7:0] O
);
wire Or8_inst0_O;
wire Or8_inst1_O;
wire Or8_inst2_O;
wire Or8_inst3_O;
wire Or8_inst4_O;
wire Or8_inst... | 7.05471 |
module Or8x8 (
input [7:0] I0,
input [7:0] I1,
input [7:0] I2,
input [7:0] I3,
input [7:0] I4,
input [7:0] I5,
input [7:0] I6,
input [7:0] I7,
output [7:0] O
);
wire Or8_inst0_O;
wire Or8_inst1_O;
wire Or8_inst2_O;
wire Or8_inst3_O;
wire Or8_inst4_O;
wire Or8_inst... | 7.05471 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= ... | 7.868877 |
module Mux2xNone (
input I0,
input I1,
input S,
output O
);
reg [0:0] coreir_commonlib_mux2x1_inst0_out;
always @(*) begin
if (S == 0) begin
coreir_commonlib_mux2x1_inst0_out = I0;
end else begin
coreir_commonlib_mux2x1_inst0_out = I1;
end
end
assign O = coreir_common... | 8.404032 |
module Register2 (
input [1:0] I,
output [1:0] O,
input CLK
);
wire DFF_init0_has_ceFalse_has_resetFalse_has_async_resetFalse_inst0_O;
wire DFF_init0_has_ceFalse_has_resetFalse_has_async_resetFalse_inst1_O;
DFF_init0_has_ceFalse_has_resetFalse_has_async_resetFalse DFF_init0_has_ceFalse_has_resetFalse_... | 6.626169 |
module PISO2 (
input SI,
input [1:0] PI,
input LOAD,
output O,
input CLK
);
wire Mux2xNone_inst0_O;
wire Mux2xNone_inst1_O;
wire [1:0] Register2_inst0_O;
Mux2xNone Mux2xNone_inst0 (
.I0(SI),
.I1(PI[0]),
.S (LOAD),
.O (Mux2xNone_inst0_O)
);
Mux2xNone Mux2xNone_inst... | 8.258037 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= ... | 7.868877 |
module coreir_mux #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
input sel,
output [width-1:0] out
);
assign out = sel ? in1 : in0;
endmodule
| 8.809699 |
module commonlib_muxn__N2__width1 (
input [0:0] in_data[1:0],
input [0:0] in_sel,
output [0:0] out
);
wire [0:0] _join_out;
coreir_mux #(
.width(1)
) _join (
.in0(in_data[0]),
.in1(in_data[1]),
.sel(in_sel[0]),
.out(_join_out)
);
assign out = _join_out;
endmodule
| 7.978522 |
module Mux2xNone (
input I0,
input I1,
input S,
output O
);
wire [0:0] coreir_commonlib_mux2x1_inst0_out;
wire [0:0] coreir_commonlib_mux2x1_inst0_in_data[1:0];
assign coreir_commonlib_mux2x1_inst0_in_data[1] = I1;
assign coreir_commonlib_mux2x1_inst0_in_data[0] = I0;
commonlib_muxn__N2__wi... | 8.404032 |
module Register2 (
input [1:0] I,
output [1:0] O,
input CLK
);
wire DFF_init0_has_ceFalse_has_resetFalse_has_async_resetFalse_inst0_O;
wire DFF_init0_has_ceFalse_has_resetFalse_has_async_resetFalse_inst1_O;
DFF_init0_has_ceFalse_has_resetFalse_has_async_resetFalse DFF_init0_has_ceFalse_has_resetFalse_... | 6.626169 |
module PISO2 (
input SI,
input [1:0] PI,
input LOAD,
output O,
input CLK
);
wire Mux2xNone_inst0_O;
wire Mux2xNone_inst1_O;
wire [1:0] Register2_inst0_O;
Mux2xNone Mux2xNone_inst0 (
.I0(SI),
.I1(PI[0]),
.S (LOAD),
.O (Mux2xNone_inst0_O)
);
Mux2xNone Mux2xNone_inst... | 8.258037 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire SB_LUT4_inst0_O;
SB_LUT4 #(
.LUT_INIT(16'hCACA)
) SB_LUT4_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
assign O = SB_LUT4_inst0_O;
endmodule
| 7.615389 |
module Register2 (
input [1:0] I,
output [1:0] O,
input CLK
);
wire SB_DFF_inst0_Q;
wire SB_DFF_inst1_Q;
SB_DFF SB_DFF_inst0 (
.C(CLK),
.D(I[0]),
.Q(SB_DFF_inst0_Q)
);
SB_DFF SB_DFF_inst1 (
.C(CLK),
.D(I[1]),
.Q(SB_DFF_inst1_Q)
);
assign O = {SB_DFF_inst1_Q,... | 6.626169 |
module PISO2 (
input SI,
input [1:0] PI,
input LOAD,
output O,
input CLK
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
wire [1:0] Register2_inst0_O;
Mux2 Mux2_inst0 (
.I({PI[0], SI}),
.S(LOAD),
.O(Mux2_inst0_O)
);
Mux2 Mux2_inst1 (
.I({PI[1], Register2_inst0_O[0]}),
... | 8.258037 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire LUT3_inst0_O;
LUT3 #(
.INIT(8'hCA)
) LUT3_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.O (LUT3_inst0_O)
);
assign O = LUT3_inst0_O;
endmodule
| 7.615389 |
module Register2 (
input [1:0] I,
output [1:0] O,
input CLK
);
wire FDRSE_inst0_Q;
wire FDRSE_inst1_Q;
FDRSE #(
.INIT(1'h0)
) FDRSE_inst0 (
.C (CLK),
.CE(1'b1),
.R (1'b0),
.S (1'b0),
.D (I[0]),
.Q (FDRSE_inst0_Q)
);
FDRSE #(
.INIT(1'h0)
) FDRSE_i... | 6.626169 |
module PISO2 (
input SI,
input [1:0] PI,
input LOAD,
output O,
input CLK
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
wire [1:0] Register2_inst0_O;
Mux2 Mux2_inst0 (
.I({PI[0], SI}),
.S(LOAD),
.O(Mux2_inst0_O)
);
Mux2 Mux2_inst1 (
.I({PI[1], Register2_inst0_O[0]}),
... | 8.258037 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire LUT3_inst0_O;
LUT3 #(
.INIT(8'hCA)
) LUT3_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.O (LUT3_inst0_O)
);
assign O = LUT3_inst0_O;
endmodule
| 7.615389 |
module Register2 (
input [1:0] I,
output [1:0] O,
input CLK
);
wire FDRSE_inst0_Q;
wire FDRSE_inst1_Q;
FDRSE #(
.INIT(1'h0)
) FDRSE_inst0 (
.C (CLK),
.CE(1'b1),
.R (1'b0),
.S (1'b0),
.D (I[0]),
.Q (FDRSE_inst0_Q)
);
FDRSE #(
.INIT(1'h0)
) FDRSE_i... | 6.626169 |
module PISO2 (
input SI,
input [1:0] PI,
input LOAD,
output O,
input CLK
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
wire [1:0] Register2_inst0_O;
Mux2 Mux2_inst0 (
.I({PI[0], SI}),
.S(LOAD),
.O(Mux2_inst0_O)
);
Mux2 Mux2_inst1 (
.I({PI[1], Register2_inst0_O[0]}),
... | 8.258037 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= ... | 7.868877 |
module Mux2xNone (
input I0,
input I1,
input S,
output O
);
reg [0:0] coreir_commonlib_mux2x1_inst0_out;
always @(*) begin
if (S == 0) begin
coreir_commonlib_mux2x1_inst0_out = I0;
end else begin
coreir_commonlib_mux2x1_inst0_out = I1;
end
end
assign O = coreir_common... | 8.404032 |
module Register4 (
input [3:0] I,
output [3:0] O,
input CLK
);
wire DFF_init0_has_ceFalse_has_resetFalse_has_async_resetFalse_inst0_O;
wire DFF_init0_has_ceFalse_has_resetFalse_has_async_resetFalse_inst1_O;
wire DFF_init0_has_ceFalse_has_resetFalse_has_async_resetFalse_inst2_O;
wire DFF_init0_has_ce... | 7.403606 |
module PISO4 (
input SI,
input [3:0] PI,
input LOAD,
output O,
input CLK
);
wire Mux2xNone_inst0_O;
wire Mux2xNone_inst1_O;
wire Mux2xNone_inst2_O;
wire Mux2xNone_inst3_O;
wire [3:0] Register4_inst0_O;
Mux2xNone Mux2xNone_inst0 (
.I0(SI),
.I1(PI[0]),
.S (LOAD),
.O... | 7.845645 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= ... | 7.868877 |
module coreir_mux #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
input sel,
output [width-1:0] out
);
assign out = sel ? in1 : in0;
endmodule
| 8.809699 |
module commonlib_muxn__N2__width1 (
input [0:0] in_data[1:0],
input [0:0] in_sel,
output [0:0] out
);
wire [0:0] _join_out;
coreir_mux #(
.width(1)
) _join (
.in0(in_data[0]),
.in1(in_data[1]),
.sel(in_sel[0]),
.out(_join_out)
);
assign out = _join_out;
endmodule
| 7.978522 |
module Mux2xNone (
input I0,
input I1,
input S,
output O
);
wire [0:0] coreir_commonlib_mux2x1_inst0_out;
wire [0:0] coreir_commonlib_mux2x1_inst0_in_data[1:0];
assign coreir_commonlib_mux2x1_inst0_in_data[1] = I1;
assign coreir_commonlib_mux2x1_inst0_in_data[0] = I0;
commonlib_muxn__N2__wi... | 8.404032 |
module Register4 (
input [3:0] I,
output [3:0] O,
input CLK
);
wire DFF_init0_has_ceFalse_has_resetFalse_has_async_resetFalse_inst0_O;
wire DFF_init0_has_ceFalse_has_resetFalse_has_async_resetFalse_inst1_O;
wire DFF_init0_has_ceFalse_has_resetFalse_has_async_resetFalse_inst2_O;
wire DFF_init0_has_ce... | 7.403606 |
module PISO4 (
input SI,
input [3:0] PI,
input LOAD,
output O,
input CLK
);
wire Mux2xNone_inst0_O;
wire Mux2xNone_inst1_O;
wire Mux2xNone_inst2_O;
wire Mux2xNone_inst3_O;
wire [3:0] Register4_inst0_O;
Mux2xNone Mux2xNone_inst0 (
.I0(SI),
.I1(PI[0]),
.S (LOAD),
.O... | 7.845645 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire SB_LUT4_inst0_O;
SB_LUT4 #(
.LUT_INIT(16'hCACA)
) SB_LUT4_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
assign O = SB_LUT4_inst0_O;
endmodule
| 7.615389 |
module Register4 (
input [3:0] I,
output [3:0] O,
input CLK
);
wire SB_DFF_inst0_Q;
wire SB_DFF_inst1_Q;
wire SB_DFF_inst2_Q;
wire SB_DFF_inst3_Q;
SB_DFF SB_DFF_inst0 (
.C(CLK),
.D(I[0]),
.Q(SB_DFF_inst0_Q)
);
SB_DFF SB_DFF_inst1 (
.C(CLK),
.D(I[1]),
.Q(SB_D... | 7.403606 |
module PISO4 (
input SI,
input [3:0] PI,
input LOAD,
output O,
input CLK
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
wire Mux2_inst2_O;
wire Mux2_inst3_O;
wire [3:0] Register4_inst0_O;
Mux2 Mux2_inst0 (
.I({PI[0], SI}),
.S(LOAD),
.O(Mux2_inst0_O)
);
Mux2 Mux2_inst1 (
... | 7.845645 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire LUT3_inst0_O;
LUT3 #(
.INIT(8'hCA)
) LUT3_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.O (LUT3_inst0_O)
);
assign O = LUT3_inst0_O;
endmodule
| 7.615389 |
module Register4 (
input [3:0] I,
output [3:0] O,
input CLK
);
wire FDRSE_inst0_Q;
wire FDRSE_inst1_Q;
wire FDRSE_inst2_Q;
wire FDRSE_inst3_Q;
FDRSE #(
.INIT(1'h0)
) FDRSE_inst0 (
.C (CLK),
.CE(1'b1),
.R (1'b0),
.S (1'b0),
.D (I[0]),
.Q (FDRSE_inst0_Q)
... | 7.403606 |
module PISO4 (
input SI,
input [3:0] PI,
input LOAD,
output O,
input CLK
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
wire Mux2_inst2_O;
wire Mux2_inst3_O;
wire [3:0] Register4_inst0_O;
Mux2 Mux2_inst0 (
.I({PI[0], SI}),
.S(LOAD),
.O(Mux2_inst0_O)
);
Mux2 Mux2_inst1 (
... | 7.845645 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire LUT3_inst0_O;
LUT3 #(
.INIT(8'hCA)
) LUT3_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.O (LUT3_inst0_O)
);
assign O = LUT3_inst0_O;
endmodule
| 7.615389 |
module Register4 (
input [3:0] I,
output [3:0] O,
input CLK
);
wire FDRSE_inst0_Q;
wire FDRSE_inst1_Q;
wire FDRSE_inst2_Q;
wire FDRSE_inst3_Q;
FDRSE #(
.INIT(1'h0)
) FDRSE_inst0 (
.C (CLK),
.CE(1'b1),
.R (1'b0),
.S (1'b0),
.D (I[0]),
.Q (FDRSE_inst0_Q)
... | 7.403606 |
module PISO4 (
input SI,
input [3:0] PI,
input LOAD,
output O,
input CLK
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
wire Mux2_inst2_O;
wire Mux2_inst3_O;
wire [3:0] Register4_inst0_O;
Mux2 Mux2_inst0 (
.I({PI[0], SI}),
.S(LOAD),
.O(Mux2_inst0_O)
);
Mux2 Mux2_inst1 (
... | 7.845645 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= ... | 7.868877 |
module Mux2xNone (
input I0,
input I1,
input S,
output O
);
reg [0:0] coreir_commonlib_mux2x1_inst0_out;
always @(*) begin
if (S == 0) begin
coreir_commonlib_mux2x1_inst0_out = I0;
end else begin
coreir_commonlib_mux2x1_inst0_out = I1;
end
end
assign O = coreir_common... | 8.404032 |
module Register8 (
input [7:0] I,
output [7:0] O,
input CLK
);
wire DFF_init0_has_ceFalse_has_resetFalse_has_async_resetFalse_inst0_O;
wire DFF_init0_has_ceFalse_has_resetFalse_has_async_resetFalse_inst1_O;
wire DFF_init0_has_ceFalse_has_resetFalse_has_async_resetFalse_inst2_O;
wire DFF_init0_has_ce... | 6.73316 |
module PISO8 (
input SI,
input [7:0] PI,
input LOAD,
output O,
input CLK
);
wire Mux2xNone_inst0_O;
wire Mux2xNone_inst1_O;
wire Mux2xNone_inst2_O;
wire Mux2xNone_inst3_O;
wire Mux2xNone_inst4_O;
wire Mux2xNone_inst5_O;
wire Mux2xNone_inst6_O;
wire Mux2xNone_inst7_O;
wire [7:0] Reg... | 7.793453 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= ... | 7.868877 |
module coreir_mux #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
input sel,
output [width-1:0] out
);
assign out = sel ? in1 : in0;
endmodule
| 8.809699 |
module commonlib_muxn__N2__width1 (
input [0:0] in_data[1:0],
input [0:0] in_sel,
output [0:0] out
);
wire [0:0] _join_out;
coreir_mux #(
.width(1)
) _join (
.in0(in_data[0]),
.in1(in_data[1]),
.sel(in_sel[0]),
.out(_join_out)
);
assign out = _join_out;
endmodule
| 7.978522 |
module Mux2xNone (
input I0,
input I1,
input S,
output O
);
wire [0:0] coreir_commonlib_mux2x1_inst0_out;
wire [0:0] coreir_commonlib_mux2x1_inst0_in_data[1:0];
assign coreir_commonlib_mux2x1_inst0_in_data[1] = I1;
assign coreir_commonlib_mux2x1_inst0_in_data[0] = I0;
commonlib_muxn__N2__wi... | 8.404032 |
module Register8 (
input [7:0] I,
output [7:0] O,
input CLK
);
wire DFF_init0_has_ceFalse_has_resetFalse_has_async_resetFalse_inst0_O;
wire DFF_init0_has_ceFalse_has_resetFalse_has_async_resetFalse_inst1_O;
wire DFF_init0_has_ceFalse_has_resetFalse_has_async_resetFalse_inst2_O;
wire DFF_init0_has_ce... | 6.73316 |
module PISO8 (
input SI,
input [7:0] PI,
input LOAD,
output O,
input CLK
);
wire Mux2xNone_inst0_O;
wire Mux2xNone_inst1_O;
wire Mux2xNone_inst2_O;
wire Mux2xNone_inst3_O;
wire Mux2xNone_inst4_O;
wire Mux2xNone_inst5_O;
wire Mux2xNone_inst6_O;
wire Mux2xNone_inst7_O;
wire [7:0] Reg... | 7.793453 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire SB_LUT4_inst0_O;
SB_LUT4 #(
.LUT_INIT(16'hCACA)
) SB_LUT4_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
assign O = SB_LUT4_inst0_O;
endmodule
| 7.615389 |
module Register8 (
input [7:0] I,
output [7:0] O,
input CLK
);
wire SB_DFF_inst0_Q;
wire SB_DFF_inst1_Q;
wire SB_DFF_inst2_Q;
wire SB_DFF_inst3_Q;
wire SB_DFF_inst4_Q;
wire SB_DFF_inst5_Q;
wire SB_DFF_inst6_Q;
wire SB_DFF_inst7_Q;
SB_DFF SB_DFF_inst0 (
.C(CLK),
.D(I[0]),
... | 6.73316 |
module PISO8 (
input SI,
input [7:0] PI,
input LOAD,
output O,
input CLK
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
wire Mux2_inst2_O;
wire Mux2_inst3_O;
wire Mux2_inst4_O;
wire Mux2_inst5_O;
wire Mux2_inst6_O;
wire Mux2_inst7_O;
wire [7:0] Register8_inst0_O;
Mux2 Mux2_inst0 (
... | 7.793453 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire LUT3_inst0_O;
LUT3 #(
.INIT(8'hCA)
) LUT3_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.O (LUT3_inst0_O)
);
assign O = LUT3_inst0_O;
endmodule
| 7.615389 |
module Register8 (
input [7:0] I,
output [7:0] O,
input CLK
);
wire FDRSE_inst0_Q;
wire FDRSE_inst1_Q;
wire FDRSE_inst2_Q;
wire FDRSE_inst3_Q;
wire FDRSE_inst4_Q;
wire FDRSE_inst5_Q;
wire FDRSE_inst6_Q;
wire FDRSE_inst7_Q;
FDRSE #(
.INIT(1'h0)
) FDRSE_inst0 (
.C (CLK),
... | 6.73316 |
module PISO8 (
input SI,
input [7:0] PI,
input LOAD,
output O,
input CLK
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
wire Mux2_inst2_O;
wire Mux2_inst3_O;
wire Mux2_inst4_O;
wire Mux2_inst5_O;
wire Mux2_inst6_O;
wire Mux2_inst7_O;
wire [7:0] Register8_inst0_O;
Mux2 Mux2_inst0 (
... | 7.793453 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire LUT3_inst0_O;
LUT3 #(
.INIT(8'hCA)
) LUT3_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.O (LUT3_inst0_O)
);
assign O = LUT3_inst0_O;
endmodule
| 7.615389 |
module Register8 (
input [7:0] I,
output [7:0] O,
input CLK
);
wire FDRSE_inst0_Q;
wire FDRSE_inst1_Q;
wire FDRSE_inst2_Q;
wire FDRSE_inst3_Q;
wire FDRSE_inst4_Q;
wire FDRSE_inst5_Q;
wire FDRSE_inst6_Q;
wire FDRSE_inst7_Q;
FDRSE #(
.INIT(1'h0)
) FDRSE_inst0 (
.C (CLK),
... | 6.73316 |
module PISO8 (
input SI,
input [7:0] PI,
input LOAD,
output O,
input CLK
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
wire Mux2_inst2_O;
wire Mux2_inst3_O;
wire Mux2_inst4_O;
wire Mux2_inst5_O;
wire Mux2_inst6_O;
wire Mux2_inst7_O;
wire [7:0] Register8_inst0_O;
Mux2 Mux2_inst0 (
... | 7.793453 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= ... | 7.868877 |
module reg_P_wrapped (
input [1:0] I,
input CLK,
output [1:0] O
);
coreir_reg #(
.clk_posedge(1'b1),
.init(2'h0),
.width(2)
) reg_P_inst0 (
.clk(CLK),
.in (I),
.out(O)
);
endmodule
| 7.438605 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= ... | 7.868877 |
module reg_P_wrapped (
input [1:0] I,
input CLK,
output [1:0] O
);
wire [1:0] reg_P_inst0_out;
coreir_reg #(
.clk_posedge(1'b1),
.init(2'h0),
.width(2)
) reg_P_inst0 (
.clk(CLK),
.in (I),
.out(reg_P_inst0_out)
);
assign O = reg_P_inst0_out;
endmodule
| 7.438605 |
module Register2 (
input [1:0] I,
output [1:0] O,
input CLK
);
wire SB_DFF_inst0_Q;
wire SB_DFF_inst1_Q;
SB_DFF SB_DFF_inst0 (
.C(CLK),
.D(I[0]),
.Q(SB_DFF_inst0_Q)
);
SB_DFF SB_DFF_inst1 (
.C(CLK),
.D(I[1]),
.Q(SB_DFF_inst1_Q)
);
assign O = {SB_DFF_inst1_Q,... | 6.626169 |
module Register2 (
input [1:0] I,
output [1:0] O,
input CLK
);
wire FDRSE_inst0_Q;
wire FDRSE_inst1_Q;
FDRSE #(
.INIT(1'h0)
) FDRSE_inst0 (
.C (CLK),
.CE(1'b1),
.R (1'b0),
.S (1'b0),
.D (I[0]),
.Q (FDRSE_inst0_Q)
);
FDRSE #(
.INIT(1'h0)
) FDRSE_i... | 6.626169 |
module Register2 (
input [1:0] I,
output [1:0] O,
input CLK
);
wire FDRSE_inst0_Q;
wire FDRSE_inst1_Q;
FDRSE #(
.INIT(1'h0)
) FDRSE_inst0 (
.C (CLK),
.CE(1'b1),
.R (1'b0),
.S (1'b0),
.D (I[0]),
.Q (FDRSE_inst0_Q)
);
FDRSE #(
.INIT(1'h0)
) FDRSE_i... | 6.626169 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= ... | 7.868877 |
module reg_P_wrapped (
input [3:0] I,
input CLK,
output [3:0] O
);
coreir_reg #(
.clk_posedge(1'b1),
.init(4'h0),
.width(4)
) reg_P_inst0 (
.clk(CLK),
.in (I),
.out(O)
);
endmodule
| 7.438605 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= ... | 7.868877 |
module reg_P_wrapped (
input [3:0] I,
input CLK,
output [3:0] O
);
wire [3:0] reg_P_inst0_out;
coreir_reg #(
.clk_posedge(1'b1),
.init(4'h0),
.width(4)
) reg_P_inst0 (
.clk(CLK),
.in (I),
.out(reg_P_inst0_out)
);
assign O = reg_P_inst0_out;
endmodule
| 7.438605 |
module Register4 (
input [3:0] I,
output [3:0] O,
input CLK
);
wire SB_DFF_inst0_Q;
wire SB_DFF_inst1_Q;
wire SB_DFF_inst2_Q;
wire SB_DFF_inst3_Q;
SB_DFF SB_DFF_inst0 (
.C(CLK),
.D(I[0]),
.Q(SB_DFF_inst0_Q)
);
SB_DFF SB_DFF_inst1 (
.C(CLK),
.D(I[1]),
.Q(SB_D... | 7.403606 |
module Register4 (
input [3:0] I,
output [3:0] O,
input CLK
);
wire FDRSE_inst0_Q;
wire FDRSE_inst1_Q;
wire FDRSE_inst2_Q;
wire FDRSE_inst3_Q;
FDRSE #(
.INIT(1'h0)
) FDRSE_inst0 (
.C (CLK),
.CE(1'b1),
.R (1'b0),
.S (1'b0),
.D (I[0]),
.Q (FDRSE_inst0_Q)
... | 7.403606 |
module Register4 (
input [3:0] I,
output [3:0] O,
input CLK
);
wire FDRSE_inst0_Q;
wire FDRSE_inst1_Q;
wire FDRSE_inst2_Q;
wire FDRSE_inst3_Q;
FDRSE #(
.INIT(1'h0)
) FDRSE_inst0 (
.C (CLK),
.CE(1'b1),
.R (1'b0),
.S (1'b0),
.D (I[0]),
.Q (FDRSE_inst0_Q)
... | 7.403606 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= ... | 7.868877 |
module reg_P_wrapped (
input [7:0] I,
input CLK,
output [7:0] O
);
coreir_reg #(
.clk_posedge(1'b1),
.init(8'h00),
.width(8)
) reg_P_inst0 (
.clk(CLK),
.in (I),
.out(O)
);
endmodule
| 7.438605 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= ... | 7.868877 |
module reg_P_wrapped (
input [7:0] I,
input CLK,
output [7:0] O
);
wire [7:0] reg_P_inst0_out;
coreir_reg #(
.clk_posedge(1'b1),
.init(8'h00),
.width(8)
) reg_P_inst0 (
.clk(CLK),
.in (I),
.out(reg_P_inst0_out)
);
assign O = reg_P_inst0_out;
endmodule
| 7.438605 |
module Register8 (
input [7:0] I,
output [7:0] O,
input CLK
);
wire SB_DFF_inst0_Q;
wire SB_DFF_inst1_Q;
wire SB_DFF_inst2_Q;
wire SB_DFF_inst3_Q;
wire SB_DFF_inst4_Q;
wire SB_DFF_inst5_Q;
wire SB_DFF_inst6_Q;
wire SB_DFF_inst7_Q;
SB_DFF SB_DFF_inst0 (
.C(CLK),
.D(I[0]),
... | 6.73316 |
module Register8 (
input [7:0] I,
output [7:0] O,
input CLK
);
wire FDRSE_inst0_Q;
wire FDRSE_inst1_Q;
wire FDRSE_inst2_Q;
wire FDRSE_inst3_Q;
wire FDRSE_inst4_Q;
wire FDRSE_inst5_Q;
wire FDRSE_inst6_Q;
wire FDRSE_inst7_Q;
FDRSE #(
.INIT(1'h0)
) FDRSE_inst0 (
.C (CLK),
... | 6.73316 |
module Register8 (
input [7:0] I,
output [7:0] O,
input CLK
);
wire FDRSE_inst0_Q;
wire FDRSE_inst1_Q;
wire FDRSE_inst2_Q;
wire FDRSE_inst3_Q;
wire FDRSE_inst4_Q;
wire FDRSE_inst5_Q;
wire FDRSE_inst6_Q;
wire FDRSE_inst7_Q;
FDRSE #(
.INIT(1'h0)
) FDRSE_inst0 (
.C (CLK),
... | 6.73316 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= ... | 7.868877 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= ... | 7.868877 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= ... | 7.868877 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= ... | 7.868877 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= ... | 7.868877 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= ... | 7.868877 |
module coreir_sge2_wrapped (
input [1:0] I0,
input [1:0] I1,
output O
);
assign O = ($signed(I0)) >= ($signed(I1));
endmodule
| 7.319461 |
module coreir_sge #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output out
);
assign out = $signed(in0) >= $signed(in1);
endmodule
| 7.874388 |
module coreir_sge2_wrapped (
input [1:0] I0,
input [1:0] I1,
output O
);
wire coreir_sge2_inst0_out;
coreir_sge #(
.width(2)
) coreir_sge2_inst0 (
.in0(I0),
.in1(I1),
.out(coreir_sge2_inst0_out)
);
assign O = coreir_sge2_inst0_out;
endmodule
| 7.319461 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire SB_LUT4_inst0_O;
wire SB_CARRY_inst0_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) SB_LUT4_inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
SB_CARRY SB_CARR... | 7.610141 |
module Add2_CIN (
input [1:0] I0,
input [1:0] I1,
input CIN,
output [1:0] O
);
wire FullAdder_inst0_O;
wire FullAdder_inst0_COUT;
wire FullAdder_inst1_O;
wire FullAdder_inst1_COUT;
FullAdder FullAdder_inst0 (
.I0(I0[0]),
.I1(I1[0]),
.CIN(CIN),
.O(FullAdder_inst0_O),
... | 6.821676 |
module SGE2 (
input signed [1:0] I0,
input signed [1:0] I1,
output O
);
wire [1:0] Sub2_inst0_O;
wire SB_LUT4_inst0_O;
Sub2 Sub2_inst0 (
.I0(I0),
.I1(I1),
.O (Sub2_inst0_O)
);
SB_LUT4 #(
.LUT_INIT(16'h0071)
) SB_LUT4_inst0 (
.I0(Sub2_inst0_O[1]),
.I1(I0[1]),
... | 7.019438 |
module SGE2 (
input signed [1:0] I0,
input signed [1:0] I1,
output O
);
wire [1:0] Sub2_cin1_inst0_O;
wire LUT3_inst0_O;
Sub2_cin1 Sub2_cin1_inst0 (
.I0(I0),
.I1(I1),
.O (Sub2_cin1_inst0_O)
);
LUT3 #(
.INIT(8'h71)
) LUT3_inst0 (
.I0(Sub2_cin1_inst0_O[1]),
.I1(... | 7.019438 |
module SGE2 (
input signed [1:0] I0,
input signed [1:0] I1,
output O
);
wire [1:0] Sub2_cin1_inst0_O;
wire LUT3_inst0_O;
Sub2_cin1 Sub2_cin1_inst0 (
.I0(I0),
.I1(I1),
.O (Sub2_cin1_inst0_O)
);
LUT3 #(
.INIT(8'h71)
) LUT3_inst0 (
.I0(Sub2_cin1_inst0_O[1]),
.I1(... | 7.019438 |
module coreir_sge4_wrapped (
input [3:0] I0,
input [3:0] I1,
output O
);
assign O = ($signed(I0)) >= ($signed(I1));
endmodule
| 7.384384 |
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