code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module delay_timer (
input wire clk,
input wire RESET,
input wire [7:0] i_wb,
input wire i_TRIG,
input wire i_A, // A and B mode select pins
input wire i_B,
output wire o_delay_out // Active low
);
reg [7:0] Pulse_width;
reg [7:0] Del... | 7.507922 |
module delay_unit #(
parameter DELAY_COUNTER_BITS,
parameter DELAY_BITS,
parameter COUNTER_DIVISION
) (
input clk,
input reset,
input enable,
input wire [DELAY_BITS-1:0] delay,
output reg waiting
);
reg [DELAY_COUNTER_BITS:0] delay_counter; //1 more bit instead of [DELAY_COUNTER_BITS... | 7.492112 |
module delay_valid (
clk,
resetn,
valid_in,
valid_out
);
parameter N_CLOCKs = 12;
input clk;
input resetn;
input valid_in;
output valid_out;
wire out_valid;
delay_clock #(
.DATA_WIDTH(1),
.N_CLOCKs (N_CLOCKs)
) valid_inst (
clk,
resetn,
valid_in,
v... | 6.783059 |
module to combine trigger timing inputs.
`include "trigger_defs.vh"
module delay_vectorizer(
l4_rf0_pretrigger,
l4_rf1_pretrigger,
l4_cpu_pretrigger,
l4_cal_pretrigger,
l4_ext_pretrigger,
pretrigger_vector,
l4_rf0_delay,
l4_rf1_delay,
l4_cpu_delay,
l4_cal_delay,
l4_ext_delay,
delay_vector
)... | 6.602528 |
module delay_x00_ms (
input iCLOCK50,
input iTRIGGER,
output oDELAY100, // delayed ~100ms, is held asserted for ~50ms
output oDELAY200, // delayed ~200ms, is held asserted for ~50ms
output oDELAY300, // delayed ~300ms, is held asserted for ~50ms
output oDELAY400 // delayed ~400ms, is held... | 6.640536 |
module deletezero (
// input
input wire clk,
input wire rst,
input wire [47:0] data_in,
// output
output reg [39:0] out_data
);
integer i;
reg [2:0] flag;
reg [39:0] data;
always @(posedge clk or posedge rst) begin
if (rst) begin
// reset
out_data <= 40'd0;
end els... | 7.062088 |
module deletezero_tb ();
// input
reg clk, rst;
reg [47:0] data_in;
// output
wire [39:0] out_data;
deletezero deletezero_tb (
.clk(clk),
.rst(rst),
.data_in(data_in),
.out_data(out_data)
);
initial begin
clk = 0;
rst = 1;
data_in = 0;
#100;
rst = 0;
da... | 7.463931 |
module delineation (input clk,rst,[7:0]data_fr, output reg
sop_delin,eop_delin,start, output reg [7:0]data_delin);
always @ (posedge clk)
begin
if(rst)
begin
sop_delin<=1'b0;
eop_delin<=1'b0;
data_delin<=1'b0;
start<=1'b0;
end
else
begin
if((data_fr!==8'h7e)&&(start==0))
begin
sop_delin<=1'b1;
eop_delin<=1'b0;
start<=1... | 8.569489 |
module Deliverable3 (
input clock_50,
input [17:0] SW,
input [3:0] KEY,
output reg sym_clk_ena,
output reg clear_accumulator
);
//Clocks
(* noprune *) reg sam_clk_ena;
//(* noprune *) reg sym_clk_ena;
(* noprune *) reg sys_clk;
(* noprune *) reg [3:0] clk_phase;
(* keep *... | 6.633674 |
module DELLN1X2 (
INP,
Z
);
input INP;
output Z;
buf U0 (Z, INP);
specify
specparam tdelay_INP_Z_01_0 = 0.01, tdelay_INP_Z_10_0 = 0.01;
(INP + => Z) = (tdelay_INP_Z_01_0, tdelay_INP_Z_10_0);
endspecify
endmodule
| 6.856055 |
module DELLN2X2 (
INP,
Z
);
input INP;
output Z;
buf U0 (Z, INP);
specify
specparam tdelay_INP_Z_01_0 = 0.01, tdelay_INP_Z_10_0 = 0.01;
(INP + => Z) = (tdelay_INP_Z_01_0, tdelay_INP_Z_10_0);
endspecify
endmodule
| 6.959445 |
module DELLN3X2 (
INP,
Z
);
input INP;
output Z;
buf U0 (Z, INP);
specify
specparam tdelay_INP_Z_01_0 = 0.01, tdelay_INP_Z_10_0 = 0.01;
(INP + => Z) = (tdelay_INP_Z_01_0, tdelay_INP_Z_10_0);
endspecify
endmodule
| 6.575899 |
module DELTA #(parameter WLI = 1, WLF = 15, WL = WLI + WLF)(
// input CLK, RST,
// input codeWord,
// output reg signed [WL-1:0] delta
// );
// reg signed [WL-1:0] deltaP1, deltaMin, deltaMax;
// wire signed [WL-1:0] deltaUnclipped;
// initial begin deltaMin = 'b0000000010000000; deltaMax = 'b0111... | 6.500068 |
module DELTA #(
parameter WLI = 1,
WLF = 15,
WL = WLI + WLF
) (
input RST,
CLK,
codeWord,
output reg [WL-1:0] delta
);
reg signed [WL-1:0] deltaP1, deltaUnclipped;
wire [WL-1:0] deltaDiv, deltaMult;
assign deltaDiv = delta >>> 1;
assign deltaMult = delta <<< 1;
always @(*) begin
... | 6.799624 |
module that generates error of output input-hidden layer
module delta2_module (
clk, rst, controller, step, w3i1, w3i2, w3i3, w3i4,
delta31, delta32, delta33, delta34, dadz, delta2
);
input clk, rst;
input [3:0] step, controller;
input signed [15:0] w3i1, w3i2, w3i3, w3i4;
input signed [15:0] d... | 6.649759 |
module that generates error of output hidden-output layer
module delta3_module (
clk, rst, act, step, controller, reward, maxQt1, Qt, delta3
);
input clk, rst;
input [1:0] act;
input [3:0] step, controller;
input signed [15:0] reward, maxQt1, Qt;
output signed [15:0] delta3;
//gamma = 0.875
... | 6.649759 |
module deltaSigmaADC (
input i_clk, // 50MHz
input i_rst_n, // RESET_N
input i_cmpans, // LVDS INPUT
output o_cmpdac, // Compare Base Level
output [9:0] o_adc_dt, // ADC Result
output o_adc_dt_en // data enable(48828.125kHz)
);
reg de... | 6.893885 |
module
* Date : 2016/09/08
* Design : kingyo
********************************************************/
// DA分解能(bit)
localparam RESO = 6;
module DeltaSigma_DAC (
input wire i_clk,
input wire i_res_n,
input wire [RESO - 1:0] i_adata,
output wire o_out
);
reg... | 7.89417 |
module deltaU (
error,
errorPrev,
deltaU
);
input signed [15:0] error;
input signed [15:0] errorPrev;
output signed [15:0] deltaU;
parameter KpKi = 3;
parameter KiKp = 1;
assign deltaU = (KpKi * error) + (KiKp * errorPrev);
endmodule
| 7.702862 |
module delta_h (
i_a,
i_prevd,
i_w,
o
);
// parameters
parameter NUM = 2;
parameter WIDTH = 32;
// input ports
input signed [NUM*WIDTH-1:0] i_prevd;
input signed [NUM*WIDTH-1:0] i_w;
input signed [WIDTH-1:0] i_a;
// output ports
output signed [WIDTH-1:0] o;
// wires
wire signed... | 6.927823 |
module delta_limit (
clk,
rst_n,
enable,
datain,
dataout
);
input clk, rst_n, enable;
input [31:0] datain;
output [31:0] dataout;
reg [31:0] dataout;
reg [31:0] delta_max;
reg [31:0] delta_min;
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
dataout <= 32'd0;
... | 7.892757 |
module delta_out (
i_a,
i_t,
o_delta,
o_cost
);
// parameters
parameter WIDTH = 32;
parameter FRAC = 24;
// input ports
input signed [WIDTH-1:0] i_a;
input signed [WIDTH-1:0] i_t;
// output ports
output signed [WIDTH-1:0] o_delta;
output signed [WIDTH-1:0] o_cost;
// wires
wire... | 7.533689 |
module DELTA_PLUS #(
parameter WLI = 1,
WLF = 15,
WL = WLI + WLF
) (
input signed [WL-1:0] delta,
input codeWord,
output reg signed [WL-1:0] deltaP1
);
wire [WL-1:0] deltaDiv, deltaMult;
assign deltaDiv = delta >>> 1;
assign deltaMult = delta <<< 1;
always @(*) begin
if (codeWord =... | 6.975259 |
module Delta_qp_enc (
delta_qp,
codebit,
length
);
input signed [5:0] delta_qp;
output reg [10:0] codebit;
output [3:0] length;
wire [2:0] LeadingZeroNum;
wire [4:0] suffix;
reg [5:0] codenum;
//assign codenum = (~delta_qp[5]) ? ((delta_qp[4:0] << 1)-1'd1) : ((~(delta_qp[4:0]-1'd1))<<1);
a... | 6.792518 |
module delta_sigma_adc #(
parameter W = 16 //输入位宽
) (
input wire clk,
input wire rst_n,
input wire signed [W-1:0] din, //signed analog signal
output reg dout //PDM signal
);
wire signed [W-1:0] adc1b_max = {1'b0, {(W - 1) {1'b1}}};
wire signed [W-1:0] adc1b_min = {1'b1, {(W ... | 8.036112 |
module delta_w_gen (
input CLK,
input ARR y_out,
input data d,
input data learning_rate,
input gen,
output ARR delta_w_out
);
ARR gradient;
ARR delta_w_out_internal_opposite;
ARR delta_w_out_internal;
scalar_mult mult_unit1 (
.vector1(y_out),
.scalar(d),
.out(gradient... | 7.368552 |
module delvb (
rst_n,
indata,
outdata,
clk
);
input rst_n, clk;
input [1:0] indata;
output outdata;
reg [3:0] buffer;
reg bufferdata;
reg counterv;
always @(posedge clk or negedge rst_n) begin // 设置四位buffer暂存前四位数据
if (!rst_n) begin
buffer[3] <= 0;
buffer[2] <= 0;
b... | 6.841305 |
module dematrixifytestbench (
input begintest,
output reg endtest,
output reg dutpassed,
output reg [7:0] matrix[3:0][3:0],
input [127:0] rawstring
);
always @(posedge begintest) begin
$display("Testing dematrixify now...");
endtest = 0;
dutpassed = 1;
#10
//test case 0
... | 7.230024 |
module dematrixify (
input [7:0] matrix[3:0][3:0],
output reg [127:0] rawstring
);
assign rawstring[127:120] = matrix[3][3];
assign rawstring[119:112] = matrix[2][3];
assign rawstring[111:104] = matrix[1][3];
assign rawstring[103:96] = matrix[0][3];
assign rawstring[95:88] = matrix[3][2];
assign ra... | 7.104541 |
module dmemory32(
input clock,Memwrite,[31:0]address,[31:0]write_data,
output [31:0]read_data
);
// Part of dmemory32 module
//Generating a clk signal, which is the inverted clock of the clock signal
assign clk = !clock;
//Create a instance of RAM(IP core), binding the ports
RAM ram (
.clka(clk), // in... | 7.163532 |
module reverse (
input [1:0] in,
output [1:0] out
);
assign out = {in[0], in[1]};
endmodule
| 6.661478 |
module demo0_tb;
reg [1:0] in;
wire [1:0] out;
reverse m0 (
in,
out
);
initial begin
$dumpfile("demo0_tb.vcd");
$dumpvars(0, demo0_tb);
in = 2'b10;
#10;
in = 2'b01;
#10;
in = 2'b00;
#10;
end
endmodule
| 7.720094 |
module demo0_tb;
reg [1:0] in;
wire [1:0] out;
reverse m0 (
in,
out
);
initial begin
$dumpfile("demo0_tb_another.vcd");
$dumpvars(0, demo0_tb);
in = 2'b10;
#10;
in = 2'b01;
#10;
in = 2'b00;
#10;
end
endmodule
| 7.720094 |
module demo1_tb;
reg [ 7:0] in;
wire [15:0] out;
sign_extender m0 (
in,
out
);
initial begin
$dumpfile("demo1_tb.vcd");
$dumpvars(0, demo1_tb);
in = 8'b0000_0000;
#10;
in = 8'b1000_0001;
#10;
in = 8'b0000_0001;
#10;
in = 8'b1111_1111;
#10;
in = 8'b11... | 6.72989 |
module demo1_tb;
reg [7:0] in;
wire [15:0] out;
reg not_connected;
sign_extender m0 (
in,
out
);
initial begin
$dumpfile("demo1_tb_another.vcd");
$dumpvars(0, demo1_tb);
#10;
in = 8'b1000_0001;
#10;
in = 8'b0000_0001;
#10;
in = 8'b1111_1111;
#10;
in = 8... | 6.72989 |
module demo2_tb;
reg [ 7:0] in_8;
reg [15:0] in_16;
wire [15:0] out_8_16;
wire [31:0] out_16_32;
top m0 (
in_8,
in_16,
out_8_16,
out_16_32
);
initial begin
$dumpfile("demo2_tb.vcd");
$dumpvars(0, demo2_tb);
in_8 = 8'b0000_0000;
in_16 = 16'h0000;
#10;
i... | 7.266688 |
module top (
input [ 7:0] in,
output [15:0] out
);
wire [7:0] reversed;
// Module reverse be declaration somewhere else
// "module reverse(input [7:0] in, output [7:0] out);"
reverse reverse_instance (
.in (in),
.out(reversed)
);
// The module declare before
sign_extender sign_exte... | 7.233807 |
module demo7;
wire [2:0] addr = $anyseq;
reg [15:0] memory[0:7];
initial begin
memory[0] = 1331;
memory[1] = 1331 + 1;
memory[2] = 1331 + 2;
memory[3] = 1331 + 4;
memory[4] = 1331 + 8;
memory[5] = 1331 + 16;
memory[6] = 1331 + 32;
memory[7] = 1331 + 64;
end
assert property (1... | 6.82202 |
module demo8;
wire [7:0] prime = $anyconst;
wire [3:0] factor = $allconst;
always @* begin
if (1 < factor && factor < prime) assume ((prime % factor) != 0);
assume (prime > 1);
end
endmodule
| 8.401979 |
module DemodOut (
rst,
clk,
din,
Isync,
Qsync,
It,
Qt,
bit_sync,
dout
);
input rst; //复位信号，高电平有效
input clk; //时钟信号，FPGA系统时钟/输入数据速率/采样速率
input din; //输入的滤波后的同相、正交两路位定时单载波信号
input Isync; //同相位定时脉冲
input Qsync; //正交位定时脉冲
input signed [25:0] It; //输入的滤波后的同相基带波形
input... | 7.66782 |
module Demodulation_Post_Processing (
post_processing_input_1,
post_processing_input_2,
post_processing_output
);
// Define Input and Output Variables
input signed [95:0] post_processing_input_1;
input signed [127:0] post_processing_input_2;
output [15:0] post_processing_output;
// Define All In... | 6.52648 |
module demodulator (
input inbit,
clk,
rst,
result_out,
output xor_bit
);
// Reverse operation of xor_word to decode DPSK'd input
// Output at 10 MHz with 120 MHz PLL clock in the rest of the project
wire curr_bit;
dffr delay_ff (
.clk(clk),
.r (rst),
.d (inbit),
... | 7.14349 |
module demod_16QAM (
carrier_clk,
orgin_clk,
reset_n,
signal,
demod_out
);
input carrier_clk, reset_n, orgin_clk;
input signed [8:0] signal; //调制输出
output demod_out;
wire [3:0] p_data; //并行数据
wire signed [7:0] mul_i;
wire signed [7:0] mul_q;
//载波
wire signed [7:0] carrier_sin;
... | 6.758282 |
module demod_fir (
input wire clk, // clk.clk
input wire reset_n, // rst.reset_n
input wire [ 7:0] ast_sink_data, // avalon_streaming_sink.data
input wire ast_sink_valid, // .valid
... | 7.439476 |
module notgate (
in,
out
);
input [3:0] in;
output [3:0] out;
assign out = ~in;
endmodule
| 7.575943 |
module demorgan_bd_wrapper (
input1,
input2,
outinput1,
outinput2,
output1,
output2,
output3,
output4
);
input input1;
input input2;
output outinput1;
output outinput2;
output [0:0] output1;
output [0:0] output2;
output [0:0] output3;
output [0:0] output4;
wire input1;... | 7.361261 |
module demorgan_df (
input input1,
input input2,
output outinput1,
output outinput2,
output output1,
output output2,
output output3,
output output4
);
assign outinput1 = input1;
assign outinput2 = input2;
assign output1 = ~(input1 | input2);
assign output2 = (~input1) & (~i... | 7.337658 |
module demosaicing #(
parameter Nrows = 349,
parameter Ncol = 349
) // amount of lines in the frame
(
input clk,
input rst,
// slave axi stream interface
input s_axis_tvalid,
input s_axis_tuser,
input s_axis_tlast,
input [8 - 1 : 0] s_axis_tdata,
// master axi stream interf... | 8.086352 |
module demosaicing_tb ();
reg clk;
reg rst;
// slave axi stream interface
wire s_axis_tvalid;
wire s_axis_tuser;
wire s_axis_tlast;
wire [8 - 1 : 0] s_axis_tdata;
wire s_axis_tready;
// master axi stream interface
wire m_axis_tvalid;
wire m_axis_tuser;
wire m_axis_tlast;
wire [23 : 0] ... | 7.047481 |
module demosaic_neighbor_shift_reg (
clken,
clock,
shiftin,
shiftout,
taps0x,
taps1x,
taps2x,
taps3x
);
input clken;
input clock;
input [7:0] shiftin;
output [7:0] shiftout;
output [7:0] taps0x;
output [7:0] taps1x;
output [7:0] taps2x;
output [7:0] taps3x;
`ifndef ALTER... | 6.683609 |
module demosaic_neighbor_shift_reg_240p (
clken,
clock,
shiftin,
shiftout,
taps0x,
taps1x,
taps2x,
taps3x
);
input clken;
input clock;
input [7:0] shiftin;
output [7:0] shiftout;
output [7:0] taps0x;
output [7:0] taps1x;
output [7:0] taps2x;
output [7:0] taps3x;
`ifndef ... | 6.683609 |
module scalerTestbench;
parameter BUFFER_SIZE = 4;
wire [2:0] done;
//Input throttling (data source slower than data sink)
demosaicTest #(
.X_RES(640 - 1),
.Y_RES(512 - 1),
.DATA_WIDTH(8),
.X_RES_WIDTH(11),
.Y_RES_WIDTH(11),
.BUFFER_SIZE(BUFFER_SIZE), //Number of RAMs in ... | 7.938786 |
module demosaicTest #(
parameter X_RES = 640 - 1,
parameter Y_RES = 512 - 1,
parameter DATA_WIDTH = 8,
parameter X_RES_WIDTH = 11,
parameter Y_RES_WIDTH = 11,
parameter BUFFER_SIZE = 5, //Number of RAMs in RFIFO
parameter DIN_VALID_PERIOD = 1000,
parameter DIN_VALID_ON = 1000,
p... | 8.570658 |
module DemoSDRAM_xbar_0_axi_crossbar_v2_1_12_decerr_slave (
mi_bvalid,
mi_wready,
mi_rvalid,
\m_ready_d_reg[1] ,
\gen_no_arbiter.m_valid_i_reg ,
SR,
\m_atarget_hot_reg[2] ,
aclk,
m_axi_arready,
m_atarget_enc,
m_axi_bvalid,
m_ready_d,
\gen_no_arbiter.m_valid_i_reg_0 ,
... | 6.522727 |
module DemoSDRAM_xbar_0_axi_crossbar_v2_1_12_splitter__parameterized0 (
m_ready_d,
aresetn_d,
aa_grant_rnw,
m_valid_i,
\gen_axilite.s_axi_arready_i_reg ,
\m_ready_d_reg[0]_0 ,
aclk
);
output [1:0] m_ready_d;
input aresetn_d;
input aa_grant_rnw;
input m_valid_i;
input \gen_axilite.s... | 6.522727 |
module CLA_4bit__1_7 (
x,
y,
cO,
s,
p,
g
);
input [3:0] x;
input [3:0] y;
input cO;
output [3:0] s;
output p;
output g;
wire n_0_0;
wire n_0_1;
wire n_0_2;
wire n_0_3;
wire n_0_4;
wire n_0_5;
wire n_0_6;
FA_X1 i_0_0 (
.A (1'b0),
.B (x[0]),
.CI(y[0]... | 6.918115 |
module CLA_4bit__1_15 (
x,
y,
cO,
s,
p,
g
);
input [3:0] x;
input [3:0] y;
input cO;
output [3:0] s;
output p;
output g;
wire n_0_0;
wire n_0_1;
wire n_0_2;
wire n_0_3;
wire n_0_4;
wire n_0_5;
wire n_0_6;
wire n_0_7;
FA_X1 i_0_0 (
.A (cO),
.B (x[0]),
... | 7.260204 |
module CLA_4bit__1_23 (
x,
y,
cO,
s,
p,
g
);
input [3:0] x;
input [3:0] y;
input cO;
output [3:0] s;
output p;
output g;
wire n_0_0;
wire n_0_1;
wire n_0_2;
wire n_0_3;
wire n_0_4;
wire n_0_5;
wire n_0_6;
wire n_0_7;
FA_X1 i_0_0 (
.A (cO),
.B (x[0]),
... | 7.239782 |
module CLA_4bit__1_31 (
x,
y,
cO,
s,
p,
g
);
input [3:0] x;
input [3:0] y;
input cO;
output [3:0] s;
output p;
output g;
wire n_0_0;
wire n_0_1;
wire n_0_2;
wire n_0_3;
wire n_0_4;
wire n_0_5;
wire n_0_6;
wire n_0_7;
FA_X1 i_0_0 (
.A (cO),
.B (x[0]),
... | 7.175044 |
module CLA_4bit__1_39 (
x,
y,
cO,
s,
p,
g
);
input [3:0] x;
input [3:0] y;
input cO;
output [3:0] s;
output p;
output g;
wire n_0_0;
wire n_0_1;
wire n_0_2;
wire n_0_3;
wire n_0_4;
wire n_0_5;
wire n_0_6;
wire n_0_7;
FA_X1 i_0_0 (
.A (cO),
.B (x[0]),
... | 7.175044 |
module CLA_4bit (
x,
y,
cO,
s,
p,
g
);
input [3:0] x;
input [3:0] y;
input cO;
output [3:0] s;
output p;
output g;
wire n_0_0;
wire n_0_1;
wire n_0_2;
wire n_0_3;
wire n_0_4;
wire n_0_5;
wire n_0_6;
wire n_0_7;
FA_X1 i_0_0 (
.A (cO),
.B (x[0]),
.... | 7.044807 |
module demo_arbiter (
input enable_in,
input enable_out,
input load,
input [`PORT_WIDTH-1:0] port_in,
output [`PORT_WIDTH-1:0] port_out,
output [`SELECT_WIDTH-1:0] select,
output valid,
input clock,
input reset
);
wire [`ARB_WIDTH-1:0] req, grant;
shifter #(
.depth(`ARB_... | 7.451783 |
module fa__0_16 (
in1,
in2,
cin,
sum,
cout
);
input in1;
input in2;
input cin;
output sum;
output cout;
XOR2_X1 i_0_0 (
.A(in1),
.B(in2),
.Z(sum)
);
AND2_X1 i_0_1 (
.A1(in2),
.A2(in1),
.ZN(cout)
);
endmodule
| 6.870659 |
module fa__0_19 (
in1,
in2,
cin,
sum,
cout
);
input in1;
input in2;
input cin;
output sum;
output cout;
wire n_0_0;
wire n_0_1;
wire n_0_2;
NAND2_X1 i_0_0 (
.A1(n_0_2),
.A2(n_0_0),
.ZN(cout)
);
OAI21_X1 i_0_1 (
.A (in2),
.B1(cin),
.B2(in1),... | 6.925257 |
module fa__0_22 (
in1,
in2,
cin,
sum,
cout
);
input in1;
input in2;
input cin;
output sum;
output cout;
wire n_0_0;
wire n_0_1;
wire n_0_2;
NAND2_X1 i_0_0 (
.A1(n_0_2),
.A2(n_0_0),
.ZN(cout)
);
OAI21_X1 i_0_1 (
.A (in2),
.B1(cin),
.B2(in1),... | 6.782983 |
module fa (
in1,
in2,
cin,
sum,
cout
);
input in1;
input in2;
input cin;
output sum;
output cout;
wire n_0_0;
wire n_0_1;
wire n_0_2;
NAND2_X1 i_0_0 (
.A1(n_0_2),
.A2(n_0_0),
.ZN(cout)
);
OAI21_X1 i_0_1 (
.A (in2),
.B1(cin),
.B2(in1),
... | 7.005295 |
module ripple_carry_adder_4_bit (
in1,
in2,
cin,
cout,
sum
);
input [3:0] in1;
input [3:0] in2;
input cin;
output cout;
output [3:0] sum;
wire [4:0] C;
fa__0_16 genblk1_0_fa (
.in1 (in1[0]),
.in2 (in2[0]),
.cin (),
.sum (sum[0]),
.cout(C[1])
);
fa__0... | 7.682509 |
module fa__0_60 (
in1,
in2,
cin,
sum,
cout
);
input in1;
input in2;
input cin;
output sum;
output cout;
XOR2_X1 i_0_0 (
.A(in1),
.B(in2),
.Z(sum)
);
AND2_X1 i_0_1 (
.A1(in2),
.A2(in1),
.ZN(cout)
);
endmodule
| 6.887346 |
module fa__0_57 (
in1,
in2,
cin,
sum,
cout
);
input in1;
input in2;
input cin;
output sum;
output cout;
wire n_0_0;
wire n_0_1;
wire n_0_2;
NAND2_X1 i_0_0 (
.A1(n_0_2),
.A2(n_0_0),
.ZN(cout)
);
OAI21_X1 i_0_1 (
.A (in2),
.B1(cin),
.B2(in1),... | 6.982968 |
module fa__0_54 (
in1,
in2,
cin,
sum,
cout
);
input in1;
input in2;
input cin;
output sum;
output cout;
wire n_0_0;
wire n_0_1;
wire n_0_2;
NAND2_X1 i_0_0 (
.A1(n_0_2),
.A2(n_0_0),
.ZN(cout)
);
OAI21_X1 i_0_1 (
.A (in2),
.B1(cin),
.B2(in1),... | 6.650773 |
module fa__0_51 (
in1,
in2,
cin,
sum,
cout
);
input in1;
input in2;
input cin;
output sum;
output cout;
wire n_0_0;
wire n_0_1;
wire n_0_2;
NAND2_X1 i_0_0 (
.A1(n_0_2),
.A2(n_0_0),
.ZN(cout)
);
OAI21_X1 i_0_1 (
.A (in2),
.B1(cin),
.B2(in1),... | 6.847617 |
module ripple_carry_adder_4_bit__0_61 (
in1,
in2,
cin,
cout,
sum
);
input [3:0] in1;
input [3:0] in2;
input cin;
output cout;
output [3:0] sum;
wire [4:0] C;
fa__0_60 genblk1_0_fa (
.in1 (in1[0]),
.in2 (in2[0]),
.cin (),
.sum (sum[0]),
.cout(C[1])
);
... | 7.682509 |
module ha__0_48 (
in1,
in2,
cout,
sum
);
input in1;
input in2;
output cout;
output sum;
AND2_X1 i_0_0 (
.A1(in1),
.A2(in2),
.ZN(cout)
);
XOR2_X1 i_0_1 (
.A(in1),
.B(in2),
.Z(sum)
);
endmodule
| 7.686798 |
module ha__0_45 (
in1,
in2,
cout,
sum
);
input in1;
input in2;
output cout;
output sum;
AND2_X1 i_0_0 (
.A1(in1),
.A2(in2),
.ZN(cout)
);
XOR2_X1 i_0_1 (
.A(in1),
.B(in2),
.Z(sum)
);
endmodule
| 7.801992 |
module ha__0_42 (
in1,
in2,
cout,
sum
);
input in1;
input in2;
output cout;
output sum;
AND2_X1 i_0_0 (
.A1(in1),
.A2(in2),
.ZN(cout)
);
XOR2_X1 i_0_1 (
.A(in1),
.B(in2),
.Z(sum)
);
endmodule
| 7.493513 |
module ha__0_39 (
in1,
in2,
cout,
sum
);
input in1;
input in2;
output cout;
output sum;
AND2_X1 i_0_0 (
.A1(in1),
.A2(in2),
.ZN(cout)
);
XOR2_X1 i_0_1 (
.A(in1),
.B(in2),
.Z(sum)
);
endmodule
| 7.185009 |
module cia_block__0_62 (
in1,
in2,
cin,
cout,
sum
);
input [3:0] in1;
input [3:0] in2;
input cin;
output cout;
output [3:0] sum;
wire [3:0] internal_sum;
wire c;
wire ha_cout;
ripple_carry_adder_4_bit__0_61 rca (
.in1 (in1),
.in2 (in2),
.cin (),
.cout(c),
... | 6.98492 |
module fa__0_87 (
in1,
in2,
cin,
sum,
cout
);
input in1;
input in2;
input cin;
output sum;
output cout;
XOR2_X1 i_0_0 (
.A(in1),
.B(in2),
.Z(sum)
);
AND2_X1 i_0_1 (
.A1(in2),
.A2(in1),
.ZN(cout)
);
endmodule
| 7.028537 |
module fa__0_84 (
in1,
in2,
cin,
sum,
cout
);
input in1;
input in2;
input cin;
output sum;
output cout;
wire n_0_0;
wire n_0_1;
wire n_0_2;
NAND2_X1 i_0_0 (
.A1(n_0_2),
.A2(n_0_0),
.ZN(cout)
);
OAI21_X1 i_0_1 (
.A (in2),
.B1(cin),
.B2(in1),... | 6.860155 |
module fa__0_81 (
in1,
in2,
cin,
sum,
cout
);
input in1;
input in2;
input cin;
output sum;
output cout;
wire n_0_0;
wire n_0_1;
wire n_0_2;
NAND2_X1 i_0_0 (
.A1(n_0_2),
.A2(n_0_0),
.ZN(cout)
);
OAI21_X1 i_0_1 (
.A (in2),
.B1(cin),
.B2(in1),... | 6.858233 |
module fa__0_78 (
in1,
in2,
cin,
sum,
cout
);
input in1;
input in2;
input cin;
output sum;
output cout;
wire n_0_0;
wire n_0_1;
wire n_0_2;
NAND2_X1 i_0_0 (
.A1(n_0_2),
.A2(n_0_0),
.ZN(cout)
);
OAI21_X1 i_0_1 (
.A (in2),
.B1(cin),
.B2(in1),... | 6.995263 |
module ripple_carry_adder_4_bit__0_88 (
in1,
in2,
cin,
cout,
sum
);
input [3:0] in1;
input [3:0] in2;
input cin;
output cout;
output [3:0] sum;
wire [4:0] C;
fa__0_87 genblk1_0_fa (
.in1 (in1[0]),
.in2 (in2[0]),
.cin (),
.sum (sum[0]),
.cout(C[1])
);
... | 7.682509 |
module ha__0_75 (
in1,
in2,
cout,
sum
);
input in1;
input in2;
output cout;
output sum;
AND2_X1 i_0_0 (
.A1(in1),
.A2(in2),
.ZN(cout)
);
XOR2_X1 i_0_1 (
.A(in1),
.B(in2),
.Z(sum)
);
endmodule
| 7.979033 |
module ha__0_72 (
in1,
in2,
cout,
sum
);
input in1;
input in2;
output cout;
output sum;
AND2_X1 i_0_0 (
.A1(in1),
.A2(in2),
.ZN(cout)
);
XOR2_X1 i_0_1 (
.A(in1),
.B(in2),
.Z(sum)
);
endmodule
| 7.304589 |
module ha__0_69 (
in1,
in2,
cout,
sum
);
input in1;
input in2;
output cout;
output sum;
AND2_X1 i_0_0 (
.A1(in1),
.A2(in2),
.ZN(cout)
);
XOR2_X1 i_0_1 (
.A(in1),
.B(in2),
.Z(sum)
);
endmodule
| 7.401754 |
module ha__0_66 (
in1,
in2,
cout,
sum
);
input in1;
input in2;
output cout;
output sum;
AND2_X1 i_0_0 (
.A1(in1),
.A2(in2),
.ZN(cout)
);
XOR2_X1 i_0_1 (
.A(in1),
.B(in2),
.Z(sum)
);
endmodule
| 7.697795 |
module cia_block__0_89 (
in1,
in2,
cin,
cout,
sum
);
input [3:0] in1;
input [3:0] in2;
input cin;
output cout;
output [3:0] sum;
wire [3:0] internal_sum;
wire c;
wire ha_cout;
ripple_carry_adder_4_bit__0_88 rca (
.in1 (in1),
.in2 (in2),
.cin (),
.cout(c),
... | 6.98492 |
module fa__0_111 (
in1,
in2,
cin,
sum,
cout
);
input in1;
input in2;
input cin;
output sum;
output cout;
wire n_0_0;
wire n_0_1;
wire n_0_2;
NAND2_X1 i_0_0 (
.A1(n_0_2),
.A2(n_0_0),
.ZN(cout)
);
OAI21_X1 i_0_1 (
.A (in2),
.B1(cin),
.B2(in1)... | 6.649346 |
module fa__0_108 (
in1,
in2,
cin,
sum,
cout
);
input in1;
input in2;
input cin;
output sum;
output cout;
wire n_0_0;
wire n_0_1;
wire n_0_2;
NAND2_X1 i_0_0 (
.A1(n_0_2),
.A2(n_0_0),
.ZN(cout)
);
OAI21_X1 i_0_1 (
.A (in2),
.B1(cin),
.B2(in1)... | 6.800012 |
module fa__0_105 (
in1,
in2,
cin,
sum,
cout
);
input in1;
input in2;
input cin;
output sum;
output cout;
wire n_0_0;
wire n_0_1;
wire n_0_2;
NAND2_X1 i_0_0 (
.A1(n_0_2),
.A2(n_0_0),
.ZN(cout)
);
OAI21_X1 i_0_1 (
.A (in2),
.B1(cin),
.B2(in1)... | 6.765031 |
module ripple_carry_adder_4_bit__0_115 (
in1,
in2,
cin,
cout,
sum
);
input [3:0] in1;
input [3:0] in2;
input cin;
output cout;
output [3:0] sum;
wire [4:0] C;
fa__0_114 genblk1_0_fa (
.in1 (in1[0]),
.in2 (in2[0]),
.cin (),
.sum (sum[0]),
.cout(C[1])
);... | 7.682509 |
module ha__0_102 (
in1,
in2,
cout,
sum
);
input in1;
input in2;
output cout;
output sum;
AND2_X1 i_0_0 (
.A1(in1),
.A2(in2),
.ZN(cout)
);
XOR2_X1 i_0_1 (
.A(in1),
.B(in2),
.Z(sum)
);
endmodule
| 7.417259 |
module ha__0_99 (
in1,
in2,
cout,
sum
);
input in1;
input in2;
output cout;
output sum;
AND2_X1 i_0_0 (
.A1(in1),
.A2(in2),
.ZN(cout)
);
XOR2_X1 i_0_1 (
.A(in1),
.B(in2),
.Z(sum)
);
endmodule
| 7.322639 |
module ha__0_96 (
in1,
in2,
cout,
sum
);
input in1;
input in2;
output cout;
output sum;
AND2_X1 i_0_0 (
.A1(in1),
.A2(in2),
.ZN(cout)
);
XOR2_X1 i_0_1 (
.A(in1),
.B(in2),
.Z(sum)
);
endmodule
| 7.352452 |
module ha__0_93 (
in1,
in2,
cout,
sum
);
input in1;
input in2;
output cout;
output sum;
AND2_X1 i_0_0 (
.A1(in1),
.A2(in2),
.ZN(cout)
);
XOR2_X1 i_0_1 (
.A(in1),
.B(in2),
.Z(sum)
);
endmodule
| 7.554867 |
module cia_block__0_116 (
in1,
in2,
cin,
cout,
sum
);
input [3:0] in1;
input [3:0] in2;
input cin;
output cout;
output [3:0] sum;
wire [3:0] internal_sum;
wire c;
wire ha_cout;
ripple_carry_adder_4_bit__0_115 rca (
.in1 (in1),
.in2 (in2),
.cin (),
.cout(c)... | 6.98492 |
module fa__0_141 (
in1,
in2,
cin,
sum,
cout
);
input in1;
input in2;
input cin;
output sum;
output cout;
XOR2_X1 i_0_0 (
.A(in1),
.B(in2),
.Z(sum)
);
AND2_X1 i_0_1 (
.A1(in2),
.A2(in1),
.ZN(cout)
);
endmodule
| 6.743683 |
module fa__0_138 (
in1,
in2,
cin,
sum,
cout
);
input in1;
input in2;
input cin;
output sum;
output cout;
wire n_0_0;
wire n_0_1;
wire n_0_2;
NAND2_X1 i_0_0 (
.A1(n_0_2),
.A2(n_0_0),
.ZN(cout)
);
OAI21_X1 i_0_1 (
.A (in2),
.B1(cin),
.B2(in1)... | 6.819356 |
module fa__0_135 (
in1,
in2,
cin,
sum,
cout
);
input in1;
input in2;
input cin;
output sum;
output cout;
wire n_0_0;
wire n_0_1;
wire n_0_2;
NAND2_X1 i_0_0 (
.A1(n_0_2),
.A2(n_0_0),
.ZN(cout)
);
OAI21_X1 i_0_1 (
.A (in2),
.B1(cin),
.B2(in1)... | 6.98466 |
module fa__0_132 (
in1,
in2,
cin,
sum,
cout
);
input in1;
input in2;
input cin;
output sum;
output cout;
wire n_0_0;
wire n_0_1;
wire n_0_2;
NAND2_X1 i_0_0 (
.A1(n_0_2),
.A2(n_0_0),
.ZN(cout)
);
OAI21_X1 i_0_1 (
.A (in2),
.B1(cin),
.B2(in1)... | 6.816176 |
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