code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module fold_xor82 (
input [1:0] I0,
input [1:0] I1,
input [1:0] I2,
input [1:0] I3,
input [1:0] I4,
input [1:0] I5,
input [1:0] I6,
input [1:0] I7,
output [1:0] O
);
wire [1:0] xor2_inst0_out;
wire [1:0] xor2_inst1_out;
wire [1:0] xor2_inst2_out;
wire [1:0] xor2_inst3... | 6.798465 |
module XOr8 (
input [7:0] I,
output O
);
wire SB_LUT4_inst0_O;
wire SB_LUT4_inst1_O;
wire SB_LUT4_inst2_O;
wire SB_LUT4_inst3_O;
wire SB_LUT4_inst4_O;
wire SB_LUT4_inst5_O;
wire SB_LUT4_inst6_O;
wire SB_LUT4_inst7_O;
SB_LUT4 #(
.LUT_INIT(16'h6666)
) SB_LUT4_inst0 (
.I0(1'b0),
... | 6.967403 |
module XOr8x2 (
input [1:0] I0,
input [1:0] I1,
input [1:0] I2,
input [1:0] I3,
input [1:0] I4,
input [1:0] I5,
input [1:0] I6,
input [1:0] I7,
output [1:0] O
);
wire XOr8_inst0_O;
wire XOr8_inst1_O;
XOr8 XOr8_inst0 (
.I({I7[0], I6[0], I5[0], I4[0], I3[0], I2[0], ... | 7.714482 |
module XOr8 (
input [7:0] I,
output O
);
wire LUT2_inst0_O;
wire LUT2_inst1_O;
wire LUT2_inst2_O;
wire LUT2_inst3_O;
wire LUT2_inst4_O;
wire LUT2_inst5_O;
wire LUT2_inst6_O;
wire LUT2_inst7_O;
LUT2 #(
.INIT(4'h6)
) LUT2_inst0 (
.I0(1'b0),
.I1(I[0]),
.O (LUT2_inst0_O)
... | 6.967403 |
module XOr8x2 (
input [1:0] I0,
input [1:0] I1,
input [1:0] I2,
input [1:0] I3,
input [1:0] I4,
input [1:0] I5,
input [1:0] I6,
input [1:0] I7,
output [1:0] O
);
wire XOr8_inst0_O;
wire XOr8_inst1_O;
XOr8 XOr8_inst0 (
.I({I7[0], I6[0], I5[0], I4[0], I3[0], I2[0], ... | 7.714482 |
module XOr8 (
input [7:0] I,
output O
);
wire LUT2_inst0_O;
wire LUT2_inst1_O;
wire LUT2_inst2_O;
wire LUT2_inst3_O;
wire LUT2_inst4_O;
wire LUT2_inst5_O;
wire LUT2_inst6_O;
wire LUT2_inst7_O;
LUT2 #(
.INIT(4'h6)
) LUT2_inst0 (
.I0(1'b0),
.I1(I[0]),
.O (LUT2_inst0_O)
... | 6.967403 |
module XOr8x2 (
input [1:0] I0,
input [1:0] I1,
input [1:0] I2,
input [1:0] I3,
input [1:0] I4,
input [1:0] I5,
input [1:0] I6,
input [1:0] I7,
output [1:0] O
);
wire XOr8_inst0_O;
wire XOr8_inst1_O;
XOr8 XOr8_inst0 (
.I({I7[0], I6[0], I5[0], I4[0], I3[0], I2[0], ... | 7.714482 |
module fold_xor84 (
input [3:0] I0,
input [3:0] I1,
input [3:0] I2,
input [3:0] I3,
input [3:0] I4,
input [3:0] I5,
input [3:0] I6,
input [3:0] I7,
output [3:0] O
);
assign O = ((((((I0 ^ I1) ^ I2) ^ I3) ^ I4) ^ I5) ^ I6) ^ I7;
endmodule
| 7.625382 |
module coreir_xor #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output [width-1:0] out
);
assign out = in0 ^ in1;
endmodule
| 8.302408 |
module fold_xor84 (
input [3:0] I0,
input [3:0] I1,
input [3:0] I2,
input [3:0] I3,
input [3:0] I4,
input [3:0] I5,
input [3:0] I6,
input [3:0] I7,
output [3:0] O
);
wire [3:0] xor4_inst0_out;
wire [3:0] xor4_inst1_out;
wire [3:0] xor4_inst2_out;
wire [3:0] xor4_inst3... | 7.625382 |
module XOr8 (
input [7:0] I,
output O
);
wire SB_LUT4_inst0_O;
wire SB_LUT4_inst1_O;
wire SB_LUT4_inst2_O;
wire SB_LUT4_inst3_O;
wire SB_LUT4_inst4_O;
wire SB_LUT4_inst5_O;
wire SB_LUT4_inst6_O;
wire SB_LUT4_inst7_O;
SB_LUT4 #(
.LUT_INIT(16'h6666)
) SB_LUT4_inst0 (
.I0(1'b0),
... | 6.967403 |
module XOr8x4 (
input [3:0] I0,
input [3:0] I1,
input [3:0] I2,
input [3:0] I3,
input [3:0] I4,
input [3:0] I5,
input [3:0] I6,
input [3:0] I7,
output [3:0] O
);
wire XOr8_inst0_O;
wire XOr8_inst1_O;
wire XOr8_inst2_O;
wire XOr8_inst3_O;
XOr8 XOr8_inst0 (
.I({... | 6.76931 |
module XOr8 (
input [7:0] I,
output O
);
wire LUT2_inst0_O;
wire LUT2_inst1_O;
wire LUT2_inst2_O;
wire LUT2_inst3_O;
wire LUT2_inst4_O;
wire LUT2_inst5_O;
wire LUT2_inst6_O;
wire LUT2_inst7_O;
LUT2 #(
.INIT(4'h6)
) LUT2_inst0 (
.I0(1'b0),
.I1(I[0]),
.O (LUT2_inst0_O)
... | 6.967403 |
module XOr8x4 (
input [3:0] I0,
input [3:0] I1,
input [3:0] I2,
input [3:0] I3,
input [3:0] I4,
input [3:0] I5,
input [3:0] I6,
input [3:0] I7,
output [3:0] O
);
wire XOr8_inst0_O;
wire XOr8_inst1_O;
wire XOr8_inst2_O;
wire XOr8_inst3_O;
XOr8 XOr8_inst0 (
.I({... | 6.76931 |
module XOr8 (
input [7:0] I,
output O
);
wire LUT2_inst0_O;
wire LUT2_inst1_O;
wire LUT2_inst2_O;
wire LUT2_inst3_O;
wire LUT2_inst4_O;
wire LUT2_inst5_O;
wire LUT2_inst6_O;
wire LUT2_inst7_O;
LUT2 #(
.INIT(4'h6)
) LUT2_inst0 (
.I0(1'b0),
.I1(I[0]),
.O (LUT2_inst0_O)
... | 6.967403 |
module XOr8x4 (
input [3:0] I0,
input [3:0] I1,
input [3:0] I2,
input [3:0] I3,
input [3:0] I4,
input [3:0] I5,
input [3:0] I6,
input [3:0] I7,
output [3:0] O
);
wire XOr8_inst0_O;
wire XOr8_inst1_O;
wire XOr8_inst2_O;
wire XOr8_inst3_O;
XOr8 XOr8_inst0 (
.I({... | 6.76931 |
module fold_xor88 (
input [7:0] I0,
input [7:0] I1,
input [7:0] I2,
input [7:0] I3,
input [7:0] I4,
input [7:0] I5,
input [7:0] I6,
input [7:0] I7,
output [7:0] O
);
assign O = ((((((I0 ^ I1) ^ I2) ^ I3) ^ I4) ^ I5) ^ I6) ^ I7;
endmodule
| 7.312844 |
module coreir_xor #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output [width-1:0] out
);
assign out = in0 ^ in1;
endmodule
| 8.302408 |
module fold_xor88 (
input [7:0] I0,
input [7:0] I1,
input [7:0] I2,
input [7:0] I3,
input [7:0] I4,
input [7:0] I5,
input [7:0] I6,
input [7:0] I7,
output [7:0] O
);
wire [7:0] xor8_inst0_out;
wire [7:0] xor8_inst1_out;
wire [7:0] xor8_inst2_out;
wire [7:0] xor8_inst3... | 7.312844 |
module XOr8 (
input [7:0] I,
output O
);
wire SB_LUT4_inst0_O;
wire SB_LUT4_inst1_O;
wire SB_LUT4_inst2_O;
wire SB_LUT4_inst3_O;
wire SB_LUT4_inst4_O;
wire SB_LUT4_inst5_O;
wire SB_LUT4_inst6_O;
wire SB_LUT4_inst7_O;
SB_LUT4 #(
.LUT_INIT(16'h6666)
) SB_LUT4_inst0 (
.I0(1'b0),
... | 6.967403 |
module XOr8x8 (
input [7:0] I0,
input [7:0] I1,
input [7:0] I2,
input [7:0] I3,
input [7:0] I4,
input [7:0] I5,
input [7:0] I6,
input [7:0] I7,
output [7:0] O
);
wire XOr8_inst0_O;
wire XOr8_inst1_O;
wire XOr8_inst2_O;
wire XOr8_inst3_O;
wire XOr8_inst4_O;
wire XO... | 6.756891 |
module XOr8 (
input [7:0] I,
output O
);
wire LUT2_inst0_O;
wire LUT2_inst1_O;
wire LUT2_inst2_O;
wire LUT2_inst3_O;
wire LUT2_inst4_O;
wire LUT2_inst5_O;
wire LUT2_inst6_O;
wire LUT2_inst7_O;
LUT2 #(
.INIT(4'h6)
) LUT2_inst0 (
.I0(1'b0),
.I1(I[0]),
.O (LUT2_inst0_O)
... | 6.967403 |
module XOr8x8 (
input [7:0] I0,
input [7:0] I1,
input [7:0] I2,
input [7:0] I3,
input [7:0] I4,
input [7:0] I5,
input [7:0] I6,
input [7:0] I7,
output [7:0] O
);
wire XOr8_inst0_O;
wire XOr8_inst1_O;
wire XOr8_inst2_O;
wire XOr8_inst3_O;
wire XOr8_inst4_O;
wire XO... | 6.756891 |
module XOr8 (
input [7:0] I,
output O
);
wire LUT2_inst0_O;
wire LUT2_inst1_O;
wire LUT2_inst2_O;
wire LUT2_inst3_O;
wire LUT2_inst4_O;
wire LUT2_inst5_O;
wire LUT2_inst6_O;
wire LUT2_inst7_O;
LUT2 #(
.INIT(4'h6)
) LUT2_inst0 (
.I0(1'b0),
.I1(I[0]),
.O (LUT2_inst0_O)
... | 6.967403 |
module XOr8x8 (
input [7:0] I0,
input [7:0] I1,
input [7:0] I2,
input [7:0] I3,
input [7:0] I4,
input [7:0] I5,
input [7:0] I6,
input [7:0] I7,
output [7:0] O
);
wire XOr8_inst0_O;
wire XOr8_inst1_O;
wire XOr8_inst2_O;
wire XOr8_inst3_O;
wire XOr8_inst4_O;
wire XO... | 6.756891 |
module adder_32b_param (
i_a,
i_b,
i_carry,
o_carry,
o_summ
);
parameter WIDTH = 32;
input [WIDTH-1:0] i_a, i_b;
input i_carry;
output [WIDTH-1:0] o_summ;
output o_carry;
`ifdef CSLA_CLA
adder_csla_cla inst_csla (
i_a,
i_b,
i_carry,
o_carry,
o_summ
);
`en... | 8.887384 |
modules without new width define
Coder: Garfield
Organization: XXXX Group, Department of Architecture
------------------------------------------------------
Input ports: a, 8 bits(defined),operents
Output Ports: result_a, 8 bits(defined), data for module without new define (= a + 1)
result_b,... | 7.45079 |
modules without new width define
Coder: Garfield
Organization: XXXX Group, Department of Architecture
------------------------------------------------------
Input ports: a, 8 bits(defined),operents
Output Ports: result, 8 bits(defined), data for module without new define (= a + 1)
--------------------------... | 7.45079 |
modules with new width define
Coder: Garfield
Organization: XXXX Group, Department of Architecture
------------------------------------------------------
Input ports: a, 8 bits(defined),operents
Output Ports: result, 8 bits(defined), data for module without new define (= a + 1)
-----------------------------... | 7.645399 |
module
// if neither it should be a xor
`define and_module
//`define or_module
module define_syntax (a,b,c);
input a;
input b;
output c;
wire c_wire;
assign c = c_wire;
`ifdef and_module
assign c_wire = a & b;
`elsif or_module
assign c_wire = a | b;
`else
assign c_wire = a ^ b;
`endif
endmodule
| 7.111229 |
module NameA ();
parameter ident0 = 12;
parameter ident1 = 20;
wire [31:0] value0 = ident0;
wire [31:0] value1 = ident1;
endmodule
| 6.726203 |
module demonstrates the ability to use a defparam to control
* the instantation of an instance array, and to also control
* parameter values within the instance array.
*/
module main;
localparam wid = 5;
reg [wid-1:0] clk;
dut xx (.clk(clk));
// This defparam sets the desired with of the U instance v... | 7.224853 |
module target (
input wire clk
);
parameter number = 999;
always @(posedge clk) $display("%m: number=%0d", number);
endmodule
| 6.928326 |
module module_a (
out0,
in0
);
input in0;
output [5:0] out0;
parameter [5:0] ident0 = 0;
parameter [5:0] ident1 = 5'h11;
reg [5:0] out0;
// Basic MUX switches on in0
always @(in0) begin
if (in0) out0 = ident0;
else out0 = ident1;
end
endmodule
| 7.916679 |
module_a
module module_b (out0,out1,in0,in1);
input in0;
input in1;
output [5:0] out0;
output [5:0] out1;
module_a testmodA (.out0(out0),.in0(in0));
module_a testmodB (.out0(out1),.in0(in1));
endmodule
| 6.632329 |
module demonstrates the ability to use a defparam to control
* the instantation of an instance array, and to also control
* parameter values within the instance array.
*/
module main;
localparam wid = 5;
reg [wid-1:0] clk;
dut xx (.clk(clk));
// This defparam sets the desired with of the U instance v... | 7.224853 |
module target (
input wire clk
);
parameter number = 999;
always @(posedge clk) $display("%m: number=%0d", number);
endmodule
| 6.928326 |
module demonstrates the ability to use a defparam to control
* the instantation of an instance array, and to also control
* parameter values within the instance array.
*/
module main;
localparam wid = 5;
reg [wid-1:0] clk;
if (wid > 0) begin : D
dut xx (.clk(clk));
end
// This defparam sets ... | 7.224853 |
module target (
input wire clk
);
parameter number = 999;
always @(posedge clk) $display("%m: number=%0d", number);
endmodule
| 6.928326 |
module deg_clk (
clk,
d_clk
);
/* inputs */
input clk;
/* inputs */
/* outputs */
output reg d_clk;
/* outputs */
/* registradores */
reg [26:0] cont;
reg [26:0] cont_aux;
/* registradores */
always @(posedge clk) begin
if (cont == 27'd500000) begin
cont <= 0;
cont_aux ... | 6.568563 |
module dejitter (
input wire clk,
input wire btn,
output reg btn_out
);
reg [31:0] count = 0;
initial btn_out = 0;
always @(posedge clk) begin
if (btn != btn_out) count = count + 1;
else count = 0;
if (count == 5000000) begin
btn_out = btn;
count = 0;
end
end
end... | 6.541185 |
module delay1 #(
parameter word_width = 2
) (
input i_clk,
input wire signed [word_width-1:0] i_data,
output reg signed [word_width-1:0] o_data_d1
);
// delay units pipeline
always @(posedge i_clk) begin
o_data_d1 <= i_data;
end
endmodule
| 7.923808 |
module Delay2n #(
parameter WIDTH = 32,
D = 64,
B = 6
) (
input clk,
rst,
ena,
input [WIDTH-1:0] dat_in,
output [WIDTH-1:0] dat_out
);
reg [WIDTH-1:0] dat_ram [D-1:0];
reg [ B-1:0] adr_cnt;
reg dat_val;
assign dat_out = (dat_val) ? dat_ram[adr_cnt] : 0;
//integer... | 8.080714 |
module delay5 (
clock,
d5_delay_in,
d5_delay_out
);
input clock;
input [`BITS-1:0] d5_delay_in;
output [`BITS-1:0] d5_delay_out;
//FIFO delay
reg [`BITS-1:0] d5_reg1;
/*
reg [`BITS-1:0] d5_reg2;
reg [`BITS-1:0] d5_reg3;
reg [`BITS-1:0] d5_reg4;
reg [`BITS-1:0] d5_reg5;
reg [`BITS-1:0] d5_r... | 6.609939 |
module DelayBorderDetector #(
parameter TempInit = 1'b0
) (
input clk,
input rst,
input D,
output reg up,
output reg down
);
reg temp = TempInit;
always @(posedge clk or posedge rst) begin
if (rst) begin
temp = TempInit;
up = 1'b0;
down = 1'b0;
end else // if ... | 7.131074 |
module DelayBuffer #(
parameter DEPTH = 32,
parameter WIDTH = 16
) (
input clock, // Master Clock
input [WIDTH-1:0] di_re, // Data Input (Real)
input [WIDTH-1:0] di_im, // Data Input (Imag)
output [WIDTH-1:0] do_re, // Data Output (Real)
output [WIDTH-1:0] do_im // ... | 6.771151 |
module top;
reg [4:0] cntr;
wire done;
wire allone;
// A delayed comparison is only 1 bit wide. If this does not crash
// the run time then the compiler is producing correct code.
assign #1 done = cntr == 'd7;
// The same for a reduction.
assign #1 allone = &cntr;
initial $display("PASSED");
endmo... | 7.67792 |
module delayed_on_gate (
input wire clk,
input wire gate,
input wire [31:0] delay,
output reg q = 0
);
reg [3:0] state = 0;
reg [31:0] count = 0;
reg gate_buffer;
always @(posedge clk) begin
gate_buffer <= gate;
end
always @(posedge clk) begin
case (state)
default: begin
... | 7.27944 |
module delayed_on_gate_tb;
parameter MASTER_PERIOD = 20;
// Inputs
wire clk;
clock_gen #(MASTER_PERIOD) mclk (clk);
// Inputs
reg gate;
reg [31:0] delay;
// Outputs
wire q;
// Instantiate the Unit Under Test (UUT)
delayed_on_gate uut (
.clk(clk),
.gate(gate),
.delay(delay),
... | 7.27944 |
module delayGen (
input clock,
input delayEn,
output reg delayDone
);
reg [17:0] counter;
always @(posedge clock) begin
if (delayEn & counter != 200000) counter <= counter + 1;
else counter <= 0;
end
always @(posedge clock) begin
if (delayEn & counter == 200000) delayDone <= 1'b1;
... | 6.765569 |
module delayline_z1 #(
// =============================================================================
// ** Parameters
// =============================================================================
// Size of word
parameter W = 1
) (
// =====================================================... | 8.031542 |
module delayLinieBRAM_WP #(
parameter WIDTH = 11,
parameter BRAM_SIZE_W = 12
) (
input clk,
input rst,
input ce,
input [ WIDTH-1:0] din,
output [ WIDTH-1:0] dout,
input [BRAM_SIZE_W-1:0] h_size
);
reg [BRAM_SIZE_... | 7.748721 |
module delayPPS (
input clk,
input pps_in,
output pps_out,
input rst
);
localparam IDLE = 2'b00;
localparam WAIT = 2'b01;
localparam PULSE = 2'b10;
//Delay the PPS for 300ms
reg [19:0] delay_counter;
reg [19:0] pulse_counter;
reg [19:0] delay_counter_overflow;
reg [19:0] pulse_count... | 8.327915 |
module DelayPUF #(parameter LENGTH = 8) (
input clk,
input reset, // sync (diven by LA)
input [LENGTH-1:0] a_challenge, // async (if src is GPIO)
input a_run, // async (if src is GPIO)
output result
);
wire run;
wire [LENGTH-1:0] a_in, a_out, b_in, b_out;
... | 7.52774 |
module mux_pair(
input a,
input b,
input sel,
output reg out1,
output reg out2
);
`ifdef SIM_MODE
//(* via_celltype = "$_MUX_ Y" *)
//(* via_celltype_defparam_WIDTH = 1 *)
function Fmux2_1;
input A, B, S;
begin
Fmux2_1 = S ? A : B;
end
... | 7.982694 |
module d_sync (
input clk,
input reset,
input in_async,
output reg out
);
reg in_ms;
always @(posedge clk) begin
if (reset) begin
in_ms <= 1'b0;
out <= 1'b0;
end else begin
in_ms <= in_async;
out <= in_ms;
end
end
endmodule
| 6.565109 |
module DelayReg (
input wire [data-1:0] in,
input wire clock,
input wire reset_n,
output reg [data-1:0] out
);
initial begin
out = 0;
end
parameter data = 8;
always @(posedge clock or negedge reset_n) begin : pass_value
if (~reset_n) out = 0;
else out = in;
end
endmodule
| 7.128796 |
module Delays_1_block (
p_2,
pd_2_1
);
input [63:0] p_2; // double
output [63:0] pd_2_1; // double
// <S10>/mux
assign pd_2_1 = p_2;
endmodule
| 6.932368 |
module delayT #(
parameter DATA_WIDTH = 32,
parameter DELAY = 1
) (
input clock,
input reset,
input [DATA_WIDTH-1:0] data_in,
output [DATA_WIDTH-1:0] data_out
);
reg [DATA_WIDTH-1:0] ram[DELAY-1:0];
integer i;
assign data_out = ram[DELAY-1];
always @(posedge clock) begin
if (res... | 7.108301 |
module delay_15bit (
d,
clk,
rst,
q
);
input [1:15] d;
input rst, clk;
output [1:15] q;
reg [1:15] q;
always @(posedge clk or negedge rst) begin
if (!rst) begin
q <= 15'b0;
end else begin
q <= d;
end
end
endmodule
| 7.459563 |
module delay_16bit (
d,
clk,
rst,
q
);
input [1:16] d;
input rst, clk;
output [1:16] q;
reg [1:16] q;
always @(posedge clk or negedge rst) begin
if (!rst) begin
q <= 16'b0;
end else begin
q <= d;
end
end
endmodule
| 6.988899 |
module delay_1bit (
d,
clk,
rst,
q
);
input d, clk, rst;
output q;
reg q;
always @(posedge clk or negedge rst) begin
if (!rst) begin
q <= 1'b0;
end else begin
q <= d;
end
end
endmodule
| 6.884776 |
module Delay_1clk #(
parameter N = 16
) (
clk,
rst,
start,
xn,
xn_1
);
input clk, rst, start;
input [N-1:0] xn;
output reg [N-1:0] xn_1;
always @(posedge clk) begin
if (rst) xn_1 <= 0;
else begin
if (start) xn_1 <= xn;
else xn_1 <= 0;
end
end
endmodule
| 7.219226 |
module delay_1s (
input CLOCK_50,
aclr,
enable,
output Q
);
//50_000_000 - co sekunde przy clock_50
localparam x = 50_000_000;
localparam intervalSize = clogb2(x);
function integer clogb2(input [31:0] v);
for (clogb2 = 0; v > 0; clogb2 = clogb2 + 1) v = v >> 1;
endfunction
wire [int... | 6.680783 |
module delay_31bit (
d,
clk,
rst,
q
);
input [1:31] d;
input rst, clk;
output [1:31] q;
reg [1:31] q;
always @(posedge clk or negedge rst) begin
if (!rst) begin
q <= 31'b0;
end else begin
q <= d;
end
end
endmodule
| 6.757607 |
module delay_32bit (
d,
clk,
rst,
q
);
input [1:32] d;
input rst, clk;
output [1:32] q;
reg [1:32] q;
always @(posedge clk or negedge rst) begin
if (!rst) begin
q <= 32'b0;
end else begin
q <= d;
end
end
endmodule
| 6.668661 |
module delay_3_1 #(
parameter SIG_DATA_WIDTH = 1,
delay_cycles = 3
) (
input clk,
input reset,
input [SIG_DATA_WIDTH-1:0] Data_In,
output [SIG_DATA_WIDTH-1:0] Data_Out
);
reg [SIG_DATA_WIDTH-1:0] FIFO[delay_cycles-1:0];
always @(posedge clk or posedge reset) begin
if (reset) begin
... | 6.55533 |
module Delay_5s (
delay_clk,
delay_enable,
delay_key,
delay_control
);
input wire delay_clk;
input wire delay_enable;
input wire delay_key;
output reg delay_control;
reg [2:0] delay_count;
always @(posedge delay_clk or negedge delay_key) begin
if (~delay_key) begin
delay_control ... | 6.96076 |
module delay_clock (
clk,
resetn,
enable,
in,
out
);
parameter DATA_WIDTH = 8;
parameter N_CLOCKs = 12;
input clk;
input resetn;
input enable;
input [DATA_WIDTH-1:0] in;
output [DATA_WIDTH-1:0] out;
//Registers for delay n clock(s)
wire [DATA_WIDTH-1:0] tmp[0 : N_CLOCKs-1];
... | 8.287416 |
module delay_counter (
input clk,
reset_n,
start,
enable,
input [7:0] delay,
output done
);
parameter BASIC_PERIOD = 20'd500000; // can change this value to make delay longer
endmodule
| 6.853164 |
module delay_counter_tb;
parameter MASTER_PERIOD = 5;
// clocks
clock_gen #(MASTER_PERIOD) mclk (clk);
// Inputs
reg load;
reg [47:0] l;
// Outputs
wire thresh0;
wire [47:0] q;
// Instantiate the Unit Under Test (UUT)
delay_counter uut (
.clk(clk),
.load(load),
.thresh0(thres... | 6.853164 |
module delay_dynamic #(
parameter WIDTH = 16,
parameter TARGET_CHIP = 2, // currently restricted to 2=S5
parameter SIM_EMULATE = 1'b0
) (
input clk,
input [4:0] delta,
// ? avoid delta = 1, r/w collision
// minimum delta=2, latency of 1 tick
// ...
// delta = 1f, latency of... | 6.959863 |
module
// created in component editor. It ties off all outputs to ground and
// ignores all inputs. It needs to be edited to make it do something
// useful.
//
// This file will not be automatically regenerated. You should check it in
// to your version control system if you want to keep it.
`timescale 1 ps / 1 ps... | 7.702374 |
module delay_eight_cycles #(
parameter n = 1
) (
input clk,
input gwe,
input rst,
input [n-1:0] in_value,
output [n-1:0] out_value
);
wire [n-1:0] value_1_2;
wire [n-1:0] value_2_3;
wire [n-1:0] value_3_4;
wire [n-1:0] value_4_5;
wire [n-1:0] value_5_6;
w... | 6.871978 |
module delay_en (
input clk,
input reset,
input enable,
input [(WIDTH-1):0] in,
output wire [(WIDTH-1):0] out
);
parameter WIDTH = 1;
parameter DELAY = 1;
wire [(WIDTH-1):0] in_km[0:DELAY];
assign in_km[0] = in;
genvar i... | 7.239184 |
module delay_en_1 (
input clk,
input reset,
input enable,
input [(WIDTH-1):0] in,
output wire [(WIDTH-1):0] out
);
parameter WIDTH = 1;
reg [(WIDTH-1):0] in_km1;
always @(posedge clk) begin
in_km1 <= reset ? {WIDTH{1'b0}}... | 6.512231 |
module delay_example ();
wire out1, out2, out3, out4, out5, out6;
reg b, c;
// Delay for all transitions
or #5 u_or (out1, b, c);
// Rise and fall delay
and #(1, 2) u_and (out2, b, c);
// Rise, fall and turn off delay
nor #(1, 2, 3) u_nor (out3, b, c);
//One Delay, min, typ and max
nand #(1: 2: 3)... | 6.843136 |
module delay_fifo #(
parameter MAX_LEN = 1023,
parameter WIDTH = 16
) (
input clk,
input reset,
input clear,
input [$clog2(MAX_LEN+1)-1:0] len,
input [WIDTH-1:0] i_tdata,
input i_tlast,
input i_tvalid,
output i_tready,
output [WIDTH-1:0] o_tdata,
output o_tlast,
out... | 7.191961 |
module generates 150us delay, normally required before issuing any commmands
// SDR SDRAM after power ON. It divides the system clock by 64 and then uses 255
// length counter to generate 165us delay(not 150).
// ------------------------------------------------------------------------------... | 7.138045 |
module delay_generator (
input wire clk,
input wire [DelayWidth-1:0] delay,
input wire trigger,
output reg q = 1'b0
);
parameter DelayWidth = 4;
reg waiting = 1'b0;
reg [1:0] state = 2'h0;
reg [DelayWidth-1:0] timer = 0;
always @(posedge clk) begin
q <= 1'b0; // default if not overwrit... | 7.482771 |
module delay_generator_no_retrigger (
input wire clk,
input wire [DelayWidth-1:0] delay,
input wire trigger,
output reg q = 1'b0,
input wire ce
);
parameter DelayWidth = 4;
parameter [DelayWidth-1:0] Null = 0;
reg waiting = 1'b0;
reg [1:0] state = 2'h0;
reg [DelayWidth-1:0] timer = Null;... | 7.482771 |
module delay_integrator (
input clk,
input rst_n,
input fs_enb,
input [35:0] xin,
output reg [35:0] sum
);
wire [35:0] delay;
assign delay = sum + xin;
always @(posedge clk, negedge rst_n)
if (~rst_n) sum <= 1'b0;
else if (fs_enb) sum <= delay;
endmodule
| 6.793596 |
module delay_line #(
parameter WIDTH = 32
) (
input clk,
input [3:0] delay,
input [WIDTH-1:0] din,
output [WIDTH-1:0] dout
);
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : gen_delay
SRL16E srl16e (
.Q (dout[i]),
.A0 (delay[0]),
.A1 (delay[... | 6.851575 |
module delay_line_tb ();
wire [3:0] monitor;
wire data_out;
reg clk = 1'b0;
reg data_in = 1'b0;
reg data_in_gate = 1'b0;
reg data_clr = 1'b1;
delay_line #(2, 2) dl_uut (
.monitor(monitor),
.data_out(data_out),
.clk(clk),
.data_in(data_in),
... | 6.628759 |
module is a memory that stores an image row before its sent
* to the filter.
*
* Created:
* Tue May 7 21:58:44 PDT 2019
*
* Author:
* Berin Martini (berin.martini@gmail.com)
*/
`ifndef _delay_mem_
`define _delay_mem_
`default_nettype none
module delay_mem
#(parameter
IMG_WIDTH = 8,
MEM_AWIDT... | 6.803516 |
module delay_mem_tb;
/**
* Clock and control functions
*/
// Generate a clk
reg clk = 0;
always #1 clk = !clk;
// End of simulation event definition
event end_trigger;
always @(end_trigger) $finish;
`ifdef TB_VERBOSE
// Display header information
initial #1 display_head... | 7.785117 |
module delay_mlab #(
parameter WIDTH = 32,
parameter LATENCY = 5, // minimum of 2, maximum of 33 for s5, 32 for s4
parameter TARGET_CHIP = 1, // 1 S4, 2 S5
parameter FRACTURE = 1 // duplicate the addressing
) (
input clk,
input [WIDTH-1:0] din,
output [WIDTH-1:0] dout
);
//////////////... | 7.124251 |
module
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module delay_module(
CLK,
RST_n,
H2L_Sig,
... | 7.088073 |
module delay_ms (
input clk,
input [11:0] delay_time_ms,
input delay_start,
output delay_done
);
localparam Idle = 0, // state codes
Hold = 1, Done = 2;
localparam MAX = 17'd99999; // count maximum for delay, assuming 100MHz clock signal.
reg [1:0] state = Idle;
reg [... | 7.915824 |
module shift_ram_3x3_8bits (
D,
CLK,
SCLR,
Q
);
(* x_interface_info = "xilinx.com:signal:data:1.0 d_intf DATA" *) input [7:0] D;
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk_intf CLK" *) input CLK;
(* x_interface_info = "xilinx.com:signal:reset:1.0 sclr_intf RST" *) input SCLR;
(* x_in... | 8.499544 |
module shift_ram_3x3_8bits_c_shift_ram_v12_0_9 (
A,
D,
CLK,
CE,
SCLR,
SSET,
SINIT,
Q
);
input [3:0] A;
input [7:0] D;
input CLK;
input CE;
input SCLR;
input SSET;
input SINIT;
output [7:0] Q;
wire [3:0] A;
wire CE;
wire CLK;
wire [7:0] D;
wire [7:0] Q;
wire S... | 8.499544 |
module delay_out
// width of the data for the system
#(
parameter delay_time = 0,
parameter sys_w = 1,
// width of the data for the device
parameter dev_w = 1
) (
// From the device out to the system
input [dev_w-1:0] DATA_OUT_FROM_DEVICE,
output [sys_w-1:0] DATA_OUT_TO_PINS,
input ... | 8.006965 |
module delay_reg (
clock,
enable,
data_in,
data_out
);
parameter DEPTH = 7; // Minimum legal DEPTH is 2
parameter WIDTH = 64;
// RAM info
parameter ADDR_WIDTH = 4; // 2^ADDR_WIDTH must be > DEPTH
parameter NUM_WORDS = 1 << ADDR_WIDTH;
input clock,enable;
input [WIDTH-1:0] data_in;
output [WIDTH-1:0] ... | 7.031185 |
module delay_register #(
parameter WL = 8
) (
input CLK,
input EN,
input [WL - 1 : 0] in,
output reg [WL - 1 : 0] out
);
initial out <= 0;
always @(posedge CLK) if (EN) out <= in;
endmodule
| 7.006405 |
module delay_regs_ena #(
parameter WIDTH = 32,
parameter LATENCY = 5 // at least 1
) (
input clk,
input ena,
input [WIDTH-1:0] din,
output [WIDTH-1:0] dout
);
reg [WIDTH*LATENCY-1:0] storage = {(WIDTH * LATENCY) {1'b0}} /* synthesis preserve */;
generate
if (LATENCY == 1) begin
... | 6.793361 |
module delay_reg_tb ();
parameter DEPTH = 5;
parameter WIDTH = 64;
reg clock, enable;
reg [WIDTH-1:0] data_in;
wire [WIDTH-1:0] data_out;
/////////////////////
// test unit
/////////////////////
delay_reg dut (
.clock(clock),
.enable(enable),
.data_in(data_in),
.data_out(da... | 7.149471 |
module delay_sample #(
parameter DATA_WIDTH = 16,
parameter DELAY_SHIFT = 4
) (
input clock,
input enable,
input reset,
input [(DATA_WIDTH-1):0] data_in,
input input_strobe,
output [(DATA_WIDTH-1):0] data_out,
output reg output_strobe
);
localparam DELAY_SIZE = 1 << DELAY_SHIFT... | 7.837549 |
module delay_signal (
output reg [23:0] out,
input clk,
input [23:0] data,
input wren
);
always @(posedge clk) begin
if (wren) out <= data;
end
endmodule
| 7.246255 |
module is designed to provide a delay of one clock to done signal.
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module delay_sr(
output reg out,
input wire d,
input wir... | 7.739429 |
module delay_tb;
/**
* Clock and control functions
*/
// Generate a clk
reg clk = 0;
always #1 clk = !clk;
// End of simulation event definition
event end_trigger;
always @(end_trigger) $finish;
`ifdef TB_VERBOSE
// Display header information
initial #1 display_header()... | 7.717237 |
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