code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module demo_de0_sys_nios2_qsys_0_register_bank_a_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input clock;
input [31:0] data;
input [4:0] rdaddress;
input [4:0] wraddress;
input wren;
wi... | 7.671859 |
module demo_de0_sys_nios2_qsys_0_register_bank_b_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input clock;
input [31:0] data;
input [4:0] rdaddress;
input [4:0] wraddress;
input wren;
wi... | 7.671859 |
module demo_de0_sys_nios2_qsys_0_ociram_lpm_dram_bdp_component_module (
// inputs:
address_a,
address_... | 7.671859 |
module demo_de0_sys_nios2_qsys_0_nios2_avalon_reg (
// inputs:
address,
chipselect,
clk,
debugaccess,
monitor_error,
monitor_go,
monitor_ready,
reset_n,
write,
writedata,
// outputs:
oci_ienable,
oci_reg_readdata,
oci_single_step_mode,
ocireg_ers,
oci... | 7.671859 |
module demo_de0_sys_nios2_qsys_0_nios2_oci_td_mode (
// inputs:
ctrl,
// outputs:
td_mode
);
output [3:0] td_mode;
input [8:0] ctrl;
wire [2:0] ctrl_bits_for_mux;
reg [3:0] td_mode;
assign ctrl_bits_for_mux = ctrl[7 : 5];
always @(ctrl_bits_for_mux) begin
case (ctrl_bits_for_mux)
... | 7.671859 |
module demo_de0_sys_nios2_qsys_0_nios2_oci_dtrace (
// inputs:
clk,
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
jrst_n,
trc_ctrl,
// outputs:
atm,
dtm
);
output [35:0] atm;
output [35:0] dtm;
input clk;
input [24:0] c... | 7.671859 |
module demo_de0_sys_nios2_qsys_0_nios2_oci_compute_tm_count (
// inputs:
atm_valid,
dtm_valid,
itm_valid,
// outputs:
compute_tm_count
);
output [1:0] compute_tm_count;
input atm_valid;
input dtm_valid;
input itm_valid;
reg [1:0] compute_tm_count;
wire [2:0] switch_for_mux;
ass... | 7.671859 |
module demo_de0_sys_nios2_qsys_0_nios2_oci_fifowp_inc (
// inputs:
free2,
free3,
tm_count,
// outputs:
fifowp_inc
);
output [3:0] fifowp_inc;
input free2;
input free3;
input [1:0] tm_count;
reg [3:0] fifowp_inc;
always @(free2 or free3 or tm_count) begin
if (free3 & (tm_count ... | 7.671859 |
module demo_de0_sys_nios2_qsys_0_nios2_oci_fifocount_inc (
// inputs:
empty,
free2,
free3,
tm_count,
// outputs:
fifocount_inc
);
output [4:0] fifocount_inc;
input empty;
input free2;
input free3;
input [1:0] tm_count;
reg [4:0] fifocount_inc;
always @(empty or free2 or free... | 7.671859 |
module demo_de0_sys_nios2_qsys_0_nios2_oci_pib (
// inputs:
clk,
clkx2,
jrst_n,
tw,
// outputs:
tr_clk,
tr_data
);
output tr_clk;
output [17:0] tr_data;
input clk;
input clkx2;
input jrst_n;
input [35:0] tw;
wire phase;
wire tr_clk;
reg tr_clk_r... | 7.671859 |
module demo_de0_sys_nios2_qsys_0_traceram_lpm_dram_bdp_component_module (
// inputs:
address_a,
... | 7.671859 |
module demo_de0_sys_nios2_qsys_0_nios2_performance_monitors;
endmodule
| 7.671859 |
module demo_de0_sys_nios2_qsys_0_oci_test_bench (
// inputs:
dct_buffer,
dct_count,
test_ending,
test_has_ended
);
input [29:0] dct_buffer;
input [3:0] dct_count;
input test_ending;
input test_has_ended;
endmodule
| 7.671859 |
module demo_de0_sys_pio_0 (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input [1:0] address;
input clk;
input [11:0] in_port;
input reset_n;
wire clk_en;
wire [11:0] data_in;
wire [11:0] read_mux_out;
reg [31:0] read... | 7.671859 |
module demo_de0_sys_ram_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "../demo_de0_sys_ram_0.hex";
output [31:0] readdata;
input [10:0] address;
input [3:0] byteenable;
input ch... | 7.671859 |
module demo_de0_sys_sdram_0_input_efifo_module (
// inputs:
clk,
rd,
reset_n,
wr,
wr_data,
// outputs:
almost_empty,
almost_full,
empty,
full,
rd_data
);
output almost_empty;
output almost_full;
output empty;
output full;
output [40:0] rd_data;
input clk;
... | 7.671859 |
module demo_de0_sys_sdram_0_test_component_ram_module (
// inputs:
data,
rdaddress,
rdclken,
wraddress,
wrclock,
wren,
// outputs:
q
);
output [15:0] q;
input [15:0] data;
input [21:0] rdaddress;
input rdclken;
input [21:0] wraddress;
input wrclock;
input wren;
reg... | 7.671859 |
module demo_de0_sys_sysid_qsys_0 (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input address;
input clock;
input reset_n;
wire [31:0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 1345812261 : 1278338;
... | 7.671859 |
module demo_de0_sys_timing_adapter (
// Interface: clk
input clk,
// Interface: reset
input reset_n,
// Interface: in
output reg in_ready,
input in_valid,
input [31:0] in_data,
// Interface: out
input out_ready,
out... | 7.671859 |
module demo_de0_sys_timing_adapter_fifo (
output reg [3:0] fill_level,
// Interface: clock
input clk,
input reset_n,
// Interface: data_in
output reg in_ready,
input in_valid,
input [31:0] in_data,
// Interface: data_out
input ... | 7.671859 |
module demo_filters (
input in,
output out,
output valid_in,
output valid_out,
input clock,
input reset
);
wire usec_tick, msec_tick, interconnect;
pulser #(
.count(`CLOCK_MHZ-1)
) usec_pulser (
.enable(1'b1),
.out(usec_tick),
.clock(clock),
.reset(reset)
);
pulser #(
.count(1000)
) msec_pulser (
.e... | 7.367423 |
module demo_io #(
parameter WIDTH = 32, // Wishbone bus size
parameter GPO_BITS = 16, // bits of general purpose output
parameter GPI_BITS = 4 // bits of general purpose input
) (
input wire clk,
input wire rst_n,
// Wishbone Bob
input wire [ 1... | 9.297425 |
module Demo
//
module Demo (io_reset, io_leds) /* synthesis syn_module_defined=1 */ ; // /home/julien/Documents/git/3rd/SpinalJRC/Demo.v(7[8:12])
input io_reset; // /home/julien/Documents/git/3rd/SpinalJRC/Demo.v(8[23:31])
output [7:0]io_leds; // /home/julien/Documents/git/3rd/SpinalJRC/Demo.v(9[23:30])
... | 6.898641 |
module demo_reg (
clk,
reset_n,
reg_addr,
reg_data_i,
reg_data_o,
reg_rd,
reg_wr
);
input clk;
input reset_n;
input [6:0] reg_addr;
input [7:0] reg_data_i;
input reg_rd;
input reg_wr;
output [7:0] reg_data_o;
reg [7:0] reg_data_o;
reg [7:0] reg_data [0:127];
... | 6.523183 |
module fa__0_4 (
in1,
in2,
cin,
sum,
cout
);
input in1;
input in2;
input cin;
output sum;
output cout;
wire n_0_0;
wire n_0_1;
wire n_0_2;
NAND2_X1 i_0_0 (
.A1(n_0_2),
.A2(n_0_0),
.ZN(cout)
);
OAI21_X1 i_0_1 (
.A (in2),
.B1(cin),
.B2(in1),
... | 6.805331 |
module fa__0_7 (
in1,
in2,
cin,
sum,
cout
);
input in1;
input in2;
input cin;
output sum;
output cout;
wire n_0_0;
wire n_0_1;
wire n_0_2;
NAND2_X1 i_0_0 (
.A1(n_0_2),
.A2(n_0_0),
.ZN(cout)
);
OAI21_X1 i_0_1 (
.A (in2),
.B1(cin),
.B2(in1),
... | 6.848597 |
module fa__0_10 (
in1,
in2,
cin,
sum,
cout
);
input in1;
input in2;
input cin;
output sum;
output cout;
wire n_0_0;
wire n_0_1;
wire n_0_2;
NAND2_X1 i_0_0 (
.A1(n_0_2),
.A2(n_0_0),
.ZN(cout)
);
OAI21_X1 i_0_1 (
.A (in2),
.B1(cin),
.B2(in1),... | 7.045926 |
module fa__0_13 (
in1,
in2,
cin,
sum,
cout
);
input in1;
input in2;
input cin;
output sum;
output cout;
wire n_0_0;
wire n_0_1;
wire n_0_2;
NAND2_X1 i_0_0 (
.A1(n_0_2),
.A2(n_0_0),
.ZN(cout)
);
OAI21_X1 i_0_1 (
.A (in2),
.B1(cin),
.B2(in1),... | 6.9437 |
module fa__0_16 (
in1,
in2,
cin,
sum,
cout
);
input in1;
input in2;
input cin;
output sum;
output cout;
wire n_0_0;
wire n_0_1;
wire n_0_2;
NAND2_X1 i_0_0 (
.A1(n_0_2),
.A2(n_0_0),
.ZN(cout)
);
OAI21_X1 i_0_1 (
.A (in2),
.B1(cin),
.B2(in1),... | 6.870659 |
module fa__0_19 (
in1,
in2,
cin,
sum,
cout
);
input in1;
input in2;
input cin;
output sum;
output cout;
wire n_0_0;
wire n_0_1;
wire n_0_2;
NAND2_X1 i_0_0 (
.A1(n_0_2),
.A2(n_0_0),
.ZN(cout)
);
OAI21_X1 i_0_1 (
.A (in2),
.B1(cin),
.B2(in1),... | 6.925257 |
module fa__0_22 (
in1,
in2,
cin,
sum,
cout
);
input in1;
input in2;
input cin;
output sum;
output cout;
wire n_0_0;
wire n_0_1;
wire n_0_2;
NAND2_X1 i_0_0 (
.A1(n_0_2),
.A2(n_0_0),
.ZN(cout)
);
OAI21_X1 i_0_1 (
.A (in2),
.B1(cin),
.B2(in1),... | 6.782983 |
module fa__0_25 (
in1,
in2,
cin,
sum,
cout
);
input in1;
input in2;
input cin;
output sum;
output cout;
wire n_0_0;
wire n_0_1;
wire n_0_2;
NAND2_X1 i_0_0 (
.A1(n_0_2),
.A2(n_0_0),
.ZN(cout)
);
OAI21_X1 i_0_1 (
.A (in2),
.B1(cin),
.B2(in1),... | 6.925103 |
module fa__0_28 (
in1,
in2,
cin,
sum,
cout
);
input in1;
input in2;
input cin;
output sum;
output cout;
wire n_0_0;
wire n_0_1;
wire n_0_2;
NAND2_X1 i_0_0 (
.A1(n_0_2),
.A2(n_0_0),
.ZN(cout)
);
OAI21_X1 i_0_1 (
.A (in2),
.B1(cin),
.B2(in1),... | 6.701688 |
module fa__0_31 (
in1,
in2,
cin,
sum,
cout
);
input in1;
input in2;
input cin;
output sum;
output cout;
wire n_0_0;
wire n_0_1;
wire n_0_2;
NAND2_X1 i_0_0 (
.A1(n_0_2),
.A2(n_0_0),
.ZN(cout)
);
OAI21_X1 i_0_1 (
.A (in2),
.B1(cin),
.B2(in1),... | 6.705963 |
module fa__0_37 (
in1,
in2,
cin,
sum,
cout
);
input in1;
input in2;
input cin;
output sum;
output cout;
wire n_0_0;
wire n_0_1;
wire n_0_2;
NAND2_X1 i_0_0 (
.A1(n_0_2),
.A2(n_0_0),
.ZN(cout)
);
OAI21_X1 i_0_1 (
.A (in2),
.B1(cin),
.B2(in1),... | 6.962969 |
module fa__0_40 (
in1,
in2,
cin,
sum,
cout
);
input in1;
input in2;
input cin;
output sum;
output cout;
wire n_0_0;
wire n_0_1;
wire n_0_2;
NAND2_X1 i_0_0 (
.A1(n_0_2),
.A2(n_0_0),
.ZN(cout)
);
OAI21_X1 i_0_1 (
.A (in2),
.B1(cin),
.B2(in1),... | 6.583199 |
module fa__0_43 (
in1,
in2,
cin,
sum,
cout
);
input in1;
input in2;
input cin;
output sum;
output cout;
wire n_0_0;
wire n_0_1;
wire n_0_2;
NAND2_X1 i_0_0 (
.A1(n_0_2),
.A2(n_0_0),
.ZN(cout)
);
OAI21_X1 i_0_1 (
.A (in2),
.B1(cin),
.B2(in1),... | 6.907205 |
module fa__0_46 (
in1,
in2,
cin,
sum,
cout
);
input in1;
input in2;
input cin;
output sum;
output cout;
wire n_0_0;
wire n_0_1;
wire n_0_2;
NAND2_X1 i_0_0 (
.A1(n_0_2),
.A2(n_0_0),
.ZN(cout)
);
OAI21_X1 i_0_1 (
.A (in2),
.B1(cin),
.B2(in1),... | 6.913391 |
module fa__0_49 (
in1,
in2,
cin,
sum,
cout
);
input in1;
input in2;
input cin;
output sum;
output cout;
wire n_0_0;
wire n_0_1;
wire n_0_2;
NAND2_X1 i_0_0 (
.A1(n_0_2),
.A2(n_0_0),
.ZN(cout)
);
OAI21_X1 i_0_1 (
.A (in2),
.B1(cin),
.B2(in1),... | 6.714084 |
module fa__0_52 (
in1,
in2,
cin,
sum,
cout
);
input in1;
input in2;
input cin;
output sum;
output cout;
wire n_0_0;
wire n_0_1;
wire n_0_2;
NAND2_X1 i_0_0 (
.A1(n_0_2),
.A2(n_0_0),
.ZN(cout)
);
OAI21_X1 i_0_1 (
.A (in2),
.B1(cin),
.B2(in1),... | 6.785892 |
module fa__0_55 (
in1,
in2,
cin,
sum,
cout
);
input in1;
input in2;
input cin;
output sum;
output cout;
wire n_0_0;
wire n_0_1;
wire n_0_2;
NAND2_X1 i_0_0 (
.A1(n_0_2),
.A2(n_0_0),
.ZN(cout)
);
OAI21_X1 i_0_1 (
.A (in2),
.B1(cin),
.B2(in1),... | 6.878431 |
module fa__0_58 (
in1,
in2,
cin,
sum,
cout
);
input in1;
input in2;
input cin;
output sum;
output cout;
wire n_0_0;
wire n_0_1;
wire n_0_2;
NAND2_X1 i_0_0 (
.A1(n_0_2),
.A2(n_0_0),
.ZN(cout)
);
OAI21_X1 i_0_1 (
.A (in2),
.B1(cin),
.B2(in1),... | 7.069304 |
module fa__0_61 (
in1,
in2,
cin,
sum,
cout
);
input in1;
input in2;
input cin;
output sum;
output cout;
wire n_0_0;
wire n_0_1;
wire n_0_2;
NAND2_X1 i_0_0 (
.A1(n_0_2),
.A2(n_0_0),
.ZN(cout)
);
OAI21_X1 i_0_1 (
.A (in2),
.B1(cin),
.B2(in1),... | 7.033368 |
module fa__0_64 (
in1,
in2,
cin,
sum,
cout
);
input in1;
input in2;
input cin;
output sum;
output cout;
wire n_0_0;
wire n_0_1;
wire n_0_2;
NAND2_X1 i_0_0 (
.A1(n_0_2),
.A2(n_0_0),
.ZN(cout)
);
OAI21_X1 i_0_1 (
.A (in2),
.B1(cin),
.B2(in1),... | 6.833115 |
module fa__0_67 (
in1,
in2,
cin,
sum,
cout
);
input in1;
input in2;
input cin;
output sum;
output cout;
wire n_0_0;
wire n_0_1;
wire n_0_2;
NAND2_X1 i_0_0 (
.A1(n_0_2),
.A2(n_0_0),
.ZN(cout)
);
OAI21_X1 i_0_1 (
.A (in2),
.B1(cin),
.B2(in1),... | 6.964774 |
module fa__0_70 (
in1,
in2,
cin,
sum,
cout
);
input in1;
input in2;
input cin;
output sum;
output cout;
wire n_0_0;
wire n_0_1;
wire n_0_2;
NAND2_X1 i_0_0 (
.A1(n_0_2),
.A2(n_0_0),
.ZN(cout)
);
OAI21_X1 i_0_1 (
.A (in2),
.B1(cin),
.B2(in1),... | 6.990456 |
module fa__0_73 (
in1,
in2,
cin,
sum,
cout
);
input in1;
input in2;
input cin;
output sum;
output cout;
wire n_0_0;
wire n_0_1;
wire n_0_2;
NAND2_X1 i_0_0 (
.A1(n_0_2),
.A2(n_0_0),
.ZN(cout)
);
OAI21_X1 i_0_1 (
.A (in2),
.B1(cin),
.B2(in1),... | 7.067284 |
module fa__0_76 (
in1,
in2,
cin,
sum,
cout
);
input in1;
input in2;
input cin;
output sum;
output cout;
wire n_0_0;
wire n_0_1;
wire n_0_2;
NAND2_X1 i_0_0 (
.A1(n_0_2),
.A2(n_0_0),
.ZN(cout)
);
OAI21_X1 i_0_1 (
.A (in2),
.B1(cin),
.B2(in1),... | 6.937724 |
module fa__0_79 (
in1,
in2,
cin,
sum,
cout
);
input in1;
input in2;
input cin;
output sum;
output cout;
wire n_0_0;
wire n_0_1;
wire n_0_2;
NAND2_X1 i_0_0 (
.A1(n_0_2),
.A2(n_0_0),
.ZN(cout)
);
OAI21_X1 i_0_1 (
.A (in2),
.B1(cin),
.B2(in1),... | 6.817347 |
module fa__0_82 (
in1,
in2,
cin,
sum,
cout
);
input in1;
input in2;
input cin;
output sum;
output cout;
wire n_0_0;
wire n_0_1;
wire n_0_2;
NAND2_X1 i_0_0 (
.A1(n_0_2),
.A2(n_0_0),
.ZN(cout)
);
OAI21_X1 i_0_1 (
.A (in2),
.B1(cin),
.B2(in1),... | 6.781392 |
module fa__0_85 (
in1,
in2,
cin,
sum,
cout
);
input in1;
input in2;
input cin;
output sum;
output cout;
wire n_0_0;
wire n_0_1;
wire n_0_2;
NAND2_X1 i_0_0 (
.A1(n_0_2),
.A2(n_0_0),
.ZN(cout)
);
OAI21_X1 i_0_1 (
.A (in2),
.B1(cin),
.B2(in1),... | 7.079903 |
module fa__0_88 (
in1,
in2,
cin,
sum,
cout
);
input in1;
input in2;
input cin;
output sum;
output cout;
wire n_0_0;
wire n_0_1;
wire n_0_2;
NAND2_X1 i_0_0 (
.A1(n_0_2),
.A2(n_0_0),
.ZN(cout)
);
OAI21_X1 i_0_1 (
.A (in2),
.B1(cin),
.B2(in1),... | 7.120886 |
module fa__0_91 (
in1,
in2,
cin,
sum,
cout
);
input in1;
input in2;
input cin;
output sum;
output cout;
wire n_0_0;
wire n_0_1;
wire n_0_2;
NAND2_X1 i_0_0 (
.A1(n_0_2),
.A2(n_0_0),
.ZN(cout)
);
OAI21_X1 i_0_1 (
.A (in2),
.B1(cin),
.B2(in1),... | 6.962943 |
module fa__0_94 (
in1,
in2,
cin,
sum,
cout
);
input in1;
input in2;
input cin;
output sum;
output cout;
wire n_0_0;
wire n_0_1;
wire n_0_2;
NAND2_X1 i_0_0 (
.A1(n_0_2),
.A2(n_0_0),
.ZN(cout)
);
OAI21_X1 i_0_1 (
.A (in2),
.B1(cin),
.B2(in1),... | 6.794956 |
module fa (
in1,
in2,
cin,
sum,
cout
);
input in1;
input in2;
input cin;
output sum;
output cout;
wire n_0_0;
wire n_0_1;
wire n_0_2;
NAND2_X1 i_0_0 (
.A1(n_0_2),
.A2(n_0_0),
.ZN(cout)
);
OAI21_X1 i_0_1 (
.A (in2),
.B1(cin),
.B2(in1),
... | 7.005295 |
module M7S_IO_LVDS (
id_1,
id_0,
id_q_1,
id_q_0,
align_rstn,
alignwd,
clk_en_1,
clk_en_0,
io_reg_clk,
geclk,
geclk270,
geclk180,
geclk90,
od_d_1,
od_d_0,
oen_1,
oen_0,
clk_0,
clk_1,
rstn_0,
rstn_1,
setn_0,
setn_1,
PAD1,
... | 7.454371 |
module lvds_tx_v1 (
clk,
rstn,
clk_out_p,
clk_out_n,
tx_out_p,
tx_out_n,
tx_sclk,
tx_out,
tx_data_align_rstn
);
input clk, rstn, tx_data_align_rstn;
output clk_out_p, clk_out_n, tx_sclk;
input [27:0] tx_out;
output [3:0] tx_out_p;
output [3:0] tx_out_n;
wire pll_clkout1;
... | 6.705966 |
module demo_shift_reg (
input clk,
input rst_n,
input enable,
input [15:0] input_data,
output reg [415:0] result
);
reg state;
reg next_state;
reg [15:0] reg_datain;
always @(posedge clk or negedge rst_n) begin
if (rst_n == 1'b0) begin
state <... | 7.568725 |
module datapath (
b,
a,
sum
);
input [31:0] b;
input [31:0] a;
output [32:0] sum;
HA_X1 i_0 (
.A (b[0]),
.B (a[0]),
.CO(n_0),
.S (sum[0])
);
FA_X1 i_1 (
.A (b[1]),
.B (a[1]),
.CI(n_0),
.CO(n_1),
.S (sum[1])
);
FA_X1 i_2 (
.A (b[2])... | 6.91752 |
module demultiplex (
input [11:0] p0,
p1,
p2,
p3,
input [ 3:0] state,
input valid0,
valid1,
valid2,
valid3,
input clk,
output reg [11:0] demuxOut
);
reg [3:0] buffer0, buffer1;
always @(posedge clk) begin
buffer0[0] <= valid0;
buf... | 6.706991 |
module demultiplexador #(
parameter data_bits = 32,
out1_bits_size = 32,
out2_bits_size = 32,
bits_to_out1 = 32,
bits_to_out2 = 32
) (
input wire selector, //entrada de seleção da saída de dados.
input wire [ data_bits-1:0] data, //entrada de dados.
outpu... | 9.413928 |
module Demultiplexer5 (
out0,
out1,
out2,
out3,
out4,
in,
sel
);
parameter WIDTH = 1;
output reg [WIDTH-1:0] out0, out1, out2, out3, out4;
input [WIDTH-1:0] in;
input [2:0] sel;
always @(*) begin
out0 = 0;
out1 = 0;
out2 = 0;
out3 = 0;
out4 = 0;
case (sel)
... | 8.176319 |
module Demultiplexer_16 (
demuxIn,
demuxOut_0,
demuxOut_1,
demuxOut_10,
demuxOut_11,
demuxOut_12,
demuxOut_13,
demuxOut_14,
demuxOut_15,
demuxOut_2,
demuxOut_3,
demuxOut_4,
demuxOut_5,
demuxOut_6,
demuxOut_7,
demuxOut_8,
demuxOut_9,
enable,
sel... | 8.176319 |
module Demultiplexer_1_to_4 (
x,
b1,
b0,
z3,
z2,
z1,
z0
);
input x, b1, b0;
output z3, z2, z1, z0;
assign z3 = ({b1, b0} == 'B11) ? x : 0; // 'B11 = 3
assign z2 = ({b1, b0} == 'B10) ? x : 0; // 'B10 = 2
assign z1 = ({b1, b0} == 'B01) ? x : 0; // 'B01 = 1
assign z0 = ({b1, b0}... | 8.176319 |
module demuxtest_1_to_8;
reg in;
reg [2:0] select_lines;
wire [7:0] output_lines;
demultiplexer_1_to_8 wire_driver (
in,
select_lines,
output_lines
);
initial begin
in = 1;
select_lines = 3'b000;
#20 select_lines = 3'b001;
#20 select_lines = 3'b010;
#20 select_lines =... | 7.152116 |
module Demultiplexer_2 (
DemuxIn,
Enable,
Sel,
DemuxOut_0,
DemuxOut_1
);
/***************************************************************************
** Here the inputs are defined **
***************************************************************... | 8.176319 |
module Demultiplexer_8 (
DemuxIn,
Enable,
Sel,
DemuxOut_0,
DemuxOut_1,
DemuxOut_2,
DemuxOut_3,
DemuxOut_4,
DemuxOut_5,
DemuxOut_6,
DemuxOut_7
);
/***************************************************************************
** Here the inputs are defined ... | 8.176319 |
module Demultiplexor (
input wire [8:0] dataIN,
output wire [8:0] dataOUTA,
output wire [8:0] dataOUTB,
input wire sel
);
assign dataOUTA = (dataIN) * (!sel);
assign dataOUTB = (dataIN) * sel;
endmodule
| 8.595024 |
module mux_2_32bit (
out,
select,
in0,
in1
);
input select;
input [12:0] in0, in1;
output [12:0] out;
assign out = select ? in1 : in0;
endmodule
| 8.695669 |
module mux_4_32bit (
out,
select,
in0,
in1,
in2,
in3
);
input [1:0] select;
input [12:0] in0, in1, in2, in3;
output [12:0] out;
wire [12:0] w1, w2;
mux_2_32bit first_top (
w1,
select[0],
in0,
in1
);
mux_2_32bit first_bottom (
w2,
select[0],
... | 8.286061 |
module mux_8_32bit (
out,
select,
in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7
);
input [2:0] select;
input [12:0] in0, in1, in2, in3, in4, in5, in6, in7;
output [12:0] out;
wire [12:0] w1, w2;
mux_4_32bit top (
w1,
select[1:0],
in0,
in1,
in2,
... | 8.026548 |
module mux_32_32bit (
out,
select,
in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7,
in8,
in9,
in10,
in11,
in12,
in13,
in14,
in15,
in16,
in17,
in18,
in19,
in20,
in21,
in22,
in23,
in24,
in25,
in26,
in27,
in2... | 6.540275 |
module for 1:2 DEMUX
module demux1to2( Data_in, sel, Data_out_0, Data_out_1 );
//list the inputs and their sizes
input Data_in;
input sel;
//list the outputs and their sizes
output Data_out_0;
output Data_out_1;
//Internal variables
reg Data_out_0;
reg Data_out_1;
//always bl... | 8.017418 |
module demux1to #(
parameter N = 2
) (
input wire [N-1 : 0] sel,
input wire in,
output reg [0 : (1<<N)-1] out
);
always @(*) begin
out = 0;
out[sel] = in;
end
endmodule
| 7.220366 |
module deMUX1To2n #(
parameter n = 2,
parameter logn = $clog2(n)
) (
output reg [n-1:0] outDemux,
input a,
input [logn-1:0] s
);
// initially set all outputs to 0
initial begin
outDemux = 0;
end
// all outputs have to be 0, except for the selected output required
always @(a, s) begin... | 8.410923 |
module demux1to4 (
in,
sel,
out0,
out1,
out2,
out3
);
input [1:0] sel; // array type input declaration
input in;
output out0, out1, out2, out3;
reg out0, out1, out2, out3;
always @(in or sel) begin
case (sel)
2'b00: begin
out0 = in;
out1 = 0;
ou... | 6.755053 |
module demux18 (
d,
e1,
e2,
e3,
r1,
r2,
r3,
r4,
r5,
r6,
r7,
r8
);
input d, e1, e2, e3;
output r1, r2, r3, r4, r5, r6, r7, r8;
wire w1, w2;
demux12 a (
d,
e1,
w1,
w2
);
demux14 a1 (
w1,
e2,
e3,
r1,
r2,
... | 6.544482 |
module demux14 (
d,
s1,
s2,
y1,
y2,
y3,
y4
);
input d, s1, s2;
output y1, y2, y3, y4;
assign y1 = (~s1) & (~s2) & d;
assign y2 = (~s1) & (s2) & d;
assign y3 = (s1) & (~s2) & d;
assign y4 = (s1) & (s2) & d;
endmodule
| 7.945475 |
module , when 1:4 demux has to make with 1:2 demux
module demux12(d,s1,y1,y2);
input d,s1;
output y1,y2;
assign y1 = (~s1)&d;
assign y2 = (s1)&d;
endmodule
| 7.300223 |
module demux1to9 #(
parameter CATCH_START_BIT = 10
) (
clk,
Data_in,
sel,
Data_out_0,
Data_out_1,
Data_out_2,
Data_out_3,
Data_out_4,
Data_out_5,
Data_out_6,
Data_out_7,
Data_out_8
);
input clk;
input Data_in;
input [4:0] sel;
output reg Data_out_0 = 0;
outp... | 6.519594 |
module demux1x2 (
xin,
enable,
yout
);
input xin, enable;
output [1:0] yout;
reg [1:0] yout;
always @(xin or enable) begin
if (enable == 1)
case (xin)
1'b0: yout = 2'b10;
1'b1: yout = 2'b01;
endcase
else yout = 2'b00;
end
endmodule
| 7.106268 |
module demux1x2_rtl (
output reg out0,
out1,
input s,
in
);
always @(s, in) begin
out0 = ~((~(in & (~(s & s)))) & (~(in & (~(s & s)))));
out1 = ~((~(in & s)) & (~(in & s)));
end
endmodule
| 7.342222 |
module demux1x2_rtl_tb;
reg s, in;
wire out0, out1;
integer i;
demux1x2_rtl obj (
.s(s),
.in(in),
.out0(out0),
.out1(out1)
);
initial $monitor("in=%b,s=%b,out0=%b,out1=%b", in, s, out0, out1);
initial begin
for (i = 0; i <= 3; i = i + 1) begin
{s, in} = i;
#10;
... | 7.065848 |
module dmux (
in,
s,
o1,
o2,
o3,
o4
);
input in;
input [1:0] s;
output o1, o2, o3, o4;
reg o1, o2, o3, o4;
always @(in, s) begin
o1 = 0;
o2 = 0;
o3 = 0;
o4 = 0;
if (s == 2'b00) o1 = in;
else if (s == 2'b01) o2 = in;
else if (s == 2'b10) o3 = in;
else if ... | 7.328451 |
module Demux1x4data (
input x,
input s0,
input s1,
output y0,
output y1,
output y2,
output y3
);
assign y0 = x & (~s1) & (~s0);
assign y1 = x & (~s1) & (s0);
assign y2 = x & (s1) & (~s0);
assign y3 = x & (s1) & (s0);
endmodule
| 8.558828 |
module demux1_2_gate (
a,
b,
c,
s
);
input c, s;
output a, b;
wire x;
not_gate not_gate_1 (
x,
s
);
and_gate and_gate_2 (
a,
c,
s
);
and_gate and_gate_3 (
b,
c,
x
);
endmodule
| 7.61294 |
module demux1_4 (
Inp,
S,
OutA,
OutB,
OutC,
OutD
);
input Inp;
input [1:0] S;
output OutA, OutB, OutC, OutD;
wire abInp, cdInp;
demux1_2 iDEMUX1_2_3 (
.Inp(Inp),
.S(S[1]),
.OutA(abInp),
.OutB(cdInp)
);
demux1_2 iDEMUX1_2_1 (
.Inp(abInp),
.S(S[... | 6.620665 |
module demux4_1_gate (
o0,
o1,
o2,
o3,
i,
s0,
s1
);
input i, s0, s1;
output o0, o1, o2, o3;
wire x, y;
demux2_1_gate demux2_1_gate_3 (
x,
z,
i,
s1
);
demux2_1_gate demux2_1_gate_1 (
o0,
o1,
x,
s0
);
demux2_1_gate demux2_1_gate_2... | 7.53669 |
module demux8_1_gate (
o0,
o1,
o2,
o3,
o4,
o5,
o6,
o7,
i,
s0,
s1,
s2
);
input i, s0, s1, s2;
output o0, o1, o2, o3, o4, o5, o6, o7;
wire x, y;
demux2_1_gate demux2_1_gate_3 (
x,
y,
i,
s2
);
demux2_1_gate demux2_1_gate_1 (
o0,
... | 6.879082 |
module demux2 #(
parameter WIDTH = 16
) (
input [WIDTH-1:0] d_in,
input sel,
output reg [WIDTH-1:0] zero,
output reg [WIDTH-1:0] one
);
always @(*) begin
if (sel == 1'b0) begin
zero = d_in;
one = 0;
end else if (sel == 1'b1) begin
zero = 0;
one = d_in;
end el... | 7.931241 |
module demux26 (
inp,
s,
out1,
out2
);
input s;
input [31:0] inp;
output reg [25:0] out1, out2;
always @(inp) begin
if (s) out2 = inp[25:0];
else out1 = inp[25:0];
end
endmodule
| 6.626513 |
module used in spdu module
*/
module demux (in0, in1, in2, in3, d0, d1, out);
// outputs
output out;
// inputs
input in0, in1, in2, in3;
input d0, d1;
// registers
reg temp1, temp2, out;
always@(in0 or in1 or in2 or in3 or d0 or d1)
begin
temp1 = d0?in1:in0;
... | 6.715398 |
module demux (
output [3:0] s,
input [1:0] selec,
input x
);
reg [3:0] s;
always @(s or selec or x) begin
if (selec == 00) begin
s <= 4'b0001;
end else if (selec == 01) begin
s <= 4'b0010;
end else if (selec == 10) begin
s <= 4'b0100;
end else if (selec == 11) begin
... | 6.725201 |
module deMux2x4 8bits+ valid a submodule in mux4x2 8bits + valid first level L1
// Dependencies:
//
// Revision: 0.0
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module demux2x4_behav (
input wire clk,
inpu... | 7.007243 |
module demux4 #(
parameter WIDTH = 16
) (
input [WIDTH-1:0] in,
input [1:0] sel,
output reg [WIDTH-1:0] out0,
output reg [WIDTH-1:0] out1,
output reg [WIDTH-1:0] out2,
output reg [WIDTH-1:0] out3
);
always @(*) begin
case (sel)
2'b00: begin
out0 = in;
out1 = {WID... | 7.476747 |
module demux41 (
in,
sel,
out1,
out2,
out3,
out4
);
input [3:0] in;
input [1:0] sel;
output reg [3:0] out1, out2, out3, out4;
always @(*) begin
case (sel)
0: begin
out1 = in;
out2 = 0;
out3 = 0;
out4 = 0;
end
1: begin
out1 ... | 6.702604 |
module demux41_tb ();
wire [3:0] out1, out2, out3, out4;
reg [1:0] sel;
reg [3:0] in;
integer i;
demux41 test (
in,
sel,
out1,
out2,
out3,
out4
);
initial begin
in = $random;
sel = 0;
#4 $finish;
end
always @(*) begin
for (i = 0; i < 4; i++) beg... | 7.183899 |
module demux4to12 (
input [ 3:0] address,
output [11:0] out
);
reg [11:0] paths;
always @(*)
case (address)
4'b0001: paths = 12'b100000000000;
4'b0010: paths = 12'b010000000000;
4'b0011: paths = 12'b001000000000;
4'b0100: paths = 12'b000100000000;
4'b0101: paths = 12'b00... | 8.246772 |
module DEMUX4W (
input in,
input [1:0] sel,
output logic out1,
out2,
out3,
out4
);
always_comb begin
case (sel)
2'b00: begin
out1 = in;
out2 = 1'b0;
out3 = 1'b0;
out4 = 1'b0;
end
2'b01: begin
out1 = 1'b0;
out2 = in;
... | 6.897658 |
module demux4w_test;
logic in;
logic [1:0] sel;
logic out1, out2, out3, out4;
DEMUX4W dut (
in,
sel,
out1,
out2,
out3,
out4
);
initial begin
sel = 2'b00;
in = 1'b0;
#10;
assert (out1 == 1'b0 && out2 == 1'b0 && out3 == 1'b0 && out4 == 1'b0) $display("PAS... | 6.604148 |
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