code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module demux4x1 (
Y,
E,
S
);
input [1:0] S; //Select lines
input E; //Enable line
output [3:0] Y; //Output (4 bits)
wire w1, w2;
not N1 (w1, S[0]);
not N2 (w2, S[1]);
and A1 (Y[0], w2, w1, E);
and A2 (Y[1], w2, S[0], E);
and A3 (Y[2], S[1], w1, E);
and A4 (Y[3], S[1], S[0], E);
end... | 7.777341 |
module Demux4_a_1_TB;
#(parameter n=4);
reg [n-1:0] i_Datos_0;
reg [n-1:0] i_Datos_1;
reg [n-1:0] i_Datos_2;
reg [n-1:0] i_Datos_3;
reg [1:0] i_sel;
wire [n-1:0] o_demux;
Demux4x1 uut (
.i_Datos_0(i_Datos_0),
.i_Datos_1(i_Datos_1),
.i_Datos_2(i_Datos_2),
.i_Datos_... | 6.983387 |
module demuxFFT (
outFFT,
seldemuxFFT,
inFIFO2Re,
outdemuxFFT
);
input [31:0] outFFT;
input seldemuxFFT;
output [31:0] inFIFO2Re;
output [31:0] outdemuxFFT;
//wire [31:0]inFIFO2Im_32;
assign inFIFO2Re = (seldemuxFFT) ? 32'bz : outFFT;
assign outdemuxFFT = (seldemuxFFT) ? outFFT : 32'b... | 6.908846 |
module demuxFIFO (
outmult256,
seldemuxFIFO,
inFIFO4A,
inFIFO4B
);
input [31:0] outmult256;
input seldemuxFIFO;
output [31:0] inFIFO4A;
output [31:0] inFIFO4B;
assign inFIFO4A = (seldemuxFIFO) ? 32'bz : outmult256;
assign inFIFO4B = (seldemuxFIFO) ? outmult256 : 32'bz;
endmodule
| 7.075262 |
module DEMUX_1to2 (
IN,
CLK,
CLK_B,
RES,
OUT1,
OUT2
);
parameter BW = 6;
input signed [BW+3:0] IN;
input CLK, CLK_B, RES;
output signed [BW+3:0] OUT1, OUT2;
reg signed [BW+3:0] OUT1, OUT2;
always @(posedge CLK or posedge RES) begin
if (RES == 1'b1) OUT1 <= 0;
else OUT1 <= ... | 6.899852 |
module demux_1to8 (
input [83:0] idata,
input [ 2:0] isel,
output [83:0] odata0,
output [83:0] odata1,
output [83:0] odata2,
output [83:0] odata3,
output [83:0] odata4,
output [83:0] odata5,
output [83:0] odata6,
output [83:0] odata7
);
assign odata0 = (isel == 3'h0) ? idata... | 7.653008 |
module demux_1to8_for (
input in,
input [2:0] sel,
output reg [7:0] out
);
integer i;
always @(*) begin
out = 8'h00;
for (i = 0; i < 8; i = i + 1) if (i == sel) out[i] = in;
end
endmodule
| 7.134372 |
module demux_1to8_for_tb ();
reg in;
reg [2:0] sel;
wire [7:0] out;
integer i;
demux_1to8_for dut (
.in (in),
.sel(sel),
.out(out)
);
initial begin
{sel, in} = 4'h0;
end
initial begin
for (i = 0; i < 16; i = i + 1) begin
{sel, in} = i;
#... | 7.134372 |
module demux_1x2 #(
parameter WIDTH = 4
) (
input [WIDTH-1:0] IN0,
input SEL,
output [WIDTH-1:0] OUT0,
output [WIDTH-1:0] OUT1
);
reg [WIDTH-1:0] OUT0_r, OUT1_r;
always @(*) begin
OUT0_r = 0;
OUT1_r = 0;
if (!SEL) begin
OUT0_r = IN0;
end else if (SEL) begin
OUT1_r ... | 7.614111 |
module demux_1x3 (
input wire data,
input wire [1:0] select,
output reg ch1,
output reg ch2,
output reg ch3
);
always @* begin
case (select)
2'b00: begin
ch1 = data;
ch2 = 1'b0;
ch3 = 1'b0;
end
2'b01: begin
ch1 = 1'b0;
ch2 = data;
... | 7.013711 |
module demux_1x4_behavioral (
input y, // 1 Input
input [1:0] sel, // Select
output reg a,
b,
c,
d
); // 4 Outputs
// ALWAYS BLOCK with NON-BLOCKING PROCEDURAL ASSIGNMENT STATEMENT
always @(*) begin
case (sel)
2'b00: begin
a <= y;
b <= 0;... | 7.111624 |
module DeMux_1x4_beh (
input A,
input [1:0] sel,
output reg [3:0] Y
);
always @(sel or A) begin
case (sel)
2'b00: begin
Y[0] <= A;
Y[3:1] <= 3'b0;
end
2'b01: begin
Y[1] <= A;
Y[3:2] <= 2'b0;
Y[0] <= 1'b0;
end
2'b10: begin
... | 7.158721 |
module DeMux_1x4_str (
input x,
input [1:0] sel,
output [3:0] D
);
and A1 (D[0], x, ~sel[1], ~sel[0]);
and A2 (D[1], x, ~sel[1], sel[0]);
and A3 (D[2], x, sel[1], ~sel[0]);
and A4 (D[3], x, sel[1], sel[0]);
endmodule
| 7.018436 |
module DEMUX_4x1_TB;
// DATA TYPES - DECLARE REGISTERS AND WIRES (PROBES)
reg Y;
reg [1:0] SEL;
wire A, B, C, D;
// FOR TESTING
reg TICK;
reg [31:0] VECTORCOUNT, ERRORS;
reg AEXP, BEXP, CEXP, DEXP;
integer FD, COUNT;
reg [8*32-1:0] COMMENT;
// UNIT UNDER TEST (behavioral)
demux_1x4_be... | 9.103893 |
module demux_1_2(
input [1:0]a,
input sel;
output reg [1:0]f0, f1
);
always @(a or sel)
begin
case(sel)
1'b0: f0= a;
1'b1: f1 =a;
endcase
end
endmodule
| 7.172668 |
module DEMUX_1_4 #(
parameter BITS_NUM = 1
) (
input [BITS_NUM-1:0] X,
input [1:0] SEL,
output reg [BITS_NUM-1:0] Y0,
output reg [BITS_NUM-1:0] Y1,
output reg [BITS_NUM-1:0] Y2,
output reg [BITS_NUM-1:0] Y3
);
always @(X or SEL)
case (SEL)
2'b00: {Y0, Y1, Y2, Y3} = {X, {3 * BI... | 7.438172 |
module demux_1_4_case (
input din,
input [1:0] sel,
output reg dout0,
output reg dout1,
output reg dout2,
output reg dout3
);
always @(*)
case (sel)
2'b00: begin
dout0 = din;
dout1 = 0;
dout2 = 0;
dout3 = 0;
end
2'b01: begin
dout0 ... | 6.849763 |
module demux_1_4_data (
d,
s,
y
);
input d;
input [1:0] s;
output [3:0] y;
assign y[0] = d & (~s[1]) & (~s[0]);
assign y[1] = d & (~s[1]) & (s[0]);
assign y[2] = d & (s[1]) & (~s[0]);
assign y[3] = d & (s[1]) & (s[0]);
endmodule
| 7.966132 |
module DEMUX_1_4_TB;
parameter BITS_NUM = 2;
wire [BITS_NUM-1:0] a;
wire [BITS_NUM-1:0] b;
wire [BITS_NUM-1:0] c;
wire [BITS_NUM-1:0] d;
reg [1:0] sel;
reg [BITS_NUM-1:0] x;
DEMUX_1_4 #(
.BITS_NUM(BITS_NUM)
) mux_4_1 (
.X (x),
.SEL(sel),
.Y0 (a),
.Y1 (b),
.Y2 (c... | 6.766954 |
module demux_1_to_1 (
input din,
input [-1:0] sel,
output dout_1
);
assign dout_1 = din;
endmodule
| 7.639988 |
module demux_1_to_1_7bits (
input [ 6:0] din,
input [-1:0] sel,
output [ 6:0] dout_1
);
demux_1_to_1 dm_0 (
.din(din[0]),
.sel(sel),
.dout_1(dout_1[0])
);
demux_1_to_1 dm_1 (
.din(din[1]),
.sel(sel),
.dout_1(dout_1[1])
);
demux_1_to_1 dm_2 (
.din(din[2]... | 7.466981 |
module demux_1_to_2 (
input din,
input [0:0] sel,
output dout_1,
output dout_2
);
assign dout_1 = din & (~sel[0]);
assign dout_2 = din & (sel[0]);
endmodule
| 8.28682 |
module demux_1_to_2_10bits (
input [9:0] din,
input [0:0] sel,
output [9:0] dout_1,
output [9:0] dout_2
);
demux_1_to_2 dm_0 (
.din(din[0]),
.sel(sel),
.dout_1(dout_1[0]),
.dout_2(dout_2[0])
);
demux_1_to_2 dm_1 (
.din(din[1]),
.sel(sel),
.dout_1(dout_1... | 6.675661 |
module demux_1_to_2_5bits (
input [4:0] din,
input [0:0] sel,
output [4:0] dout_1,
output [4:0] dout_2
);
demux_1_to_2 dm_0 (
.din(din[0]),
.sel(sel),
.dout_1(dout_1[0]),
.dout_2(dout_2[0])
);
demux_1_to_2 dm_1 (
.din(din[1]),
.sel(sel),
.dout_1(dout_1[... | 6.675661 |
module demux_1_to_2_7bits (
input [6:0] din,
input [0:0] sel,
output [6:0] dout_1,
output [6:0] dout_2
);
demux_1_to_2 dm_0 (
.din(din[0]),
.sel(sel),
.dout_1(dout_1[0]),
.dout_2(dout_2[0])
);
demux_1_to_2 dm_1 (
.din(din[1]),
.sel(sel),
.dout_1(dout_1[... | 6.675661 |
module demux_1_to_2_8bits (
input [7:0] din,
input [0:0] sel,
output [7:0] dout_1,
output [7:0] dout_2
);
demux_1_to_2 dm_0 (
.din(din[0]),
.sel(sel),
.dout_1(dout_1[0]),
.dout_2(dout_2[0])
);
demux_1_to_2 dm_1 (
.din(din[1]),
.sel(sel),
.dout_1(dout_1[... | 6.675661 |
module demux_1_to_3 (
input din,
input [1:0] sel,
output dout_1,
output dout_2,
output dout_3
);
assign dout_1 = din & (~sel[0]) & (~sel[1]);
assign dout_2 = din & (sel[0]) & (~sel[1]);
assign dout_3 = din & (~sel[0]) & (sel[1]);
endmodule
| 7.770447 |
module DEMUX_1_to_3x8 (
input i_clk,
input i_ready,
input [7:0] i_data,
input reset,
output reg o_done,
output reg [7:0] o_num_1,
output reg [7:0] o_num_2,
output reg [7:0] o_opcode
);
reg [1:0] counter = 1;
reg [1:0] done = 0;
always @(posedge i_clk) begin
if (reset ==... | 7.326998 |
module demux_1_to_3_5bits (
input [4:0] din,
input [1:0] sel,
output [4:0] dout_1,
output [4:0] dout_2,
output [4:0] dout_3
);
demux_1_to_3 dm_0 (
.din(din[0]),
.sel(sel),
.dout_1(dout_1[0]),
.dout_2(dout_2[0]),
.dout_3(dout_3[0])
);
demux_1_to_3 dm_1 (
.... | 6.657973 |
module demux_1_to_3_7bits (
input [6:0] din,
input [1:0] sel,
output [6:0] dout_1,
output [6:0] dout_2,
output [6:0] dout_3
);
demux_1_to_3 dm_0 (
.din(din[0]),
.sel(sel),
.dout_1(dout_1[0]),
.dout_2(dout_2[0]),
.dout_3(dout_3[0])
);
demux_1_to_3 dm_1 (
.... | 6.657973 |
module DeMux_1_to_4 #(
parameter DATA_WIDTH = 32*3,
parameter NUM_OUTPUT_PORTS = 4,
parameter SEL_DIWTH = 2 // log(NUM_INPUT_PORTS) / log(2)
) (
input clk,
input rst,
input [SEL_DIWTH-1:0] sel,
input in_valid,
input [DATA_WIDTH-1:0] in,
output reg [NUM_OUTPUT_PORTS*DATA_WIDTH... | 7.70876 |
module demux_1_to_6 (
input din,
input [2:0] sel,
output dout_1,
output dout_2,
output dout_3,
output dout_4,
output dout_5,
output dout_6
);
assign dout_1 = din & (~sel[0]) & (~sel[1]) & (~sel[2]);
assign dout_2 = din & (sel[0]) & (~sel[1]) & (~sel[2]);
assign dout_3 = din & (~se... | 7.186082 |
module demux_1_to_6_10bits (
input [9:0] din,
input [2:0] sel,
output [9:0] dout_1,
output [9:0] dout_2,
output [9:0] dout_3,
output [9:0] dout_4,
output [9:0] dout_5,
output [9:0] dout_6
);
demux_1_to_6 dm_0 (
.din(din[0]),
.sel(sel),
.dout_1(dout_1[0]),
.do... | 6.510938 |
module demux_1_to_6_8bits (
input [7:0] din,
input [2:0] sel,
output [7:0] dout_1,
output [7:0] dout_2,
output [7:0] dout_3,
output [7:0] dout_4,
output [7:0] dout_5,
output [7:0] dout_6
);
demux_1_to_6 dm_0 (
.din(din[0]),
.sel(sel),
.dout_1(dout_1[0]),
.dou... | 6.510938 |
module demux_1_to_8 (
input din,
input [2:0] sel,
output dout_1,
output dout_2,
output dout_3,
output dout_4,
output dout_5,
output dout_6,
output dout_7,
output dout_8
);
assign dout_1 = din & (~sel[0]) & (~sel[1]) & (~sel[2]);
assign dout_2 = din & (sel[0]) & (~sel[1]) & (... | 7.487597 |
module demux_1_to_8_5bits (
input [4:0] din,
input [2:0] sel,
output [4:0] dout_1,
output [4:0] dout_2,
output [4:0] dout_3,
output [4:0] dout_4,
output [4:0] dout_5,
output [4:0] dout_6,
output [4:0] dout_7,
output [4:0] dout_8
);
demux_1_to_8 dm_0 (
.din(din[0]),
... | 6.888996 |
module demux_1_to_8_7bits (
input [6:0] din,
input [2:0] sel,
output [6:0] dout_1,
output [6:0] dout_2,
output [6:0] dout_3,
output [6:0] dout_4,
output [6:0] dout_5,
output [6:0] dout_6,
output [6:0] dout_7,
output [6:0] dout_8
);
demux_1_to_8 dm_0 (
.din(din[0]),
... | 6.888996 |
module demux_1_to_n #(
parameter C_FACTOR = 12,
parameter C_WIDTH = 1,
// Local parameters
parameter C_SEL_WIDTH = clog2s(C_FACTOR)
) (
input [C_WIDTH-1:0] IN, // Inputs
output [(C_FACTOR*C_WIDTH)-1:0] OUT, // Outputs
input [C_SEL_WIDTH-1:0] SEL // Selector
);
`include "common_func... | 9.275012 |
module demux_2x1 (
d,
s,
q0,
q1
);
input d, s;
output q0, q1;
(*KEEP = "true"*)assign q0 = ~s * d;
(*KEEP = "true"*)assign q1 = s * d;
endmodule
| 7.360776 |
module demux_32_2 (
input wire [31:0] in,
input wire [ 3:0] sel,
output reg [ 1:0] out /* Wire */
);
always @(*) begin
out = 2'b00;
case (sel)
4'h0: out = in[1:0];
4'h1: out = in[3:2];
4'h2: out = in[5:4];
4'h3: out = in[7:6];
4'h4: out = in[9:8];
4'h5: o... | 6.708814 |
module demux_4way (
out0,
out1,
out2,
out3,
in,
s0,
s1
);
input in, s0, s1;
output out0, out1, out2, out3;
wire x, y;
demux demux_1 (
x,
y,
in,
s1
);
demux demux_2 (
out0,
out1,
x,
s0
);
demux demux_3 (
out2,
out3... | 7.552659 |
module demux_7442 (
input wire [3:0] a,
output reg [9:0] y_n
);
always @* begin
case (a)
4'd0: y_n <= 10'b1111111110;
4'd1: y_n <= 10'b1111111101;
4'd2: y_n <= 10'b1111111011;
4'd3: y_n <= 10'b1111110111;
4'd4: y_n <= 10'b1111101111;
4'd5: y_n <= 10... | 6.703895 |
module demux_8 (
sel,
out
); // 8-output decoder
output reg [7:0] out;
input [2:0] sel;
always @(sel) begin
case (sel)
0: out = 8'b00000001;
1: out = 8'b00000010;
2: out = 8'b00000100;
3: out = 8'b00001000;
4: out = 8'b00010000;
5: out = 8'b00100000;
6: out... | 6.9698 |
module demux_83 (
input s1,
s2,
s3,
enable,
y,
output I0,
I1,
I2,
I3,
I4,
I5,
I6,
I7
);
demux_42 a (
s1,
s2,
s3 & enable,
y,
I0,
I1,
I2,
I3
);
demux_42 b (
s1,
s2,
!s3 & enable,
y,
... | 6.531318 |
module Demux_8to1 (
in,
s0,
s1,
s2,
d0,
d1,
d2,
d3,
d4,
d5,
d6,
d7
);
input in, s0, s1, s2;
output d0, d1, d2, d3, d4, d5, d6, d7;
assign d0 = (in & ~s2 & ~s1 & ~s0),
d1 = (in & ~s2 & ~s1 & s0),
d2 = (in & ~s2 & s1 & ~s0),
d3 = (in & ~s2 & s1 & s0)... | 6.682067 |
module demux_8x16 (
input [127:0] data_in,
input [ 15:0] sel,
output reg [7:0] data_out
);
always @(sel or data_in) begin
case (sel)
1: begin
data_out <= data_in[7:0];
end
2: begin
data_out <= data_in[15:8];
end
4: begin
data_out <= data_in[23:16... | 7.804641 |
module demux_actors (
input wire [11:0] position_0,
input wire [ 7:0] sprite_0,
input wire [11:0] position_1,
input wire [ 7:0] sprite_1,
input wire [ 2:0] select,
output reg [11:0] position_out,
output reg [ 7:0] sprite_out
);
always @(*) begin
case (select)
0: begin
... | 7.528945 |
module demux_assign #(
parameter DAT_WIDTH = 8,
parameter SEL_WIDTH = 4
) (
input [DAT_WIDTH-1:0] demux_in,
input [SEL_WIDTH-1:0] sel_in,
output [(2**SEL_WIDTH)*DAT_WIDTH-1:0] demux_out
);
genvar i, sel;
generate
for (sel = 0; sel < 2 ** SEL_WIDTH; sel = sel + 1) begin : GEN_DEMUX
for... | 9.053512 |
module demux_generate (
output o0,
output o1,
output o2,
output o3,
output o4,
output o5,
output o6,
output o7,
input [2:0] sel,
input i
);
reg [7:0] y_int;
assign {o7, o6, o5, o4, o3, o2, o1, o0} = y_int;
integer k;
always @(*) begin
y_int = 8'b0;
for (k = 0; k <... | 7.127016 |
module demux_initial (
input clk,
input [5:0] data_in_demux_initial,
input valid_pop_out,
input reset,
output reg [5:0] data_out_demux_initial_vc0,
output reg [5:0] data_out_demux_initial_vc1,
output reg push_vc0,
output reg push_vc1
);
always @(posedge clk) begin
if (reset == 0 |... | 6.972325 |
module demux_param (
word,
lineIn,
SEL,
lineOut
);
parameter N = 8; //number of bits wide
parameter M = 4; //number of inputs
parameter S = 2; //number of select lines
parameter W = M * N;
`define DTOTAL W-1:0
`define DWIDTH N-1:0
`define SELW S-1:0
input [`DTOTAL] lineIn;
input ... | 6.761073 |
module demux_tb ();
localparam OUTPUT_WIDTH = 2 ** 10 + 1;
localparam SELECTOR_WIDTH = $clog2(OUTPUT_WIDTH);
reg dut_enable;
reg [SELECTOR_WIDTH-1:0] dut_selector;
wire [OUTPUT_WIDTH-1:0] dut_out;
demux #(
.OUTPUT_WIDTH(OUTPUT_WIDTH)
) dut (
.enable(dut_enable),
.selector(dut_selector)... | 6.800881 |
module demux_test;
logic in, sel;
logic out1, out2;
DEMUX dut (
in,
sel,
out1,
out2
);
initial begin
in = 1'b0;
sel = 1'b0;
#10;
assert (out1 == 1'b0 && out2 == 1'b0) $display("PASSED");
else $display("FAILED (%b, %b)", out1, out2);
in = 1'b1;
sel = 1'b... | 7.465376 |
module DeMux_Tree #(
parameter DATA_WIDTH = 32 * 3,
parameter NUM_OUTPUT_PORTS = 128,
parameter SEL_DIWTH = $clog2(NUM_OUTPUT_PORTS)
) (
input clk,
input rst,
input [DATA_WIDTH-1:0] in_data,
input in_valid,
input [SEL_DIWTH-1:0] in_sel,
output reg [NUM_OUTPUT_PORTS*DATA_WIDTH-1:0] ou... | 6.779658 |
module demux_two_ins #(
parameter data_width = 256
) (
input [data_width-1:0] in0,
input demux_two,
output [data_width-1:0] out0,
out1
);
assign out0 = (demux_two == 1'b0) ? in0 : 0;
assign out1 = (demux_two == 1'b1) ? in0 : 0;
endmodule
| 8.574163 |
module demux_ver (
i_ADDR,
i_I,
o_O
);
//ports declaration
input [4:0] i_ADDR; //addres
input i_I; //input data
output reg [31:0] o_O; //output
always @* begin
o_O = i_I << i_ADDR;
end
endmodule
| 7.582782 |
module denetim_durum_birimi (
input wire clk_i,
input wire rst_i,
// GETIR sinyalleri
input wire gtr_yanlis_tahmin_i, // Dallanma ongorucu, ongoremedi
input wire gtr_hazir_i, // Getir hazir degil. L1 miss oldu vs. Buyruk gecersiz
output wire gtr_durdur_o,
output wire gtr_bosalt... | 6.846315 |
module denise_bitplane_shifter (
input wire clk, // 35ns pixel clock
input wire clk7_en, // 7MHz clock enable
input wire c1, // clock phase signals
input wire c3, // clock phase signals
input wire load, // load shift register si... | 7.574543 |
module also supports EHB (extra half brite) mode,
// it actually has a 6bit colour select input
// the 6th bit selects EHB colour while the lower 5 bit select the actual colour register
module denise_colortable
(
input wire clk, // 28MHz clock
input wire clk7_en, // 7MH... | 7.938173 |
module handles the hold and modify mode (HAM)
// the module has its own colour pallete bank, this is to let
// the sprites run simultaneously with a HAM playfield
module denise_hamgenerator
(
input wire clk, // 28MHz clock
input wire clk7_en, // 7MHz clock enable
inpu... | 7.443406 |
module denise_playfields (
input aga,
input [8:1] bpldata, //raw bitplane data in
input dblpf, //double playfield select
input [2:0] pf2of, // playfield 2 offset into color table
input [6:0] bplcon2, //bplcon2 (playfields priority)
output ... | 8.08946 |
module
// this module checks the playfields and sprites video status and
// determines if playfield or sprite data must be sent to the video output
// sprite/playfield priority is configurable through the bplcon2 bits
module denise_spritepriority
(
input [5:0] bplcon2, // playfields vs sprites priority sett... | 8.253053 |
module denise_sprites_shifter (
input clk, // 28MHz clock
input clk7_en,
input clk7n_en, // 7MHz clock enable
input reset, // reset
input aen, // address enable
input [ 1:0] address, // register addre... | 8.236709 |
module denorm (
U1,
clk,
rst,
pushin,
pushout,
delta_denorm,
fract_lt
);
parameter fpw = 63;
parameter [fpw:0] zero = 0;
parameter size = 8;
input [63:0] U1;
input clk;
input rst;
input pushin;
output [fpw:0] delta_denorm;
output [size:0] fract_lt;
output pushout;
r... | 7.184685 |
module denorm1 (
U1,
clk,
rst,
pushin,
pushout,
delta_denorm,
fract_lt
);
parameter fpw = 63;
parameter [fpw:0] zero = 0;
parameter size = 9;
input [63:0] U1;
input clk;
input rst;
input pushin;
output [fpw:0] delta_denorm;
output [size:0] fract_lt;
output pushout;
... | 7.197266 |
module dense1_serial (
input clk,
input rst_n,
input ena,
input [1919:0] dense_sum,
output reg frame_start,
output reg frame_end,
output reg valid,
output reg signed... | 6.807192 |
module denseLayer_sim ();
parameter clk_period = 10;
parameter data_length = 128000;
reg clk, rst_n;
reg [15:0] din;
reg din_valid;
wire [15:0] dout;
wire dout_valid;
denseLayer denseLayer_test (
.clk(clk),
.rst_n(rst_n),
.dense_din(din), //输入：[1,3,12]--(符号位，整数位，小数?)
.dense_di... | 6.712826 |
module deoxys_lfsr2_16 ( /*AUTOARG*/
// Outputs
so,
// Inputs
si
);
output [127:0] so;
input [127:0] si;
wire [127:0] m[16:0];
genvar i, j;
assign m[0] = si;
generate
for (i = 0; i < 16; i = i + 1) begin : lfsr_outer
for (j = 0; j < 16; j = j + 1) begin : lfsr_inner
as... | 6.628551 |
module deoxys_lfsr3_16 ( /*AUTOARG*/
// Outputs
so,
// Inputs
si
);
output [127:0] so;
input [127:0] si;
wire [127:0] m[16:0];
genvar i, j;
assign m[0] = si;
generate
for (i = 0; i < 16; i = i + 1) begin : lfsr_outer
for (j = 0; j < 16; j = j + 1) begin : lfsr_inner
as... | 6.791511 |
module check_inf_zero_non (
output reg i,
z,
n,
input [31:0] num1,
input [31:0] num2
);
always @(num1 or num2) begin
if (((|num1) & (|num2)) == 1'b0) z = 1'b1;
else z = 1'b0;
if (((&num1[30:23]) | (&num2[30:23])) == 1'b1) i = 1'b1;
else i = 1'b0;
if (((&num1[30:23] == 1'b1) ... | 6.742415 |
module final(
output reg [31:0] product,
input i,z,n,sign,
input [7:0]exp,
input [22:0]mantessa);
always @(sign or exp or mantessa)
begin
//$display("%d %b %b %b",$time,sign,exp,mantessa);
if(n==1'b1)
product ={sign,31'b1111111100000000000000000000001};
if(i==1'b1)
product ={sign,31'b1111111100000000000000000000000};
... | 7.157174 |
module: DependencyCheckBlock
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module DependencyCheckBlock_TB;
// Inputs
reg [23:0] ins;
reg clk;
reg reset;
// Outputs
wire [7:0] imm;... | 7.33665 |
module: Dependency_Check_Block
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Dependency_Check_Block_tb;
// Inputs
reg [23:0] ins;
reg clk;
reg reset;
// Outputs
wire [7:0] ... | 7.331877 |
module dependency_check_module (
ins,
clk,
reset,
mux_sel_a,
mux_sel_b,
imm_sel,
Imm,
mem_en_dec,
mem_rw_dec,
mem_mux_sel_dec,
RW_dec,
op_dec
);
input [19:0] ins; //input declaration of 20 bit instruction
input reset, clk; //input declaration of 1 bit reset and clk... | 6.974824 |
module of our microprocessor.
///////////////////////////////////////////////////////////////////
module dependency_check_tb;
// Inputs
reg [19:0] ins;
reg clk;
reg reset;
// Outputs
wire [1:0] mux_sel_a;
wire [1:0] mux_sel_b;
wire imm_sel;
wire [7:0] Imm;
wire mem_en_dec;
wire mem_rw_dec;
wire mem_mux_... | 7.266313 |
module dependent_variable_decoding (
slice_header_state,
log2_max_frame_num_minus4,
log2_max_pic_order_cnt_lsb_minus4,
BitStream_buffer_output,
dependent_variable_len,
dependent_variable_decoding_output
);
input [3:0] slice_header_state;
input [3:0] log2_max_frame_num_minus4;
input [3:0] l... | 8.350256 |
module dffe (
CK,
E,
D,
Q
);
input CK, E, D;
output Q;
wire qq;
UDP_dffe ff (
qq,
CK,
E,
D
);
buf #1 (Q, qq);
endmodule
| 7.007247 |
module had (
A,
B,
C,
S
);
input A, B;
output C, S;
xor s (S, A, B);
and c (C, A, B);
endmodule
| 6.889088 |
module deposit_next (
input clk,
input reset,
input rd,
input deposit,
input [7:0] data_sw,
output reg [7:0] deposit_out,
output deposit_latch,
output reg [7:0] data_out,
output examine_latch
);
reg [2:0] state = 3'b000;
reg prev_rd = 1'b0;
reg de_lt = 1'b0;
reg en_lt = 1'b0... | 6.697456 |
module deppbyte (
i_clk,
i_astb_n,
i_dstb_n,
i_write_n,
i_depp,
o_depp,
o_wait,
o_rx_stb,
o_rx_data,
i_tx_stb,
i_tx_data,
o_tx_busy
);
input i_clk;
// DEPP interface
input i_astb_n, i_dstb_n, i_write_n;
input [7:0] i_depp;
output reg [7:0] o_depp;
output wire ... | 7.778622 |
module Memory (
clk,
ren,
wen,
addr,
din,
dout
);
// # of words
parameter DEPTH = 128;
// # bits per words
parameter WIDTH = 8;
input clk;
input ren;
input wen;
input [7-1:0] addr;
input [8-1:0] din;
output [8-1:0] dout;
// words selector
wire [DEPTH-1:0] sel;
wire [... | 7.051739 |
module Word_8bits (
clk,
out,
ren,
wen,
en,
din
);
parameter WIDTH = 8;
input clk; // clk
input ren; // read-enable
input wen; // write-enable
input en; // enable
input [WIDTH-1:0] din; // data-in
output reg out; // output
reg [WIDTH-1:0] mem;
/**
* Sequential Circui... | 7.739472 |
module depsk(
clk,
reset_n,
data,
dm_out,
);
input clk ;
input reset_n ;
input [ 7 : 0 ] data;
output [7:0]dm_out;
reg [ 6 : 0 ] counter_value;
reg [7:0] middata;
always @( posedge clk or negedge reset_n )
begin
if(!reset_n)
begin
cou... | 6.725829 |
module depthcomp (
d1,
d2,
d3,
xc1,
xc2,
xc3,
xc4,
yc1,
yc2,
yc3,
yc4,
xout,
yout
);
input [5:0] d1, d2, d3;
input [8:0] xc1, xc2, xc3, xc4, yc1, yc2, yc3, yc4;
output [8:0] xout, yout;
reg [8:0] xreg, yreg;
always @(d1 or d2 or d3 or xc1 or xc2 or xc3 or ... | 6.922803 |
module depth_split (
we,
addr,
datain,
dataout,
clk
);
input we;
input [11 - 1:0] addr;
input [2 - 1:0] datain;
output [2 - 1:0] dataout;
wire [2 - 1:0] dataout;
input clk;
single_port_ram new_ram (
.clk (clk),
.we (we),
.data(datain),
.out (dataout),
... | 6.816352 |
module Dequantization (
input Clock,
input reset, //active high reset
input Enable, //This should be High throughout the quantization process.
input [511:0] A,
output reg [703:0] C,
output reg done //A High indicates that division is done and result is availble at C.
);
//temperory registe... | 6.984528 |
module Derivador #(
parameter Magnitud = 17,
Decimal = 0,
N = Magnitud + Decimal + 1
) //Se parametriza para hacer flexible el cambio de ancho de palabra
//Declaracion de senales de entrada y salida
(
input wire clk,
reset,
enable,
input wire signed [N-1:0] y,
output wire signed [N-1:0]... | 8.667495 |
module integral (
input [7:0] error,
input clk,
output [11:0] i
);
parameter [3:0] co = 4'b0001;
reg [7:0] prior;
wire [7:0] out;
c_addsub_0 a (
error[7:0],
prior[7:0],
clk,
1'b1,
out[7:0]
);
always @(posedge clk) begin
prior[7:0] <= out[7:0];
end
mult_gen... | 6.819181 |
module crc_inferred #(
parameter ord = 16,
parameter poly = 16'h1021,
parameter dw = 16
) (
input clk,
input [dw-1:0] din,
input zero,
output reg [ord-1:0] crc
);
wire [ord-1:0] O = zero ? {ord{1'b0}} : crc;
integer i;
reg [ord-1:0] crc_nx;
reg b;
always @(posedge clk) begin
... | 7.748183 |
module crc_explicit #(
parameter ord = 16,
parameter dw = 16
) (
input clk,
input [dw-1:0] din,
input zero,
output reg [ord-1:0] crc
);
wire [ord-1:0] O = zero ? {ord{1'b0}} : crc;
wire [ dw-1:0] D = din;
always @(posedge clk) begin
// crc_derive command line arguments must match dw a... | 8.12931 |
module top_module (
input [64:1] a,
input [48:1] key,
output [64:1] b
);
wire [32:1] l0, r0, p1, c1, sp1;
wire [48:1] e1, f1;
wire [64:1] a1;
wire [6:1] sb1, sb2, sb3, sb4, sb5, sb6, sb7, sb8;
wire [4:1] s1, s2, s3, s4, s5, s6, s7, s8;
initial_permutation I (
a,
l0,
r0
);
... | 7.203305 |
module Descale_pipeline (
input [31:0] x_scale,
input [31:0] y_scale,
input [31:0] z_scale,
input [31:0] k_in,
input [7:0] InsTagScaleOut,
input ScaleValid,
input NatLogFlagScaleOut,
input reset,
input clock,
output [31:0] x_out,
output [31:0] y_out,
output [31:0] z_out,
... | 7.567877 |
module descendSort #(
parameter DEPTH = 8,
parameter WIDTH = 8
) (
input clock,
input rstn,
input valid,
input [WIDTH -1 : 0][DEPTH - 1:0] in_data,
input [WIDTH -1 : 0][DEPTH - 1:0] in_probab,
output wire [WIDTH -1 : 0][DEPTH - 1:0] out_data,
output reg ready
);
localparam DEPTH... | 8.059622 |
module descrack_stream_core #(
parameter CORE = 0
) (
input clk,
input rst,
input des_clk,
input clken,
input fsl_clk,
input fsl_rst_i,
input [31:0] fsl_data_i,
input fsl_valid_i,
output fsl_rst_o,
output [31:0] fsl_data_o,
output fsl_valid_o,
output [255:0] DEBUG
);
... | 7.627122 |
module descrack_stream_region #(
parameter REGION = 0
) (
input clk,
input rst,
input des_clk,
input clken,
input fsl_clk,
input fsl_rst_i,
input [31:0] fsl_data_i,
input fsl_valid_i,
output fsl_rst_o,
output [31:0] fsl_data_o,
output fsl_valid_o,
output [255:0] DEBUG... | 7.627122 |
module descramble (
input clock,
input enable,
input reset,
input in_bit,
input input_strobe,
output reg out_bit,
output reg output_strobe
);
reg [6:0] state;
reg [4:0] bit_count;
reg inited;
wire feedback = state[6] ^ state[3];
always @(posedge clock) begin
if (reset) be... | 6.629731 |
module descrambler #(
parameter WIDTH = 512
) (
input clk,
arst,
ena,
input [WIDTH-1:0] din, // bit 0 is used first
output reg [WIDTH-1:0] dout
);
reg [57:0] scram_state;
wire [WIDTH+58-1:0] history;
wire [WIDTH-1:0] dout_w;
assign history = {din, scram_state};
genvar i;
generate
... | 7.97151 |
module: descrambler
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module descrambler_tb;
// Inputs
reg clk;
reg reset;
reg rx;
// Outputs
wire descrambled_data;
// Instantiate t... | 9.370232 |
module descrambler_wys #(
parameter TARGET_CHIP = 2,
parameter WIDTH = 1024
) (
input clk,
input skip, // this din word isn't valid
input [WIDTH-1:0] din, // bit 0 is used first
output reg [WIDTH-1:0] dout
);
reg [57:0] scram_state = {58{1'b1}};
wire [WIDTH+58-1:0] history;
wire [WIDTH-... | 6.523181 |
module Descriptor_Buffer (
aclr,
clken,
clock,
shiftin,
shiftout,
taps0x,
taps10x,
taps11x,
taps12x,
taps13x,
taps14x,
taps15x,
taps1x,
taps2x,
taps3x,
taps4x,
taps5x,
taps6x,
taps7x,
taps8x,
taps9x
);
input aclr;
input clken;
in... | 8.298605 |
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