code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module Descriptor_Buffer_Hold (
iclk,
ireset,
igradient,
ogradient
);
//=============================================================================
// PARAMETER declarations
//=============================================================================
`include "SIFT_Parameter.v"
//=====... | 8.298605 |
module name - descriptor_delay_manage
// Version:V3.2.0.20210722
// Created:
// by - fenglin
////////////////////////////////////////////////////////////////////////////
// Description:
// send the descriptor delayed
// avoid reading pkt data before it is written to the bufm
//////////////////... | 8.103595 |
module name -descriptor_dispatch
// Version: DES_V1.0
// Created:
// by - fenglin
// at - 10.2020
////////////////////////////////////////////////////////////////////////////
// Description:
// Descriptor Send
///////////////////////////////////////////////////////////////////////////
`timesca... | 7.928546 |
module descriptor_memory (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
write,
writedata,
// outputs:
readdata
);
output [31:0] readdata;
input [8:0] address;
input [3:0] byteenable;
input chipselect;
input clk;
input clken;
input write;
input [31:0] ... | 7.80281 |
module name - descriptor_select
// Version: V3.2.0.20210727
// Created:
// by - fenglin
////////////////////////////////////////////////////////////////////////////
// Description:
// control bufid and tsntag to input queue
//
//
////////////////////////////////////////////... | 8.103595 |
module Descriptor_Table (
SYS_ADR,
Descriptor_Line
);
input [63:0] SYS_ADR;
output [95:0] Descriptor_Line;
wire [63:0] SYS_ADR;
reg [95:0] Descriptor_Line;
initial begin
Descriptor_Line[0] <= 1; //Valid
Descriptor_Line[1] <= 0; //End
Descriptor_Line[2] <= 0; //Int
Des... | 7.43416 |
module MINIMO_3 (
a,
b,
c,
min
);
input [7:0] a, b, c;
output [7:0] min;
wire [7:0] min_a_b;
MINIMO_2 m1 (
a,
b,
min_a_b
);
wire [7:0] min_a_b_c;
MINIMO_2 m2 (
min_a_b,
c,
min_a_b_c
);
assign min = min_a_b_c;
endmodule
| 7.162935 |
module descrypt_salt (
input [63:0] Din,
input [63:0] K,
input [11:0] salt,
output [67:0] Kout,
input CLK,
output [31:0] L_out,
output [31:0] R_out
);
// TODO: fix bit reversal of salt!!!
wire [31:0] L_out_tmp;
wire [31:0] R_out_tmp;
wire [63:0] D_ip;
wire [31:0] Ltmp[23:0];
wi... | 7.345203 |
module
// DEPARTMENT: communication and electronics department
// AUTHOR: Mina Hanna
// AUTHOR EMAIL: mina.hannaone@gmail.com
//------------------------------------------------
// Release history
// VERSION DATE AUTHOR DESCRIPTION
// 1.0 22/7/2022 Mina Hanna final version
//---------------------------------------------... | 8.923686 |
module Deserialize (
input clk_1d5M, //3MhzʱźţЧ
input reset, //λź
input [15:0] data_in, //16λ
input shift, //תʹ
input read, //ȡFIFOʹ
output reg dout //ת
);
reg [ 4:0] index;
reg [15:0] data;
always @(posedge... | 6.501651 |
module deserializer (
input wire sampled_bit,
input wire data_valid,
input wire deser_en,
input wire clk,
input wire rst,
output wire [`WIDTH-1:0] p_data
);
reg [`WIDTH-1:0] register;
always @(posedge clk or negedge rst) ... | 8.075096 |
module deser_data_16bit_ddr (
input DATA0P,
input DATA0N,
input DATA1P,
input DATA1N,
input IOCLKP,
input IOCLKN,
input GCLK,
input IOSTROBE,
output [15:0] DATAOUT,
input RESET,
input DESERSYNC,
output DEBUG
);
parameter integer DESERF = 8;
parameter integer SIM_TAP_... | 6.668577 |
module desgin_1_tb ();
reg clk_0;
reg pc_load_0;
reg rst_0;
design_1 design_1_i (
.clk_0(clk_0),
.pc_load_0(pc_load_0),
.rst_0(rst_0)
);
always #20 clk_0 = ~clk_0;
initial begin
clk_0 = 0;
rst_0 = 1;
#100 rst_0 = 0;
pc_load_0 = 1;
#10 pc_load_0 = 0;
end
endmodule... | 6.591483 |
module max_pool #(
parameter BW = 8
) (
// clock and reset
input clk_i,
input rst_n_i,
// streaming input
input signed [BW - 1 : 0] data_i,
input valid_i,
input last_i,
output ready_o,
// streaming output
output... | 7.092411 |
module quantizer #(
parameter I_BW = 32,
parameter O_BW = 8,
parameter SHIFT_BW = $clog2(I_BW)
) (
input clk_i,
input rst_n_i,
input [SHIFT_BW - 1 : 0] shift_i,
input [I_BW - 1 : 0] data_i,
input valid_i,
input last_i,
output ... | 7.42514 |
module relu #(
parameter BW = 32
) (
input clk_i,
input rst_n_i,
input signed [BW - 1 : 0] data_i,
input valid_i,
input last_i,
output ready_o,
output signed [BW - 1 : 0] data_o,
output valid_o,
... | 7.430505 |
module vec_mul #(
parameter I_BW = 8,
parameter O_BW = 16,
parameter VECTOR_LEN = 13
) (
// clock and reset
input clk_i,
input rst_n_i,
// streaming input
input signed [(VECTOR_LEN * I_BW) - 1 : 0] data0_i,
input valid0_i,
input ... | 6.538296 |
module to just 1 cycle.
// =============================================================================
module zero_pad #(
parameter BW = 8,
parameter VECTOR_LEN = 13,
// =========================================================================
// Local Parameters - Do Not Edit
// =======... | 7.040164 |
module wake #(
parameter NUM_CLASSES = 3
) (
// clock and reset
input clk_i,
input rst_n_i,
// streaming input
input [NUM_CLASSES - 1 : 0] data_i,
input valid_i,
input last_i,
output ready_o,
// wake output
... | 8.944599 |
module comb #(
parameter I_BW = 8,
parameter O_BW = 9
) (
// clock and reset
input clk_i,
input rst_n_i,
input en_i,
// streaming input
input signed [I_BW - 1 : 0] data_i,
input valid_i,
// streaming output
output signed [O_BW - 1 : 0] data_o,
outp... | 7.300399 |
module of the digital front end. Contains PDM clock generation,
// PDM sampling, and PDM filtering. Produces a 8b 16kHz audio stream which is
// sent to ACO.
// =============================================================================
module dfe #(
// ===========================================================... | 8.182828 |
module integrator #(
parameter I_BW = 5,
parameter O_BW = 8
) (
// clock and reset
input clk_i,
input rst_n_i,
// streaming input
input en_i,
input signed [I_BW - 1 : 0] data_i,
input valid_i,
// streaming output
output signed [O_... | 7.330864 |
module pdm_clk (
// clock and reset
input clk_i,
input rst_n_i,
// input
input en_i,
// output
output pdm_clk_o
);
// =========================================================================
// Local Parameters
// ====================================================================... | 7.817577 |
module sampler (
// clock and reset
input clk_i,
input rst_n_i,
// input
input en_i,
input pdm_clk_i,
input data_i,
// streaming output
output data_o,
output valid_o
);
// =========================================================================
// PDM Clock Positive Edge ... | 7.773786 |
module clzi #(
// external parameter
parameter N = 2,
// internal parameters
parameter WI = 2 * N,
parameter WO = N + 1
) (
input wire [WI-1:0] d,
// output logic [WO-1:0] q
output [WO-1:0] q
);
// original source:
// always_comb begin
// if (d[N - 1 + N] == 1'b0) begi... | 7.846939 |
module packing #(
// =========================================================================
// Local Parameters - Do Not Edit
// =========================================================================
parameter I_BW = 8,
parameter N_COEF = 13,
parameter O_BW = I_BW * N_COEF
) (
// c... | 7.918029 |
module power_spectrum #(
// =========================================================================
// Local Parameters - Do Not Edit
// =========================================================================
parameter I_BW = 21,
parameter O_BW = 32
) (
// clock and reset
input clk_i,
... | 7.048875 |
module preemphasis #(
// =========================================================================
// Local Parameters - Do Not Edit
// =========================================================================
parameter I_BW = 8, // PCM input
parameter O_BW = 9
) (
// clock and reset
input ... | 6.866647 |
module quant #(
// =========================================================================
// Local Parameters - Do Not Edit
// =========================================================================
parameter I_BW = 16,
parameter O_BW = 8
) (
// clock and reset
input clk_i,
input rs... | 7.701824 |
module dbg #(
parameter DFE_OUTPUT_BW = 8,
parameter ACO_OUTPUT_BW = 8 * 13
)(
// clock and reset
input clk_i,
input rst_n_i,
// logic analyzer signals
input [127:0] la_data_in_i,
output [127:0] la_data_out_o,
inpu... | 6.99095 |
module fifo #(
parameter DATA_WIDTH = 16,
parameter FIFO_DEPTH = 3
) (
input clk_i,
input rst_n_i,
input enq_i,
input deq_i,
input [DATA_WIDTH - 1 : 0] din_i,
output [DATA_WIDTH - 1 : 0] dout_o,
output full_o_n,
output empty_o_n
);
SizedFIFO #(
.p1width (DATA_WID... | 8.01468 |
module dffram #(
parameter WIDTH = 32,
parameter DEPTH = 256,
// ========================================================================
// Local Parameters - Do Not Edit
// ========================================================================
parameter ADDR_BW = $clog2(DEPTH)
) (
input... | 8.216377 |
module bimpy #(
// {{{
parameter BW = 18, // Number of bits in i_b
// DESIGN COMPILER MODIFICATON - Parameters must be declared before use
parameter LUTB = 2 // Number of bits in i_a for our LUT multiply
// }}}
) (
// {{{
input wire i_clk,
i_reset,
i_ce,
input wire [(LUTB-1... | 6.898984 |
module desgin1 (
input [7:0] kaiguan, //k1-k8
input rst,
clk, //λаť
output [6:0] seven_LED, //λ
output [7:0] LED
);
reg n; //nΪÿһλ
reg next;
reg cout = 0;
reg state; //ǰλõֵ
integer i = 0; //жѭʹ
reg [4:0] num = 0; //ƥɹĴ
reg [6:0] seven_LED;
reg [7:0] LED;
parameter s1 = 0;
... | 6.540766 |
module Design_Example_RTL (
A,
E,
F,
Start,
clock,
reset_b
);
(* src = "top.v:7" *)
output [3:0] A;
(* src = "top.v:8" *)
output E;
(* src = "top.v:8" *)
output F;
(* src = "top.v:9" *)
input Start;
(* src = "top.v:9" *)
input clock;
(* src = "top.v:11" *)
wire clr_A_F;
... | 6.562526 |
module designA_tests ();
// Input and output to the design
reg [10:0] input_signal;
wire [10:0] output_signal;
// Clocks and helper vars for clocks
reg clk = 0;
reg posedge_big_clk = 0;
reg [31:0] counter = 0;
reg [31:0] big_clk_time = 2000;
// Start the clocks - big_clk is 22 clk ... | 7.482885 |
module designB_tests ();
// Input and output to the design
reg [10:0] input_signal;
wire [10:0] output_signal;
// Clocks and helper vars for clocks
reg clk = 0;
reg posedge_big_clk = 0;
reg [31:0] counter = 0;
reg [31:0] big_clk_time = 2000;
// Start the clocks - big_clk is 22 clk ... | 7.417361 |
module designExampleDDMano (
A,
E,
F,
clk,
rstAL,
start
);
output [3:0] A;
output E, F;
input clk, rstAL, start;
// instantiating control unit and datapath unit
designExampleDTP datapathUnit (
A,
E,
F,
clrE,
clrAF,
setE,
setF,
incrA,
... | 6.787509 |
module designExampleCTRL (
clrE,
setE,
setF,
clrAF,
incrA,
A3,
A2,
start,
rstAL,
clk
);
output reg clrE, setE, setF, clrAF, incrA;
input A3, A2, start, rstAL, clk;
reg [1:0] currState, nextState;
parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b11;
always @(posedge clk, nege... | 6.787509 |
module designExampleDTP (
A,
E,
F,
clrE,
clrAF,
setE,
setF,
incrA,
clk
);
output reg [3:0] A;
output reg E, F;
input clrE, clrAF, setE, setF, incrA, clk;
always @(posedge clk) begin
if (setE) E <= 1;
if (setF) F <= 1;
if (clrE) E <= 0;
if (clrAF) begin
... | 6.787509 |
module D_Latch (
D,
E,
Q
);
input wire D;
input wire E;
output wire Q;
wire nand2_out = ~(D & E);
wire D_neg = ~(D & D);
wire nand3_out = ~(D_neg & E);
wire Q_neg = ~(nand3_out & Q);
assign Q = ~(nand2_out & Q_neg);
endmodule
| 6.568937 |
module D_Flip_Flop (
D,
CLK,
Q,
E
);
input wire D;
input wire CLK;
input wire E;
output wire Q;
wire dff_connection;
wire ff_input = ~E & Q | E & D;
D_Latch d_latch1 (
ff_input,
~CLK,
dff_connection
);
D_Latch d_latch2 (
dff_connection,
~(~CLK),
Q... | 7.225235 |
module MUX2_1_1bit (
S0,
S1,
O,
S
);
input wire S0;
input wire S1;
input wire S;
output wire O;
assign O = (S0 & (~S)) | (S1 & S);
endmodule
| 6.913585 |
module Full_Adder_1bit (
A,
B,
Cin,
O,
Cout
);
input wire A;
input wire B;
input wire Cin;
output wire O;
output wire Cout;
wire controlled_Cout = A & B | A & Cin | B & Cin;
assign O = Cin === 1'bX ? 1'b0 : Cin & ~B & ~A | ~Cin & B & ~A | Cin & B & A | ~Cin & ~B & A;
assign Cout =... | 6.621769 |
module Adder_Substractor_4bit (
A,
B,
Cin,
O,
Cout
);
input wire [3:0] A;
input wire [3:0] B;
input wire Cin;
output wire [3:0] O;
output wire Cout;
wire B0 = Cin & ~B[0] | ~Cin & B[0];
wire B1 = Cin & ~B[1] | ~Cin & B[1];
wire B2 = Cin & ~B[2] | ~Cin & B[2];
wire B3 = Cin & ~B[3... | 6.812895 |
module Adder_Substractor_8bit (
A,
B,
Cin,
O,
Cout
);
input wire [7:0] A;
input wire [7:0] B;
input wire Cin;
output wire [7:0] O;
output wire Cout;
wire B0 = Cin & ~B[0] | ~Cin & B[0];
wire B1 = Cin & ~B[1] | ~Cin & B[1];
wire B2 = Cin & ~B[2] | ~Cin & B[2];
wire B3 = Cin & ~B[3... | 6.812895 |
module Adder_Substractor_16bit (
A,
B,
Cin,
O,
Cout
);
input wire [15:0] A;
input wire [15:0] B;
input wire Cin;
output wire [15:0] O;
output wire Cout;
wire cout0;
Adder_Substractor_8bit as0 (
A[7:0],
B[7:0],
Cin,
O[7:0],
cout0
);
Adder_Substractor... | 6.812895 |
module PART1_8bit (
E,
FunSel,
I,
Q,
CLK
);
input wire E;
input wire [1:0] FunSel;
input wire [7:0] I;
input wire CLK;
output wire [7:0] Q;
//Mux if S=0, output is 0, if S=1, output is I
//Also mean, S=0 is for clear, S=1 is for load
wire [7:0] I_funsel_mux;
MUX2_1_8bit mux0 (
... | 6.639392 |
module PART2_a (
FunSel,
OutASel,
OutBSel,
RegSel,
I,
OutA,
OutB,
CLK
);
input wire [1:0] FunSel;
input wire [1:0] OutASel;
input wire [1:0] OutBSel;
input wire [3:0] RegSel;
input wire [7:0] I;
input wire CLK;
wire [7:0] Q1; //Output of R1
wire [7:0] Q2; //Output of R... | 6.985308 |
module PART2_b (
FunSel,
OutCSel,
OutDSel,
RegSel,
I,
OutC,
OutD,
CLK
);
input wire [1:0] FunSel;
input wire [1:0] OutCSel;
input wire [1:0] OutDSel;
input wire [2:0] RegSel;
input wire [7:0] I;
input wire CLK;
wire [7:0] PC; //Output of PC register
wire [7:0] AR; //Ou... | 7.0302 |
module PART3 (
A,
B,
FunSel,
OutALU,
OutFlag,
CLK
);
input wire [7:0] A;
input wire [7:0] B;
input wire [3:0] FunSel;
output wire [7:0] OutALU;
output wire [3:0] OutFlag;
input wire CLK;
wire [3:0] InFlag;
//adder
wire [7:0] B_adder;
wire cin;
wire cout;
wire [7:0] adde... | 7.01162 |
module Memory (
input wire [7:0] address,
input wire [7:0] data,
input wire wr, //Read = 0, Write = 1
input wire cs, //Chip is enable when cs = 0
input wire clock,
output reg [7:0] o // Output
);
//Declaration o�f the RAM Area
reg [7:0] RAM_DATA[0:255];
//Read Ram data from the file
i... | 7.051739 |
module ALUSystem (
input wire [1:0] RF_OutASel,
input wire [1:0] RF_OutBSel,
input wire [1:0] RF_FunSel,
input wire [3:0] RF_RegSel,
input wire [3:0] ALU_FunSel,
input wire [1:0] ARF_OutCSel,
input wire [1:0] ARF_OutDSel,
input wire [1:0] ARF_FunSel,
input wire [2:0] ARF_RegSel,
... | 7.39045 |
module SequenceCounter (
CLK,
Reset,
T
);
input CLK;
input Reset;
output [2:0] T;
reg [2:0] counter = 3'd7; //Start counter from T7. Because at the beginning we will reset all registers
always @(posedge CLK) begin
counter = counter + 3'd1;
if (Reset == 1'b1) begin //Reset counter to T0
... | 7.141471 |
module Decoder_8_1 (
input [2:0] s,
output S0,
output S1,
output S2,
output S3,
output S4,
output S5,
output S6,
output S7
);
assign S0 = (~s[0] & ~s[1] & ~s[2]),
S1 = (~s[2] & ~s[1] & s[0]),
S2 = (~s[2] & s[1] & ~s[0]),
S3 = (~s[2] & s[1] & s[0]),
S4 = (s[2... | 6.78452 |
module HardwiredControlUnit (
CLK,
Reset_out,
T_out,
R1_out,
R2_out,
R3_out,
R4_out,
PC_out,
AR_out,
SP_out
);
//module HardwiredControlUnit(CLK);
input CLK;
output Reset_out;
output [2:0] T_out;
output [7:0] R1_out;
output [7:0] R2_out;
output [7:0] R3_out;
outp... | 7.607372 |
module designware_divmod (
clock,
reset,
dividend,
divisor,
quot_out,
rem_out
);
parameter DIVIDEND_BIT_WIDTH = 16;
parameter DIVISOR_BIT_WIDTH = 16;
parameter SIGNED = 0; // 0 means unsigned, 1 means two's complement signed numbers
parameter IS_DIV = 1; // 0 means mod, 1 means div
... | 7.218582 |
module designware_mult (
clock,
reset,
in0,
in1,
out
);
parameter IN0_BIT_WIDTH = 16;
parameter IN1_BIT_WIDTH = 16;
parameter OUT_BIT_WIDTH = 16;
parameter SIGNED = 0; //0 means unsigned, 1 means two's complement signed numbers
parameter NUM_STAGES = 2; //number of pipeline stages, the l... | 7.08314 |
module design_1_AD7887_0_0 (
X_AXIS_OUT,
Y_AXIS_OUT,
clk_in,
SAMPLE_PULSER,
DATA_IN,
DATA_OUT,
DATA_READY_IN
);
output [11:0] X_AXIS_OUT;
output [11:0] Y_AXIS_OUT;
input clk_in;
output SAMPLE_PULSER;
input [15:0] DATA_IN;
output [15:0] DATA_OUT;
input DATA_READY_IN;
wire \<c... | 7.177439 |
module design_1_adder_0_0 (
addend_1,
addend_2,
sum,
cin,
cout
);
input wire [8 : 0] addend_1;
input wire [8 : 0] addend_2;
output wire [8 : 0] sum;
input wire cin;
output wire cout;
adder inst (
.addend_1(addend_1),
.addend_2(addend_2),
.sum(sum),
.cin(cin),
... | 6.632633 |
module design_1_adder_0_0 (
addend_1,
addend_2,
sum,
cin,
cout
);
input [8:0] addend_1;
input [8:0] addend_2;
output [8:0] sum;
input cin;
output cout;
wire [8:0] addend_1;
wire [8:0] addend_2;
wire cin;
wire cout;
wire [8:0] sum;
design_1_adder_0_0_adder inst (
.addend... | 6.632633 |
module design_1_adder_1_0 (
addend_1,
addend_2,
sum,
cin,
cout
);
input wire [8 : 0] addend_1;
input wire [8 : 0] addend_2;
output wire [8 : 0] sum;
input wire cin;
output wire cout;
adder inst (
.addend_1(addend_1),
.addend_2(addend_2),
.sum(sum),
.cin(cin),
... | 6.632633 |
module design_1_adder_1_0 (
addend_1,
addend_2,
sum,
cin,
cout
);
input [8:0] addend_1;
input [8:0] addend_2;
output [8:0] sum;
input cin;
output cout;
wire [8:0] addend_1;
wire [8:0] addend_2;
wire cin;
wire cout;
wire [8:0] sum;
design_1_adder_1_0_adder inst (
.addend... | 6.632633 |
module design_1_ALU_0_0 (
alu_out,
data1,
data2,
sign_extend_data,
func,
ALUSrc
);
output wire [7 : 0] alu_out;
input wire [7 : 0] data1;
input wire [7 : 0] data2;
input wire [15 : 0] sign_extend_data;
input wire [3 : 0] func;
input wire ALUSrc;
ALU #(
.ADD('B000010),
... | 6.825675 |
module design_1_ALU_0_0 (
alu_out,
data1,
data2,
sign_extend_data,
func,
ALUSrc
);
output [7:0] alu_out;
input [7:0] data1;
input [7:0] data2;
input [15:0] sign_extend_data;
input [3:0] func;
input ALUSrc;
wire ALUSrc;
wire [7:0] alu_out;
wire [7:0] data1;
wire [7:0] data2;
... | 6.825675 |
module design_1_ALU_control_0_0 (
op,
func,
ALU_func
);
input wire [5 : 0] op;
input wire [5 : 0] func;
output wire [3 : 0] ALU_func;
ALU_control #(
.ADD('B000010),
.SUB('B000110),
.AND('B000000),
.OR ('B000001)
) inst (
.op(op),
.func(func),
.ALU_func(A... | 6.825675 |
module design_1_ALU_control_0_0 (
op,
func,
ALU_func
);
input [5:0] op;
input [5:0] func;
output [3:0] ALU_func;
endmodule
| 6.825675 |
module design_1_AND_0_0 (
A,
B,
F
);
input wire A;
input wire B;
output wire F;
AND inst (
.A(A),
.B(B),
.F(F)
);
endmodule
| 6.608399 |
module design_1_AND_1_0 (
A,
B,
F
);
input wire A;
input wire B;
output wire F;
AND inst (
.A(A),
.B(B),
.F(F)
);
endmodule
| 6.608399 |
module design_1_AND_2_0 (
A,
B,
F
);
input wire A;
input wire B;
output wire F;
AND inst (
.A(A),
.B(B),
.F(F)
);
endmodule
| 6.608399 |
module design_1_AND_3_0 (
A,
B,
F
);
input wire A;
input wire B;
output wire F;
AND inst (
.A(A),
.B(B),
.F(F)
);
endmodule
| 6.608399 |
module design_1_AND_4_0 (
A,
B,
F
);
input wire A;
input wire B;
output wire F;
AND inst (
.A(A),
.B(B),
.F(F)
);
endmodule
| 6.608399 |
module design_1_ARM_SOC_0_1 (
CLK,
RESET,
TDI,
TCK,
TMS,
TDO,
haddrs,
hbursts,
hmastlocks,
hprots,
hsizes,
htranss,
hwdatas,
hwrites,
hrdatas,
hreadys,
fclk_ss,
srs_rst_ss
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, ASSOCIATED_RESET RE... | 6.601101 |
module design_1_clk_wiz_0_0 (
// Clock in ports
input clk_in1,
// Clock out ports
output clk_out1,
// Status and control signals
input reset,
output locked
);
design_1_clk_wiz_0_0_clk_wiz inst (
// Clock in ports
.clk_in1(clk_in1),
// Clock out ports
.clk_out1(... | 6.972061 |
module design_1_clk_wiz_0_0_clk_wiz ( // Clock in ports
input clk_in1,
// Clock out ports
output clk_out1,
// Status and control signals
input reset,
output locked
);
// Input buffering
//------------------------------------
IBUF clkin1_ibufg (
.O(clk_in1_design_1_clk_wiz_0_0),
... | 6.972061 |
module design_1_clk_wiz_0_1 (
// Clock out ports
output sys_clk,
// Status and control signals
input reset,
// Clock in ports
input clk_in1_p,
input clk_in1_n
);
design_1_clk_wiz_0_1_clk_wiz inst (
// Clock out ports
.sys_clk(sys_clk),
// Status and control signals ... | 6.972061 |
module design_1_clk_wiz_0_1_clk_wiz ( // Clock in ports
// Clock out ports
output sys_clk,
// Status and control signals
input reset,
input clk_in1_p,
input clk_in1_n
);
// Input buffering
//------------------------------------
wire clk_in1_design_1_c... | 6.972061 |
module design_1_clk_wiz_0_1 (
sys_clk,
reset,
clk_in1_p,
clk_in1_n
);
output sys_clk;
input reset;
input clk_in1_p;
input clk_in1_n;
(* IBUF_LOW_PWR *)wire clk_in1_n;
(* IBUF_LOW_PWR *)wire clk_in1_p;
wire reset;
wire sys_clk;
design_1_clk_wiz_0_1_design_1_clk_wiz_0_1_clk_wiz inst (
... | 6.972061 |
module design_1_clk_wiz_1_0 (
// Clock in ports
input clk_in1_p,
input clk_in1_n,
// Clock out ports
output clk_out1,
// Status and control signals
input reset,
output locked
);
design_1_clk_wiz_1_0_clk_wiz inst (
// Clock in ports
.clk_in1_p(clk_in1_p),
.clk_in1_... | 6.972061 |
module design_1_clk_wiz_1_0_clk_wiz ( // Clock in ports
input clk_in1_p,
input clk_in1_n,
// Clock out ports
output clk_out1,
// Status and control signals
input reset,
output locked
);
// Input buffering
//------------------------------------
IBUFDS clkin1_ibufgds (
.O (clk... | 6.972061 |
module design_1_clk_wiz_1_0 (
clk_in1_p,
clk_in1_n,
clk_out1,
reset,
locked
);
input clk_in1_p;
input clk_in1_n;
output clk_out1;
input reset;
output locked;
(* IBUF_LOW_PWR *)wire clk_in1_n;
(* IBUF_LOW_PWR *)wire clk_in1_p;
wire clk_out1;
wire locked;
wire reset;
design_1_c... | 6.972061 |
module design_1_clk_wiz_1_1 (
// Clock out ports
output clk_out1,
// Status and control signals
input reset,
output locked,
// Clock in ports
input clk_in1_p,
input clk_in1_n
);
design_1_clk_wiz_1_1_clk_wiz inst (
// Clock out ports
.clk_out1(clk_out1),
// Statu... | 6.972061 |
module design_1_clk_wiz_1_1 (
clk_out1,
reset,
locked,
clk_in1_p,
clk_in1_n
);
output clk_out1;
input reset;
output locked;
input clk_in1_p;
input clk_in1_n;
(* DIFF_TERM = 0 *) (* IBUF_LOW_PWR *)wire clk_in1_n;
(* DIFF_TERM = 0 *) (* IBUF_LOW_PWR *)wire clk_in1_p;
wire clk_out1;
... | 6.972061 |
module design_1_D_trigger_0_0 (
D,
CLK,
CLRN,
Q
);
input wire D;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 signal_clock CLK" *)
input wire CLK;
input wire CLRN;
output wire Q;
D_trigger inst (
.D(D),
.CLK(CLK),
.CLRN(CLRN),
.Q(Q)
);
endmodule
| 7.180903 |
module design_1_D_trigger_1_0 (
D,
CLK,
CLRN,
Q
);
input wire D;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 signal_clock CLK" *)
input wire CLK;
input wire CLRN;
output wire Q;
D_trigger inst (
.D(D),
.CLK(CLK),
.CLRN(CLRN),
.Q(Q)
);
endmodule
| 7.180903 |
module design_1_D_trigger_2_0 (
D,
CLK,
CLRN,
Q
);
input wire D;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 signal_clock CLK" *)
input wire CLK;
input wire CLRN;
output wire Q;
D_trigger inst (
.D(D),
.CLK(CLK),
.CLRN(CLRN),
.Q(Q)
);
endmodule
| 7.180903 |
module design_1_D_trigger_3_0 (
D,
CLK,
CLRN,
Q
);
input wire D;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 signal_clock CLK" *)
input wire CLK;
input wire CLRN;
output wire Q;
D_trigger inst (
.D(D),
.CLK(CLK),
.CLRN(CLRN),
.Q(Q)
);
endmodule
| 7.180903 |
module design_1_FlipD_0_0 (
q,
data,
clk
);
output wire q;
input wire data;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN design_1_clk, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *)
input wi... | 6.517995 |
module design_1_FlipD_0_0_FlipD (
q,
data,
clk
);
output q;
input data;
input clk;
wire clk;
wire data;
wire q;
FDRE q_reg (
.C (clk),
.CE(1'b1),
.D (data),
.Q (q),
.R (1'b0)
);
endmodule
| 6.517995 |
module design_1_FlipD_0_0 (
q,
data,
clk
);
output q;
input data;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0" *) input clk;
wire clk;
wire data;
wire q;
de... | 6.517995 |
module design_1_FlipD_0_1 (
q,
data,
clk
);
output wire q;
input wire data;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *)
input wire clk;
FlipD inst (
... | 6.517995 |
module design_1_FlipD_1_0 (
q,
data,
clk
);
output wire q;
input wire data;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *)
input wire clk;
FlipD inst (
... | 6.517995 |
module design_1_FlipD_1_0_FlipD (
q,
data,
clk
);
output q;
input data;
input clk;
wire clk;
wire data;
wire q;
FDRE q_reg (
.C (clk),
.CE(1'b1),
.D (data),
.Q (q),
.R (1'b0)
);
endmodule
| 6.517995 |
module design_1_FlipD_1_0 (
q,
data,
clk
);
output q;
input data;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0" *) input clk;
wire clk;
wire data;
wire q;
de... | 6.517995 |
module design_1_IM_0_0 (
Addr,
op,
func,
rs,
rt,
rd,
sign_extend,
J_addr
);
input wire [31 : 0] Addr;
output wire [5 : 0] op;
output wire [5 : 0] func;
output wire [4 : 0] rs;
output wire [4 : 0] rt;
output wire [4 : 0] rd;
output wire [15 : 0] sign_extend;
output wire [... | 7.071596 |
module design_1_instruction_memory_0_0 (
op,
rs,
rt,
rd,
func,
sign_extend,
pc_addr,
clk
);
output wire [5 : 0] op;
output wire [4 : 0] rs;
output wire [4 : 0] rt;
output wire [4 : 0] rd;
output wire [5 : 0] func;
output wire [15 : 0] sign_extend;
input wire [4 : 0] pc_add... | 7.638441 |
module design_1_instruction_memory_0_0 (
op,
rs,
rt,
rd,
func,
sign_extend,
pc_addr,
clk
);
output [5:0] op;
output [4:0] rs;
output [4:0] rt;
output [4:0] rd;
output [5:0] func;
output [15:0] sign_extend;
input [4:0] pc_addr;
(* X_INTERFACE_INFO = "xilinx.com:signal:cloc... | 7.638441 |
module design_1_JK_f_f_0_0 (
clk,
clr,
J,
K,
Q,
Qb
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *)
input wire clk;
input wire clr;
input wire J;
input wire K;
output wire Q;
output wire Qb;
JK_f_f inst (
.clk(clk),
.clr(clr),
.J (J),
.... | 7.051557 |
module design_1_JK_f_f_1_0 (
clk,
clr,
J,
K,
Q,
Qb
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *)
input wire clk;
input wire clr;
input wire J;
input wire K;
output wire Q;
output wire Qb;
JK_f_f inst (
.clk(clk),
.clr(clr),
.J (J),
.... | 7.051557 |
module design_1_JK_f_f_2_0 (
clk,
clr,
J,
K,
Q,
Qb
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *)
input wire clk;
input wire clr;
input wire J;
input wire K;
output wire Q;
output wire Qb;
JK_f_f inst (
.clk(clk),
.clr(clr),
.J (J),
.... | 7.051557 |
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