code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module full_adder__0_248 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.... | 6.521523 |
module full_adder__0_243 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_car... | 6.521523 |
module full_adder__0_239 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.... | 6.521523 |
module full_adder__0_272 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XNOR2_X1 i_0_0 (
.A (i_bit2),
.B (i_bit1),
.ZN(o_sum)
);
OR2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_... | 6.521523 |
module full_adder__0_268 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.... | 6.521523 |
module full_adder__0_263 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_car... | 6.521523 |
module full_adder__0_259 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.... | 6.521523 |
module full_adder__0_292 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XNOR2_X1 i_0_0 (
.A (i_bit1),
.B (i_bit2),
.ZN(o_sum)
);
endmodule
| 6.521523 |
module full_adder__0_283 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(o_sum)
);
endmodule
| 6.521523 |
module division_core ();
reg clk = 1'b0;
reg [31:0] dividend = 'd5421; //'d113;
reg [31:0] divisor = 'd3; //'d2;
reg [31:0] result;
// Instantiate the Unit Under Test (UUT)
core divider (
.i_clk(clk_internal),
.i_dividend(dividend),
.i_divisor(divisor),
.result(result)
);
... | 6.536099 |
module Division_Frecuencia (
input [2:0] Frecuencia_Escogida,
input CLK,
input Reset,
output DivCLK
);
//Genera el codigo en binario para la division de frecuencia (Div) para el divisor.
wire [6:0] Div;
Generate_Div Gen_Div (
.Frec(Frecuencia_Escogida),
.Div (Div)
);
Divisor_CLK... | 7.035462 |
module
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Division_module(input clk, start, input [15:0] div... | 7.088073 |
module division_t ();
reg [7:0] a, b;
wire [15:0] out;
division div (
a,
b,
out
);
initial begin
#5 a = 8'd100;
b = 8'd200;
#5 a = 8'd14;
b = 8'd160;
#5 $finish;
end
endmodule
| 6.733008 |
module
// Module Name: C:/Users/Markazi.co/Desktop/Computer architecture Lab/PipelineMIPS/division_test.v
// Project Name: PipelineMIPS
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Division_module
//
// Dependencies:
//
// Revision:
// Revision 0.01 ... | 6.999332 |
module divison #(
parameter W = 48, //չλ
parameter N = 24 //ijͱλ
) (
input pixelclk,
input rst_n,
input i_hs,
input i_vs,
input i_de,
input [N-1:0] dividend,
input [N-1:0] divisor,
output wire [N-1:0] quotient,
output wire [N-1:0]... | 7.739885 |
module Divisor_Clock_ADC
//Declaracion de senales de entrada y salida
(
input wire Clck_in,
input wire reset_Clock,
output reg Clock_out
);
//Declaracion de senales utilizadas dentro del modulo
reg [13:0] contador;
always @(posedge Clck_in,posedge reset_Clock) //Lista sensitiva, responde ante un... | 6.903411 |
module divisor_clk (
input clk,
output reg clk_out1 = 1'b1,
output reg clk_out2 = 1'b1
);
reg [18:0] cont_1 = 19'b0;
reg [18:0] cont_2 = 19'b0;
parameter valor_divisor2 = 19'd50000; //50000; //1KHz fecuencia de muestreo
//parameter valor_divisor1 = 26'd5000000; //500000; //100Hz fecuencia de mue... | 6.897688 |
module clock_divisor (
input CLK_entrada,
output reg CLK_saida
);
reg [24:0] contador = 25'h0;
always @(posedge CLK_entrada) begin
if (contador == 25'd25000) begin
contador <= 25'h0;
CLK_saida = ~CLK_saida;
end else contador <= contador + 1;
end
endmodule
| 6.578994 |
module Divisor_Frequencia (
clock_in,
clock_out
);
input clock_in; // input clock on FPGA (50 MHz)
output reg clock_out; // output clock after dividing the input clock by divisor
reg [27:0] counter = 28'd0;
parameter DIVISOR = 28'd2; //para sair o clock de 1H
//28'd2 para dividir pela metade apen... | 6.557788 |
module divisor_reloj (
input clk, // 100 Mhz
input reset,
output reg clk_dividido
);
//Divisor para obtener la divisin de salida deseada
localparam divisor = 4999; //Para obtener una seal dividida de 10 kHz
//Formula para tener la frecuencia de la seal que se quiere:
//Valor_dividido = [100 Mhz/(2... | 6.741234 |
module clk_div_sim ();
reg clk;
reg rst_n;
reg [10:0] period;
wire clk_out;
wire [10:0] counter;
clk_div cd (
clk,
rst_n,
period,
clk_out,
counter
);
initial begin
clk = 0;
rst_n = 0;
period = 4;
#10 rst_n = 1;
#100 period = 2;
end
always begin
#... | 6.664124 |
module Divider (
input RST,
input CLK,
input [10:0] DIV_FACTOR, //最大分频 2048, 分频数 N+1
output DIV_CLK,
output RISING_EDGE, //
output FALLING_EDGE
);
reg DIV_CLK_REG, RISING_EDGE_REG, FALLING_EDGE_REG;
reg [10:0] Counter;
always @(posedge CLK, nege... | 7.440694 |
module divM (
input wire clk_in,
output wire clk_out
);
//-- Valor por defecto del divisor
//-- Como en la iCEstick el reloj es de 12MHz, ponermos un valor de 12M
//-- para obtener una frecuencia de salida de 1Hz
parameter M = 12;
//-- Numero de bits para almacenar el divisor
//-- Se calculan con... | 7.6574 |
module divM (
input wire clk_in,
output wire clk_out
);
parameter number = 12_000_000;
//-- Numero de bits para almacenar el divisor
//-- Se calculan con la funcion de verilog $clog2, que nos devuelve el
//-- numero de bits necesarios para representar el numero M
//-- Es un parametro local, que no se... | 7.6574 |
module synchroneous. (Sorgelig)
//
module divmmc
(
input clk_sys,
input [1:0] mode, //00-off, 01-divmmc, 10-zxmmc, 11-divmmc+esxdos
output ready,
// CPU interface
input nWR,
input nRD,
input nMREQ,
input nRFSH,
input nIORQ,
... | 6.508547 |
module
module spi_divmmc
(
input clk_sys,
output ready,
input tx, // Byte ready to be transmitted
input rx, // request to read one byte
input [7:0] din,
output [7:0] dout,
input spi_ce,
output spi_clk,
input spi_di,
output spi_do
);
assign... | 7.34369 |
module divr2 (
rst,
clk,
ce,
ld,
su,
ri,
a,
b,
i,
q,
r,
divByZero,
done
);
parameter WID = 32;
parameter IDLE = 3'd0;
parameter DIV = 3'd1;
parameter SGN = 3'd2;
input rst;
input clk;
input ce; // clock enable
input ld; // pulse to initiate divide
... | 6.828642 |
module divrem #(
parameter WIDTH_LOG = 4
) (
clk,
go,
rst,
num,
den,
ready,
error,
quot,
rem
);
localparam WIDTH = 1 << WIDTH_LOG;
localparam HI = WIDTH - 1;
input clk;
input go;
input rst;
input [HI:0] num;
input [HI:0] den;
output reg ready;
output reg error... | 6.824951 |
module divrem_tb;
reg clk = 0;
wire rst;
reg go = 0;
reg [15:0] num = 0;
reg [15:0] den = 0;
wire m1_ready;
wire m1_error;
wire [15:0] m1_quot;
wire [15:0] m1_rem;
reg [15:0] quot;
reg [15:0] rem;
por por_inst (
.clk(clk),
.rst(rst)
);
divrem dm1 (
.clk(clk),
.g... | 7.287981 |
module Divs (
input clk_in,
output reg clk_div8
);
//分频数
parameter N = 8;
reg [8:0] cnt = 0;
always @(posedge clk_in) begin
if (cnt == N / 2 - 1) begin
clk_div8 <= !clk_div8;
cnt <= 0;
end else cnt <= cnt + 1;
end
endmodule
| 6.528772 |
module divSqrtRecFN_small #(
parameter expWidth = 3,
parameter sigWidth = 3,
parameter options = 0
) (
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
input nReset,
input clock,
/*--------... | 6.994768 |
module divSqrtRecF16_small_div (
input nReset,
input clock,
input [(`floatControlWidth - 1):0] control,
output inReady,
input inValid,
input [16:0] a,
input [16:0] b,
input [2:0] roundingMode,
output outValid,
output [16:0] out,
output [4:0] exceptionFlags
);
wire sqrtOpOu... | 6.845856 |
module divSqrtRecF64_small_div (
input nReset,
input clock,
input [(`floatControlWidth - 1):0] control,
output inReady,
input inValid,
input [64:0] a,
input [64:0] b,
input [2:0] roundingMode,
output outValid,
output [64:0] out,
output [4:0] exceptionFlags
);
wire sqrtOpOu... | 6.505443 |
module divSqrtRecF16_small_sqrt (
input nReset,
input clock,
input [(`floatControlWidth - 1):0] control,
output inReady,
input inValid,
input [16:0] a,
input [2:0] roundingMode,
output outValid,
output [16:0] out,
output [4:0] exceptionFlags
);
wire sqrtOpOut;
divSqrtRecFN_s... | 6.845856 |
module divSqrtRecF64_small_sqrt (
input nReset,
input clock,
input [(`floatControlWidth - 1):0] control,
output inReady,
input inValid,
input [64:0] a,
input [2:0] roundingMode,
output outValid,
output [64:0] out,
output [4:0] exceptionFlags
);
wire sqrtOpOut;
divSqrtRecFN_s... | 6.505443 |
module DIVU (
input [31:0] dividend,
input [31:0] divisor,
input start,
input clock,
input reset,
output [31:0] q,
output [31:0] r,
output reg busy
);
reg [4:0] count;
reg [31:0] tmp_q, tmp_r, tmp_d;
reg r_sign;
assign q = tmp_q;
assign r = r_sign == 1 ? tmp_r + tmp_d : tmp_r... | 6.80715 |
module divux8 (
input [7:0] a,
input [7:0] b,
input clk,
input start,
input resetn,
output [7:0] q,
output [15:0] r,
output busy
);
// module divu
// #(parameter WIDTH = 8 )(
// input [WIDTH-1:0] a,
// input [WIDTH-1:0] b,
// input clk,
// input start,
// ... | 7.208476 |
module divu_0 (
a,
b,
clk,
start,
resetn,
q,
r,
busy
);
input wire [7 : 0] a;
input wire [7 : 0] b;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME clk, ASSOCIATED_RESET resetn, FREQ_HZ 100000000, PHASE 0.000" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *)
... | 6.876924 |
module divu_0 (
a,
b,
clk,
start,
resetn,
q,
r,
busy
);
input [7:0] a;
input [7:0] b;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME clk, ASSOCIATED_RESET resetn, FREQ_HZ 100000000, PHASE 0.000" *) input clk;
input sta... | 6.876924 |
module divWrapper (
input clk,
rst,
input clear,
input [31:0] a,
input [31:0] b,
input [7:0] op,
output [63:0] div_result,
output reg divstall //除法发出的stall信号
);
wire div_ready;
reg div_start;
reg div_sign;
reg div_refresh;
div div (
.clk(clk),
.rst(rst),
... | 7.073314 |
module divx8 (
input [7:0] a,
input [7:0] b,
input clk,
input start,
input resetn,
output [7:0] q,
output [15:0] r,
output busy
);
// module divu
// #(parameter WIDTH = 8 )(
// input [WIDTH-1:0] a,
// input [WIDTH-1:0] b,
// input clk,
// input start,
// ... | 7.274872 |
module divx_short (
input Clock,
input Reset,
output ena
);
parameter div = 10;
reg [31:0] count;
assign ena = ~|count;
always @(posedge Clock, negedge Reset)
if (~Reset) count <= div - 1;
else count <= ~|count ? div - 1 : count - 1;
endmodule
| 6.517834 |
module DIV_ #(
parameter N = 8,
M = N
) (
input [N-1:0] A,
input [M-1:0] B,
output [N-1:0] O
);
assign O = A / B;
endmodule
| 9.032108 |
module div_0 (
a,
b,
clk,
start,
resetn,
q,
r,
busy
);
input wire [7 : 0] a;
input wire [7 : 0] b;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME clk, ASSOCIATED_RESET resetn, FREQ_HZ 100000000, PHASE 0.000" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *)
... | 6.638152 |
module div_0 (
a,
b,
clk,
start,
resetn,
q,
r,
busy
);
input [7:0] a;
input [7:0] b;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME clk, ASSOCIATED_RESET resetn, FREQ_HZ 100000000, PHASE 0.000" *) input clk;
input star... | 6.638152 |
module Div_100 (
low_out,
high_in
);
output wire low_out;
input wire high_in;
reg [7:0] count;
initial begin
count = 7'b0000000;
end
always @(posedge high_in) begin
count = count + 1;
if (count >= 100) // 0~99
count = 0;
end
assign low_out = (count < 50) ? 1 : 0;
endmodule
| 6.711777 |
module div_12 (
numerator,
quotient,
remainder
);
input [5:0] numerator;
output reg [2:0] quotient;
output [3:0] remainder;
reg [3:0] remainder_bits;
assign remainder = {remainder_bits, numerator[1:0]};
always @(*) begin
case (numerator[5:2])
0: begin
quotient = 0;
... | 6.765552 |
module div_16 (
clk,
rst,
init_in,
A,
B,
Result,
done
);
input rst;
input clk;
input init_in;
input [15:0] A;
input [15:0] B;
output [15:0] Result;
output done;
wire INIT, SH, LDA;
wire MSB;
wire [15:0] Result_Sub;
wire [15:0] Reg_A;
wire DEC, z, DV0;
lsr_div... | 6.635745 |
module div_1k (
input clk_i,
input rst_n_i,
output clk_o
);
reg [15:0] cnt = 'h0;
always @(posedge clk_i or negedge rst_n_i) begin
if (~rst_n_i) cnt <= 15'h0;
else begin
cnt <= cnt + 1;
end
end
assign clk_o = cnt[15];
endmodule
| 6.654806 |
module div_25HZ (
input clk,
input rst_n,
output reg VGA_clk
);
//2分频
always @(posedge clk or negedge rst_n) begin
if (!rst_n) VGA_clk <= 1'b0;
else VGA_clk <= ~VGA_clk;
end
endmodule
| 7.660316 |
module div_26 (
clock,
denom,
numer,
quotient,
remain
);
input clock;
input [17:0] denom;
input [25:0] numer;
output [25:0] quotient;
output [17:0] remain;
wire [17:0] sub_wire0;
wire [25:0] sub_wire1;
wire [17:0] remain = sub_wire0[17:0];
wire [25:0] quotient = sub_wire1[25:0];
... | 6.618523 |
module div_26 (
clock,
denom,
numer,
quotient,
remain
);
input clock;
input [17:0] denom;
input [25:0] numer;
output [25:0] quotient;
output [17:0] remain;
endmodule
| 6.618523 |
module div_32bit_4fp (
input clk,
input rst_n,
input [`N-1:0] A,
input [`N-1:0] B,
input valid,
output [`N-1:0] OUT,
output ovrflow,
output ready,
output inv
);
wire [`N+`FP-1:0] Q, R;
wire [`N+`FP-1:0] FP_A, FP_B;
assign FP_A = (A << 4);
assign FP_B = {4'b0, B};
div_3... | 7.025077 |
module div_32_bit (
input signed [31:0] dividend,
divisor,
output reg [32*2-1:0] z
);
reg [63:32] high, low;
always @(*) begin
high = dividend % divisor;
low = (dividend - high) / divisor;
begin
z = {high, low};
end
end
endmodule
| 6.508945 |
module div_5 (
input wire sys_clk,
input wire sys_rst_n,
output wire clk_5
);
reg [2:0] cnt_rise;
reg [2:0] cnt_fall;
reg clk_rise;
reg clk_fall;
always @(posedge sys_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) cnt_rise <= 3'd0;
else if (cnt_rise == 3'd4) cnt_rise <= 3'd0;
else ... | 7.837547 |
module div_aegp (
input clk, // System clock
input reset, // Asynchron reset
input [8:0] n_in, // Nominator
input [8:0] d_in, // Denumerator
output reg [8:0] q_out
); // Quotient
// --------------------------------------------------------
reg [1:0] state... | 7.755059 |
module div_by3 (
input clk_in,
input reset_n,
output clk_out
);
reg clk_out_a;
reg clk_out_b;
reg clk_out_c;
always @(posedge clk_in or negedge reset_n) begin
if (!reset_n) begin
clk_out_a <= 1'b0;
end else begin
clk_out_a <= (~clk_out_b && ~clk_out_a);
end
end
alwa... | 7.001894 |
module div_by_4 (
input clk_in,
input reset_n,
output reg clk_out
);
//-----------------------------------------------
// Register Declaration
//-----------------------------------------------
reg clk_out_a;
//-----------------------------------------------
// 1st Flip Flop Delayin... | 6.531323 |
module div_by_two (
input clk_in,
input reset_n,
output reg clk_out
);
always @(posedge clk_in or negedge reset_n) begin
if (!reset_n) begin
clk_out <= 1'b0;
end else begin
clk_out <= ~clk_out;
end
end
endmodule
| 7.335233 |
module div_calc (
divisor,
remainder_in,
quotient_in,
quotient_out,
remainder_out
);
/*need to Subtract the Divisor register from the
left half of the Remainder register, & place the
result in the left half of the Remainder register.*/
input [31:0] divisor;
input [63:0] remainder_in;
inp... | 7.099765 |
module
////////////////////////////////////////////////////
module div_cell(
T_in,
Divisor_in,
Remainder_in,
Remainder_out,
C_in,
C_out
);
input T_in, Divisor_in, Remainder_in, C_in;
output Remainder_out, C_out;
//Output for curry
assign C_out = Remainder_in & C_in | (Divisor_in ^ T_in)&(Remainder_in | C_... | 8.28859 |
module div_check (
d_out
);
parameter N = 32;
parameter Q = 16;
output reg [N-1:0] d_out;
parameter [N-1:0] d1_in1 = 32'b0000000000000001_0101000001101110;
parameter [N-1:0] d1_in2 = 32'b1000000000000100_1110011001001110;
wire [N-1:0] d1_out;
fpdiv #(Q, N) divider1 (
d1_in1,
d1_in2,
... | 6.767791 |
module div_clk (
input CLK,
output reg CLK_div_N
);
parameter N = 1000000;
reg [31:0] count = 0;
always @(posedge CLK) begin
if (count == 2 * N) count <= 0;
else count <= count + 1;
CLK_div_N = (count < N) ? 0 : 1;
end
endmodule
| 7.591807 |
module div_clock (
input clk,
input rst_clk,
output div_clk_w
);
reg div_clk;
assign div_clk_w = div_clk;
reg [21:0] cnt;
always @(posedge clk or negedge rst_clk) begin
if (rst_clk == 1) begin
cnt = 0;
div_clk = 0;
end else if (cnt == 22'd50000) begin
div_clk = ~div_clk;
... | 6.802261 |
module div_even (
iCLK,
oCLK,
div
);
input iCLK;
parameter WIDE = 32;
input [WIDE-1:0] div;
output oCLK;
reg outCLK;
initial outCLK = 1'b0;
reg [WIDE-1:0] cnt;
initial cnt = 0;
always @(posedge iCLK) begin
if (cnt < (div[WIDE-1:1] - 1)) cnt <= cnt + 32'b1; // div /2 eg. div2 is 1 d... | 7.545694 |
module DIV_FREQ (
input [31:0] Din,
input conf_div,
input enable,
input reset,
input clk,
output reg clk_out
);
reg [31:0] t = 32'h1;
reg [31:0] count = 32'h0;
reg [31:0] pos_count = 32'h0;
reg [31:0] neg_count = 32'h0;
always @(posedge clk, posedge reset) begin
if (reset) begin... | 7.474813 |
module div_int (
denom,
numer,
quotient,
remain
);
input [3:0] denom;
input [3:0] numer;
output [3:0] quotient;
output [3:0] remain;
wire [3:0] sub_wire0;
wire [3:0] sub_wire1;
wire [3:0] quotient = sub_wire0[3:0];
wire [3:0] remain = sub_wire1[3:0];
lpm_divide LPM_DIVIDE_component ... | 7.178432 |
module div_int (
denom,
numer,
quotient,
remain
);
input [3:0] denom;
input [3:0] numer;
output [3:0] quotient;
output [3:0] remain;
endmodule
| 7.178432 |
module Div_magnitude_comparator #(
parameter dataIN_width = 4
) (
input [dataIN_width - 1 : 0] A,
B,
output reg equal_to,
greater_than,
less_than
);
always @(A, B) begin
equal_to <= 1'b0;
greater_than <= 1'b0;
less_than <= 1'b0;
if (A > B) greater_than <= 1'b1;
else... | 6.750827 |
module div_mantissa #(
parameter DATAWIDTH = 24
) (
input clk,
input rst_n,
input en,
input [DATAWIDTH-1:0] dividend,
input [DATAWIDTH-1:0] divisor,
input [2:0] mode,
output isdone,
//output ready,
output [DATAWIDTH-1:0] quotient //,
//output [DATAWIDTH-1:0] remainder
);
... | 8.53849 |
module
//File : Div_mod_top_level.v
//Discreption : Top level module for divider
////////////////////////////////////////////////////
module Div_mod_top_level(
clk,
reset,
divisor,
dividend,
mode,
valid_input,
valid_output,
final_output
);
input signed [31:0] dividend;
input signed [15:0] divisor;
input cl... | 7.584829 |
module div_mult (
input clk,
input reset,
input [1:0] controle,
input [31:0] A,
B,
output reg [31:0] HI,
LO,
output wire div0
);
wire [31:0] HI_MULT;
wire [31:0] LO_MULT;
wire [31:0] HI_DIV;
wire [31:0] LO_DIV;
multiplier mult (
.mc(A),
.mp(B),
.clk(clk),
... | 7.119464 |
module Div_mux_2_to_1 #(
parameter dataIN_width = 4
) (
input [dataIN_width - 1 : 0] d1,
d0,
input sel,
output reg [dataIN_width - 1 : 0] y
);
always @(d1, d0, sel) begin
if (sel) y <= d1;
else y <= d0;
end
endmodule
| 7.714066 |
module div_mux1 (
input [4:0] in1,
in2,
input s2,
output reg [4:0] m1out
);
always @(in1, in2, s2) begin
if (s2) m1out = in1;
else m1out = in2;
end
endmodule
| 7.320327 |
module div_m_n (
input wire sys_clk,
input wire sys_rst_n,
output wire clk_out
);
parameter M_N = 8'd87;
parameter c89 = 8'd24; // 8/9时钟切换点
parameter div_e = 5'd8; //偶数周期
parameter div_o = 5'd9; //奇数周期
//用于产生分频输出的计数，当div_flag==0,计数最大值是div_e-1；当div_flag==1,计数最大值是div_o-1；
reg [3:0] clk_cnt;
... | 7.830516 |
module div_N (
input CLK,
output reg CLK_div_N
);
parameter N = 1000;
reg [31:0] count = 0;
always @(posedge CLK) begin
if (count == 2 * N) count <= 0;
else count <= count + 1;
CLK_div_N = (count < N) ? 0 : 1;
end
endmodule
| 7.713354 |
module div_N1 (
input CLK,
output reg CLK_div_N
);
parameter N = 250000;
reg [31:0] count = 0;
always @(posedge CLK) begin
if (count == 2 * N) count <= 0;
else count <= count + 1;
CLK_div_N = (count < N) ? 0 : 1;
end
endmodule
| 7.409057 |
module data_extract_N32_ES6 (
in,
rc,
regime,
exp,
mant
);
function [31:0] log2;
input reg [31:0] value;
begin
value = value - 1;
for (log2 = 0; value > 0; log2 = log2 + 1) value = value >> 1;
end
endfunction
parameter N = 32;
parameter Bs = log2(N);
parameter es =... | 8.552482 |
module DSR_left_N_S (
a,
b,
c
);
parameter N = 16;
parameter S = 4;
input [N-1:0] a;
input [S-1:0] b;
output [N-1:0] c;
wire [N-1:0] tmp[S-1:0];
assign tmp[0] = b[0] ? a << 7'd1 : a;
genvar i;
generate
for (i = 1; i < S; i = i + 1) begin : loop_blk
assign tmp[i] = b[i] ? tmp[i-1... | 6.55013 |
module DSR_right_64_lat1 (
clk,
a,
b,
c
);
parameter N = 32;
input clk;
input [N-1:0] a;
input [5:0] b;
output [N-1:0] c;
wire [N-1:0] tmp32, tmp16, tmp8, tmp4, tmp2, tmp1;
assign tmp32 = b[5] ? a >> 7'd32 : a;
assign tmp16 = b[4] ? tmp32 >> 7'd16 : tmp32;
assign tmp8 = b[3] ? tmp1... | 6.918586 |
module LOD16_4 (
in,
out,
out_v
);
input [15:0] in;
output [3:0] out;
output out_v;
wire [2:0] out_l, out_h;
wire out_vl, out_vh;
LOD8_3 pl (
.in(in[7:0]),
.out(out_l),
.out_v(out_vl)
);
LOD8_3 ph (
.in(in[15:8]),
.out(out_h),
.out_v(out_vh)
);
assign ... | 6.780402 |
module LOD8_3 (
in,
out,
out_v
);
input [7:0] in;
output [2:0] out;
output out_v;
wire [1:0] out_l, out_h;
wire out_vl, out_vh;
LOD4_2 pl (
.in(in[3:0]),
.out(out_l),
.out_v(out_vl)
);
LOD4_2 ph (
.in(in[7:4]),
.out(out_h),
.out_v(out_vh)
);
assign ou... | 6.634091 |
module LOD4_2 (
in,
out,
out_v
);
input [3:0] in;
output [1:0] out;
output out_v;
wire out_l, out_h;
wire out_vl, out_vh;
LOD2_1 pl (
.in(in[1:0]),
.out(out_l),
.out_v(out_vl)
);
LOD2_1 ph (
.in(in[3:2]),
.out(out_h),
.out_v(out_vh)
);
assign out = ... | 6.607174 |
module LOD2_1 (
in,
out,
out_v
);
input [1:0] in;
output out;
output out_v;
assign out = ~in[1] & in[0];
assign out_v = |in;
endmodule
| 7.042873 |
module Add_full_0 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
tri c_in;
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
Add_half_0 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_511 M2 (
.sum(sum),... | 6.995469 |
module Add_full_255 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
Add_half_510 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_509 M2 (
.sum(sum),
.... | 7.223695 |
module Add_full_254 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
Add_half_508 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_507 M2 (
.sum(sum),
.... | 7.622175 |
module Add_full_253 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
Add_half_506 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_505 M2 (
.sum(sum),
.... | 7.449095 |
module Add_rca_4_0 (
sum,
c_out,
a,
b,
c_in
);
output [3:0] sum;
input [3:0] a;
input [3:0] b;
input c_in;
output c_out;
wire c_in2, c_in3, c_in4;
tri c_in;
Add_full_0 M1 (
.sum(sum[0]),
.c_out(c_in2),
.a(a[0]),
.b(b[0]),
.c_in(c_in)
);
Add_full_255... | 6.672672 |
module Add_full_252 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
Add_half_504 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_503 M2 (
.sum(sum),
.... | 7.549191 |
module Add_full_251 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
Add_half_502 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_501 M2 (
.sum(sum),
.... | 7.355414 |
module Add_full_250 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
Add_half_500 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_499 M2 (
.sum(sum),
.... | 7.377879 |
module Add_full_249 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
Add_half_498 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_497 M2 (
.sum(sum),
.... | 7.440479 |
module Add_rca_4_63 (
sum,
c_out,
a,
b,
c_in
);
output [3:0] sum;
input [3:0] a;
input [3:0] b;
input c_in;
output c_out;
wire c_in2, c_in3, c_in4;
Add_full_252 M1 (
.sum(sum[0]),
.c_out(c_in2),
.a(a[0]),
.b(b[0]),
.c_in(c_in)
);
Add_full_251 M2 (
... | 6.789871 |
module Add_full_248 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
Add_half_496 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_495 M2 (
.sum(sum),
.... | 8.058176 |
module Add_full_247 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
Add_half_494 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_493 M2 (
.sum(sum),
.... | 7.918448 |
module Add_full_246 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
Add_half_492 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_491 M2 (
.sum(sum),
.... | 7.602096 |
module Add_full_245 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
Add_half_490 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_489 M2 (
.sum(sum),
.... | 7.80642 |
module Add_rca_4_62 (
sum,
c_out,
a,
b,
c_in
);
output [3:0] sum;
input [3:0] a;
input [3:0] b;
input c_in;
output c_out;
wire c_in2, c_in3, c_in4;
Add_full_248 M1 (
.sum(sum[0]),
.c_out(c_in2),
.a(a[0]),
.b(b[0]),
.c_in(c_in)
);
Add_full_247 M2 (
... | 7.082214 |
module Add_full_244 (
sum,
c_out,
a,
b,
c_in
);
input a, b, c_in;
output sum, c_out;
wire w1, w2, w3;
COR2X1 U1 (
.A(w2),
.B(w3),
.Z(c_out)
);
Add_half_488 M1 (
.sum(w1),
.c_out(w2),
.a(a),
.b(b)
);
Add_half_487 M2 (
.sum(sum),
.... | 7.802129 |
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