code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module divider_ip (
clock,
denom,
numer,
quotient,
remain
);
input clock;
input [63:0] denom;
input [63:0] numer;
output [63:0] quotient;
output [63:0] remain;
wire [63:0] sub_wire0;
wire [63:0] sub_wire1;
wire [63:0] remain = sub_wire0[63:0];
wire [63:0] quotient = sub_wire1[63:... | 6.974841 |
module divider_ip (
clock,
denom,
numer,
quotient,
remain
);
input clock;
input [63:0] denom;
input [63:0] numer;
output [63:0] quotient;
output [63:0] remain;
endmodule
| 6.974841 |
module lab6Part3 (
input [9:0] SW,
input [3:0] KEY,
input CLOCK_50,
output [9:0] LEDR,
output [6:0] HEX0,
HEX1
);
wire reset;
wire go;
wire [7:0] data_result;
/*
* Sw[7:0] is data_in
* KEY[0] synchronous reset when pressed
* KEY[1] go signal
* LEDR displays result
... | 7.960879 |
module divider (
input clk,
reset,
go,
input [7:0] data_in,
output [7:0] data_result
);
// wires to connect datapath and control
wire ld_a, ld_b, ld_c, ld_x, ld_r;
wire ld_alu_out;
wire [1:0] alu_select_a, alu_select_b;
wire alu_op;
control C0 (
.clk(clk),
.reset(reset),
... | 7.389371 |
module control (
input clk,
reset,
go,
output reg ld_a,
ld_b,
ld_c,
ld_x,
ld_r,
ld_alu_out,
output reg [1:0] alu_select_a,
alu_select_b,
output reg alu_op
);
reg [5:0] current_state, next_state;
localparam S_LOAD_A = 5'd0,
S_LOAD_A_WAIT = 5'd1,
... | 7.715617 |
module datapath (
input clk,
reset,
ld_x,
ld_a,
ld_b,
ld_c,
ld_r,
alu_op,
input [7:0] data_in,
ld_alu_out,
input [1:0] alu_select_a,
alu_select_b,
output reg [7:0] data_result
);
reg [7:0] a, b, c, x; // input registers
reg [7:0] alu_out; // output of the alu
... | 6.91752 |
module hex_decoder (
input [3:0] hex_digit,
output reg [6:0] segments
);
always @(*) begin
case (hex_digit)
4'h0: segments = 7'b100_0000;
4'h1: segments = 7'b111_1001;
4'h2: segments = 7'b010_0100;
4'h3: segments = 7'b011_0000;
4'h4: segments = 7'b001_1001;
4'h5: segm... | 7.584821 |
module divider_man #(
parameter N = 40,
parameter M = 32,
parameter N_ACT = M + N - 1
) (
input clk,
input rstn,
input data_rdy,
input [N-1:0] dividend,
input [M-1:0] divisor,
output res_rdy,
output [N_ACT-M:0] merchant, //width = N_ACT-M+1
output [ ... | 7.198369 |
module Divider_module //分频器，8个拨码开关选择特定频率，缺省值为10M。
(
input clk_50M,
input rst,
input [7:0] sw,
output signal_out
);
reg signal_reg;
reg [31:0] cntFlag;
reg [31:0] cnt;
reg [2:0] flag; //逻辑门选择信号
//实际为7选1选择器，用flag值来快速实现
assign signal_out = (signal_reg & (flag == 0)) //clk_50M分频
| (... | 7.455754 |
module divider_module_1 (
clk,
rst_n,
start_sig,
dividend,
divisor,
done_sig,
quotient,
reminder
);
input clk;
input rst_n;
input start_sig;
input [7:0] dividend;
input [7:0] divisor;
output done_sig;
output [7:0] quotient;
output [7:0] reminder;
/****************... | 6.612016 |
module divider_module_2 (
clk,
rst_n,
start_sig,
dividend,
divisor,
done_sig,
quotient,
reminder
);
input clk;
input rst_n;
input start_sig;
input [7:0] dividend;
input [7:0] divisor;
output done_sig;
output [7:0] quotient;
output [7:0] reminder;
/****************... | 6.612016 |
module divider_module_3 (
input CLK,
input RSTn,
input Start_Sig,
input [7:0] Dividend,
input [7:0] Divisor,
output Done_Sig,
output [7:0] Quotient,
output [7:0] Reminder
);
/*****************************/
reg [3:0] i;
reg [7:0] Dend;
reg [7:0] Dsor;
reg [7:0] Q;
reg [7:0... | 6.612016 |
module divider_module_tb;
reg clk;
reg rst_n;
reg start_sig;
reg [7:0] dividend;
reg [7:0] divisor;
wire done_sig;
wire [7:0] quotient;
wire [7:0] reminder;
// divider_module_1 u1(
// .clk(clk),
// .rst_n(rst_n),
// .start_sig(start_sig),
// .dividend(dividend),
// .divisor(divisor),
//... | 6.612016 |
module Divider_Pipelined_TB ();
parameter divisorBITS = 8;
parameter dividendBITS = 16;
parameter NumTests = 1000;
localparam addBITS = divisorBITS + dividendBITS - 1; // parameterizing
reg [divisorBITS-1:0] divisor;
reg [dividendBITS-1:0] dividend;
reg clock;
wire [dividendBITS-1:0] quotient;
wire ... | 7.094357 |
module divider_restoring #(
parameter WN = 8, // width of N [1]
parameter WD = 6
) // width of D [1]
(
input clk, // system synchronous clock
input [WN-1:0] n_in, // input value n [1]
input [WD-1:0] d_in, // input value d [1]
output [WD-1:0] r_out, // output value r [1]
... | 7.308109 |
module divider_six (
input wire sys_clk, //系统时钟50Mhz
input wire sys_rst_n, //全局复位
output reg clk_out //对系统时钟6分频后的信号
);
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//******************************... | 6.796197 |
module divider_six (
input wire sys_clk, //系统时钟50Mhz
input wire sys_rst_n, //全局复位
output reg clk_flag //指示系统时钟6分频后的脉冲标志信号
);
reg [2:0] cnt; //用于计数的寄存器
//cnt:计数器从0到5循环计数
always @(posedge sys_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) cnt <= 3'b0;
else if (cnt == 3'd5) cnt <= 3'b0;
... | 6.796197 |
module divider_synth #(
parameter FF_NUM = 27
) (
input clk_in,
input RST,
output clk_out
);
wire [(FF_NUM - 1):0] D_in;
wire [(FF_NUM - 1):0] clk_div;
dff dff_0 (
.clk(clk_in),
.RST(RST),
.D (D_in[0]),
.Q (clk_div[0])
);
genvar i;
generate
for (i = 1; i < F... | 7.207044 |
module dff (
input D,
input clk,
input RST,
output reg Q
);
always @(posedge clk or posedge RST) begin
if (RST == 1) begin
Q <= 1'b0;
end else begin
Q <= D;
end
end
endmodule
| 7.174483 |
module divider_tb ();
parameter WIDTH_N = 10;
parameter WIDTH_D = 10;
reg clk, rst, load;
reg [WIDTH_N-1:0] n;
reg [WIDTH_D-1:0] d;
wire [WIDTH_N-1:0] q_a, q_b;
wire [WIDTH_D-1:0] r_a, r_b;
wire ready_a, ready_b;
/////////////////
// radix 4 DUT
/////////////////
divider_rad4 dva (
.cl... | 7.542702 |
module: Divider
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Divider_test;
// Inputs
reg clk;
reg rst;
// Outputs
wire oneHz_enable;
// Instantiate the Unit Under Test (... | 6.759597 |
module test_counter_and_timer ();
reg clk;
reg reset;
wire enable;
wire expire;
reg [3:0] value;
reg start;
initial begin
clk = 0;
forever #19 clk = ~clk;
end
counter testcounter (
.clock (clk),
.reset (reset),
.enable(enable)
);
timer testtimer (
.clock_27mhz(clk... | 6.546598 |
module divider_steve (
Clock,
Resetn,
s,
LA,
EB,
DataA,
DataB,
R,
Q,
Done
);
parameter n = 8, logn = 3;
input Clock, Resetn, s, LA, EB;
input [n-1:0] DataA, DataB;
output [n-1:0] R, Q;
output reg Done;
wire Cout, z, R0;
wire [n-1:0] DataR;
wire [ n:0] Sum;
reg... | 7.390419 |
module regne (
R,
Clock,
Resetn,
E,
Q
);
parameter n = 8;
input [n-1:0] R;
input Clock, Resetn, E;
output reg [n-1:0] Q;
always @(posedge Clock, negedge Resetn)
if (Resetn == 0) Q <= 0;
else if (E) Q <= R;
endmodule
| 6.644365 |
module shiftlne (
R,
L,
E,
w,
Clock,
Q
);
parameter n = 8;
input [n-1:0] R;
input L, E, w, Clock;
output reg [n-1:0] Q;
integer k;
always @(posedge Clock) begin
if (L) Q <= R;
else if (E) begin
Q[0] <= w;
for (k = 1; k < n; k = k + 1) Q[k] <= Q[k-1];
end
en... | 6.932014 |
module downcount (
Clock,
E,
L,
Q
);
parameter n = 4;
input Clock, L, E;
output reg [n-1:0] Q;
always @(posedge Clock)
if (L) Q <= {n{1'b1}};
else if (E) Q <= Q - 1;
endmodule
| 6.742076 |
module mdivider (
reset,
ratio,
remainder,
error,
divisor,
dividend
);
input reset;
input [16:0] divisor; //输入17位除数
input [16:0] dividend; //输入17位被除数
output [16:0] ratio; //输出17位比率
output [16:0] remainder; //输出17位余数
output error; //错误信号
reg [33:0] shift_dividend; //用来移位的34位... | 7.039734 |
module divider_wrapper (
input wire clk,
input wire [63:0] dividend,
input wire [63:0] divisor,
input wire start,
output wire [127:0] result,
output wire result_valid
);
wire start_pulse;
clk_monoflop cmf (
.clk(clk),
.enable(1'b1),
.trigger(start),
.q(start_pulse)
... | 6.956356 |
module divider_wrapper_tb;
parameter MASTER_PERIOD = 10;
// Inputs
wire clk;
clock_gen #(MASTER_PERIOD) mclk (clk);
reg [63:0] dividend;
reg [63:0] divisor;
reg start;
// Outputs
wire [127:0] result;
wire result_valid;
// Instantiate the Unit Under Test (UUT)
divider_wrapper uut (
.clk... | 6.956356 |
module divide (
input [31:0] dividend,
divisor,
output reg [31:0] quotient
);
reg [31:0] m, q;
reg [32:0] a;
integer i;
always @(*) begin
begin
q = dividend;
m = divisor;
a = 0;
for (i = 0; i < 32; i = i + 1) begin
a = {a[30:0], q[31]};
q[31:1] = q[30:0];... | 7.270098 |
module division(clk, dividend, divisor, Q, R, ready);
input clk;
input [15:0] dividend, divisor;
output[15:0] Q, R;
output ready;
reg[31:0] copyDivi, copyDivis, difference;
reg[31:0] bit;
reg [15:0] Q;
assign ready = !bit;
assign remainder = copyDivi[15:0];
initial bit = 0;
always @ (posedge clk)
if (ready)
begin ... | 7.394152 |
module Divide_72562 (
clk,
oclk,
rst
);
input clk;
input rst;
output reg oclk;
reg [15:0] Q;
parameter n = 36281;
//assign oclk=clk;
always @(posedge clk or negedge rst) begin
if (!rst) begin
Q <= 0;
oclk = 0;
end else if (Q == n - 1) begin
Q <= 0;
oclk = ~oclk;... | 7.452713 |
module divide_by_10 (
Clockin,
Clockout
); //Defines clock divide_by_10 module
input Clockin; //Declares Clockin input
output Clockout; //Declares Clockout output
wire clock; //Declares a clock wire
divide_by_2(
Clockin, clock
); //Instantiates the divide_by_2 module, feeds clock wire t... | 6.704062 |
module divide_by_10 (
Clockin,
Clockout
); //Defines clock divide_by_10 module
input Clockin; //Declares Clockin input
output Clockout; //Declares Clockout output
wire clock; //Declares a clock wire
divide_by_2(
Clockin, clock
); //Instantiates the divide_by_2 module, feeds clock wire t... | 6.704062 |
module divide_by_2 (
clk_out,
clk,
rst
);
input clk, rst;
output reg clk_out;
initial begin
clk_out = 0;
end
always @(posedge clk) begin
if (rst) begin
clk_out <= 0;
end else begin
clk_out <= ~clk_out;
end
end
endmodule
| 6.734585 |
module divide_by_2 (
Clockin,
Clockout
); //Defines clock divide_by_2 module
input Clockin; //Declares Clockin input
output Clockout; //Declares Clockout output
reg [2:0] counter1; //Declares 3 bit wide register counter1
wire clkout1; //Declares wire for clkout1
always @(posedge Clockin) begi... | 6.734585 |
module divide_by_3 (
input clk_i, // Input Clock
input rst_i, // Reset
output clk_o // Output Clock
);
wire [2:0] d;
wire [2:0] q;
assign d[0] = ~(q[0] | q[1]);
assign d[1] = q[0];
assign d[2] = q[1];
assign clk_o = q[1] | q[2];
// Positive Edge Triggered DFF 0
dff #(
.EDG... | 6.789167 |
module dff #(
parameter EDGE = "posedge" // posedge, negedge
) (
input clk_i,
input rst_i,
input d_i,
output reg q_o
);
generate
if (EDGE == "posedge") begin
always @(posedge clk_i) begin
if (rst_i) begin
q_o <= 1'b0;
end else begin
q_... | 7.149811 |
module divide_by_5 (
Clockin,
Clockout
); //Defines clock divide_by_5 module
input Clockin; // Declares Clockin input
output Clockout; //Declares Clockout output
reg [2:0] counter1; //Declares 3 bit wide register counter1
reg [2:0] counter2; //Declares 3 bit wide register counter2
wire clkou... | 6.679742 |
module divide_by_5 (
Clockin,
Clockout
); //Defines clock divide_by_5 module
input Clockin; // Declares Clockin input
output Clockout; //Declares Clockout output
reg [2:0] counter1; //Declares 3 bit wide register counter1
reg [2:0] counter2; //Declares 3 bit wide register counter2
wire clkou... | 6.679742 |
module divide_counterTB ();
wire up;
reg i8, i7, i6, i5, i4, i3, i2, i1;
reg down, preset;
wire Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q1;
wire out3;
divide_counter1 divv (
Q1,
i4,
i3,
i2,
i1,
up,
down,
i8,
i7,
i6,
i5,
preset,
Q2,
Q3,... | 6.648417 |
module
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module divide_module(Clk, data_in, reset, enable, textOut... | 7.088073 |
module divide_Newton #(
parameter DSIZE = 24,
PN = 6 //control precision ԽԽС
)(
input clock,
input rst,
input [DSIZE-1:0] N,
input [DSIZE-1:0] D,
input enable,
output[DSIZE+DSIZE-1:0] Q,
output reg[5:0] EXP,
output reg VALID,
output reg RDY
);
reg [DSIZE-1:0] fN;
reg [... | 6.845293 |
module divide_Newton_tb;
reg clock = 0;
reg rst = 0;
always #10 clock = ~clock;
initial begin
rst = 0;
repeat (2) @(posedge clock);
rst = 1;
repeat (2) @(posedge clock);
rst = 0;
end
reg [23:0] dividend = 0;
reg [23:0] divisor = 0;
wire [47:0] QUO;
wire [ 5:0] EXP;
wire RDY, ... | 6.845293 |
module divide_tb ();
reg clk, rst_n;
wire clkout;
initial begin
clk = 0;
rst_n = 0;
#20 rst_n = 1;
end
always #10 clk = ~clk;
divide #(
.WIDTH(3),
.N(5)
) u1 (
.clk(clk),
.rst_n(rst_n),
.clkout(clkout)
);
endmodule
| 6.832897 |
module clkdiv10 (
originalClock,
dividedClock
);
input originalClock;
output dividedClock;
reg [2:0] count;
reg dividedClock;
always @(posedge originalClock) begin
if (count == 3'b100) begin
count <= 3'b000;
end else begin
count <= count + 1;
end
end
always @(posedge cou... | 6.808896 |
module dividor (
clk,
inp,
rst,
out
);
input clk;
input [`INPUT_WIDTH-1:0] inp;
input rst;
//////////////inputs/////////////////
output reg [`INPUT_WIDTH-1:0] out;
//////////////output/////////////////
wire [`INPUT_WIDTH-1:0] DIVISOR = `INPUT_WIDTH'd360;
always @(posedge clk)
... | 7.703792 |
module DFlipFlop (
Q,
data,
clk,
reset
);
input data, clk;
input reset;
output reg Q;
always @(posedge clk) Q <= data;
always @(reset == 1) Q <= 0;
endmodule
| 7.170064 |
module divisible_by_3 (
input a_i, // Bit 3
input b_i, // Bit 2
input c_i, // Bit 1
input d_i, // Bit 0
output y_o // Output
);
wire a_b, b_b, c_b, d_b; // Complemented Inputs
wire [5:0] y; // Partial outputs
// Combinational Logic
// Inverted Inputs
nand nand_0 (a_b, a_i, a_... | 6.660766 |
module divisible_by_3_and_4 (
input a_i, // Bit 3
input b_i, // Bit 2
input c_i, // Bit 1
input d_i, // Bit 0
output y_o // Output
);
wire a_b, b_b; // Complemented Inputs
wire [1:0] y; // Partial outputs
// Combinational Logic
// Inverted Inputs
nor nor_0 (a_b, a_i, a_i);
... | 6.660766 |
module divisible_by_3_and_4_tb ();
// Signal Decleration
reg a_i, b_i, c_i, d_i;
wire y_o;
integer i;
// Instantiation
divisible_by_3_and_4 dut (
.a_i(a_i), // Bit 3
.b_i(b_i), // Bit 2
.c_i(c_i), // Bit 1
.d_i(d_i), // Bit 0
.y_o(y_o) // Output
);
// Logic to dri... | 6.660766 |
module divisible_by_3_tb ();
// Signal Decleration
reg a_i, b_i, c_i, d_i;
wire y_o;
integer i;
// Instantiation
divisible_by_3 dut (
.a_i(a_i), // Bit 3
.b_i(b_i), // Bit 2
.c_i(c_i), // Bit 1
.d_i(d_i), // Bit 0
.y_o(y_o) // Output
);
// Logic to drive inputs an... | 6.660766 |
module based on Newton Raphson method to calculate reciporical of divisor
// then multiply reciporical by Dividend
module division(dividend,divsor,outDiv);
localparam [31:0] one=32'b00111111100000000000000000000000;
input [31:0] dividend ;
input [31:0] divsor;
output [31:0] outDiv;
wire [31:0] reciporical2;
recipori... | 6.932712 |
module Division16 (
A,
B,
Res,
remainder
);
parameter WIDTH = 16;
//input and output ports.
input [WIDTH-1:0] A;
input [WIDTH-1:0] B;
output [WIDTH-1:0] Res;
output reg [WIDTH-1:0] remainder;
//internal variables
reg [WIDTH-1:0] Res = 0;
reg [WIDTH-1:0] a1, b1;
reg [WIDTH:0] p1;... | 7.706341 |
module Division32 (
A,
B,
Res,
remainder
);
parameter WIDTH = 32;
input [WIDTH-1:0] A;
input [WIDTH-1:0] B;
output [WIDTH-1:0] Res;
output reg [WIDTH-1:0] remainder;
reg [WIDTH-1:0] Res = 0;
reg [WIDTH-1:0] a1, b1;
reg [WIDTH:0] p1;
reg [7:0] remainderL;
integer i;
always @(A or ... | 7.337647 |
module division(ready,quotient,dividend,divider,sign,clk);
task division64;
input clk;
input sign;
input [31:0] dividend, divider;
output [31:0] quotient, remainder;
output ready;
reg [31:0] quotient, quotient_temp;
reg [63:0] dividend_copy, divider_copy, diff;
reg negati... | 6.772082 |
module DivisionTestbench ();
// Generiere Eingabe Stimuli
reg clk, s;
wire [31:0] qres;
wire [31:0] rres;
initial begin
s <= 1'b0;
#1;
s <= 1'b1;
#4;
s <= 1'b0;
#160;
$finish;
end
always begin
clk <= 1'b1;
#2;
clk <= 1'b0;
#2;
end
// Module unter Test
... | 7.165134 |
module Division_9bit (
quotient,
remainder,
dividend,
divisor
);
parameter Size = 9;
output reg [Size-1:0] quotient;
output reg [Size-1:0] remainder;
input [Size-1:0] dividend, divisor;
// reg [Size-1:0] a,b;
integer a_digit, b_digit;
integer i;
always @(dividend, divisor) begin
if... | 6.598724 |
module division (
denom,
numer,
quotient,
remain
);
input [31:0] denom;
input [31:0] numer;
output [31:0] quotient;
output [31:0] remain;
endmodule
| 6.685853 |
module full_adder__0_303 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
INV_X1 i_3 (
.A (i_bit1),
.ZN(o_sum)
);
endmodule
| 6.521523 |
module full_adder__0_299 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_carry),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_carry),
.A2(i_bit1),
.ZN(o_c... | 6.521523 |
module full_adder__0_328 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_carry),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_carry),
.A2(i_bit1),
.ZN(o_c... | 6.521523 |
module full_adder__0_49 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_carry),
.Z(o_sum)
);
endmodule
| 6.521523 |
module full_adder__0_72 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XNOR2_X1 i_0_0 (
.A (i_bit2),
.B (i_bit1),
.ZN(o_sum)
);
OR2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_c... | 6.521523 |
module full_adder__0_68 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.B... | 6.521523 |
module full_adder__0_63 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_carr... | 6.521523 |
module full_adder__0_59 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.B... | 6.521523 |
module full_adder__0_92 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XNOR2_X1 i_0_0 (
.A (i_bit2),
.B (i_bit1),
.ZN(o_sum)
);
OR2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_c... | 6.521523 |
module full_adder__0_88 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.B... | 6.521523 |
module full_adder__0_83 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_carr... | 6.521523 |
module full_adder__0_79 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.B... | 6.521523 |
module full_adder__0_112 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XNOR2_X1 i_0_0 (
.A (i_bit2),
.B (i_bit1),
.ZN(o_sum)
);
OR2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_... | 6.521523 |
module full_adder__0_108 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.... | 6.521523 |
module full_adder__0_103 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_car... | 6.521523 |
module full_adder__0_99 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.B... | 6.521523 |
module full_adder__0_132 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XNOR2_X1 i_0_0 (
.A (i_bit2),
.B (i_bit1),
.ZN(o_sum)
);
OR2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_... | 6.521523 |
module full_adder__0_128 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.... | 6.521523 |
module full_adder__0_123 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_car... | 6.521523 |
module full_adder__0_119 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.... | 6.521523 |
module full_adder__0_152 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XNOR2_X1 i_0_0 (
.A (i_bit2),
.B (i_bit1),
.ZN(o_sum)
);
OR2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_... | 6.521523 |
module full_adder__0_148 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.... | 6.521523 |
module full_adder__0_143 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_car... | 6.521523 |
module full_adder__0_139 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.... | 6.521523 |
module full_adder__0_172 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XNOR2_X1 i_0_0 (
.A (i_bit2),
.B (i_bit1),
.ZN(o_sum)
);
OR2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_... | 6.521523 |
module full_adder__0_168 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.... | 6.521523 |
module full_adder__0_163 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_car... | 6.521523 |
module full_adder__0_159 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.... | 6.521523 |
module full_adder__0_192 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XNOR2_X1 i_0_0 (
.A (i_bit2),
.B (i_bit1),
.ZN(o_sum)
);
OR2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_... | 6.521523 |
module full_adder__0_188 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.... | 6.521523 |
module full_adder__0_183 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_car... | 6.521523 |
module full_adder__0_179 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.... | 6.521523 |
module full_adder__0_212 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XNOR2_X1 i_0_0 (
.A (i_bit2),
.B (i_bit1),
.ZN(o_sum)
);
OR2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_... | 6.521523 |
module full_adder__0_208 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.... | 6.521523 |
module full_adder__0_203 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_car... | 6.521523 |
module full_adder__0_199 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.... | 6.521523 |
module full_adder__0_232 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XNOR2_X1 i_0_0 (
.A (i_bit2),
.B (i_bit1),
.ZN(o_sum)
);
OR2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_... | 6.521523 |
module full_adder__0_228 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.... | 6.521523 |
module full_adder__0_223 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(o_sum)
);
AND2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_car... | 6.521523 |
module full_adder__0_219 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
wire n_0_1;
wire n_0_0;
XOR2_X1 i_0_0 (
.A(i_bit1),
.B(i_bit2),
.Z(n_0_1)
);
XOR2_X1 i_0_1 (
.A(n_0_1),
.... | 6.521523 |
module full_adder__0_252 (
i_bit1,
i_bit2,
i_carry,
o_sum,
o_carry
);
input i_bit1;
input i_bit2;
input i_carry;
output o_sum;
output o_carry;
XNOR2_X1 i_0_0 (
.A (i_bit2),
.B (i_bit1),
.ZN(o_sum)
);
OR2_X1 i_0_1 (
.A1(i_bit2),
.A2(i_bit1),
.ZN(o_... | 6.521523 |
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