code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module div100_TB ();
reg clock_TB = 1;
wire clock_div100_TB;
div100 DUT (
.clock_div100(clock_div100_TB), // saidas
.clock(clock_TB)
); // entradas
integer i;
initial begin
$dumpfile("test/div100_TB.vcd");
$dumpvars(0, div100_TB);
for (i = 0; i < 2500; i = i + 1) begin
... | 6.909927 |
module divider(output reg [15:0] q, output [15:0] r, output ready, input [15:0] a,b, input start, clk);
// """"""""|
// 1011 | <---- ta
// -0011 | <---- tb
// """"""""| 0 Diff is negative: copy a and put 0 in q.
// 1011 | <---- ta
// -0011 | <---- tb
// """"""""| 00 Diff is negative: co... | 6.705686 |
module div16a (
ain,
bin,
mod,
iv,
qout,
rout,
ov,
clk,
rst
);
input [15:0] ain, bin; // dividend and divisor input
input mod; // 1=integer remainder, 0=fractional remainder
input iv; // inputs valid
output [15:0] qout; // quotient
output [15:0] rout; // remainder
ou... | 7.136774 |
module div16q16 (
input [15:0] ain,
bin, // dividend and divisor input
input iv, // inputs valid
output [15:0] qout, // quotient
output ov, // quotient and remainder valid
input clk // master clock
);
// Internal signals
wire [15:0] d; // dividend less divisor
wire s; // sig... | 7.109082 |
module div16q24 (
input [15:0] ain,
bin, // dividend and divisor input
input iv, // inputs valid
output [23:0] qout, // quotient (8.16)
output ov, // quotient and remainder valid
input clk // master clock
);
// Internal signals
wire [15:0] d; // dividend less divisor
wire s; ... | 7.281996 |
module div16_8 (
input [15:0] numerator,
input [ 7:0] denominator,
output [15:0] quotient,
output [ 7:0] remainder
);
wire [15:0] numerator;
wire [ 7:0] denominator;
reg [15:0] quotient;
reg [ 7:0] remainder;
reg [ 7:0] remH;
reg [ 7:0] remL;
reg [ 7:0] quotH;
reg [ 7:0] quotL;
... | 7.349033 |
module div_pipelined2 (
clk,
rst,
z,
d,
quot,
rem
);
parameter WIDTH = 32;
localparam ZBITS = WIDTH * 2;
localparam DBITS = ZBITS / 2;
localparam STAGES = DBITS / 2;
input clk;
input rst;
input [WIDTH -1:0] z;
input [DBITS -1:0] d;
output [DBITS -1:0] quot;
output [DBITS -1... | 6.698593 |
module DIV27_19 (
clock,
denom,
numer,
quotient,
remain
);
input clock;
input [34:0] denom;
input [42:0] numer;
output [42:0] quotient;
output [34:0] remain;
wire [42:0] sub_wire0;
wire [34:0] sub_wire1;
wire [42:0] quotient = sub_wire0[42:0];
wire [34:0] remain = sub_wire1[34:0]... | 7.169875 |
module DIV27_19 (
clock,
denom,
numer,
quotient,
remain
);
input clock;
input [34:0] denom;
input [42:0] numer;
output [42:0] quotient;
output [34:0] remain;
endmodule
| 7.169875 |
module div2_negedge (
input reset,
input clk,
output reg div_clk
);
always @(negedge clk or negedge reset) begin
if (~reset) div_clk <= 1'd1;
else div_clk <= ~div_clk;
end
endmodule
| 6.890364 |
module div2_posedge (
input reset,
input clk,
output reg div_clk
);
always @(posedge clk or negedge reset) begin
if (~reset) div_clk <= 1'd1;
else div_clk <= ~div_clk;
end
endmodule
| 7.487586 |
module div3 (
input wire clk_in,
output wire clk_out
);
reg [1:0] divcounter = 0;
//-- Modulus 3 counter
always @(posedge clk_in) begin
divcounter <= (divcounter == 2) ? 0 : divcounter + 1;
end
//Take out MSB
assign clk_out = divcounter[1];
endmodule
| 7.362961 |
module divider(output reg [31:0] q, output [31:0] r, output ready, input [31:0] a,b, input start, clk);
reg [63:0] ta, tb, diff;
reg [5:0] bit;
wire ready = !bit;
initial bit = 0;
assign r = ta[31:0];
always @( posedge clk )
if( ready && start ) begin
bit = 32;... | 6.705686 |
module div3_tb;
reg clk_in = 0;
wire clk_out;
div3 uut (
.clk_in (clk_in),
.clk_out(clk_out)
);
//Clock generator
always #1 clk_in = ~clk_in;
initial begin
$dumpfile("div3_tb.vcd");
$dumpvars;
#30 $display("Simulation finished");
$finish;
end
endmodule
| 6.626191 |
module div4 (
input wire clk,
output wire out_clk
);
reg [1:0] cnt = 0;
always @(posedge clk) cnt <= cnt + 1;
assign out_clk = cnt[1];
endmodule
| 7.311724 |
module DIV5 (
// INPUTS
Clk, // posedge active
rst_n, // negedge active
// OUTPUTS
clk_div, // posedge active
clk_pose, // posedge of clk
clk_nege, // negedge of clk
coutpose, // posedge of counter
coutnege // negedge of counter
);
// N = 5
// div1 ＝ (N - 1) / 2, d... | 8.074393 |
module div64_top (
clk,
rst,
sel,
data_in,
data_out,
done,
err
);
input clk;
input rst;
input sel;
input [7:0] data_in;
output [7:0] data_out;
output done;
output err;
wire [3:0] cnt;
wire [63:0] data_o_a;
wire [63:0] data_o_b;
wire [63:0] yshang;
wire [63:0] yyushu... | 7.61285 |
module div8 (
denom,
numer,
quotient,
remain
);
input [7:0] denom;
input [7:0] numer;
output [7:0] quotient;
output [7:0] remain;
wire [7:0] sub_wire0;
wire [7:0] sub_wire1;
wire [7:0] quotient = sub_wire0[7:0];
wire [7:0] remain = sub_wire1[7:0];
lpm_divide LPM_DIVIDE_component (
... | 6.807209 |
module div84 (
input [7:0] numerator,
input [3:0] denominator,
output [7:0] quotient,
output [3:0] remainder
);
wire [7:0] numerator;
wire [3:0] denominator;
reg [7:0] quotient;
reg [3:0] remainder;
reg [3:0] remH;
reg [3:0] remL;
reg [3:0] quotH;
reg [3:0] quotL;
always @(*) b... | 7.118763 |
module div8 (
denom,
numer,
quotient,
remain
);
input [7:0] denom;
input [7:0] numer;
output [7:0] quotient;
output [7:0] remain;
endmodule
| 6.807209 |
module DivClock (
input CLK,
output CLKOut
);
reg [16:0] counter;
always @(posedge CLK) counter <= counter + 1;
assign CLKOut = counter[16];
endmodule
| 7.163109 |
module divconv (
q,
rega_out,
regb_out,
regc_out,
d,
x,
sel_muxa,
sel_muxb,
load_rega,
load_regb,
load_regc
);
input [7:0] d, x;
input [1:0] sel_muxa, sel_muxb;
input load_rega, load_regb, load_regc;
output [7:0] q, rega_out, regb_out, regc_out;
wire [7:0] muxa_o... | 7.893139 |
module divdec (
input [7:0] alucontrol,
input wire div_ready,
flushM,
output reg div_start,
div_signed,
div_annul
);
always @(*) begin
case (alucontrol)
`EXE_DIV_OP: begin
if (div_ready) {div_start, div_signed, div_annul} = 3'b010;
else {div_start, div_signed, div_an... | 7.159192 |
module DIVDetector (
clk,
instr_in,
instr_src_out,
instr_src_in,
pc_out,
pc_in,
pc_next_out,
pc_next_in,
startCount,
preJump
);
input clk, preJump;
input [31:0] instr_src_in, pc_in, pc_next_in, instr_in;
output reg [31:0] instr_src_out, pc_out, pc_next_out;
output reg st... | 7.091302 |
module diven (
clk,
rst_n,
en1,
diven
);
input clk;
input rst_n;
input en1;
output reg diven;
reg [3:0] counter;
reg enint1 = 0;
reg enint2 = 0;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
enint1 <= 0;
enint2 <= 0;
end else begin
enint1 <= e... | 7.14618 |
module Diverser_16bits (
IN,
OUT
);
input [0:15] IN;
output [15:0] OUT;
assign OUT[0] = IN[0];
assign OUT[1] = IN[1];
assign OUT[2] = IN[2];
assign OUT[3] = IN[3];
assign OUT[4] = IN[4];
assign OUT[5] = IN[5];
assign OUT[6] = IN[6];
assign OUT[7] = IN[7];
assign OUT[8] = IN[8];
... | 6.915437 |
module dff (
output q,
output qnot,
input d,
input clk
);
reg q, qnot;
always @(posedge clk) begin
q <= d;
qnot <= ~d;
end
endmodule
| 7.02102 |
module mux1 (
output [3:0] s,
input [3:0] i0,
input [3:0] i1,
input key
);
reg [3:0] s;
always @(key or i1 or i0) begin
if (~key) begin
s = i0;
end else begin
s = i1;
end
end
endmodule
| 6.95677 |
module ram2x4 (
output [3:0] s,
input [3:0] e,
input clock,
input rw,
input addr,
input clear
);
reg demuxE;
wire w0, w1;
wire [3:0] aux0;
wire [3:0] aux1;
dmux1 DX1 (
w0,
w1,
demuxE,
addr
);
ram1x4 RAM1 (
aux0,
e,
clock,
rw,
w... | 6.763999 |
module ram1x8 (
output [7:0] s,
input [7:0] e,
input clock,
input rw,
input addr,
input clear
);
ram1x4 RAM1 (
s[3:0],
e[3:0],
clock,
rw,
addr,
clear
);
ram1x4 RAM2 (
s[7:4],
e[7:4],
clock,
rw,
addr,
clear
);
endmo... | 6.890243 |
module mux2 (
output [7:0] s,
input [7:0] i0,
input [7:0] i1,
input [7:0] i2,
input [7:0] i3,
input [1:0] key
);
reg [7:0] s;
always @(key or i0 or i1 or i2 or i3) begin
if (key == 0) s = i0;
else if (key == 1) s = i1;
else if (key == 2) s = i2;
else if (key == 3) s = i... | 6.762042 |
module mux3 (
output [7:0] s,
input [7:0] i0,
input [7:0] i1,
input [7:0] i2,
input [7:0] i3,
input [7:0] i4,
input [7:0] i5,
input [7:0] i6,
input [7:0] i7,
input [2:0] key
);
reg [7:0] s;
always @(key or i0 or i1 or i2 or i3 or i4 or i5 or i6 or i7) begin
if ... | 7.29964 |
module DivFrec (
clk,
rst,
div,
clkd,
clk_1kHz
);
input wire clk, rst;
input wire [6:0] div;
output wire clkd;
output wire clk_1kHz;
reg [6:0] q = 0;
reg cd = 0;
reg [15:0] q_1kHz = 0;
reg cd_1kHz = 0;
/*reg [5:0]q_sincronizacion = 0;
reg cd_sincronizacion = 0;*/
// Para genera... | 6.646094 |
module: DivFrec
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module DivFrec_tb;
// Inputs
reg clk;
reg rst;
reg [15:0] div;
// Outputs
wire clkd;
// Instantiate the Unit Under T... | 7.590808 |
module divfreq (
clk,
clk1hz
);
input clk;
output reg clk1hz = 0;
reg [27:0] count = 0;
always @(posedge clk) begin
if (count < 'd5_000_000) begin
count = count + 1;
end else begin
count = 0;
clk1hz = !clk1hz;
end
end
endmodule
| 6.846501 |
module divfreq_faster (
input clk,
output reg freq
);
integer cont;
parameter lim = 1200000;
initial begin
cont = 0;
freq = 0;
end
always @(posedge clk) begin
if (cont < lim) cont = cont + 1;
else begin
cont = 0;
freq = ~freq;
end
end
endmodule
| 7.773317 |
module divfunc
#(
parameter XLEN = 32,
parameter `N(XLEN) STAGE_LIST = 0
)
(
input clk,
input rst,
input `N(XLEN) a,
input `N(XLEN) b,
input vld,
output `N(XLEN) quo,
output `N(XLEN) ... | 7.216192 |
module divi (
input clk,
input enable,
output reg clkout
);
reg [25:0] cnt;
always @(posedge clk) begin
if (enable == 1) begin
cnt = cnt + 1;
end
//if (cnt==26'b00000110101111000010000000)
if (cnt==26'b00000000000000000000010100) // faster clock ftw
begin
... | 6.608124 |
module divide (
counter,
tens,
ones
);
wire _00_;
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
wire _11_;
wire _12_;
wire _13_;
wire _14_;
wire _15_;
wire _16_;
wire _17_;
wire _18_;
wire _19_;
wire _2... | 7.270098 |
module divide (
input clk,
input sign,
input [15:0] dividend,
input [15:0] divider,
output done,
output reg [15:0] quotient,
output [15:0] remainder
);
reg [15:0] quotient_temp;
reg [31:0] dividend_copy, divider_copy, diff;
reg negative_output;
assign remainder = (!negative_output)... | 7.270098 |
module divide10 (
quotient,
remainder,
ready,
clk,
rst,
start,
value
);
output reg [9:0] quotient;
output [3:0] remainder;
output ready;
input clk, rst, start;
input [13:0] value;
reg [13:0] dividend;
reg [13:0] divisor;
reg run;
assign ready = divisor[0];
as... | 6.689064 |
module Divide16 (
clock,
denom,
numer,
quotient,
remain
);
input clock;
input [9:0] denom;
input [15:0] numer;
output [15:0] quotient;
output [9:0] remain;
wire [15:0] sub_wire0;
wire [ 9:0] sub_wire1;
wire [15:0] quotient = sub_wire0[15:0];
wire [ 9:0] remain = sub_wire1[9:0];
... | 7.025009 |
module Divide16 (
clock,
denom,
numer,
quotient,
remain
);
input clock;
input [9:0] denom;
input [15:0] numer;
output [15:0] quotient;
output [9:0] remain;
endmodule
| 7.025009 |
module divide2 (
denom,
numer,
quotient,
remain
);
input [11:0] denom;
input [15:0] numer;
output [15:0] quotient;
output [11:0] remain;
wire [15:0] sub_wire0;
wire [11:0] sub_wire1;
wire [15:0] quotient = sub_wire0[15:0];
wire [11:0] remain = sub_wire1[11:0];
lpm_divide LPM_DIVIDE_... | 7.336527 |
module divide32_unsigned_restoring_remainder (
quotient,
remainder,
ready,
busy,
count,
dividend,
divisor,
start,
clock,
reset
);
input reset;
// in simulation, use reset negedge to initialize the state registers of division server(count, busy, busy2).
// the negedge reset ... | 7.33148 |
module divide4 (
quotient,
Sum,
Carry,
op1,
op2,
clk,
state0
);
input [7:0] op1, op2;
input clk, state0;
output [3:0] quotient;
output [10:0] Sum, Carry;
wire [7:0] qtotal;
wire [10:0] SumN, CarryN, SumN2, CarryN2;
wire [10:0] divi1, divi2, divi1c, divi2c, dive1;
wire [10:... | 7.171041 |
module divideby8 (
input [`DATA_WIDTH-1:0] data,
output reg [`DATA_WIDTH-1:0] out
);
reg [`DATA_WIDTH-1:0] mask;
always @(*) begin
if (data[`DATA_WIDTH-1] == 1) mask = 16'b1110000000000000;
else mask = 0;
out = mask | (data >> 3);
end
endmodule
| 7.698216 |
module divideByFifty #(
parameter N = 50,
parameter M = 8
) (
input CLK,
CLEAR,
output reg [M-1:0] COUNT,
// COUNT is defined as a M-bit register
output reg OUT
);
always @(negedge CLK, negedge CLEAR)
if (CLEAR == 1'b0) COUNT <= 0;
// COUNT is loaded with all 0's
else begin
... | 8.158494 |
module divideByFive #(
parameter N = 5,
parameter M = 3
) (
input CLK,
CLEAR,
output reg [M-1:0] COUNT,
// COUNT is defined as a M-bit register
output reg OUT
);
always @(negedge CLK, negedge CLEAR)
if (CLEAR == 1'b0) COUNT <= 0;
// COUNT is loaded with all 0's
else begin
... | 8.208589 |
module divideBySix #(
parameter N = 6,
parameter M = 3
) (
input CLK,
CLEAR,
output reg [M-1:0] COUNT,
// COUNT is defined as a M-bit register
output reg OUT
);
always @(negedge CLK, negedge CLEAR)
if (CLEAR == 1'b0) COUNT <= 0;
// COUNT is loaded with all 0's
else begin
... | 7.746258 |
module divideByTen #(
parameter N = 10,
parameter M = 8
) (
input CLK,
CLEAR,
output reg [M-1:0] COUNT,
// COUNT is defined as a M-bit register
output reg OUT
);
always @(negedge CLK, negedge CLEAR)
if (CLEAR == 1'b0) COUNT <= 0;
// COUNT is loaded with all 0's
else begin
... | 8.027796 |
module DivideClk (
input clk,
input rst,
output reg clock
);
parameter period = 1000;
reg [19:0] cnt;
always @(posedge clk) begin
if (rst) begin
cnt <= 0;
clock <= 0;
end else begin
if (cnt == ((period >> 1) - 1)) begin
clock <= ~clock;
cnt <= 0;
en... | 6.881565 |
module clock_divider #(
parameter CLK_FREQUENCY = 50000000,
parameter BAUD_RATE = 50000000
) (
input i_clock,
output o_divided_clock
);
integer clks_per_bit = CLK_FREQUENCY / BAUD_RATE;
integer counter = 1;
reg divided_clock = 0;
always @(posedge i_clock)
if (counter == clks_per_bit) beg... | 6.818038 |
module Divider (
A,
B,
Res,
remainder
);
//the size of input and output ports of the division module is generic.
parameter WIDTH = 16;
//input and output ports.
input [WIDTH-1:0] A;
input [WIDTH-1:0] B;
output [WIDTH-1:0] Res;
output reg [WIDTH-1:0] remainder;
//internal variables
... | 7.440694 |
module Divider (
input clk,
run,
output stall,
input [31:0] x,
y, // x >= 0, y > 0
output [31:0] quot,
rem
);
reg [4:0] S; // state
reg [31:0] R, Q;
wire [31:0] r0, r1, r2, q0, q1, d;
assign stall = run & ~(S == 31);
assign r0 = (S == 0) ? 0 : R;
assign d = r1 - y;
assign r... | 7.440694 |
module divider1 (
aclr,
clken,
clock,
denom,
numer,
quotient,
remain
);
input aclr;
input clken;
input clock;
input [7:0] denom;
input [13:0] numer;
output [13:0] quotient;
output [7:0] remain;
wire [13:0] sub_wire0;
wire [ 7:0] sub_wire1;
wire [13:0] quotient = sub_wir... | 7.259919 |
module divider10 (
input clk,
input start,
input [9:0] dividend,
input [9:0] divider,
output ready,
output [9:0] quotient,
output [9:0] remainder
);
reg [19:0] qr;
reg [10:0] diff;
assign remainder = qr[19:10];
assign quotient = qr[9:0];
reg [3:0] counter;
assign ready = (c... | 6.849037 |
module Divider100MHz (
CP_100MHz,
nCLR,
CP_1Hz
);
parameter N = 26;
parameter CLK_Freq = 100000000;
parameter OUT_Freq = 1;
input nCLR, CP_100MHz;
output reg CP_1Hz;
reg [N - 1:0] Count_DIV;
always @(posedge CP_100MHz or negedge nCLR) begin
if (!nCLR) begin // 첽
CP_1Hz <= 0;
C... | 7.183203 |
module Divider16t (
input clk,
input rst,
input en,
input [31:0] divident,
input [31:0] divisor,
output [31:0] quotient,
output [31:0] remainder,
output reg div0,
output done
);
parameter kDivFree = 2'b00, kDi... | 7.401055 |
module divider1 (
aclr,
clken,
clock,
denom,
numer,
quotient,
remain
);
input aclr;
input clken;
input clock;
input [7:0] denom;
input [13:0] numer;
output [13:0] quotient;
output [7:0] remain;
endmodule
| 7.259919 |
module divider2 (
aclr,
clken,
clock,
denom,
numer,
quotient,
remain
);
input aclr;
input clken;
input clock;
input [7:0] denom;
input [15:0] numer;
output [15:0] quotient;
output [7:0] remain;
wire [15:0] sub_wire0;
wire [ 7:0] sub_wire1;
wire [15:0] quotient = sub_wir... | 7.481668 |
module divider2 (
aclr,
clken,
clock,
denom,
numer,
quotient,
remain
);
input aclr;
input clken;
input clock;
input [7:0] denom;
input [15:0] numer;
output [15:0] quotient;
output [7:0] remain;
endmodule
| 7.481668 |
module divider32_tb;
// Inputs
reg clk;
reg sync_rst;
reg valid;
reg signed [31:0] DIVIDEND;
reg signed [31:0] DIVISOR;
// Outputs
wire [31:0] Q;
wire [31:0] R;
wire ready;
// Instantiate the Unit Under Test (UUT)
divider32 uut (
.clk(clk),
.sync_rst(sync_rst),
.valid(valid)... | 6.6124 |
module Divider4 (
clk,
oclk,
rst
);
input clk;
input rst;
output reg oclk;
reg [1:0] Q;
parameter n = 2;
//assign oclk=clk;
always @(posedge clk or negedge rst) begin
if (!rst) begin
Q <= 0;
oclk = 0;
end else if (Q == n - 1) begin
Q <= 0;
oclk = ~oclk;
end... | 6.649878 |
module Divider50MHz (
CLK_50M,
nCLR,
CLK_1HzOut
); //1HZ
parameter N = 26;
parameter CLK_Freq = 100000000;
parameter OUT_Freq = 1;
input CLK_50M, nCLR;
output reg CLK_1HzOut;
reg [N-1:0] Cout_DIV;
always @(posedge CLK_50M or negedge nCLR) begin
if (!nCLR) begin
CLK_1HzOut <= 0;
... | 7.148963 |
module Divider50MHzAvoid (
CLK_50M,
nCLR,
CLK_1HzOut
); //1HZ
parameter N = 26;
parameter CLK_Freq = 100000000;
parameter OUT_Freq = 1;
input CLK_50M, nCLR;
output reg CLK_1HzOut;
reg [N-1:0] Cout_DIV;
always @(posedge CLK_50M or negedge nCLR) begin
if (!nCLR) begin
CLK_1HzOut <= 0... | 7.030355 |
module Divider_tb ();
reg I_CLK;
reg Rst;
wire O_CLK;
Divider uut (
.I_CLK(I_CLK),
.Rst (Rst),
.O_CLK(O_CLK)
);
initial begin
I_CLK = 1'b0;
forever #5 I_CLK = ~I_CLK;
end
initial begin
Rst = 1'b1;
#20 Rst = 1'b0;
end
endmodule
| 7.311619 |
module DividerControl (
clk,
startCount,
SignaltoDIV
);
input clk, startCount;
output reg [5:0] SignaltoDIV;
reg [5:0] temp;
reg [6:0] counter;
always @(startCount) begin
if (startCount == 1) counter = 0;
end
always @(posedge clk) begin
if (startCount == 1) begin
temp = 6'd27;... | 6.836013 |
module dividerp1 (
input wire clk,
input wire [17:0] pos,
input wire timer_ena,
output wire clk_out
);
//-- Valor por defecto de la velocidad en baudios
parameter M = `T_20ms;
//-- Numero de bits para almacenar el divisor de baudios
parameter N = 18;
//-- Registro para implementar el contad... | 7.312235 |
module DIVIDERS (
CLK,
RESET,
LED
);
input CLK;
input RESET;
output [7:0] LED;
wire [ 7:0] LED;
reg [28:0] DIVIDER;
//DIVIDER
always @(posedge CLK or negedge RESET) begin
if (!RESET) DIVIDER <= {28'h0000000, 1'b0};
else DIVIDER <= DIVIDER + 1'b1;
end
assign LED[0] = DIVIDER[21]... | 6.533273 |
module Divider_100 (
clk,
rst,
oclk
);
input clk;
input rst;
output reg oclk;
reg [8:0] Q;
parameter n = 50;
//assign oclk=clk;
always @(posedge clk or negedge rst) begin
if (!rst) begin
Q <= 0;
oclk <= 0;
end else if (Q == n - 1) begin
Q <= 0;
oclk <= ~oclk;
... | 6.705056 |
module divider_120k (
input clk_in, // 24MHz
output reg clk_out = 1'd0
); // 200Hz
// 功能：把 24MHz 的时钟分频 12k 倍，输出 200Hz 的时钟
reg [15:0] counter = 'd0;
always @(posedge clk_in) begin
if (counter < 'd59999) begin
counter = counter + 1;
end else begin
counter = 'd0;
cl... | 7.283692 |
module divider_120k_tb ();
// 输入
reg clk_in;
// 输出
wire clk_out;
// 例化待测模块
divider_120k uut_divider (
.clk_in (clk_in),
.clk_out(clk_out)
);
// 描述输入信号
initial begin
clk_in = 0;
repeat (1000000) #10 clk_in = ~clk_in;
end
endmodule
| 6.783054 |
module divider (
input enable,
clk,
reset_n,
accept_in,
output accept_out,
ready_out,
//
input [15:0] Q,
M,
output [15:0] quot
);
//xử lý bit dấu
assign quot[15] = Q[15] ^ M[15];
/*
còn 15 bit cần phải xử lý, mà phần thập phân có 12 bit. suy ra cần dịch trái dividend 12 bit... | 7.389371 |
module DIVIDER_1HZ (
CLK,
RESET,
LED
);
input CLK;
input RESET;
output [7:0] LED;
reg [7:0] LED;
integer DIVIDER;
//40MHZ FREQUENCY
always @(posedge CLK or negedge RESET) begin
if (!RESET) DIVIDER <= 0;
else begin
if (DIVIDER == 39999999) DIVIDER <= 0;
else DIVIDER <= DIV... | 7.92567 |
module divider_1kHz (
input clk,
output clk_out
);
//Ƶ1000Hz,ˢʾ
reg [19:0] cnt;
reg clk_out;
always @(posedge clk) begin
if (cnt == 20'd999_99) cnt <= 20'd0;
else cnt <= cnt + 20'd1;
end
always @(posedge clk)
if (cnt < 20'd500_00) begin
clk_out <= 1'b1;
end else begin
... | 6.965976 |
module divider_2 (
clock,
reset,
datain,
dataout
);
input clock;
input reset;
input [10:0] datain;
output [9:0] dataout;
reg [10:0] Q;
integer i;
always @(posedge clock)
if (reset) Q <= 10'b0;
else begin
for (i = 0; i < 10; i = i + 1) Q[i] <= datain[i+1];
Q[10] <= 1'... | 6.510005 |
module Divider_25MHZ (
input I_CLK,
input rst,
output reg O_CLK
);
integer i = 0;
parameter num = 2;
always @(posedge I_CLK) begin
if (rst == 1) begin
O_CLK <= 0;
i <= 0;
end else begin
if (i == num - 1) begin
O_CLK <= ~O_CLK;
i <= 0;
end//end reset num
... | 7.895383 |
module Divider_2kHZ (
input I_CLK,
input rst,
output reg O_CLK
);
integer i = 0;
parameter num = 50000;
always @(posedge I_CLK) begin
if (rst == 1) begin
O_CLK = 0;
i = 0;
end else begin
if (i == num - 1) begin
O_CLK = ~O_CLK;
i = 0;
end//end reset num
... | 7.455442 |
module divider_2over1 (
input enable,
clk,
reset_n,
accept_in,
output accept_out,
ready_out,
//
input [63:0] vec,
input [31:0] el,
output [63:0] res
);
wire [1:0] accept_outs, ready_outs;
assign accept_out = (accept_outs == 2'b11);
assign ready_out = (ready_outs == 2'b11)... | 7.439679 |
module divider_32 (
input clk,
input start,
input reset,
input [31:0] dividend,
input [31:0] divisor,
output rdy,
output [63:0] div_out
);
wire [31:0] Q32;
//DividerBlock Signals
wire A;
wire [31:0] Rin, Rout, R;
wire Q;
//Control Signals
wire [4:0] mux_A_sel;
wire mux_Rin... | 6.990163 |
module div_array (
input [31:0] a,
input [31:0] b,
output [31:0] r,
output q
);
wire [32:0] r_temp;
wire q_temp;
assign r_temp = a - b;
assign q_temp = ~r_temp[32];
assign r = q_temp ? r_temp[31:0] : a;
assign q = q_temp;
endmodule
| 7.911489 |
module div_block (
input A,
input [31:0] B,
input [31:0] Rin,
output [31:0] Rout,
output Q
);
div_array row_0 (
{Rin[30:0], A},
B,
Rout,
Q
);
endmodule
| 7.930013 |
module div_control (
input start,
input clk,
input reset,
output reg [4:0] mux_A_sel,
output reg mux_Rin_sel,
output reg reg_Rin_en,
output reg reg_Q_en,
output reg rdy
);
parameter R1 = 1'b0, Rounds = 1'b1;
reg current_state;
reg next_state;
reg [4:0] round_count;
reg start_... | 7.499706 |
module divider_4 (
input clkin,
output reg clkout
);
reg [1:0] cnt = 0;
initial begin
clkout = 0;
end
always @(posedge clkin) begin
if (cnt < 2) begin
clkout <= 1;
cnt <= 0;
end else begin
clkout <= 0;
end
cnt <= cnt + 1;
end
endmodule
| 7.143281 |
module Divider_8Bit (
//define inputs
input _clk,
_reset,
_start,
input [7:0] _dataInA,
_dataInB,
//define outputs
output _doneOut,
_errorOut,
output [7:0] _quotientOut,
_remainderOut
);
wire [7:0] _count;
wire _clearOut, _loadAOut, _loadBOut, _countUpOut, _holdAOut, _... | 6.660931 |
module divider_4over1 (
input enable,
clk,
reset_n,
accept_in,
output accept_out,
ready_out,
//
input [127:0] vec,
input [31:0] el,
output [127:0] res
);
wire [3:0] accept_outs, ready_outs;
assign accept_out = (accept_outs == 4'b1111);
assign ready_out = (ready_outs == 4'... | 8.141307 |
module tb_divider_8bit ();
wire [7:0] quotient, remainder;
wire eop;
reg [7:0] divisor, dividend;
reg clk, rst;
divider_8bit uut (
quotient,
remainder,
eop,
divisor,
dividend,
clk,
rst
);
initial begin
#0 clk = 1'b0;
forever #10 clk = ~clk;
end
ini... | 7.482939 |
module divider_8bit (
quotient,
remainder,
eop,
divisor,
dividend,
clk,
rst
);
output reg [7:0] quotient, remainder;
output reg eop;
input wire [7:0] divisor, dividend;
input wire clk, rst;
reg [7:0] divd;
//Negative Edge Triggered Clock and Active High Asynchronous Reset
//C... | 7.829322 |
module divider_async (
quotient,
remainder,
ready,
dividend,
divider,
start,
clk,
rst
);
input [15:0] dividend, divider;
input start, clk, rst;
output quotient, remainder;
output ready;
// """"""""|
// 1011 | <---- dividend_copy
// -0011 | <---- divider_copy
... | 7.651525 |
module: divider_async
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module divider_async_tb;
// Inputs
reg [15:0] dividend;
reg [15:0] divider;
reg start;
reg clk;
reg rst;
// Ou... | 7.523087 |
module divider (
aclr,
clken,
clock,
denom,
numer,
quotient,
remain
);
input aclr;
input clken;
input clock;
input [31:0] denom;
input [31:0] numer;
output [31:0] quotient;
output [31:0] remain;
endmodule
| 7.389371 |
module divider_by_2 (
input i_CLK,
input i_RSTN,
output reg o_CLK_DIV_2
);
// After reset, starting with same rising edge with skew
always @(posedge i_CLK, negedge i_RSTN) begin
if (!i_RSTN) o_CLK_DIV_2 <= 1'b0;
else o_CLK_DIV_2 <= ~o_CLK_DIV_2;
end
endmodule
| 7.285242 |
module divider_cell #(
parameter N = 5,
parameter M = 3
) (
input clk,
input rstn,
input en,
input [ M:0] dividend,
input [ M-1:0] divisor,
input [ N-M:0] merchant_ci, //merchant info from last cell
input [N-M-1:0] dividend_ci, //original dividend remained
output reg [N-... | 7.5468 |
module div_2 (
in_clk,
out_clk
);
input in_clk;
output out_clk;
reg tmp;
always @(posedge in_clk) begin
tmp = ~tmp;
end
assign out_clk = tmp;
endmodule
| 7.005999 |
module Divider_instr (
input I_CLK,
input Rst,
output reg O_CLK
);
reg [27:0] cnt;
parameter N = 50000000;
always @(posedge I_CLK) begin
if (Rst) begin
cnt <= 0;
O_CLK <= 0;
end else begin
if (cnt == N / 2 - 1) begin
O_CLK <= !O_CLK;
cnt <= 0;
end el... | 7.38107 |
module divider_conv_filter (
clock,
denom,
numer,
quotient,
remain
);
input clock;
input [4:0] denom;
input [15:0] numer;
output [15:0] quotient;
output [4:0] remain;
wire [15:0] sub_wire0;
wire [ 4:0] sub_wire1;
wire [15:0] quotient = sub_wire0[15:0];
wire [ 4:0] remain = sub_wi... | 7.522142 |
module divider_five (
input wire sys_clk, //系统时钟50Mhz
input wire sys_rst_n, //全局复位
output wire clk_out //对系统时钟5分频后的信号
);
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//****************************... | 6.644118 |
module divider_five (
input wire sys_clk, //系统时钟50Mhz
input wire sys_rst_n, //全局复位
output reg clk_flag //指示系统时钟5分频后的脉冲标志信号
);
reg [2:0] cnt; //用于计数的寄存器
//cnt:计数器从0到4循环计数
always @(posedge sys_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) cnt <= 3'b0;
else if (cnt == 3'd4) cnt <= 3'b0;... | 6.644118 |
module divider_integer #(
parameter WIDTH = 24,
parameter N = 12000000
) (
input clk,
output reg clkout
);
reg [WIDTH-1:0] cnt;
always @(posedge clk) begin
if (cnt >= (N - 1)) cnt <= 1'b0;
else cnt <= cnt + 1'b1;
clkout <= (cnt < N / 2) ? 1'b1 : 1'b0;
end
endmodule
| 6.687714 |
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