code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module etc_address_generator (
sclk,
rsrt,
addr_rtr,
// input
blockX,
blockY,
pixIdx,
width,
// output
out_addr,
addr_valid
);
input sclk;
input rsrt;
input addr_rtr;
// input
input [7:0] blockY;
input [7:0] blockX;
input [10:0] width;
input [3 : 0] pixIdx... | 7.315775 |
module etc_plannar_decoder (
sclk,
rsrt,
// input
rtr,
mode,
block,
aplha,
pixIdx,
// output
color_rts,
r,
g,
b,
a
);
input sclk;
input rsrt;
// input
input rtr;
input aplha;
input [3 : 0] pixIdx;
input [63:0] block;
input [0 : 2] mode;
// ou... | 6.659884 |
module WishboneRegs (
input clk,
input rst,
input [ADDRESS_WIDTH-1:0] wbAdrI,
input [DATA_WIDTH-1:0] wbDatI,
output reg [DATA_WIDTH-1:0] wbDatO,
input wbStbI,
input wbCycI,
input wbWeI,
output wbAckO
);
parameter ADDRESS_WIDTH = 16;
parameter DATA_WIDTH = 16;
localparam MEMORY... | 7.823512 |
module generic_mem_small (
wclk,
wrst_n,
wen,
waddr,
wdata,
rclk,
rrst_n,
ren,
roen,
raddr,
rdata
);
parameter DWIDTH = 32;
parameter AWIDTH = 3;
parameter RAM_DEPTH = (1 << AWIDTH);
parameter REGISTER_READ = 0;
input wclk;
input wrst_n;
input wen;
input [(AWI... | 8.080441 |
module generic_mem_medium (
wclk,
wrst_n,
wen,
waddr,
wdata,
rclk,
rrst_n,
ren,
roen,
raddr,
rdata
);
parameter DWIDTH = 32;
parameter AWIDTH = 3;
parameter RAM_DEPTH = (1 << AWIDTH);
parameter REGISTER_READ = 0;
input wclk;
input wrst_n;
input wen;
input [(AW... | 7.571094 |
module generic_fifo_ctrl (
wclk,
wrst_n,
wen,
wfull,
walmost_full,
mem_wen,
mem_waddr,
rclk,
rrst_n,
ren,
rempty,
ralmost_empty,
mem_ren,
mem_raddr
);
parameter AWIDTH = 3;
parameter RAM_DEPTH = (1 << AWIDTH);
parameter EARLY_READ = 0;
parameter CLOCK_CROS... | 6.701278 |
module generic_fifo (
wclk,
wrst_n,
wen,
wdata,
wfull,
walmost_full,
rclk,
rrst_n,
ren,
rdata,
rempty,
ralmost_empty
);
parameter DWIDTH = 32;
parameter AWIDTH = 3;
parameter RAM_DEPTH = (1 << AWIDTH);
parameter REGISTER_READ = 0;
parameter EARLY_READ = 0;
par... | 7.803344 |
module meta_sync (
out,
clk,
reset_n,
in
);
parameter DWIDTH = 1;
parameter EDGE_DETECT = 0;
input clk;
input reset_n;
input [(DWIDTH - 1):0] in;
output [(DWIDTH - 1):0] out;
genvar i;
for (i = 0; (i < DWIDTH); i = (i + 1)) begin : meta
meta_sync_single #(
.EDGE_DETECT(EDGE... | 6.780599 |
module sync_clk_wb (
status_crc_error,
status_fragment_error,
status_lenght_error,
status_txdfifo_ovflow,
status_txdfifo_udflow,
status_rxdfifo_ovflow,
status_rxdfifo_udflow,
status_pause_frame_rx,
status_local_fault,
status_remote_fault,
wb_clk_i,
wb_rst_i,
status_cr... | 6.854147 |
module sync_clk_xgmii_tx (
ctrl_tx_enable_ctx,
status_local_fault_ctx,
status_remote_fault_ctx,
clk_xgmii_tx,
reset_xgmii_tx_n,
ctrl_tx_enable,
status_local_fault_crx,
status_remote_fault_crx
);
input clk_xgmii_tx;
input reset_xgmii_tx_n;
input ctrl_tx_enable;
input status_local_... | 7.832497 |
module tx_stats_fifo (
txsfifo_rdata,
txsfifo_rempty,
clk_xgmii_tx,
reset_xgmii_tx_n,
wb_clk_i,
wb_rst_i,
txsfifo_wdata,
txsfifo_wen
);
input clk_xgmii_tx;
input reset_xgmii_tx_n;
input wb_clk_i;
input wb_rst_i;
input [13:0] txsfifo_wdata;
input txsfifo_wen;
output [13:0] t... | 6.984053 |
module stats_sm (
stats_tx_octets,
stats_tx_pkts,
stats_rx_octets,
stats_rx_pkts,
wb_clk_i,
wb_rst_i,
txsfifo_rdata,
txsfifo_rempty,
rxsfifo_rdata,
rxsfifo_rempty,
clear_stats_tx_octets,
clear_stats_tx_pkts,
clear_stats_rx_octets,
clear_stats_rx_pkts
);
input wb... | 7.586322 |
module eth1g_transmitter (
input clk
, input rst_n
);
mac_head_transmitter mac_head_transmitter (
.clk (clk)
, .rst_n(rst_n)
//control signals
, .mac_start()
//packet parameters
, .mac_src_addr() //i48
, .mac_dst_addr() //i48
, .mac_type () //i... | 6.862759 |
module ether_send (
rst,
clk_50mhz,
crs_dv_phy,
buf_data,
txen_mac,
buf_len,
txd_phy,
buf_addr,
txen_phy,
ready
);
input wire rst;
input wire clk_50mhz;
input wire crs_dv_phy;
input wire [7:0] buf_data;
input wire txen_mac;
input wire [11:0] buf_len;
output wire [1:... | 7.553814 |
module xilinx_simple_dual_port_2_clock_ram #(
parameter RAM_WIDTH = 36, // Specify RAM data width
parameter RAM_DEPTH = 512, // Specify RAM depth (number of entries)
parameter RAM_PERFORMANCE = "HIGH_PERFORMANCE", // Select "HIGH_PERFORMANCE" or "LOW_LATENCY"
parameter INIT_FILE = "" ... | 9.367668 |
module mac_tx_v1_0_M00_AXI #(
parameter C_M_TARGET_SLAVE_BASE_ADDR = 32'h40000000,
parameter integer C_M_AXI_BURST_LEN = 256,
parameter integer C_M_AXI_ID_WIDTH = 1,
parameter integer C_M_AXI_ADDR_WIDTH = 32,
parameter integer C_M_AXI_DATA_WIDTH = 64,
parameter integer C_M_AXI_ARUSER_WIDTH = 1
)... | 8.61394 |
module main (
clk
);
input clk;
wire fin_bt0, fin_bt1, CS, llc_ack0, llc_ack1,
frame_ready0, frame_ready1, CD, send_plr0, send_plr1;
wire [0:1] ack0, ack1;
wire [0:1] in0, in1, bt0, bt1, send_pls0, send_pls1, chnl_data_in, chnl_data_out0, chnl_data_out1;
wire req0, req1;
// additions by hi... | 7.779865 |
module BitTransmitter (
clk,
send_bt,
finished_bt,
send_pls
);
input clk;
input [0:1] send_bt;
output [0:1] send_pls;
output finished_bt;
wire finished_bt;
wire [0:1] send_pls, send_bt;
reg [0:1] sendpls;
reg finishedbt;
assign send_pls = sendpls;
assign finished_bt = finishedbt;... | 6.566127 |
module FrameTransmitter(clk, llc_f_ready, okay, send_bt, finished_bt, CS, CD);
input clk;
input llc_f_ready, finished_bt, CS, CD;
output [0:1] okay, send_bt;
wire finished_bt, CS, CD;
wire [0:1] okay;
wire [0:1] send_bt;
wire llc_f_ready;
reg [0:1] sendbt;
reg [0:1] oka;
assign send_bt = sendbt;
assign okay = oka;
... | 6.53189 |
module PLR (
clk,
send_next_bit,
send_FR_signal,
channel
);
input clk;
input send_next_bit;
input [0:1] channel;
output [0:1] send_FR_signal;
wire [0:1] channel, send_FR_signal, connect;
wire send_next_bit;
reg [0:1] channel_receive_data;
reg [0:1] receive_to_FR;
assign connect ... | 6.590543 |
module CHNL (
clk,
data_in_1,
data_in_2,
carrier_sense,
collision_detect,
data_out
);
input clk;
input [0:1] data_in_1, data_in_2;
output [0:1] data_out;
output carrier_sense, collision_detect;
wire [0:1] data_in_1, data_in_2, data_out;
wire carrier_sense, collision_detect;
reg c... | 6.785821 |
module provided full functions
`include "common.v"
module EthernetModule(reset, clk_10K,
ff_clk, ff_en_source, ff_en_sink, ff_data_source, ff_data_sink, //ff_clk should be a 270.33KHz clock
phy_rxd, phy_rxen, phy_rxclk, phy_rxer,
phy_txd, phy_txen, phy_txclk, phy_txer,
phy_reset, phy_col, phy_lin... | 7.003451 |
module Divider (
I_CLK,
Rst,
O_CLK
);
parameter times = 20;
input I_CLK, Rst;
output O_CLK;
reg temp = 1'b0;
parameter tmp_times = times / 2;
assign O_CLK = temp;
integer cnt = 0;
always @(posedge I_CLK) begin
if (Rst == 1'b1) begin
cnt <= 0;
temp <= 1'b0;
end else be... | 7.440694 |
module Divider (
I_CLK,
Rst,
O_CLK
);
parameter times = 20;
input I_CLK, Rst;
output O_CLK;
reg temp = 1'b0;
parameter tmp_times = times / 2;
assign O_CLK = temp;
integer cnt = 0;
always @(posedge I_CLK) begin
if (Rst == 1'b1) begin
cnt <= 0;
temp <= 1'b0;
end else be... | 7.440694 |
module ethernet_100m (
`ifdef USE_POWER_PINS
inout vccd1, // User area 1 1.8V supply
inout vssd1, // User area 1 digital ground
`endif
/*
* Clock: 125MHz
* Synchronous reset
*/
input wire clk,
input wire rst,
/*
* Ethernet: 100BASE-T MII
*/
input wire ... | 6.532797 |
module ethernet_100m_tb;
reg clock;
reg RSTB;
reg CSB;
reg power1, power2;
reg power3, power4;
wire gpio;
wire [37:0] mprj_io;
reg rst;
wire [3:0] phy_txd;
wire phy_tx_en;
wire phy_tx_clk;
wire phy_rx_clk;
wire [3:0] phy_rxd;
wire phy_rx_dv;
wire phy_rx_er;
integer clock_counter = 0;
... | 6.532797 |
module ethernet_altera_merlin_traffic_limiter_181_qwneafy #(
parameter IMPL = "reg",
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 4,
parameter FIFO_DEPTH = 4,
parameter CHANNEL_WIDTH = 0,
parameter ERROR_WIDTH = 0,
param... | 6.868407 |
module contains two main blocks :
// physical layer block and media access control (MAC)
//
// (MAC) has interfaces with => 1- PHY module by (MII interface)
// 2- Soc AXI BUS by (AXI4-Lite)
// 3- direct memo... | 6.942464 |
module contains two main blocks :
// physical layer block and media access control (MAC)
//
// (MAC) has interfaces with => 1- PHY module by (MII interface)
// 2- Soc AXI BUS by (AXI4-Lite)
// 3- direct memo... | 6.942464 |
module ethernet_parser #(
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = DATA_WIDTH / 8,
parameter NUM_IQ_BITS = 3,
parameter INPUT_ARBITER_STAGE_NUM = 2
) ( // --- Interface to the previous stage
input [DATA_WIDTH-1:0] in_data,
input [CTRL_WIDTH-1:0] in_ctrl,
input in_w... | 7.369521 |
module ethernet_parser_32bit #(
parameter DATA_WIDTH = 32,
parameter CTRL_WIDTH = DATA_WIDTH / 8,
parameter NUM_IQ_BITS = 3,
parameter INPUT_ARBITER_STAGE_NUM = 2
) ( // --- Interface to the previous stage
input [DATA_WIDTH-1:0] in_data,
input [CTRL_WIDTH-1:0] in_ctrl,
input ... | 7.369521 |
module ethernet_parser_64bit #(
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = DATA_WIDTH / 8,
parameter NUM_IQ_BITS = 3,
parameter INPUT_ARBITER_STAGE_NUM = 2
) ( // --- Interface to the previous stage
input [DATA_WIDTH-1:0] in_data,
input [CTRL_WIDTH-1:0] in_ctrl,
input ... | 7.369521 |
module to simplify the timing where a pattern
// generator and address swap module can be muxed into the data path
//
//------------------------------------------------------------------------------
`timescale 1 ps/1 ps
module ethernet_rgmii_axi_pipe (
input axi_tclk,
input a... | 6.900006 |
module: TENBASET_TxD
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module ethernet_tb;
// Inputs
reg reset;
reg clk;
// Outputs
wire [3:0] out;
wire ctrl;
wire phy_reset;
wire T... | 6.95246 |
module ethernet_test (
input reset_n,
input fpga_gclk,
output e_reset,
// output CLK_25_ASIC,
output e_mdc,
inout e_mdio,
input e_rxc, //125Mhz ethernet gmii rx clock
input e_rxdv,
input e_rxer,
input [7:0] e_rxd,
input e_txc, ... | 7.043526 |
module ethernet_tx (
input wire clk125MHz,
input wire clk125MHz90,
input wire [7:0] raw_data,
input wire raw_data_valid,
input wire raw_data_enable,
input wire phy_ready,
// output
output wire [3:0] eth_txd,
output wire eth_txck,
output wire eth_txctl
);
wire [7:0] with_crc;... | 6.656028 |
module rxClkgen (
rxclk_in,
reset,
rxclk,
rxclk_180,
locked
);
input rxclk_in;
input reset;
output rxclk;
output rxclk_180;
output locked;
// 2x clock should be provided with dcm
wire rxclk;
wire rxclk_180;
// wire rxclk_2x;
/*dcm0 rx_dcm(.CLKIN_IN(rxclk_in),
.R... | 6.819799 |
module rxRSIO (
rxclk,
rxclk_180,
rxclk_2x,
reset,
rxd_in,
rxc_in,
rxd64,
rxc8,
local_fault,
remote_fault
);
input rxclk;
input rxclk_180;
input rxclk_2x;
input reset;
input [31:0] rxd_in;
input [3:0] rxc_in;
output [63:0] rxd64;
output [7:0] rxc8;
output local_... | 7.067817 |
module rxRSLayer (
rxclk,
rxclk_180,
rxclk_2x,
reset,
link_fault,
rxd64,
rxc8,
rxd_in,
rxc_in
);
input rxclk;
input rxclk_180;
input rxclk_2x;
input reset;
input [31:0] rxd_in;
input [3:0] rxc_in;
output [1:0] link_fault;
output [63:0] rxd64;
output [7:0] rxc8;
w... | 6.612035 |
module SwitchAsyncFIFO (
inReset,
iWClk,
iWEn,
ivDataIn,
qWFull,
qvWCount,
iRClk,
iREn,
ovDataOut,
qREmpty,
qvRNumberLeft
);
// Default address and data width
parameter pDepthWidth = 5;
parameter pWordWidth = 16;
input inReset;
input iWClk;
input iWEn;
input [... | 8.02377 |
module DualPortRAM_ASYN (
// Generic synchronous two-port RAM interface
WriteClock,
MemWEn,
MemWAddr,
MemDataIn,
ReadClock,
MemRAddr,
MemDataOut
);
// Default address and data width
parameter pDepthWidth = 5;
parameter pWordWidth = 16;
// Generic synchronous two-port RAM interf... | 8.984598 |
module SwitchSyncFIFO (
nReset,
iClk,
iWEn,
ivDataIn,
iREn,
ovDataOut,
qEmpty,
qFull,
qvCount
);
// Default address and data width
parameter pDepthWidth = 5;
parameter pWordWidth = 16;
input nReset;
input iClk;
input iWEn;
input [pWordWidth-1:0] ivDataIn;
input iREn... | 8.40197 |
module DualPortRAM (
clock,
MemWEn,
qvWAddr,
vDataIn,
qvRAddr,
vDataOut
);
// Default address and data width
parameter pDepthWidth = 5;
parameter pWordWidth = 16;
// Generic synchronous two-port RAM interface
input clock; // clock
input MemWEn; // write enable input
input [pDep... | 8.237962 |
module ack_counter (
clock, // 156 MHz clock
reset, // active high, asynchronous Reset input
ready,
tx_start, // Active high tx_start signal for counter
max_count, //16 bit reg for the maximum count to generate the ack signal
tx_ack // Active high signal
);
// Ports declaration
input c... | 7.485899 |
module ethrx_realign (
input clk,
input reset,
input clear,
input [35:0] datain,
input src_rdy_i,
output dst_rdy_o,
output [35:0] dataout,
output src_rdy_o,
input dst_rdy_i
);
reg [1:0] state;
reg [15:0] held;
reg [1:0] held_occ;
wire xfer_in = src_rdy_i & dst_r... | 7.158761 |
module ethtx_realign (
input clk,
input reset,
input clear,
input [35:0] datain,
input src_rdy_i,
output dst_rdy_o,
output [35:0] dataout,
output src_rdy_o,
input dst_rdy_i
);
reg [ 1:0] state;
reg [15:0] held;
reg [ 1:0] held_occ;
reg held_sof;
wire xfe... | 7.116766 |
module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be ... | 7.379264 |
module eth_controller (
input wire in_txen, // mcu/cpu to mac transmit enable
input wire [7:0] in_txd, // mcu/cpu to mac transmit data
input wire in_rxen, // wire to phy receive enable
input wire [7:0] in_rxd, // wire to phy receive data
output wire out_tx_ready, // mac to mcu/cpu transmit read... | 9.135858 |
module eth_encode #(
parameter MAC = 48'h010203040506,
parameter TYPE = 16'habcd
) (
input clk,
input rst,
output reg ack_rd_en_out,
input [63:0] ack_rd_d_in,
input ack_rd_empty_in,
output reg ps2_rd_en_out,
input [63:0] ps2_rd_d_in,
input ps2_rd_empty_in,
output reg ctl_wr_en_out,
output reg [15:0] c... | 6.57817 |
module eth_fifo (
data_in,
data_out,
clk,
reset,
write,
read,
clear,
almost_full,
full,
almost_empty,
empty,
cnt
);
parameter DATA_WIDTH = 32;
parameter DEPTH = 8;
parameter CNT_WIDTH = 4;
parameter Tp = 1;
input clk;
input reset;
input write;
input rea... | 7.753817 |
module eth_simple_dual_port_ram #(
parameter Dw = 8,
parameter Aw = 6
) (
data,
read_addr,
write_addr,
we,
clk,
q
);
input [Dw-1 : 0] data;
input [Aw-1 : 0] read_addr;
input [Aw-1 : 0] write_addr;
input we;
input clk;
output reg [Dw-1 : 0] q;
// Declare the RAM variable
... | 8.346598 |
module eth_single_port_ram #(
parameter Dw = 8,
parameter Aw = 6
) (
data,
addr,
we,
clk,
q
);
input [(Dw-1):0] data;
input [(Aw-1):0] addr;
input we, clk;
output [(Dw-1):0] q;
// Declare the RAM variable
reg [Dw-1:0] ram[2**Aw-1:0];
// Variable to hold the registered read a... | 7.991995 |
module eth_gtx_hook #(
parameter JUMBO_DW = 14, // Not used, just holdover for compatibility with older eth_gtx_bridge
parameter EVENINIT = 0,
parameter ENC_DISPINIT = 1'b0,
parameter GTX_DW = 20
) // Parallel GTX data width; Supported values are 10b and 20b
(
input gtx_tx_clk, // ... | 6.721636 |
module eth_host (
// WISHBONE common
wb_clk_i,
wb_rst_i,
// WISHBONE master
wb_adr_o,
wb_sel_o,
wb_we_o,
wb_dat_i,
wb_dat_o,
wb_cyc_o,
wb_stb_o,
wb_ack_i,
wb_err_i
);
parameter Tp = 1;
input wb_clk_i, wb_rst_i;
input [31:0] wb_dat_i;
input wb_ack_i, wb_err... | 6.705477 |
module eth_l3_checksum (
MRxClk,
Reset,
RxData,
ByteCnt,
CheckSum,
CSready
);
input MRxClk;
input Reset;
input [7:0] RxData;
input [15:0] ByteCnt;
output [15:0] CheckSum;
output CSready;
reg [15:0] CheckSum;
reg [31:0] Sum;
reg CSready;
reg [ 1:0] StartCalc;
reg ... | 6.506276 |
module
// by liam davey (29/4/11)
//
module eth_loop (
input clk,
input rst,
output reg rd_en_out,
input rd_end_in,
input [8:0] rd_d_in,
input rd_empty_in,
output reg wr_chk_out,
output reg wr_clr_out,
output reg wr_en_out,
output reg [8:0] wr_d_out,
input wr_full_in
);
reg [1:0] state;
reg [1:0] su... | 6.972959 |
module eth_mac_conf #(
parameter SRC_MAC = 48'h001122334455
) (
output wire [79:0] mac_tx_configuration_vector,
output wire [79:0] mac_rx_configuration_vector
);
// TX Configuration
assign mac_tx_configuration_vector[79:32] = SRC_MAC;
assign mac_tx_configuration_vector[30:16] = 1518;
assign mac_tx_... | 7.941077 |
module eth_mac_mii #(
// target ("SIM", "GENERIC", "XILINX", "ALTERA")
parameter TARGET = "GENERIC",
// Clock input style ("BUFG", "BUFR", "BUFIO", "BUFIO2")
// Use BUFR for Virtex-5, Virtex-6, 7-series
// Use BUFG for Ultrascale
// Use BUFIO2 for Spartan-6
parameter CLOCK_INPUT_STYLE = "BUF... | 7.854696 |
module eth_mac_phy_10g_rx #(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH / 8),
parameter HDR_WIDTH = (DATA_WIDTH / 32),
parameter PTP_PERIOD_NS = 4'h6,
parameter PTP_PERIOD_FNS = 16'h6666,
parameter PTP_TS_ENABLE = 0,
parameter PTP_TS_WIDTH = 96,
parameter USER_WIDTH = ... | 6.816642 |
module eth_mac_phy_10g_tx #(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH / 8),
parameter HDR_WIDTH = (DATA_WIDTH / 32),
parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter PTP_PERIOD_NS = 4'h6,
parameter PTP_PERIOD_FNS = 16... | 6.816642 |
module
// by liam davey (30/4/11)
//
// reads data and addresses from a fifo and
// writes them to the dram mcb fifo's.
//
module eth_mcb_if (
input clk,
input rst,
output reg rd_en_out,
input [35:0] rd_d_in,
input rd_empty_in,
output reg mcb_cmd_en_out,
output [2:0] mcb_cmd_instr_out,
output [5:0] mcb_cmd... | 6.972959 |
module eth_memory (
wb_clk_i,
wb_rst_i,
wb_adr_i,
wb_sel_i,
wb_we_i,
wb_cyc_i,
wb_stb_i,
wb_ack_o,
wb_err_o,
wb_dat_o,
wb_dat_i
);
parameter Tp = 1;
input wb_clk_i, wb_rst_i;
input [31:0] wb_adr_i, wb_dat_i;
input [3:0] wb_sel_i;
input wb_we_i, wb_cyc_i, wb_stb_i;... | 6.615497 |
module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be ... | 7.379264 |
module eth_parser #(
parameter C_S_AXIS_DATA_WIDTH = 256,
parameter C_S_AXIS_TUSER_WIDTH = 128,
parameter SRC_PORT_POS = 16,
parameter NUM_QUEUES = 8
) (
// --- Interface to the previous stage
input [ C_S_AXIS_DATA_WIDTH-1:0] tdata,
input [C_S_AXIS_TUSER_WIDTH-1:0] tuser,
... | 8.673171 |
module eth_phy_10g #(
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = (DATA_WIDTH / 8),
parameter HDR_WIDTH = 2,
parameter BIT_REVERSE = 0,
parameter SCRAMBLER_DISABLE = 0,
parameter PRBS31_ENABLE = 0,
parameter TX_SERDES_PIPELINE = 0,
parameter RX_SERDES_PIPELINE = 0,
parameter BI... | 8.261117 |
module eth_phy_10g_rx #(
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = (DATA_WIDTH / 8),
parameter HDR_WIDTH = 2,
parameter BIT_REVERSE = 0,
parameter SCRAMBLER_DISABLE = 0,
parameter PRBS31_ENABLE = 0,
parameter SERDES_PIPELINE = 0,
parameter BITSLIP_HIGH_CYCLES = 1,
parameter B... | 7.902033 |
module eth_phy_10g_rx_ber_mon #(
parameter HDR_WIDTH = 2,
parameter COUNT_125US = 125000 / 6.4
) (
input wire clk,
input wire rst,
/*
* SERDES interface
*/
input wire [HDR_WIDTH-1:0] serdes_rx_hdr,
/*
* Status
*/
output wire rx_high_ber
);
// bus width assertio... | 7.902033 |
module eth_phy_10g_rx_frame_sync #(
parameter HDR_WIDTH = 2,
parameter BITSLIP_HIGH_CYCLES = 1,
parameter BITSLIP_LOW_CYCLES = 8
) (
input wire clk,
input wire rst,
/*
* SERDES interface
*/
input wire [HDR_WIDTH-1:0] serdes_rx_hdr,
output wire serdes_rx_bitsli... | 7.902033 |
module eth_phy_10g_rx_watchdog #(
parameter HDR_WIDTH = 2,
parameter COUNT_125US = 125000 / 6.4
) (
input wire clk,
input wire rst,
/*
* SERDES interface
*/
input wire [HDR_WIDTH-1:0] serdes_rx_hdr,
output wire serdes_rx_reset_req,
/*
* Monitor inputs
... | 7.902033 |
module eth_phy_10g_tx #(
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = (DATA_WIDTH / 8),
parameter HDR_WIDTH = 2,
parameter BIT_REVERSE = 0,
parameter SCRAMBLER_DISABLE = 0,
parameter PRBS31_ENABLE = 0,
parameter SERDES_PIPELINE = 0
) (
input wire clk,
input wire rst,
/*
... | 7.609146 |
module eth_reframe #(
parameter WORDS = 4
) (
input [64*WORDS-1:0] din_data,
input [ 2*WORDS-1:0] din_frame,
output [66*WORDS-1:0] dout
);
genvar i;
generate
for (i = 0; i < WORDS; i = i + 1) begin : lp
// merge the framing and data bits
assign dout[(i+1)*66-1:i*66] = {din_data[(i... | 7.019177 |
module eth_register (
DataIn,
DataOut,
Write,
Clk,
Reset,
SyncReset
);
parameter WIDTH = 8; // default parameter of the register width
parameter RESET_VALUE = 0;
input [WIDTH-1:0] DataIn;
input Write;
input Clk;
input Reset;
input SyncReset;
output [WIDTH-1:0] DataOut;
reg... | 7.59973 |
module eth_rx (
input clk_mac,
input rst_n,
input eth_crsdv,
input eth_rxerr,
input [1:0] eth_rxd,
output reg rx_vld,
output reg [7:0] rx_dat,
output reg rx_sof,
output reg rx_eof,
output reg rx_err
);
`include "util.vh"
reg eth_c... | 7.701743 |
module eth_rxaddrcheck (
MRxClk,
Reset,
RxData,
Broadcast,
r_Bro,
r_Pro,
ByteCntEq2,
ByteCntEq3,
ByteCntEq4,
ByteCntEq5,
ByteCntEq6,
ByteCntEq7,
HASH0,
HASH1,
CrcHash,
CrcHashGood,
StateData,
RxEndFrm,
Multicast,
MAC,
RxAbort,
Addre... | 7.924255 |
module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be ... | 7.379264 |
module eth_smi (
input clk_mac,
input rst_n,
output ready,
input valid,
input write,
input [ 4:0] phyaddr,
input [ 4:0] register,
output [15:0] read_value,
input [15:0] write_value,
output reg eth_mdc,
inout eth_mdio
);
reg [3:0] counter;
... | 7.549756 |
module eth_config (
input clk_mac,
input rst_n,
input eth_intn,
output eth_mdc,
inout eth_mdio,
input reg_vld,
input [ 4:0] reg_addr,
input reg_write,
input [15:0] reg_wval,
output reg [15:0] reg_rval,
output reg reg_ack,
outp... | 6.850916 |
module eth_top_tb;
reg clk, resetn;
reg eth_col;
reg eth_crs;
wire eth_ref_clk;
wire eth_rx_clk;
reg eth_rxdv;
reg eth_rxerr;
wire eth_tx_clk;
reg [3:0] eth_rx_data;
wire eth_tx_en;
wire [3:0] eth_tx_data;
wire eth_rst_n;
reg s... | 6.571508 |
module eth_tx_scheduler (
input wire clk,
input wire rst_n,
input wire [7:0] rx_error,
input wire dim_error,
input wire data_available,
input wire read,
output wire [2:0] frame,
output wire frame_available
);
/* Frame types */
localparam [2:0] FRAME_NONE = 3'b000;
localparam [2:0]... | 7.180213 |
module eth_unframe #(
parameter WORDS = 4,
parameter LATENCY = 2
) (
input clk,
input [66*WORDS-1:0] din,
output [2*WORDS-1:0] dout_frame_lag,
output [64*WORDS-1:0] dout_data
);
wire [2*WORDS-1:0] dout_frame;
genvar i;
generate
for (i = 0; i < WORDS; i = i + 1) begin : lp
// s... | 6.886556 |
module ha_0 (
A,
B,
S,
C
);
input A, B;
output S, C;
XOR2X1 U1 (
.A(B),
.B(A),
.Y(S)
);
AND2X1 U2 (
.A(A),
.B(B),
.Y(C)
);
endmodule
| 7.918671 |
module ha_238 (
A,
B,
S,
C
);
input A, B;
output S, C;
XOR2X1 U1 (
.A(B),
.B(A),
.Y(S)
);
AND2X1 U2 (
.A(A),
.B(B),
.Y(C)
);
endmodule
| 7.767256 |
module ha_239 (
A,
B,
S,
C
);
input A, B;
output S, C;
XOR2X1 U1 (
.A(B),
.B(A),
.Y(S)
);
AND2X1 U2 (
.A(A),
.B(B),
.Y(C)
);
endmodule
| 7.466803 |
module fa_0 (
A,
B,
Cin,
S,
Cout
);
input A, B, Cin;
output S, Cout;
wire s1, c1, c2;
ha_239 HA1 (
.A(A),
.B(B),
.S(s1),
.C(c1)
);
ha_238 HA2 (
.A(s1),
.B(Cin),
.S(S),
.C(c2)
);
OR2X1 U1 (
.A(c1),
.B(c2),
.Y(Cout)
)... | 7.346768 |
module ha_35 (
A,
B,
S,
C
);
input A, B;
output S, C;
XOR2X1 U1 (
.A(B),
.B(A),
.Y(S)
);
AND2X1 U2 (
.A(A),
.B(B),
.Y(C)
);
endmodule
| 7.976383 |
module ha_1 (
A,
B,
S,
C
);
input A, B;
output S, C;
XOR2X1 U1 (
.A(B),
.B(A),
.Y(S)
);
AND2X1 U2 (
.A(A),
.B(B),
.Y(C)
);
endmodule
| 8.251464 |
module ha_2 (
A,
B,
S,
C
);
input A, B;
output S, C;
XOR2X1 U1 (
.A(B),
.B(A),
.Y(S)
);
AND2X1 U2 (
.A(A),
.B(B),
.Y(C)
);
endmodule
| 8.820539 |
module fa_1 (
A,
B,
Cin,
S,
Cout
);
input A, B, Cin;
output S, Cout;
wire s1, c1, c2;
ha_2 HA1 (
.A(A),
.B(B),
.S(s1),
.C(c1)
);
ha_1 HA2 (
.A(s1),
.B(Cin),
.S(S),
.C(c2)
);
OR2X1 U1 (
.A(c1),
.B(c2),
.Y(Cout)
);
en... | 7.561253 |
module ha_3 (
A,
B,
S,
C
);
input A, B;
output S, C;
XOR2X1 U1 (
.A(B),
.B(A),
.Y(S)
);
AND2X1 U2 (
.A(A),
.B(B),
.Y(C)
);
endmodule
| 8.241723 |
module ha_4 (
A,
B,
S,
C
);
input A, B;
output S, C;
XOR2X1 U1 (
.A(B),
.B(A),
.Y(S)
);
AND2X1 U2 (
.A(A),
.B(B),
.Y(C)
);
endmodule
| 8.54402 |
module fa_2 (
A,
B,
Cin,
S,
Cout
);
input A, B, Cin;
output S, Cout;
wire s1, c1, c2;
ha_4 HA1 (
.A(A),
.B(B),
.S(s1),
.C(c1)
);
ha_3 HA2 (
.A(s1),
.B(Cin),
.S(S),
.C(c2)
);
OR2X1 U1 (
.A(c1),
.B(c2),
.Y(Cout)
);
en... | 7.487957 |
module ha_5 (
A,
B,
S,
C
);
input A, B;
output S, C;
XOR2X1 U1 (
.A(B),
.B(A),
.Y(S)
);
AND2X1 U2 (
.A(A),
.B(B),
.Y(C)
);
endmodule
| 8.445306 |
module ha_6 (
A,
B,
S,
C
);
input A, B;
output S, C;
XOR2X1 U1 (
.A(B),
.B(A),
.Y(S)
);
AND2X1 U2 (
.A(A),
.B(B),
.Y(C)
);
endmodule
| 8.462988 |
module fa_3 (
A,
B,
Cin,
S,
Cout
);
input A, B, Cin;
output S, Cout;
wire s1, c1, c2;
ha_6 HA1 (
.A(A),
.B(B),
.S(s1),
.C(c1)
);
ha_5 HA2 (
.A(s1),
.B(Cin),
.S(S),
.C(c2)
);
OR2X1 U1 (
.A(c1),
.B(c2),
.Y(Cout)
);
en... | 7.622918 |
module ha_7 (
A,
B,
S,
C
);
input A, B;
output S, C;
XOR2X1 U1 (
.A(B),
.B(A),
.Y(S)
);
AND2X1 U2 (
.A(A),
.B(B),
.Y(C)
);
endmodule
| 8.192229 |
module ha_8 (
A,
B,
S,
C
);
input A, B;
output S, C;
XOR2X1 U1 (
.A(B),
.B(A),
.Y(S)
);
AND2X1 U2 (
.A(A),
.B(B),
.Y(C)
);
endmodule
| 8.302319 |
module fa_4 (
A,
B,
Cin,
S,
Cout
);
input A, B, Cin;
output S, Cout;
wire s1, c1, c2;
ha_8 HA1 (
.A(A),
.B(B),
.S(s1),
.C(c1)
);
ha_7 HA2 (
.A(s1),
.B(Cin),
.S(S),
.C(c2)
);
OR2X1 U1 (
.A(c1),
.B(c2),
.Y(Cout)
);
en... | 7.659597 |
module ha_9 (
A,
B,
S,
C
);
input A, B;
output S, C;
XOR2X1 U1 (
.A(B),
.B(A),
.Y(S)
);
AND2X1 U2 (
.A(A),
.B(B),
.Y(C)
);
endmodule
| 8.400956 |
module ha_10 (
A,
B,
S,
C
);
input A, B;
output S, C;
XOR2X1 U1 (
.A(B),
.B(A),
.Y(S)
);
AND2X1 U2 (
.A(A),
.B(B),
.Y(C)
);
endmodule
| 8.137426 |
module fa_5 (
A,
B,
Cin,
S,
Cout
);
input A, B, Cin;
output S, Cout;
wire s1, c1, c2;
ha_10 HA1 (
.A(A),
.B(B),
.S(s1),
.C(c1)
);
ha_9 HA2 (
.A(s1),
.B(Cin),
.S(S),
.C(c2)
);
OR2X1 U1 (
.A(c1),
.B(c2),
.Y(Cout)
);
e... | 7.197287 |
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