code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module Equal (
read_data_1_i,
read_data_2_i,
zero_o
);
input wire [31:0] read_data_1_i;
input wire [31:0] read_data_2_i;
output wire zero_o;
assign zero_o = (read_data_1_i == read_data_2_i) ? 1'b1 : 1'b0;
endmodule
| 7.205968 |
module equalityGate #(
parameter WIDTH = 32
) (
input [WIDTH-1:0] A,
B,
output Out
);
assign Out = (A == B) ? 1'h1 : 1'h0;
endmodule
| 7.655631 |
module equalizer_line_0_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 2;
parameter AWIDTH = 4;
parameter MEM_SIZE = 16;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "distributed" *) ... | 6.652013 |
module equalizer_line_0 (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd2;
parameter AddressRange = 32'd16;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
... | 6.652013 |
module equalOrNot #(
parameter Width = 32
) (
req,
fin,
equal,
notEqual,
x,
y
);
input req;
input [Width-1:0] x, y;
output wire equal, notEqual, fin;
reg [1:0] result = 2'b00;
assign equal = result[1];
assign notEqual = result[0];
assign fin = (result == 2'b01) | (result == 2... | 7.09465 |
module equalsZero (
dataA,
out
);
input [31:0] dataA;
output out;
wire w1, w2, w3, w4;
nor nor1 (w1, dataA[0], dataA[1], dataA[2], dataA[3], dataA[4], dataA[5], dataA[6], dataA[7]);
nor nor2 (
w2, dataA[8], dataA[9], dataA[10], dataA[11], dataA[12], dataA[13], dataA[14], dataA[15]
);
nor no... | 6.502894 |
module Equal_cond_holder (
input in,
input clk,
output reg out
);
always @(negedge clk) begin
out <= in;
end
endmodule
| 6.632421 |
module equal_const (
dat,
out
);
parameter WIDTH = 8;
parameter CONST_VAL = 8'h45;
parameter METHOD = 0;
input [WIDTH-1:0] dat;
output out;
wire out;
generate
if (METHOD == 0) begin
///////////////////////
// Generic style
///////////////////////
assign out = (dat ==... | 7.099476 |
module equal_control (
input [31:0] data_A,
input [31:0] data_B,
input clk,
input reset,
output reg equal
);
always @(posedge clk) begin
if (reset == 0) begin
equal = 1'b0;
end else begin
equal = (data_A == data_B) ? 1'b1 : 1'b0;
end
end
endmodule
| 6.849375 |
module equal_flag_operator (
X,
Y,
equal
);
//parameter definitions
parameter BUSSIZE = 32;
//port definitions - customize for different bit widths
input wire [BUSSIZE-1:0] X, Y;
output wire equal;
wire [BUSSIZE-1:0] Z;
assign Z = ~(X ^ Y);
assign equal = &Z;
endmodule
| 9.151248 |
module for comparing the output of comparator
module EQZ (output wire eqz,
input wire [15:0] data
);
assign eqz= (data==1);
endmodule
| 7.507798 |
module Eq_1bit (
out,
a,
b
);
input a;
input b;
output out;
wire c, d;
or or0 (c, a, b);
nand nand0 (d, a, b);
nand nand1 (out, c, d);
endmodule
| 6.621476 |
module EQ_5 (
A,
B,
Y
);
input wire [4:0] A;
input wire [4:0] B;
output wire Y;
wire Bit0EQ;
wire Bit1EQ;
wire Bit2EQ;
wire Bit3EQ;
wire Bit4EQ;
wire Power;
assign Y = Bit3EQ & Power & Bit4EQ & Bit2EQ & Bit1EQ & Bit0EQ;
assign Bit4EQ = A[4] ~^ B[4];
assign Bit3EQ = A[3] ~^ ... | 7.567772 |
module EqForwardingHandler (
input [4:0] reg_read_addr_i, // Address of the register.
input [31:0] reg_read_data_i, // Data of the register.
input reg_write_ctrl_from_ex_to_mem_i, // Flag for writing back or not.
input [4:0] reg_write_addr_from_ex_to_mem_i, // Previous WB address.
input [31:0] r... | 7.820466 |
module
* All inputs are defined in TUBOSIM spec
*
* PARAMETERS:
* data_wd: width of single Q entry.
* q_add_wd: address width of event q store element (RAM). for example
* q_add_wd=5 => maximal numbers of entries in q is 32.
* q_max_len: maximal length of Event Q
* lo: bit select. TIME low bit offset.... | 7.43345 |
module erase (
input clk,
reset,
enableDraw,
output [7:0] x_out,
output [6:0] y_out,
output [2:0] c_out,
output done,
input inEraseStateMain
);
reg [7:0] counterX, xOut; //placeholder for x_out and the counter assosciated with it
reg [6:0] counterY, yOut; //placeholder for y_out a... | 8.200543 |
module EraseHearts
(
iCLOCK_50,
iresetn,
iEraseP1Heart,
iEraseP2Heart,
iP1Life,
iP2Life,
ocolor_out,
ox,
oy,
owriteEn,
oDoneSignal,
);
input iCLOCK_50, iresetn, iEraseP1Heart, iEraseP2Heart;
input [1:0]iP1Life, iP2Life;
output [2:0]ocolor_out;
output reg [8:0]ox;
output reg [7:0]oy;
output reg ow... | 7.371643 |
module eraseScreen (
input clock, //put clock 50 into this
input draw, //put rate divider into this
input reset, //put reset into this
output reg [7:0] xOut, //send to VGA x
output reg [7:0] yOut, //send to VGA y
output [2:0] colourOut,
output reg plot,
output reg done
); //send to... | 7.215219 |
module erase_all (
input clk,
resetn,
enable,
output [7:0] x_out,
output [6:0] y_out,
output [2:0] color_out
);
reg [15:0] counter;
always @(posedge clk) begin
if (!resetn) counter <= 16'd0;
else begin
if (counter == 16'd65530) counter <= 16'd0;
else counter <= counter + ... | 7.717163 |
module part2 (
CLOCK_50, // On Board 50 MHz
// Your inputs and outputs here
KEY,
SW,
// The ports below are for the VGA output. Do not change.
VGA_CLK, // VGA Clock
VGA_HS, // VGA H_SYNC
VGA_VS, // VGA V_SYNC
VGA_BLANK_N, // VGA BLANK
VGA_SYNC_N, // VGA SYNC
VGA_R, //... | 7.840046 |
module datapath (
clock,
reset_n,
x_or_y,
colour,
enable_x,
enable_y,
enable_colour,
x_out,
y_out,
colour_out,
enable,
writeEn,
enable_erase
);
input clock, reset_n, enable_x, enable_y, enable_colour, enable, writeEn, enable_erase;
input [6:0] x_or_y;
input [2:0... | 6.91752 |
module ratedivider (
enable,
load,
clock,
reset_n,
q
);
input enable, clock, reset_n;
input [27:0] load;
output reg [27:0] q;
always @(posedge clock) begin
if (reset_n == 1'b0) //reset
q <= load;
else if (enable == 1'b1) begin
if (q == 0) //reset
q <= load;
... | 8.084012 |
module control (
clock,
reset_n,
go,
enable,
enable_x,
enable_y,
enable_colour,
write_en,
start
);
input go, clock, reset_n, start;
output reg enable, enable_x, enable_y, enable_colour, write_en;
reg [3:0] curr_state, next_state;
localparam LOAD_X = 4'd0, LOAD_X_WAIT = 4'd1... | 7.715617 |
module combination (
input clock,
input reset_n,
input go,
output [7:0] x_out,
output [6:0] y_out,
output [2:0] colour_out,
input [6:0] x_or_y,
input colour,
input start
);
wire enable_x, enable_y, enable_colour, writeEn, enable;
// Instansiate datapath
datapath d0 (
.c... | 6.541906 |
module part2
// (
// CLOCK_50, // On Board 50 MHz
// // Your inputs and outputs here
// KEY,
// SW,
// // The ports below are for the VGA output. Do not change.
// VGA_CLK, // VGA Clock
// VGA_HS, // VGA H_SYNC
// VGA_VS, // VGA V_SYNC
// VGA_BLANK_N, // VGA BLANK
// ... | 7.735443 |
module control(
// input clk,
// input resetn,
// input go,
//
// output reg ld_x, ld_y, ld_draw
// );
//
// reg [3:0] current_state, next_state;
//
// localparam S_LOAD_X = 4'd0,
// S_LOAD_X_WAIT = 4'd1,
// S_LOAD_Y = 4'd2,
// S_LOAD_Y... | 7.605694 |
module erase_flash (
input rst,
clk,
en_erase_page,
input [4:0]state,
input [23:0] erase_addr_row,
output reg [1:0]erase_addr_row_error, //˿ַõַǷΪ,0Ϊδ1Ϊÿ飬2Ϊ黵
input [7:0]erase_flash_dataout, //FLASHݣ״̬Ĵļ
output [7:0] erase_flash_datain, //ģ
output [11:0]erase_bad_block_ram_ad... | 6.972208 |
module erase_flash_control (
input clk,
rst,
input en_erase,
end_erase_page,
output end_erase,
output reg en_erase_page,
input [1:0] erase_addr_row_error, // 2 Ϊ飬1Ϊÿ飬 0Ϊδ
input [23:0] erase_addr_start,
erase_addr_finish,
output reg [23:0] erase_addr_row
);
wire [2:0] erase_... | 6.946593 |
module erase_flash_state_control(
input clk,rst,en_erase,end_erase_page,
input [23:0]erase_addr_finish,erase_addr_row,
input [1:0]erase_addr_row_error, // 2 Ϊ飬1Ϊÿ飬 0Ϊδ
output reg[2:0] erase_state
);
reg n;
always @(posedge clk or posedge rst)
begin
if(rst)
erase_state <= 0;
else
case(erase_state)
... | 6.590499 |
module EReg (
input wire cnd,
input wire clk,
input wire [`icodeBus] icode,
input wire [`ifunBus] ifun,
input wire [`digitsBus] valC,
valA,
valB, //valA valBdecode.v module д
input wire [`regBus] dstE,
dstM,
input wire [2:0] stat,
input wire bubble,
output reg [`icodeBu... | 7.229636 |
module JumpIfEqual (
OperatorA,
OperatorB,
Initial,
Count,
Result
);
endmodule
| 6.741213 |
module was generated automatically
* using the icepll tool from the IceStorm project.
* Use at your own risk.
*
* Given input frequency: 100.000 MHz
* Requested output frequency: 25.000 MHz
* Achieved output frequency: 25.000 MHz
*/
module pll(
input clock_in,
output clock_out,
output locked
);
... | 7.841705 |
module erode (
input rst_n,
input pclk,
input sobel_hs,
input sobel_vs,
input sobel_de,
input sobel_din,
output erode_hs,
output erode_vs,
output erode_de,
output erode_dout
);
reg p11, p12, p13;
reg p21, p22, p23;
reg p31, p32, p33;
wire p1, p2, p3;
reg erode1,... | 6.546038 |
module ErodeNode #(
parameter Width = 3,
parameter Height = 3
) (
input [Width*Height-1:0] element,
input [Width*Height-1:0] D,
output Q
);
wire [Width*Height-1:0] sums;
assign Q = &sums;
genvar l, c;
generate
for (l = 0; l < Height; l = l + 1) begin : _line_
for (c = 0; c < Wid... | 7.149523 |
module ErodeTest;
parameter Width = 8;
parameter Height = 4;
reg [Width*Height-1:0] imageIn;
reg [8:0] mask;
wire [Width*Height-1:0] imageOut;
Erode #(
.Width (Width),
.Height(Height)
) erode (
.imageIn(imageIn),
.mask(mask),
.imageOut(imageOut)
);
initial begin
... | 6.700636 |
module Erosion (
input [71:0] image_in, //Input
output [ 7:0] pixel_out //Output
);
//For parallel calculations
wire temp, temp2, temp3, temp4, temp5;
//Calculating for two pixel whiteness
assign temp = (image_in[7:0] > 127) & (image_in[15:8] > 127);
assign temp2 = (image_in[23:16] > 127) & (imag... | 6.80845 |
module Bit_Erosion_Detector #(
parameter [10:0] IMG_HDISP = 11'd640, //640*480
parameter [10:0] IMG_VDISP = 11'd480
) (
//global clock
input clk, //cmos video pixel clock
input rst_n, //global reset
//Image data prepred to be processd
input per_frame_vsync, //Prepared Image data vsync... | 7.309875 |
module: lclErrCtrlSplitter
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module errCtrlSplitters_tb;
localparam InWidth = 5;
localparam LocalNum = 6;
localparam Sub1Width = 4;
local... | 6.54801 |
module ErrDetecer #(
parameter SYM_WIDTH = 1,
parameter INT_WIDTH = 1,
parameter DEC_WIDTH = 14
) (
input wire clk,
input wire rstn,
input wire data_ready, //输入数据有效位
input wire signed [`DATA_WIDTH-1 : 0] ErrDetecerInputDataQ,
input wire signed [`DATA_WIDTH-1 : 0] ErrDetecerInputDataI,
... | 6.970124 |
module main; //: root_module
reg w4; //: /sn:0 {0}(111,321)(191,321)(191,320)(201,320){1}
reg w3; //: /sn:0 {0}(112,291)(201,291){1}
reg w0; //: /sn:0 {0}(113,195)(201,195){1}
reg w1; //: /sn:0 {0}(113,225)(201,225){1}
reg w2; //: /sn:0 {0}(112,257)(202,257){1}
reg w5; //: /sn:0 {0}(112,353)(191,353)... | 6.5859 |
module bar;
wire a;
wire b;
wire a;
assign h = a;
foo g1 (
.I1(a),
.I2(b)
);
initial begin
a = b + 1;
x = y;
end
endmodule
| 6.512865 |
module not1 (
input i1,
output reg o1
);
assign o1 = !i1;
endmodule
| 7.35925 |
module not1 (
input i1,
output o1
);
always @(i1) begin
o1 = !i1;
end
endmodule
| 7.35925 |
module main; //: root_module
reg w0; //: /sn:0 {0}(150,141)(198,141)(198,178)(208,178){1}
//: enddecls
//: SWITCH g1 (w0) @(133,141) /sn:0 /w:[ 0 ] /st:0
foo g0 (.A(w0)); //: @(209, 153) /sz:(84, 95) /sn:0 /p:[ Li0>1 ]
endmodule
| 6.5859 |
module main; //: root_module
reg w0; //: /sn:0 {0}(150,141)(198,141)(198,178)(208,178){1}
reg w1; //: /sn:0 {0}(129,228)(208,228){1}
//: enddecls
//: SWITCH g2 (w1) @(112,228) /sn:0 /w:[ 0 ] /st:0
//: SWITCH g1 (w0) @(133,141) /sn:0 /w:[ 0 ] /st:0
foo g0 (
.B(w1),
.A(w0)
); //: @(209, 153... | 6.5859 |
module main; //: root_module
wire w0; //: /sn:0 {0}(159,147)(174,147){1}
wire w3; //: /sn:0 {0}(279,245)(291,245){1}
wire w1; //: /sn:0 {0}(159,152)(174,152){1}
wire w2; //: /sn:0 {0}(195,150)(210,150){1}
//: enddecls
foo g2 (); //: @(195, 289) /sz:(40, 40) /sn:0 /p:[ ]
foo g1 (.A(w3)); //: @(292,... | 6.5859 |
module _GGAND2 #(.Diz(1)) (I0, I1, Z);
output Z;
input I0;
input I1;
assign #Diz Z = I0 & I1;
endmodule
| 6.682468 |
module ErrorCombiner #(
parameter ERROR_WIDTH = 8,
parameter WEIGHT_WIDTH = 4
) (
input wire reset_i,
input wire signed [WEIGHT_WIDTH-1:0] weight_0_i,
input wire signed [WEIGHT_WIDTH-1:0] weight_1_i,
input wire signed [WEIGHT_WIDTH-1:0] weight_2_i,
input wire signed [WEIGHT_WIDTH-1:0] weigh... | 7.245036 |
module errorConvert (
input clk,
input wire writeStrobe,
input wire csrStrobe,
input wire [31:0] writeData,
output wire [31:0] status,
output wire [31:0] resultHi,
output wire [31:0] resultLo
);
wire [31:0] floatValue, productValue;
wire floatValid, productValid;
wire ... | 7.050984 |
module ErrorGen (
input clear_accumulator,
input sym_clk_ena,
input [20:0] MSamples,
input [7:0] shiftVal,
input signed [17:0] error,
output reg signed [17:0] accumulated_error,
output reg signed [35:0] accumulated_squared_error
);
//reg signed [17:0] error;
reg signed [35:0] error_squa... | 7.685274 |
module errorInjectionControlRouter (
input err_en,
input [15:0] err_ctrl,
output reg [LCL-1:0] lcl_err
);
parameter LWB = 0; // Lower bound
parameter UPB = 1; // Upper bound
parameter LCL = 1; // Number of local dffs
wire inBounds = (err_ctrl <= UPB) | (err_ctrl >= LWB);
wire [15:0] shft_err_... | 7.866478 |
module: errorInjectionControlRouter
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module errorInjectionControlRouter_tb;
// Inputs
reg error_en;
reg [15:0] error_control;
// Outputs... | 6.740881 |
module errorLogic (
goal,
actual,
error,
clk,
direction,
unsignedGoal,
unsignedActual
);
input signed [7:0] goal, actual; //goalSpeed and actualSpeed are received as signed 8-bit numbers, representing a pwm duty cycle
output reg [7:0] error; //output is an unsigned, 8-bit number represe... | 6.979748 |
module ErrorLp (
rst,
clk,
strobe,
yik,
yqk,
yi,
yq,
sync,
er,
wk
);
input rst; //复位信号，高电平有效
input clk; //时钟信号/数据输入速率/4倍符号速率/4 MHz
input strobe; //gnco模块送来的选通信号
input signed [17:0] yik; //插值滤波后的I路数据/4 MHz
input signed [17:0] yqk; //插值滤波后的Q路数据/4 MHz
output sign... | 8.219547 |
module second_level (
clk,
three,
four,
//*****[ERROR CAPTURE MODULE INOUTS]*****
err_en, // Error injection enable
err_ctrl // Error injection control
);
//*****[ERROR CAPTURE MODULE INOUTS INSTANTIATIONS]*****
input err_en; // Error injection enable
input [0:0] err_ctrl; // Error in... | 6.813036 |
module first_level (
clk,
one,
two,
//*****[ERROR CAPTURE MODULE INOUTS]*****
err_en, // Error injection enable
err_ctrl // Error injection control
);
//*****[ERROR CAPTURE MODULE INOUTS INSTANTIATIONS]*****
input err_en; // Error injection enable
input [1:0] err_ctrl; // Error inject... | 7.055956 |
module second_level (
clk,
three,
four
);
input clk;
input [2:0] three;
output [2:0] four;
wire [2:0] threePointFive;
dffr_ns #(3) dffThree (
.clk(clk),
.rst(three[0]),
.din(three),
.q (threePointFive)
);
assign four = {threePointFive[0], threePointFive[1], threePoint... | 6.813036 |
module first_level (
clk,
one,
two
);
input clk;
input [5:0] one;
output [5:0] two;
wire [5:0] onePointFive;
dff_ns #(6) dffOne (
.clk(clk),
.din(one),
.q (onePointFive)
);
wire [2:0] twoPartOne;
dff_ns #(3) dffTwo (
.clk(clk),
.din(onePointFive[5:3]),
... | 7.055956 |
module
// created in component editor. It ties off all outputs to ground and
// ignores all inputs. It needs to be edited to make it do something
// useful.
//
// This file will not be automatically regenerated. You should check it in
// to your version control system if you want to keep it.
module error_adapter2 ... | 7.702374 |
module ERROR_CONTROLLER (
input clk_error,
input en_error,
output reg error_busy,
output clk_abs1,
clk_abs2,
clk_sub,
clk_abs3,
clk_out,
output reg en_abs1,
en_abs2,
en_sub,
en_abs3,
en_out
);
assign clk_abs1 = clk_error;
assign clk_abs2 = clk_error;
assign cl... | 6.599784 |
module error_controllerV2 (
// input signals
clk,
reset,
start,
last_count,
less_than_zero,
// output signals
e_sel_mux_in,
e_sel_mux_out,
y_sel_mux_in,
en_counter,
reset_all,
WE_error_reg,
WE_y_reg
);
input clk, reset, start, less_than_zero, last_count;
out... | 6.966266 |
module error_counter #(
parameter width = 12
) (
input wire data_i,
input wire data_o,
input wire rst,
input wire signal_clk,
output reg [width:0] number_right,
output reg [width:0] number_wrong
);
reg [width:0] number_total;
always @(posedge rst, posedge signal_clk) begin
if (rst)... | 8.462504 |
module error_datapath #(
parameter WIDTH = 13
) (
clk,
rst,
WE_error_reg,
WE_y_reg,
e_sel_mux_in,
e_sel_mux_out,
y_sel_mux_in,
deltax,
y0,
deltay,
ystep,
xcount,
x0,
y_coord_out,
less_than_zero
);
input [WIDTH-1:0] deltax, y0, deltay, ystep, xcount, x0;
... | 8.499906 |
module Error_Estimation (
input a1,
input a,
output error
);
assign error = a ~^ a1;
endmodule
| 7.123397 |
module DOMmul (
port_a,
port_b,
port_u_0,
port_u_1
);
input [1:0] port_a;
input [1:0] port_b;
output [1:0] port_u_0;
output [1:0] port_u_1;
AND2_X1 U1 (
.A1(port_b[1]),
.A2(port_a[1]),
.ZN(port_u_1[1])
); // We provoke an error here.
AND2_X1 U2 (
.A1(port_a[1]),
... | 6.587872 |
module DOM (
port_a,
port_b,
port_c,
port_r,
clk,
reset
);
input [1:0] port_a;
input [1:0] port_b;
output [1:0] port_c;
input [0:0] port_r;
input clk, reset;
wire [1:0] mul_port_u_0;
wire [1:0] mul_port_u_1;
wire [1:0] ref_1_port_v_0;
wire [1:0] ref_1_port_v_1;
DOMmul mul (... | 6.588448 |
module error_handle (
output [1:0] exception_sig,
// exception_sig[1]: MemWrite,
// exception_sig[0]: Mem2Reg
input pc_exception,
mem_write,
mem_2_reg,
input [7:0] alu_status
);
assign exception_sig[1] = (pc_exception == 1'b1 || alu_status[6] == 1'b1 || alu_status[3] == 1'b1 || alu_status... | 6.719429 |
module ERROR_OUT (
input clk_out,
input en_out,
input signed [25:0] i1_11,
i1_12,
i1_13,
i1_14,
input signed [25:0] i1_21,
i1_22,
i1_23,
i1_24,
input signed [25:0] i1_31,
i1_32,
i1_33,
i1_34,
input signed [25:0] i1_41,
i1_42,
i1_43,
i1_44,
in... | 6.987812 |
module DOMmul (
port_a,
port_b,
port_u_0,
port_u_1
);
input [1:0] ERROR; // We provoke an error here.
input [1:0] port_b;
output [1:0] port_u_0;
output [1:0] port_u_1;
AND2_X1 U1 (
.A1(port_b[1]),
.A2(port_a[1]),
.ZN(port_u_1[1])
);
AND2_X1 U2 (
.A1(port_a[1]),
... | 6.587872 |
module DOM (
port_a,
port_b,
port_c,
port_r,
clk,
reset
);
input [1:0] port_a;
input [1:0] port_b;
output [1:0] port_c;
input [0:0] port_r;
input clk, reset;
wire [1:0] mul_port_u_0;
wire [1:0] mul_port_u_1;
wire [1:0] ref_1_port_v_0;
wire [1:0] ref_1_port_v_1;
DOMmul mul (... | 6.588448 |
module error_response (
input wire clk,
input wire Enable,
input wire Error_Invalid_Request,
input wire Error_Invalid_Request_challenge,
input wire Error_Invalid_Request_GetCertificate,
input wire Error_Busy,
input wire Error_Unsupported_Protocol,
input wire Error_Unspecified,
output... | 7.446005 |
module ERROR_SOLVER #(
ERR_NUM = 16'd5 // Колличество ошибок при котором инициализируется сброс
) (
input iCLK,
input iFULL_ERROR,
iHEAD_ERROR,
iEPILOG_ERROR,
output reg oRST_BLVDS_RECEIVER,
output [15:0] oFULL_ERR_CNT,
oHEAD_ERR_CNT,
oEPILOG_ERR_CNT
);
reg rFULL_ERROR... | 6.749205 |
module error_unit #(
parameter WIDTH = 13
) (
clk,
rst,
start,
last_count,
deltax,
y0,
deltay,
ystep,
xcount,
x0,
y_coord_out,
en_counter
);
input [WIDTH-1:0] deltax, y0, deltay, ystep, xcount, x0;
input clk, rst, start, last_count;
output [WIDTH-1:0] y_coord_ou... | 7.082778 |
module DOMmul (
port_a,
port_b,
port_u_0,
port_u_1
);
input [1:0] port_a;
input [1:0] port_b;
output [1:0] port_u_0;
output [1:0] port_u_1;
AND2_X1 U1 (
.A1(port_b[1]),
.A2(port_a[1]),
.ZN(port_u_1[1])
);
AND2_X1 U2 (
.A1(port_a[1]),
.A2(port_b[0]),
.Z... | 6.587872 |
module DOM (
port_a,
port_b,
port_c,
port_r,
clk,
reset
);
input [1:0] port_a;
input [1:0] port_b;
output [1:0] port_c;
input [0:0] port_r;
input clk, reset;
wire [1:0] mul_port_u_0;
wire [1:0] mul_port_u_1;
wire [1:0] ref_1_port_v_0;
wire [1:0] ref_1_port_v_1;
DOMmul mul (... | 6.588448 |
module Err_detect (
input wire x1,
x2,
x3,
x4,
output wire D
);
assign D = (x1 & x2) + (x3 & x4);
endmodule
| 7.15028 |
module err_detect_rom #(
parameter P_D_WIDTH = 16
)
(
input wire[fn_ecc_synd_width(P_D_WIDTH)-1:0] syndromes_i,
output wire[P_D_WIDTH-1:0] msk_o
);
//######################################################################
`include"bch_func.inc"
`include"err_func_31.inc"
`include"err_func_63.... | 7.676627 |
module err_func_31_rom (
input clk,
input en,
input [9:0] syndromes,
output reg [30:0] errs
);
`include "err_func_31.inc"
always @(posedge clk) if (en) errs <= fn_err_pat_dcd_gf5_rom(syndromes);
endmodule
| 7.67465 |
module err_gen (
hburst_s3,
hmastlock,
hprot_s3,
hrdata_s3,
hready_s3,
hresp_s3,
hsel_s3,
hsize_s3,
htrans_s3,
hwdata_s3,
hwrite_s3,
pad_cpu_rst_b,
pll_core_cpuclk
);
input [2 : 0] hburst_s3;
input hmastlock;
input [3 : 0] hprot_s3;
input hsel_s3;
input [2... | 7.103204 |
module err_mngr (
input clk, // System clock
input rst_n, // Reset (active low)
input err_wr, // Write from downstream
input [31:0] err_in, // Error data in
output reg [31:0] err_out = 0, // Error data out
output reg ... | 7.851621 |
module err_reg ( /*AUTOARG*/
// Outputs
err_req,
err_sts,
// Inputs
sys_clk,
sys_rst,
phyclk,
err_we,
err_wdata,
err_ack
);
input sys_clk;
input sys_rst;
input phyclk;
input err_we;
input [7:0] err_wdata;
input [7:0] err_ack;
output [7:0] err_req;
output [7:0] ... | 6.698487 |
module erx_arbiter ( /*AUTOARG*/
// Outputs
rx_rd_wait,
rx_wr_wait,
edma_wait,
ecfg_wait,
rxwr_access,
rxwr_packet,
rxrd_access,
rxrd_packet,
rxrr_access,
rxrr_packet,
// Inputs
erx_access,
erx_packet,
mailbox_wait,
edma_access,
edma_packet,
ecfg_... | 7.24387 |
module erx_protocol ( /*AUTOARG*/
// Outputs
erx_access,
erx_packet,
// Inputs
clk,
test_mode,
rx_packet,
rx_burst,
rx_access
);
parameter AW = 32;
parameter DW = 32;
parameter PW = 104;
parameter ID = 12'h999; //link id
// System reset input
input clk;
//test mode... | 8.150313 |
module erx_remap ( /*AUTOARG*/
// Outputs
emesh_access_out,
emesh_packet_out,
// Inputs
clk,
emesh_access_in,
emesh_packet_in,
remap_mode,
remap_sel,
remap_pattern,
remap_base
);
parameter AW = 32;
parameter DW = 32;
parameter PW = 104;
parameter ID = 12'h808;
//... | 7.009439 |
module ESC (
input wire clk,
input wire rst,
output wire [7:0] pc_out,
output wire [15:0] A_out,
output wire [15:0] mdr_out
);
// Internal registers
reg [15:0] inst_reg;
wire [15:0] MDR; // concurrent assignment
reg [15:0] A;
reg [7:0] PC;
reg [7:0] MAR;
reg mem_write;
// Drivin... | 8.149568 |
module \1dff (
q, // Q output
\q~ , // Q_out output
d, // D input
cl$k, // CLOCK input
\reset* // Reset input
);
input d, cl$k, \reset* ;
output q, \q~ ;
endmodule
| 7.062834 |
module Escape_Top( input clk,
input rst,
input key_clk,
input key_data,
output reg [2:0] r,
output reg [2:0] g,
output reg [1:0] b,
output hs,
output vs
);
wire [7:0] key_out; //key pressed
reg [1:0] p_c, e_c; //choice of player and enemy
wire ... | 8.805101 |
module ESLab_VGA (
CLOCK_50,
VGA_R,
VGA_G,
VGA_B,
VGA_BLANK_N,
VGA_CLK,
VGA_HS,
VGA_SYNC_N,
VGA_VS,
KEY,
SW,
LEDR,
LEDG
);
wire start, reset;
input CLOCK_50;
//input KEY[0],KEY[1],KEY[2],KEY[3];
output [7:0] VGA_B;
output VGA_BLANK_N;
output reg VGA_CLK;
... | 8.496904 |
module esp32_spi_gamepad #(
parameter integer PAD_BUTTONS = 12
) (
input clk,
input reset,
// ESP32 reset support
input user_reset,
output esp32_en,
output esp32_gpio0,
output esp32_gpio12,
// SPI gamepad input
input spi_csn,
input spi_clk,
input spi_mosi,
outpu... | 8.977602 |
module (ESPMRX) and transmitting
* module (ESPMTX) of the duplex communication between the dVRK board
* and the ESPM board on the da Vinci Si PSM.
* The communication is in three stages.
* FRAME: Looks for 32-bit frame, 32'hAC450F28
* R_DATA: Expects 25 32-bit words
*... | 8.009 |
modules before without altering them */
module EST
(
input wire cin,
input wire [14:0] x1,
input wire [14:0] x2,
output wire [15:0] U,
output wire [15:0] V
);
wire [14:0] tempU, tempV;
assign tempU = cin ? ~x1+1 : x1;
assign tempV = cin ? ~x2+1 : x2;
assign U = {1'b0, tempU ... | 7.13734 |
module estNormDistPNNegSumS (
a,
b,
out
);
parameter N = 24;
parameter size = 50;
localparam normDistSize = `ceilLog2(size + N);
input [size-1:0] a, b;
output [normDistSize-1:0] out;
wire [size-1:0] key;
reg [normDistSize-1:0] out;
integer i;
assign key = (a ^ b) ^~ ((a & b) << 1);
... | 6.659157 |
module estNormDistPNPosSumS (
a,
b,
out
);
parameter N = 24;
parameter size = 50;
localparam normDistSize = `ceilLog2(size + N);
input [size-1:0] a, b;
output [normDistSize-1:0] out;
wire [size-1:0] key;
reg [normDistSize-1:0] out;
integer i;
assign key = (a ^ b) ^ ((a | b) << 1);
... | 6.659157 |
module ES_IMM_Decoder #(
parameter size = 32
) (
input [size-1 : 0] instruction,
output [size-1 : 0] IMM_out
);
wire [size-1:0] I_imm;
wire [size-1:0] S_imm;
wire [size-1:0] B_imm;
wire [size-1:0] U_imm;
wire [size-1:0] J_imm;
wire [2:0] IMM_sel;
wire S;
wire B;
wire U;
wire J;
as... | 7.479755 |
module es_trng (
rst,
clk,
gen,
rnb,
val
);
parameter Ne = 3; // number of entropy sources
input rst, clk;
input gen;
output rnb;
output val;
wire fro1_ena;
wire fro2_ena;
wire clr;
wire valid;
wire ran_bit;
es_trng_ctrl ctrl_ins (
.rst(rst),
.clk(clk),
.... | 7.147875 |
module es (
fro1_ena,
fro2_ena,
clr,
valid,
ran_bit
);
input fro1_ena, fro2_ena, clr;
output valid, ran_bit;
//free-running ring oscillator 1
wire fro1_lut_nand_o;
(* dont_touch = "true", ALLOW_COMBINATORIAL_LOOPS = "true", KEEP = "true" *)wire fro1_fb;
LUT2 #(
.INIT(4'b1000)
) ... | 7.410882 |
module es_trng_ctrl (
rst,
clk,
gen,
rnb,
val,
fro1_ena,
fro2_ena,
clr,
valid,
ran_bit
);
input rst, clk;
input gen;
output reg rnb;
output reg val;
output reg fro1_ena;
output reg fro2_ena;
output reg clr;
input valid;
input ran_bit;
//FSM controller
lo... | 7.060677 |
module eTBDECISION_322.v
Traceback Decision Unit for (3,2,2) decoder
Determine pointer to initial state for traceback
by finding the state with minimum accumulated metric
==================================================================*/
`timescale 1 ns/1 ns
module eTBDECISION_322 (best_state,
... | 6.548268 |
module etc1_sat_add (
input [4:0] table_index,
input [7:0] colour_in,
output [7:0] sum_out
);
reg [8:0] table_colour;
always @(*) begin
case (table_index)
5'd0: table_colour = 9'd2;
5'd1: table_colour = 9'd8;
5'd2: table_colour = 9'd510;
5'd3: table_colour = 9'd504;
... | 6.767274 |
module etc1_decode (
input clk,
input reset,
input [63:0] block,
input [ 1:0] x,
input [ 1:0] y,
output [23:0] pixel
);
wire [32:0] palette;
assign palette = block[63:32];
// diffbit 0
// 4:4:4 => 8:8:8
wire [23:0] base0_non_diff = {
palette[31:28], palette[31... | 7.176706 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.