code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module enc_bcd_tb;
reg [9:0] a;
wire [3:0] out;
integer idx = 0;
`define TEST_CASE(VAR, VALUE) \
idx = idx + 1; \
if(VAR == VALUE) $display("Case %d passed!", idx); \
else begin $display("Case %d failed!", idx); $finish; end
enc_bcd dut (
.a (a),
.out(out)
);
ini... | 6.62427 |
module enc_btn (
input wire clk,
input wire btn_l_pin_i,
input wire btn_r_pin_i,
input wire btn_u_pin_i,
input wire btn_d_pin_i,
input wire btn_c_pin_i,
output reg move_en_o,
output reg [1:0] direct_o,
output reg rst,
output wire press_vali_o
);
reg [`RS... | 8.207098 |
module enc_filter (
input sys_clk,
input filter_nrst,
input filter_en,
input enc_a_in,
input enc_b_in,
input enc_z_in,
output reg enc_a_out_r = 1'b0,
output reg enc_b_out_r = 1'b0,
output reg enc_z_out_r = 1'b0
);
reg [2:0] enc_a_r = 3'd0;
reg [2:0] enc_b_r = 3'd0;
reg [2:0]... | 6.708799 |
module enc_gray (
input wire [7:0] a,
output wire [2:0] out
);
assign out[2] = a[7] | a[6] | a[5] | a[4];
assign out[1] = a[5] | a[4] | a[3] | a[2];
assign out[0] = a[6] | a[5] | a[2] | a[1];
endmodule
| 6.601927 |
module enc_gray_tb;
reg [7:0] a;
wire [2:0] out;
integer idx = 0;
`define TEST_CASE(VAR, VALUE) \
idx = idx + 1; \
if(VAR == VALUE) $display("Case %d passed!", idx); \
else begin $display("Case %d failed!", idx); $finish; end
enc_gray dut (
.a (a),
.out(out)
);
i... | 6.669848 |
module is detect the rise and fall of the clock
//
//
//================================================================================
// Revision History :
// V1.0 2012-12-12 FPGA IP Grp, first created
// V2.0 2013-03-01 FPGA IP Grp, support spi data width of 8,16,32
// V3.0 2013-03-01 FPGA IP... | 7.608524 |
module: Enc_lag3_pipe
// Dependencies: Enc_lag3.v
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Enc_lag3_test;
`include "paramList.v"
// Inputs
reg clk;
reg reset;
reg start;
reg Enc_lag3MuxSe... | 6.580867 |
module enc_param (
i_one_hot,
o_bin,
o_active
);
parameter ONEHOT_WIDTH = 16;
parameter BIN_WIDTH = $clog2(ONEHOT_WIDTH);
input [ONEHOT_WIDTH-1:0] i_one_hot;
output [BIN_WIDTH-1:0] o_bin;
output o_active;
genvar i, j;
assign o_active = |i_one_hot;
generate
for (j = 0; j < BIN_WIDTH;... | 7.252426 |
module testbench;
parameter DELAY = 20;
reg [15:0] one_hot;
wire [ 3:0] bin;
wire active;
enc_param #(
.ONEHOT_WIDTH(16)
) enc_inst (
.i_one_hot(one_hot),
.o_bin(bin),
.o_active(active)
);
initial begin
one_hot = 16'b0;
#DELAY;
one_hot = 16'b1;
repe... | 7.015571 |
module enc_synd_calc #(
parameter P_D_WIDTH = 21,
parameter P_SYND_GEN = 1 // 0 -> parity generator, 1-> syndrome generator
) (
input wire [fn_calc_dat_ecc_width(P_D_WIDTH,P_SYND_GEN)-1:0] d_i,
output wire [ fn_ecc_synd_width(P_D_WIDTH)-1:0] p_o
);
//*******************************... | 7.343287 |
module enc_synd_calc_dec #(
parameter P_D_WIDTH = 21,
parameter P_SYND_GEN = 1 // 0 -> parity generator, 1-> syndrome generator
) (
input wire [30:0] d_i,
output wire [ 9:0] p_o
);
//**********************************************************************
`include "bch_func.inc"
//****... | 7.343287 |
module enc_synd_calc_enc #(
parameter P_D_WIDTH = 21,
parameter P_SYND_GEN = 0 // 0 -> parity generator, 1-> syndrome generator
) (
input wire [P_D_WIDTH-1:0] d_i,
output wire [9:0] p_o
);
//**********************************************************************
`include "bch_func.inc"
... | 7.343287 |
module: Encoder
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module enc_test;
// Inputs
reg clk;
reg pulse;
reg reset;
// Outputs
wire [6:0] enc;
wire new_clk;
// Instantiate t... | 7.373394 |
module enDataIn (
dataOut,
dataIn,
enDataIn
);
output reg [7:0] dataOut;
input wire [7:0] dataIn;
input wire enDataIn;
always @(enDataIn) begin
if (enDataIn) begin
dataOut <= dataIn;
end
end
endmodule
| 7.639758 |
module enDataOut (
dataOut,
dataIn,
enDataOut
);
output reg [7:0] dataOut;
input wire [7:0] dataIn;
input wire enDataOut;
always @(enDataOut) begin
if (enDataOut) begin
dataOut <= dataIn;
end
end
endmodule
| 7.777115 |
module endframeVGA (
input wire [22:0] strVGA, // Stream VGA input.
output wire endframe // End frame signal.
);
// Dimensions.
localparam width_screen = 800;
localparam height_screen = 600;
// Alias address in stream.
`define XC 22:13
`define YC 12:3
// Check endframe.
assign end... | 6.986947 |
module endian_exchange #(
parameter DATA_WIDTH = 32, // 数据总线宽度
parameter UNIT_WIDTH = 8 // 存储单元宽度
) (
input [DATA_WIDTH-1:0] din, // input data
output reg [DATA_WIDTH-1:0] dout, // output data
input en
);
localparam EXC_NUM = DATA_WIDTH / UNIT_WIDTH; // 交换次数
... | 8.805854 |
module endian_swap #(
parameter BYTES = 1
) (
input [0:8*BYTES-1] data_in,
input little_endian,
output [0:8*BYTES-1] data_out
);
genvar i;
generate
for (i = 0; i < BYTES; i = i + 1) begin : block
assign data_out[8*i:8*i+7] = (little_endian) ?
data_in[8*(BYTE... | 7.966474 |
module converts little endian to big endian.
module endian_transformer (
input [31:0] input_32,
output [31:0] output_32
);
assign output_32 = {input_32[7:0], input_32[15:8], input_32[23:16], input_32[31:24]};
endmodule
| 6.805339 |
module ending (
input clk,
input [10:0] pos_x,
input [10:0] pos_y,
input [5:0] count,
output reg [3:0] endingr,
output reg [3:0] endingg,
output reg [3:0] endingb,
output reg isendingregion
);
reg [18:0] pic_addr;
wire [11:0] pic_color;
reg [11:0] font_color;
always @(posedge... | 6.7766 |
module endless_reader (
input wire clk,
input wire rst_n,
input wire [31:0] image_size,
output wire mem_master_control_fixed_location,
output wire [31:0] mem_master_control_read_base,
output wire [31:0] mem_master_control_read_length,
output wire mem_master_control_go,
input wire mem_m... | 6.73444 |
module color_mapper (
input wire [ 3:0] short,
output wire [32:0] long
);
assign long = (short[3] == 1'b0) ? ({
short[0]?8'hff:8'h00,
short[1]?8'hff:8'h00,
short[2]?8'hff:8'h00,
8'hff
}):(
(short == 4'hf) ? 32'h00_00_00_02 : (
(short == 4'he) ? 32'h00_00_00_01 : 32'h00_00_00_00
)
);
endmodu... | 6.645748 |
module ENdreg #(
parameter WIDTH = 32
) (
input wire clk,
input wire rst,
input wire EN,
input wire [WIDTH-1:0] d,
output reg [WIDTH-1:0] q
);
always @(posedge clk, posedge rst) begin
if (rst) q <= 0;
else if (EN) q <= d;
else q <= q;
end... | 8.184632 |
module end_bgm (
input mp3_clk,
input rst,
input DREQ,
output RSET,
output CS,
output DCS,
output MOSI,
output SCLK
);
parameter MUSIC_SIZE = 53353;
wire [20:0] mp3_addr;
wire [31:0] mp3_data;
wire music_over;
mp3_driver #(
.MUSIC_SIZE(MUSIC_SIZE)
) display_music ... | 7.183324 |
module end_goal (
flag,
x_cord,
y_cord,
clock
);
// input values
input [8:0] x_cord, y_cord;
input clock;
// output values
output [2:0] flag;
reg [2:0] colour;
always @(posedge clock) begin
// set the default value for collision checking
colour = 3'b111;
if (x_cord >= 9'd... | 6.531613 |
module end_of_blk_decoding (
reset_n,
cavlc_decoder_state,
TotalCoeff,
i_TotalCoeff,
end_of_one_residual_block,
end_of_NonZeroCoeff_CAVLC
);
input reset_n;
input [3:0] cavlc_decoder_state;
input [4:0] TotalCoeff;
input [3:0] i_TotalCoeff;
output end_of_one_residual_block;
output end_... | 6.687777 |
module end_part (
input vga_clk, //VGA时钟，25.175MHz
input rst, //置位信号，高电平有效
input ena, //模块有效信号
output reg [3:0] red, //输出到VGA的红色数据信号
output reg [3:0] green, //输出到VGA的绿色数据信号
output reg [3:0] blue, //输出到VGA的蓝色数据信号
output hs, //行时序有效信号
output vs, //场时序有效信号
//mp3
input mp3_cl... | 7.721255 |
module enemyControl (
clk,
resetn,
enable,
updatePosition,
bottomReached,
inResetState,
inUpdatePositionStateE,
collidedWithBullet,
collidedWithPlayer,
maxHealth,
currHealth,
score
);
input clk, resetn, enable, updatePosition, bottomReached, collidedWithBullet, collided... | 6.945147 |
module enemyenable (
clock,
start,
enable
); //Behavioural code for clock divider
input clock;
//input CLOCK_50; //50MHz clock;
input start;
output enable;
wire [26:0] count; //Stores the count value
twentySevenBitCounter counter27bit (
clock,
start,
enable,
count
... | 6.907676 |
module twentySevenBitCounter (
clock,
start,
reset_synch,
count
); //Behavioral code for 25bit counter with active high synch reset
input clock; //50MHz clock;//Clock signal
input start;
input reset_synch; //Active high synch reset
output reg [26:0] count = 27'd0; //Stored number initialized... | 6.550814 |
module enemyenable (
clock,
reset,
start,
enable
); //Behavioural code for clock divider
input clock; //50MHz clock;
input start;
input reset;
output enable;
wire [26:0] count; //Stores the count value
twentySevenBitCounter counter27bit (
clock,
start,
reset,
e... | 6.907676 |
module twentySevenBitCounter (
clock,
start,
reset,
reset_synch,
count
); //Behavioral code for 25bit counter with active high synch reset
input clock; //50MHz clock;//Clock signal
input start, reset;
input reset_synch; //Active high synch reset
output reg [26:0] count = 27'd0; //Stored ... | 6.550814 |
module enemy_collision (
input direction, // current direction of yoshi
input wire [9:0] y_x,
y_y, // yoshi x/y
input wire [9:0] g_c_x,
g_c_y, // ghost_crazy x/y
input wire [9:0] g_t_x,
g_t_y, // ghost_top x/y
input wire [9:0] g_b_x,
g_b_y, // ghost_bottom x/y
... | 8.481058 |
module enemy_gun_handler (
clock,
gun_cooldown,
startGameEn,
enemy_shoot
);
input clock; // 50mhz clock from de2 board
input [3:0] gun_cooldown; // 4 bit value keeping trck of the gun's cooldown, overheats when it reaches 4'b1111
input startGameEn; // FSM reset signal to reset everything
outpu... | 6.504218 |
module enemy_laser_controller (
input clk,
input [2:0] random_3,
input [1:0] state,
input [7:0] enemy_enable,
output reg [7:0] enemy_waring_enable,
output reg [7:0] enemy_laser_enable
);
always @(posedge clk) begin
case (state)
0: enemy_waring_enable <= 0;
1:
if(enemy_war... | 6.658499 |
module enemy_movement_handler (
clock,
x_val,
startGameEn
);
input clock; // 50mhz clock from de2 board
input startGameEn; // reset signal to reset the game
output reg [7:0] x_val; // output values
wire [27:0] rd_2hz_out;
rate_divider rd_2hz (
.enable(1'b1),
.countdown_start(28'd2... | 7.501018 |
module
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module energy_detection_module(
input clo... | 7.088073 |
module enet_dp_ram #(
parameter WIDTH = 32
, parameter ADDR_W = 5
) (
// Inputs
input clk0_i
, input [ADDR_W-1:0] addr0_i
, input [ WIDTH-1:0] data0_i
, input wr0_i
, input clk1_i
, input [ADDR_W-1:0] addr1_i
, input [ WIDTH-1:0] data1_... | 7.506218 |
module enfreq (
input clk,
input rst,
output reg [3:0] syscnt
);
parameter DIVCNT_MAX = 5'd19;
reg [4:0] divcnt;
reg clk_en;
/////////////////////////////////////////
// ʱ 20 Ƶ
////////////////////////////////////////
always @(posedge clk or negedge rst) begin
... | 6.98457 |
module engine_ctrl #(
parameter N_CORES = 3,
parameter N_CORES_MSB = `MSB(N_CORES - 1),
parameter N_THREADS = 2 * N_CORES,
parameter N_THREADS_MSB = `MSB(2 * N_CORES - 1),
parameter COMP_INTERVAL = 144 / N_THREADS
) (
input CLK,
output reg [N_CORES-1:0] core_start = 0
//output reg core_m... | 6.693613 |
module busy_updown_alloc (
busy,
regCnt,
retCnt,
busy_new
);
input [6:0] busy;
input [3:0] regCnt;
input [3:0] retCnt;
output [6:0] busy_new;
wire [3:-3] en;
assign en[3] = regCnt[3] && retCnt[0];
assign en[2] = (regCnt[3] && retCnt[1]) || (regCnt[2] && retCnt[0]);
assign en[1] = (... | 6.802474 |
module get_flag_infl (
rs0i1_flagDep,
rs0i2_flagDep,
rs1i1_flagDep,
rs1i2_flagDep,
rs2i1_flagDep,
rs2i2_flagDep,
srcFlight,
infl
);
input [3:0] rs0i1_flagDep;
input [3:0] rs0i2_flagDep;
input [3:0] rs1i1_flagDep;
input [3:0] rs1i2_flagDep;
input [3:0] rs2i1_flagDep;
input [3... | 6.827408 |
module get_funit (
rs0i0_index,
rs0i0_port,
rs0i0_en,
rs0i1_index,
rs0i1_port,
rs0i1_en,
rs0i2_index,
rs0i2_port,
rs0i2_en,
rs1i0_index,
rs1i0_port,
rs1i0_en,
rs1i1_index,
rs1i1_port,
rs1i1_en,
rs1i2_index,
rs1i2_port,
rs1i2_en,
rs2i0_index,
... | 7.308976 |
module get_LDQ_new_en (
rs0i0_port,
rs0i0_ldst_flg,
rs1i0_port,
rs1i0_ldst_flg,
rs2i0_port,
rs2i0_ldst_flg,
rs0i1_port,
rs0i1_ldst_flg,
rs1i1_port,
rs1i1_ldst_flg,
rs2i1_port,
rs2i1_ldst_flg,
new_mask
);
localparam PORT_WIDTH = 4;
localparam PORT_LOAD = 4'd1;
... | 6.774333 |
module wrtdata_combine (
data,
dataN,
pdata,
en,
odata,
odataN,
opdata,
low,
sz
);
input [135:0] data;
input [135:0] dataN;
input [1:0] pdata;
input en;
output [127:0] odata;
output [127:0] odataN;
output [1:0] opdata;
input [1:0] low;
input [4:0] sz;
generate
... | 7.415588 |
module get_lsi_en (
lsi0,
flag0,
lsi1,
flag1,
lsi2,
flag2,
lsi3,
flag3,
lsi4,
flag4,
lsi5,
flag5,
lsi_en
);
input [2:0] lsi0;
input flag0;
input [2:0] lsi1;
input flag1;
input [2:0] lsi2;
input flag2;
input [2:0] lsi3;
input flag3;
input [2:0] lsi4;... | 6.796278 |
module csrss_watch (
clk,
rst,
csrss_addr,
csrss_data,
csrss_en,
data_out
);
parameter [15:0] ADDR = 16'b0;
parameter [63:0] INITVAL = 64'b0;
input clk;
input rst;
input [15:0] csrss_addr;
input [63:0] csrss_data;
input csrss_en;
output reg [1:0][63:0] data_out;
always @(posed... | 7.056735 |
module cmpx4(
clk,
clkREF,
clkREF2,
clkREF3,
clkREF4,
data_in,
data_out);
parameter WIDTH=65;
input clk;
input clkREF;
input clkREF2;
input clkREF3;
input clkREF4;
input [WIDTH-1:0] data_in;
output [WIDTH-1:0] data_out;
wire [3:0][WIDTH-1:0] dataREG;
`ifdef simulation
assign d... | 7.147718 |
module enh_fp_adder (
input wire sign1,
sign2,
input wire [3:0] exp1,
exp2,
input wire [7:0] frac1,
frac2,
output reg sign_out,
output reg [3:0] exp_out,
output reg [7:0] frac_out
);
// signal declaration
// suffixes:
// b - big
// s - small
// a - aligne... | 7.573737 |
module enh_fp_adder_test (
input wire clk,
input wire [15:0] sw,
output wire [ 3:0] an,
output wire [ 7:0] sseg
);
// signal declaration
wire sign1, sign2, sign_out;
wire [3:0] exp1, exp2, exp_out;
wire [7:0] frac1, frac2, frac_out;
wire [7:0] led0, led1, led2, led3;
// body
// ... | 7.798409 |
module enigma (
input wire clk,
input wire rset,
input wire [14:0] offset_init, //3 ring * 5 bits
input wire [14:0] ringst_init,
input wire [25*5+4:0] plug_tbl,
input wire [7:0] in_char,
input wire in_char_write,
output wire [7:0] out_char,
output reg out_char_ready
);
`include "... | 6.681122 |
module decodificador (
number,
display
);
input [3:0] number;
output reg [0:6] display;
always @(number) begin
case (number)
1: display <= 7'b1001111;
2: display <= 7'b0010010;
3: display <= 7'b0000110;
4: display <= 7'b1001100;
5: display <= 7'b0100100;
6: displa... | 6.55702 |
module enpoint_arbitration (
input trn_clk,
input trn_lnk_up_n,
// Rx
output reg rx_turn,
input rx_driven,
// Tx
output reg tx_turn,
input tx_driven
);
wire reset_n;
// localparam
localparam s0 = 8'b00000000;
localparam s1 = 8'b00000001;
localparam s2 = 8'b00000... | 6.535519 |
module EnRegister (
clk,
pi,
po,
en,
rst
);
parameter size = 8;
input clk, en, rst;
input [size-1:0] pi;
output reg [size-1:0] po = 0;
always @(posedge clk) begin
if (rst) po <= 0;
else if (en) po <= pi;
end
endmodule
| 6.928683 |
module PS2_Demo (
// Inputs
CLOCK_50,
KEY,
// Bidirectionals
PS2_CLK,
PS2_DAT,
// Outputs
enter_pressed_out,
esc_pressed_out
);
/*****************************************************************************
* Parameter Declarations ... | 8.682108 |
module entrada (
switches_fpga,
In,
saida_RE
);
input [9:0] switches_fpga;
input In;
output reg [31:0] saida_RE;
always @(*) begin
saida_RE = 32'b0;
if (In) saida_RE = switches_fpga;
end
endmodule
| 6.757674 |
module Parallel_IN (
input [7:0] MemData,
Address,
DataIn,
output reg [7:0] RegData
);
always @* begin
if (Address == 8'hFF) RegData = DataIn;
else RegData = MemData;
end
endmodule
| 7.05273 |
module entradaSwitches (
input [15:0] switches,
input enter,
input clk_read,
output reg [15:0] imediato,
output espera
);
always @(posedge clk_read) begin
if (enter) imediato <= switches;
end
assign espera = ~enter;
endmodule
| 7.966153 |
module tri_length_control (
attack,
decay,
length,
enable_out,
rst,
note_clk,
square_in,
square_out
);
input rst; //this input reloads the length counter
input [1:0] attack;
input [1:0] decay;
input [2:0] length;
output reg enable_out; //enable_out is the control signal which... | 8.427392 |
module enviroment_map #(
parameter LOCATION_LENGTH = 6,
parameter MAP_SIZE = 25,
parameter MAP_DATA_FILE = "C:/Users/Hoang Thien/OneDrive/LSIDesign_2020/Q_and_DynaQ/map_data/map_data_file_5x5_2.txt"
) (
input wire clk,
input wire reset,
input wire [LOCATION_LENGTH - 1 : 0] w_ad... | 6.606346 |
module envolve_core (
input clk,
input reg has_wall
);
parameter CANVAS_WIDTH = 128;
parameter CANVAS_HEIGHT = 96;
reg core_num;
reg clka;
reg write_en;
wire addr;
reg [3:0] neibor_0;
reg [3:0] neibor_1;
reg [3:0] neibor_2;
reg [127:0] din1;
reg [127:0] dout1;
reg [127:0] din0;
reg ... | 6.710318 |
module env_rate_counter (
input wire clk,
input wire sample_clk_en,
input wire [`BANK_NUM_WIDTH-1:0] bank_num,
input wire [`OP_NUM_WIDTH-1:0] op_num,
input wire ksr, // key scale rate
input wire nts, // keyboard split selection
input wire [`REG_FNUM_WIDTH-1:0] fnum,
input wire [`RE... | 6.814231 |
module en_cnt (
input wire clk,
input wire rstn,
input wire en,
output reg [31:0] cnt
);
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
cnt <= 0;
end else begin
if (en) begin
cnt <= cnt + 1;
end
end
end
endmodule
| 8.07711 |
module EN_FOR_CHANGE_FSM (
clk,
rst,
sel,
en
);
//Inputs
input clk, rst, sel;
//Outputs
output reg en;
//States S0 means 0->1, S1 means 1->1 S2 means 1->0, S2 state means the user finish selecting
//Once FSM leaves S0, it would not come back to S0
//S0 needed for inital start after reset... | 6.756095 |
module EN_FOR_CHANGE_FSM_TB;
reg RST = 0, CLK = 1, SEL = 0;
wire EN;
integer i;
EN_FOR_CHANGE_FSM DUT (
.clk(CLK),
.rst(RST),
.sel(SEL),
.en (EN)
);
initial begin
CLK = 1;
#5;
for (i = 0; i < 40; i = i + 1) begin
//RST
RST = (i == 1 | i == 31) ? 1 : 0;
... | 6.756095 |
module en_gen (
//inputs
haddr,
haddr_reg,
hsize,
hsize_reg,
rd_aphase,
wr_dphase,
rd_dphase,
RW_conf_dphase,
//Outputs
cen,
wen,
SRAM_addr
);
//------------Ports----------------------------------
input [31:0] haddr, haddr_reg;
input [2:0] hsize, hsize_reg;
i... | 7.472651 |
module en_nrzi (
clk,
rst,
data_in,
DP,
DM,
en_nrzi
);
input clk, rst, data_in, en_nrzi;
output DP, DM;
reg en_data_DP, DP, DM;
reg data_bf;
/*
assign DM = (!rst) ? 1'b1 : ~DP;
always @(data_in, en_data_DP)
begin
DP <= ~(data_in ^ en_data_DP);
// DM <= (data_in ^ en... | 7.35876 |
module En_RAM (
feature_start,
feature_stop,
Enable,
RAM_start,
RAM_stop
);
input [11:0] feature_start;
input [11:0] feature_stop; //输入的是真实的维度数
output reg [7:0] Enable; //输出RAM分块的使能
output reg [8:0] RAM_start;//输出的是第一个使能的RAM块的，块内计算的起始特征数
output reg [8:0] RAM_stop;
localparam RAM_widt... | 7.264825 |
module ep2c5t144_clock_gen
(input wire i_clk,
output wire o_clk,
output wire o_rst);
wire locked;
reg [9:0] r;
assign o_rst = r[9];
always @(posedge o_clk)
if (locked)
r <= {r[8:0],1'b0};
else
r <= 10'b1111111111;
altpll altpll_component (
.inclk (i_clk),
... | 6.792326 |
module epb_wb_bridge (
clk,
reset,
epb_cs_n,
epb_oe_n,
epb_we_n,
epb_be_n,
epb_addr,
epb_data_i,
epb_data_o,
epb_data_oe,
epb_rdy_o,
epb_rdy_oe,
wb_cyc_o,
wb_stb_o,
wb_we_o,
wb_sel_o,
wb_adr_o,
wb_dat_o,
wb_dat_i,
wb_ack_i
);
input clk, r... | 7.410662 |
module epcs (
// inputs:
address,
chipselect,
clk,
data0,
read_n,
reset_n,
write_n,
writedata,
// outputs:
dataavailable,
dclk,
endofpacket,
irq,
readdata,
readyfordata,
sce,
sdo
);
parameter INIT_FILE = "epcs_boot_rom.hex";
output dataavai... | 6.66202 |
module epcs_controller (
// inputs:
address,
chipselect,
clk,
read_n,
reset_n,
write_n,
writedata,
... | 6.53685 |
module Epipe (
clk,
clr,
stall,
res_d,
instr_d,
a1_d,
a2_d,
a3_d,
v1_d,
v2_d,
oth_d,
pc8_d,
bd_d,
exccode_d,
res_e,
instr_e,
a1_e,
a2_e,
a3_e,
v1_e,
v2_e,
oth_e,
pc8_e,
bd_e,
exccode_e
);
input clk, clr, stall, bd_d;
... | 6.612543 |
module EPJ (
clk,
rst,
a,
unlock,
enter,
h1,
h2,
h3,
h4
);
output reg unlock;
input clk, rst, enter;
input [0:9] a;
output reg [0:6] h1;
output reg [0:6] h2;
output reg [0:6] h3;
output reg [0:6] h4;
reg [2:0] state;
reg [2:0] next_state;
parameter [2:0] s_rst =... | 7.115999 |
module epm7064_clock (
clk,
dig_sel,
segs,
btn_HH,
btn_MM,
btn_SS,
btn_SAFE,
led_second_tick
);
input wire clk;
output wire [3:0] dig_sel;
output wire [6:0] segs;
output wire led_second_tick;
input wire btn_HH, btn_MM, btn_SS, btn_SAFE;
wire SAFE_MODE = ~btn_SAFE;
//clk ... | 7.740225 |
module EppStartAddress (
rst,
clk,
wr,
ad,
dbi,
dbo,
myad,
trigger,
startAddress
);
input rst;
input clk;
input wr;
input [7:0] ad;
input [7:0] dbi;
output [7:0] dbo;
reg [7:0] dbo;
output myad;
output trigger;
output [47:0] startAddress;
reg [47:0] startAddress... | 6.868056 |
module eproto_tx ( /*AUTOARG*/
// Outputs
emtx_rd_wait,
emtx_wr_wait,
emtx_ack,
txframe_p,
txdata_p,
// Inputs
reset,
emtx_access,
emtx_write,
emtx_datamode,
emtx_ctrlmode,
emtx_dstaddr,
emtx_srcaddr,
emtx_data,
txlclk_p,
tx_rd_wait,
tx_wr_wait
);... | 7.70178 |
module epwm (
input clk,
reset,
input [3:0] d,
w,
output reg pulse
); // I-O Ports Declaration
reg [3:0] d_reg;
reg [3:0] w_reg;
always @(posedge clk) //Positive Edge Triggering
begin
if (reset) begin
d_reg <= 0;
w_reg <= 0; //Reset sequence
pulse <= 0;
end
... | 7.392659 |
module epwmblock #(
parameter CNT_WIDTH = 8,
DIV_WIDTH = 8
) (
input clk,
input reset,
input [CNT_WIDTH-1:0] endval,
input [CNT_WIDTH-1:0] match,
input [DIV_WIDTH-1:0] scale,
output pwm
);
pwmblock #(
.CNT_WIDTH(CNT_WIDTH),
.DIV_WIDTH(DIV_WIDTH)
) pwmb (
clk,
... | 7.340002 |
module ep_rst (
input clk250,
input trn_reset_n,
input trn_lnk_up_n,
output reg rst250
);
// localparam
localparam s0 = 15'b000000000000000;
localparam s1 = 15'b000000000000001;
localparam s2 = 15'b000000000000010;
localparam s3 = 15'b000000000000100;
localparam s4 = 15'b000... | 8.09755 |
module ep_tb #(
parameter TCQ = 100
);
// Internal regs and nets declaration
wire sys_clk;
wire sys_clk_sim;
reg ep_tb_reset_n;
wire srio_txp0;
wire srio_txn0;
wire srio_txp0_sim;
wire srio_txn0_sim;
wire srio_rxp0;
wire srio_rxn0;
wire srio_rxp0_sim;
wire srio_rxn0_sim;
assign srio_... | 6.93192 |
module implements the equation Xnew = A*Y + B*U + I
// It takes in the A template, B template, I template, U input, Y matrix and gives the output which is Ynew
// The values are defined to be 9 bits since we want it to be signed.
`define WIDTH 9
module eq1 (
A1, A2, A3, A4, A5, A6, A7, A8, A9,
B1, B2, B3, B4, B5,... | 7.842559 |
module eq1_always (
input wire i0,
i1,
output reg eq // eq declared as reg
);
// p0 and p1 declared as reg
reg p0, p1;
always @(i0, i1) // i0 an i1 must be in sensitivity list
begin
// the order of statements is important
p0 = ~i0 & ~i1;
p1 = i0 & i1;
eq = p0 | p1;
end
endmo... | 6.708179 |
module implements the Y = 1/2*{|X+1|-|X-1|} equation
// Here X is the initial X.
`define WIDTH 9
module eq2 (
X,
out
);
input wire signed [2 * `WIDTH - 1:0] X;
wire signed [2 * `WIDTH - 1:0] Xplus1;
wire signed [2 * `WIDTH - 1:0] Xminus1;
wire signed [2 * `WIDTH - 1:0] Xplus;
wire signed [2 * `WIDTH - 1:0] Xmin... | 7.842559 |
module eq2 (
input wire [1:0] a,
b,
output wire res1
);
wire r1, r2;
// Call to Module eq1 which is 1 Bit Comparator
eq1 Bit0 (
.i0(a[0]),
.i1(b[0]),
.eq(r1)
);
eq1 Bit1 (
.i0(a[1]),
.i1(b[1]),
.eq(r2)
);
assign res1 = r1 & r2;
endmodule
| 7.299338 |
module EQ2 (
input [1:0] I0,
input [1:0] I1,
output O
);
wire inst0_O;
SB_LUT4 #(
.LUT_INIT(16'h9009)
) inst0 (
.I0(I0[0]),
.I1(I1[0]),
.I2(I0[1]),
.I3(I1[1]),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 6.852235 |
module main (
input [3:0] J1,
output J3
);
wire inst0_O;
EQ2 inst0 (
.I0({J1[1], J1[0]}),
.I1({J1[3], J1[2]}),
.O (inst0_O)
);
assign J3 = inst0_O;
endmodule
| 7.081372 |
module EQ2 (
input [1:0] I0,
input [1:0] I1,
output O
);
wire inst0_O;
LUT4 #(
.INIT(16'h9009)
) inst0 (
.I0(I0[0]),
.I1(I1[0]),
.I2(I0[1]),
.I3(I1[1]),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 6.852235 |
module EQ2 (
input [1:0] I0,
input [1:0] I1,
output O
);
wire inst0_O;
LUT4 #(
.INIT(16'h9009)
) inst0 (
.I0(I0[0]),
.I1(I1[0]),
.I2(I0[1]),
.I3(I1[1]),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 6.852235 |
module eq4(
input wire clock,
input wire [3:0] n0, // Slider Input
input wire p1, p2, // Push Buttons
output wire res2
);
reg [3:0] n1, n2; // Two 4 bit numbers to be compared
wire x1, x2;
always @(posedge clock)
if (p1==1) begin // If push button North, Then input of slider to n1
n1 <= n0;
end
if (p2==1... | 7.866145 |
module EQ4 (
input [3:0] I0,
input [3:0] I1,
output O
);
wire inst0_O;
wire inst1_O;
wire inst2_O;
wire inst3_O;
SB_LUT4 #(
.LUT_INIT(16'h8282)
) inst0 (
.I0(1'b1),
.I1(I0[0]),
.I2(I1[0]),
.I3(1'b0),
.O (inst0_O)
);
SB_LUT4 #(
.LUT_INIT(16'h8282)
)... | 6.717664 |
module main (
input [7:0] J1,
output J3
);
wire inst0_O;
EQ4 inst0 (
.I0({J1[3], J1[2], J1[1], J1[0]}),
.I1({J1[7], J1[6], J1[5], J1[4]}),
.O (inst0_O)
);
assign J3 = inst0_O;
endmodule
| 7.081372 |
module EQ4 (
input [3:0] I0,
input [3:0] I1,
output O
);
wire inst0_O;
wire inst1_O;
wire inst2_O;
wire inst3_O;
LUT4 #(
.INIT(16'h9009)
) inst0 (
.I0(I0[0]),
.I1(I1[0]),
.I2(I0[1]),
.I3(I1[1]),
.O (inst0_O)
);
MUXCY inst1 (
.DI(1'b0),
.CI(1'b1... | 6.717664 |
module main (
input [7:0] SWITCH,
output LED
);
wire inst0_O;
EQ4 inst0 (
.I0({SWITCH[3], SWITCH[2], SWITCH[1], SWITCH[0]}),
.I1({SWITCH[7], SWITCH[6], SWITCH[5], SWITCH[4]}),
.O (inst0_O)
);
assign LED = inst0_O;
endmodule
| 7.081372 |
module EQ4 (
input [3:0] I0,
input [3:0] I1,
output O
);
wire inst0_O5;
wire inst0_O6;
wire inst1_O;
wire inst2_O5;
wire inst2_O6;
wire inst3_O;
LUT6_2 #(
.INIT(64'h9009900900000000)
) inst0 (
.I0(I0[0]),
.I1(I1[0]),
.I2(I0[1]),
.I3(I1[1]),
.I4(1'b0),
... | 6.717664 |
module eq4_test;
reg [3:0] inp1, inp2;
wire out;
// Call to Module eq2 which is 2 Bit Comparator
eq4 uut (
.n1 (inp1),
.n2 (inp2),
.res2(out)
);
initial // Test Cases
begin
inp1 = 4'b0000;
inp2 = 4'b0001;
#200;
$display("Result = %d", out);
inp1 = 4... | 6.819052 |
module eq8 (
input wire [7:0] a,
b,
output out
);
wire [7:0] e;
wire ee1, ee2, ee3, ee4;
wire g1, g2, g3, g4;
wire x1, x2, x3;
wire y1, y2;
wire z1, z2;
wire equals, greater;
//check if they're all equal
eq1 eq_bit0_unit (
.i0(a[0]),
.i1(b[0]),
.eq(e[0])
);
eq1 eq_bi... | 7.122433 |
module eqcmp (
input wire [31:0] a,
b,
output wire y
);
assign y = (a == b) ? 1 : 0;
endmodule
| 7.480273 |
module EqModule ( // @[:@3.2]
input clock, // @[:@4.4]
input reset, // @[:@5.4]
input [9:0] io_in, // @[:@6.4]
output [9:0] io_out // @[:@6.4]
);
wire _T_5 = $signed(io_in) == 10'sh0; // @[SIntTypeClass.scala 55:48:@11.4]
assign io_out = _T_5 ? $signed(10'sh1) : $signed(io_in); ... | 6.601793 |
module EqModule (
input clock,
input reset,
input [9:0] io_in,
output [9:0] io_out
);
wire _T_5 = $signed(io_in) == 10'sh0; // @[SIntTypeClass.scala 55:48]
assign io_out = _T_5 ? $signed(10'sh1) : $signed(io_in); // @[TypeclassSpec.scala 38:51]
endmodule
| 7.348157 |
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