code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module exam1_A (
input wire clk,
input wire rst,
input wire signed [`WIDTH-1:0] A,
input wire signed [`WIDTH-1:0] B,
input wire [1:0] ctrl,
output reg signed [`WIDTH*2-1:0] out // You can modify "reg" to "wire" if needed
);
//Your design here
always @(posedge clk or posedge rst) begin
i... | 8.348546 |
module SevenSegment (
output reg [6:0] display,
output reg [3:0] digit,
input wire [15:0] nums, // four 4-bits BCD number
input wire rst,
input wire clk // Input 100Mhz clock
);
reg [15:0] clk_divider;
reg [ 3:0] display_num;
always @(posedge clk, posedge rst) begin
if (rst) begin
... | 7.922915 |
module clock_divider (
clk,
clk_div
);
parameter n = 26;
input clk;
output clk_div;
reg [n-1:0] num;
wire [n-1:0] next_num;
always @(posedge clk) begin
num <= next_num;
end
assign next_num = num + 1;
assign clk_div = num[n-1];
endmodule
| 6.818038 |
module ExamenDSD #(
parameter WORD_LENGTH = 8
) (
// Input Ports
input clk,
input reset,
input start,
input [WORD_LENGTH-1:0] x_input,
output error,
output [WORD_LENGTH-1:0] y_output
);
//---------------Internal signals-----------------------
wire [1:0] Constant_control;
wire [1... | 6.902614 |
module examine (
input clk,
input reset,
input rd,
input examine,
input [7:0] lo_addr,
input [7:0] hi_addr,
output reg [7:0] data_out,
output examine_latch
);
reg [2:0] state = 3'b000;
reg prev_rd = 1'b0;
reg en_lt = 1'b0;
always @(posedge clk) begin
if (reset) begin
... | 7.385846 |
module examine_next (
input clk,
input reset,
input rd,
input examine,
output reg [7:0] data_out,
output examine_latch
);
reg [2:0] state = 3'b000;
reg prev_rd = 1'b0;
reg en_lt = 1'b0;
always @(posedge clk) begin
if (reset) begin
en_lt <= 1'b0;
end else if (examine) begi... | 6.664421 |
module AHB_BUS (
input wire HCLK,
input wire HRESETn,
`AHB_MASTER_BUS_IFC( ),
`AHB_SLAVE_BUS_IFC(S0),
`AHB_SLAVE_BUS_IFC(S1),
`AHB_SLAVE_BUS_IFC(S2),
`AHB_SLAVE_BUS_IFC(S3)
);
// The salves bases addresses
localparam S0_PAGE = 8'h40;
localparam S1_PAGE = 8'h41;
localpa... | 8.588355 |
module top (
input clk,
output LED1,
output LED2,
output LED3,
output LED4,
output LED5
);
localparam BITS = 5;
localparam LOG2DELAY = 22;
function [BITS-1:0] bin2gray(input [BITS-1:0] in);
integer i;
reg [BITS-1:0] temp;
begin
temp = in;
for (i = 0; i < BITS; i ... | 7.233807 |
module AHB_SLAVE_0(
input wire HCLK,
input wire HRESETn,
`AHB_SLAVE_IFC
);
`AHB_SLAVE_EPILOGUE
// R1 is a 20-bit register @ offset 0x20
// It has 3 fields:
// F1 (bit 0), F2 (bit 1), F3 (bits 2:19)
`AHB_REG(R1, 20, 8'h20, 0)
`REG_FIELD(R1, F1, 0, 0)
`REG_FIELD(R1, F2, 1, 1)
... | 6.796919 |
module AHB_SLAVE_1(
input wire HCLK,
input wire HRESETn,
`AHB_SLAVE_IFC
);
`AHB_SLAVE_EPILOGUE
// R1 is a 8-bit register @ offset 0x0
// It has 1 field: F1 (bits 7:0)
// F1 (bit 0), F2 (bit 1), F3 (bits 19:2)
`AHB_REG(R1, 8, 8'h0, 0)
`REG_FIELD(R1, F1, 0, 7)
`AHB_READ
... | 6.745746 |
module AHB_SYS (
input wire HCLK,
input wire HRESETn,
`AHB_MASTER_BUS_IFC()
);
`AHB_SLAVE_SIGNALS(S0)
`AHB_SLAVE_SIGNALS(S1)
`AHB_SLAVE_SIGNALS(S2)
`AHB_SLAVE_SIGNALS(S3)
AHB_BUS BUS (
.HCLK(HCLK),
.HRESETn(HRESETn),
`AHB_MASTER_CONN,
`AHB_SLAVE_BUS_CONN(S0),
`AH... | 6.519246 |
module APB_SYS (
input wire HCLK,
input wire HRESETn,
`AHB_SLAVE_IFC
);
wire PCLK;
wire PRESETn;
`APB_MASTER_SIGNALS
AHB_APB_BRIDGE #(
.SLOW_PCLK(0)
) APB_BR (
.HCLK(HCLK),
.HRESETn(HRESETn),
`AHB_SLAVE_INST_CONN_NP,
// APB Master Port
.PCLK(PCLK),
... | 6.54701 |
module top (
input clk,
input sel,
output LED1,
output LED2,
output LED3,
output LED4,
output LED5,
output LED6,
output LED7,
output LED8
);
localparam BITS = 8;
localparam LOG2DELAY = 22;
function [BITS-1:0] bin2gray(input [BITS+1:0] in);
integer i;
reg [BITS+1... | 7.233807 |
module DMIToTL ( // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@87420.2]
input auto_out_a_ready, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@87423.4]
output [8:0] auto_out_a_bits_address, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@87423.4]
input auto_out_d_valid, ... | 6.634693 |
module AsyncResetRegVec_w32_i0 ( // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@88785.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@88786.4]
input reset, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@88787.4]
input [31:0] io_d, // @[:e... | 6.68936 |
module AsyncResetRegVec_w1_i0 ( // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@88815.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@88816.4]
input reset, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@88817.4]
input io_d, // @[:example.TestHarness.Gem... | 6.68936 |
module IntSyncCrossingSource ( // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@89834.2]
input auto_in_0, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@89837.4]
output auto_out_sync_0 // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@89837.4]
);
assign auto_out_sync_0 = auto_in... | 6.689384 |
module AsyncResetSynchronizerShiftReg_w1_d3_i0( // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@91299.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@91300.4]
input reset, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@91301.4]
input io_d, // @[:example.... | 6.605499 |
module AsyncValidSync ( // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@91451.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@91452.4]
input reset, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@91453.4]
output io_out // @[:example.TestHarness.GemminiSocT... | 6.70336 |
module AsyncResetSynchronizerShiftReg_w1_d1_i0( // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@91481.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@91482.4]
input reset, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@91483.4]
input io_d, // @[:example.... | 6.605499 |
module AsyncValidSync_1 ( // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@91497.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@91498.4]
input reset, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@91499.4]
input io_in, // @[:example.TestHarness.GemminiSo... | 6.70336 |
module AsyncValidSync_2 ( // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@91585.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@91586.4]
input reset, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@91587.4]
input io_in, // @[:example.TestHarness.GemminiSo... | 6.70336 |
module SynchronizerShiftReg_w43_d1( // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@91783.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@91784.4]
input [42:0] io_d, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@91786.4]
output [42:0] io_q // @[... | 6.820992 |
module SynchronizerShiftReg_w55_d1( // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@116649.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@116650.4]
input [54:0] io_d, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@116652.4]
output [54:0] io_q //... | 6.820992 |
module SynchronizerShiftReg_w15_d1( // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@117757.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@117758.4]
input [14:0] io_d, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@117760.4]
output [14:0] io_q //... | 6.820992 |
module IntXbar_4 ( // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@123354.2]
input auto_int_in_3_0, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@123357.4]
input auto_int_in_2_0, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@123357.4]
input auto_int_in_1_0, // @[:exa... | 6.635383 |
module PE ( // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@163986.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@163987.4]
input [7:0] io_inR, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@163989.4]
input [7:0] io_inD, // @[:example.TestHarn... | 7.352624 |
module compressor_3_2_group (
in1,
in2,
in3,
s,
c
);
parameter GRP_WIDTH = 32;
input [GRP_WIDTH-1:0] in1, in2, in3;
output [GRP_WIDTH-1:0] s, c;
compressor_3_2 compress[GRP_WIDTH-1:0] (
in1,
in2,
in3,
s,
c
);
endmodule
| 7.237792 |
module compressor_3_2 (
in1,
in2,
in3,
s,
c
);
input in1, in2, in3;
output s, c;
assign c = (in1 & in2) | (in2 & in3) | (in3 & in1);
assign s = (in1 & in2 & in3) | (in1 & ~in2 & ~in3) | (~in1 & in2 & ~in3) | (~in1 & ~in2 & in3);
endmodule
| 7.237792 |
module booth_encoder (
x,
single,
double,
neg,
pzero,
nzero
);
input [2:0] x;
output single;
output double;
output neg;
output pzero;
output nzero;
wire w0;
wire w1;
assign single = x[0] ^ x[1];
assign neg = x[2];
assign w0 = ~(x[1] ^ x[2]);
assign w1 = (x[0] ^ ... | 7.829276 |
module booth_selector (
double,
shifted,
single,
y,
neg,
p
);
input double;
input shifted;
input single;
input y;
input neg;
output p;
assign p = (neg ^ ((y & single) | (shifted & double)));
endmodule
| 7.153136 |
module HALF_ADDER (
a,
b,
sum,
cout
);
input a;
input b;
output sum;
output cout;
assign sum = a ^ b;
assign cout = a & b;
endmodule
| 6.537169 |
module SynchronizerShiftReg_w1_d3( // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@201601.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@201602.4]
input io_d, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@201604.4]
output io_q // @[:example.TestHarnes... | 6.820992 |
module IntSyncCrossingSink ( // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@201617.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@201618.4]
input auto_in_sync_0, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@201620.4]
output auto_out_0 // @[:example.Test... | 6.689384 |
module IntSyncCrossingSink_1 ( // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@201645.2]
input auto_in_sync_0, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@201648.4]
input auto_in_sync_1, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@201648.4]
output auto_out_0, // @[:... | 6.689384 |
module IntSyncCrossingSink_2 ( // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@201661.2]
input auto_in_sync_0, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@201664.4]
output auto_out_0 // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@201664.4]
);
assign auto_out_0 = auto_in_s... | 6.689384 |
module _1_97 ( // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@209347.2]
input [53:0] io_x_ppn, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@209350.4]
input io_x_d, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@209350.4]
input io_x_a, // @[:example... | 7.048251 |
module AsyncResetRegVec_w2_i0 ( // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@221788.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@221789.4]
input reset, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@221790.4]
input [1:0] io_d, // @[:ex... | 6.68936 |
module IntSyncCrossingSource_2( // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@221803.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@221804.4]
input reset, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@221805.4]
input auto_in_0, // @[:example.TestHarness.... | 6.689384 |
module IntSyncCrossingSource_3( // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@221844.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@221845.4]
input reset, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@221846.4]
input auto_in_0, // @[:example.TestHarness.... | 6.689384 |
module SynchronizerShiftReg_w2_d3( // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@265807.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@265808.4]
input [1:0] io_d, // @[:example.TestHarness.GemminiSocTest1RocketConfig.fir@265810.4]
output [1:0] io_q // @[:... | 6.820992 |
module DMIToTL ( // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@87420.2]
input auto_out_a_ready, // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@87423.4]
output [8:0] auto_out_a_bits_address, // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@87423.4]
input auto_out_d... | 6.634693 |
module AsyncResetRegVec_w32_i0( // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@88785.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@88786.4]
input reset, // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@88787.4]
input [31:0] io_d, ... | 6.68936 |
module AsyncResetRegVec_w1_i0( // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@88815.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@88816.4]
input reset, // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@88817.4]
input io_d, // @[:example.TestHarn... | 6.68936 |
module IntSyncCrossingSource( // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@89834.2]
input auto_in_0, // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@89837.4]
output auto_out_sync_0 // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@89837.4]
);
assign auto_out_sync_0 = ... | 6.689384 |
module AsyncResetSynchronizerShiftReg_w1_d3_i0( // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@91299.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@91300.4]
input reset, // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@91301.4]
input io_d, // @[... | 6.605499 |
module AsyncValidSync ( // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@91451.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@91452.4]
input reset, // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@91453.4]
output io_out // @[:example.TestHarness.Ge... | 6.70336 |
module AsyncResetSynchronizerShiftReg_w1_d1_i0( // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@91481.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@91482.4]
input reset, // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@91483.4]
input io_d, // @[... | 6.605499 |
module AsyncValidSync_1 ( // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@91497.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@91498.4]
input reset, // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@91499.4]
input io_in, // @[:example.TestHarness.... | 6.70336 |
module AsyncValidSync_2 ( // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@91585.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@91586.4]
input reset, // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@91587.4]
input io_in, // @[:example.TestHarness.... | 6.70336 |
module SynchronizerShiftReg_w43_d1( // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@91783.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@91784.4]
input [42:0] io_d, // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@91786.4]
output [42:0] io_q... | 6.820992 |
module SynchronizerShiftReg_w55_d1( // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@116649.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@116650.4]
input [54:0] io_d, // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@116652.4]
output [54:0] i... | 6.820992 |
module SynchronizerShiftReg_w15_d1( // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@117757.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@117758.4]
input [14:0] io_d, // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@117760.4]
output [14:0] i... | 6.820992 |
module IntXbar_4 ( // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@123354.2]
input auto_int_in_3_0, // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@123357.4]
input auto_int_in_2_0, // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@123357.4]
input auto_int_in_1_0, ... | 6.635383 |
module PE ( // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@163602.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@163603.4]
input [7:0] io_inR, // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@163605.4]
input [7:0] io_inD, // @[:example... | 7.352624 |
module SynchronizerShiftReg_w1_d3( // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@201169.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@201170.4]
input io_d, // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@201172.4]
output io_q // @[:example.T... | 6.820992 |
module IntSyncCrossingSink ( // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@201185.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@201186.4]
input auto_in_sync_0, // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@201188.4]
output auto_out_0 // @[:exa... | 6.689384 |
module IntSyncCrossingSink_1( // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@201213.2]
input auto_in_sync_0, // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@201216.4]
input auto_in_sync_1, // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@201216.4]
output auto_out_0, ... | 6.689384 |
module IntSyncCrossingSink_2( // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@201229.2]
input auto_in_sync_0, // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@201232.4]
output auto_out_0 // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@201232.4]
);
assign auto_out_0 = au... | 6.689384 |
module _1_97 ( // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@208915.2]
input [53:0] io_x_ppn, // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@208918.4]
input io_x_d, // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@208918.4]
input io_x_a, // @... | 7.048251 |
module AsyncResetRegVec_w2_i0( // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@221356.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@221357.4]
input reset, // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@221358.4]
input [1:0] io_d, /... | 6.68936 |
module IntSyncCrossingSource_2( // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@221371.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@221372.4]
input reset, // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@221373.4]
input auto_in_0, // @[:example.Tes... | 6.689384 |
module IntSyncCrossingSource_3( // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@221412.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@221413.4]
input reset, // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@221414.4]
input auto_in_0, // @[:example.Tes... | 6.689384 |
module SynchronizerShiftReg_w2_d3( // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@265375.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@265376.4]
input [1:0] io_d, // @[:example.TestHarness.GemminiSocTest1RocketConfig816.fir@265378.4]
output [1:0] io_q ... | 6.820992 |
module DMIToTL ( // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@87420.2]
input auto_out_a_ready, // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@87423.4]
output [8:0] auto_out_a_bits_address, // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@87423.4]
input auto_out_d... | 6.634693 |
module AsyncResetRegVec_w32_i0( // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@88785.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@88786.4]
input reset, // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@88787.4]
input [31:0] io_d, ... | 6.68936 |
module AsyncResetRegVec_w1_i0( // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@88815.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@88816.4]
input reset, // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@88817.4]
input io_d, // @[:example.TestHarn... | 6.68936 |
module IntSyncCrossingSource( // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@89834.2]
input auto_in_0, // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@89837.4]
output auto_out_sync_0 // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@89837.4]
);
assign auto_out_sync_0 = ... | 6.689384 |
module AsyncResetSynchronizerShiftReg_w1_d3_i0( // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@91299.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@91300.4]
input reset, // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@91301.4]
input io_d, // @[... | 6.605499 |
module AsyncValidSync ( // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@91451.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@91452.4]
input reset, // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@91453.4]
output io_out // @[:example.TestHarness.Ge... | 6.70336 |
module AsyncResetSynchronizerShiftReg_w1_d1_i0( // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@91481.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@91482.4]
input reset, // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@91483.4]
input io_d, // @[... | 6.605499 |
module AsyncValidSync_1 ( // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@91497.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@91498.4]
input reset, // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@91499.4]
input io_in, // @[:example.TestHarness.... | 6.70336 |
module AsyncValidSync_2 ( // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@91585.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@91586.4]
input reset, // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@91587.4]
input io_in, // @[:example.TestHarness.... | 6.70336 |
module SynchronizerShiftReg_w43_d1( // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@91783.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@91784.4]
input [42:0] io_d, // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@91786.4]
output [42:0] io_q... | 6.820992 |
module SynchronizerShiftReg_w55_d1( // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@116649.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@116650.4]
input [54:0] io_d, // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@116652.4]
output [54:0] i... | 6.820992 |
module SynchronizerShiftReg_w15_d1( // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@117757.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@117758.4]
input [14:0] io_d, // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@117760.4]
output [14:0] i... | 6.820992 |
module IntXbar_4 ( // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@123354.2]
input auto_int_in_3_0, // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@123357.4]
input auto_int_in_2_0, // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@123357.4]
input auto_int_in_1_0, ... | 6.635383 |
module PE ( // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@164753.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@164754.4]
input [7:0] io_inR, // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@164756.4]
input [7:0] io_inD, // @[:example... | 7.352624 |
module SynchronizerShiftReg_w1_d3( // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@202464.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@202465.4]
input io_d, // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@202467.4]
output io_q // @[:example.T... | 6.820992 |
module IntSyncCrossingSink ( // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@202480.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@202481.4]
input auto_in_sync_0, // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@202483.4]
output auto_out_0 // @[:exa... | 6.689384 |
module IntSyncCrossingSink_1( // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@202508.2]
input auto_in_sync_0, // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@202511.4]
input auto_in_sync_1, // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@202511.4]
output auto_out_0, ... | 6.689384 |
module IntSyncCrossingSink_2( // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@202524.2]
input auto_in_sync_0, // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@202527.4]
output auto_out_0 // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@202527.4]
);
assign auto_out_0 = au... | 6.689384 |
module _1_97 ( // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@210210.2]
input [53:0] io_x_ppn, // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@210213.4]
input io_x_d, // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@210213.4]
input io_x_a, // @... | 7.048251 |
module AsyncResetRegVec_w2_i0( // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@222651.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@222652.4]
input reset, // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@222653.4]
input [1:0] io_d, /... | 6.68936 |
module IntSyncCrossingSource_2( // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@222666.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@222667.4]
input reset, // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@222668.4]
input auto_in_0, // @[:example.Tes... | 6.689384 |
module IntSyncCrossingSource_3( // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@222707.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@222708.4]
input reset, // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@222709.4]
input auto_in_0, // @[:example.Tes... | 6.689384 |
module SynchronizerShiftReg_w2_d3( // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@266670.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@266671.4]
input [1:0] io_d, // @[:example.TestHarness.GemminiSocTest1RocketConfig864.fir@266673.4]
output [1:0] io_q ... | 6.820992 |
module DMIToTL ( // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@87420.2]
input auto_out_a_ready, // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@87423.4]
output [8:0] auto_out_a_bits_address, // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@87423.4]
input auto_out_d... | 6.634693 |
module AsyncResetRegVec_w32_i0( // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@88785.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@88786.4]
input reset, // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@88787.4]
input [31:0] io_d, ... | 6.68936 |
module AsyncResetRegVec_w1_i0( // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@88815.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@88816.4]
input reset, // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@88817.4]
input io_d, // @[:example.TestHarn... | 6.68936 |
module IntSyncCrossingSource( // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@89834.2]
input auto_in_0, // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@89837.4]
output auto_out_sync_0 // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@89837.4]
);
assign auto_out_sync_0 = ... | 6.689384 |
module AsyncResetSynchronizerShiftReg_w1_d3_i0( // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@91299.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@91300.4]
input reset, // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@91301.4]
input io_d, // @[... | 6.605499 |
module AsyncValidSync ( // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@91451.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@91452.4]
input reset, // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@91453.4]
output io_out // @[:example.TestHarness.Ge... | 6.70336 |
module AsyncResetSynchronizerShiftReg_w1_d1_i0( // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@91481.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@91482.4]
input reset, // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@91483.4]
input io_d, // @[... | 6.605499 |
module AsyncValidSync_1 ( // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@91497.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@91498.4]
input reset, // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@91499.4]
input io_in, // @[:example.TestHarness.... | 6.70336 |
module AsyncValidSync_2 ( // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@91585.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@91586.4]
input reset, // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@91587.4]
input io_in, // @[:example.TestHarness.... | 6.70336 |
module SynchronizerShiftReg_w43_d1( // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@91783.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@91784.4]
input [42:0] io_d, // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@91786.4]
output [42:0] io_q... | 6.820992 |
module SynchronizerShiftReg_w55_d1( // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@116649.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@116650.4]
input [54:0] io_d, // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@116652.4]
output [54:0] i... | 6.820992 |
module SynchronizerShiftReg_w15_d1( // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@117757.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@117758.4]
input [14:0] io_d, // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@117760.4]
output [14:0] i... | 6.820992 |
module IntXbar_4 ( // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@123354.2]
input auto_int_in_3_0, // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@123357.4]
input auto_int_in_2_0, // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@123357.4]
input auto_int_in_1_0, ... | 6.635383 |
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