code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module PE ( // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@163602.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@163603.4]
input [7:0] io_inR, // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@163605.4]
input [7:0] io_inD, // @[:example... | 7.352624 |
module SynchronizerShiftReg_w1_d3( // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@201169.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@201170.4]
input io_d, // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@201172.4]
output io_q // @[:example.T... | 6.820992 |
module IntSyncCrossingSink ( // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@201185.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@201186.4]
input auto_in_sync_0, // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@201188.4]
output auto_out_0 // @[:exa... | 6.689384 |
module IntSyncCrossingSink_1( // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@201213.2]
input auto_in_sync_0, // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@201216.4]
input auto_in_sync_1, // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@201216.4]
output auto_out_0, ... | 6.689384 |
module IntSyncCrossingSink_2( // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@201229.2]
input auto_in_sync_0, // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@201232.4]
output auto_out_0 // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@201232.4]
);
assign auto_out_0 = au... | 6.689384 |
module _1_97 ( // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@208915.2]
input [53:0] io_x_ppn, // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@208918.4]
input io_x_d, // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@208918.4]
input io_x_a, // @... | 7.048251 |
module AsyncResetRegVec_w2_i0( // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@221356.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@221357.4]
input reset, // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@221358.4]
input [1:0] io_d, /... | 6.68936 |
module IntSyncCrossingSource_2( // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@221371.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@221372.4]
input reset, // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@221373.4]
input auto_in_0, // @[:example.Tes... | 6.689384 |
module IntSyncCrossingSource_3( // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@221412.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@221413.4]
input reset, // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@221414.4]
input auto_in_0, // @[:example.Tes... | 6.689384 |
module SynchronizerShiftReg_w2_d3( // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@265375.2]
input clock, // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@265376.4]
input [1:0] io_d, // @[:example.TestHarness.GemminiSocTest1RocketConfig8x8.fir@265378.4]
output [1:0] io_q ... | 6.820992 |
module PLICFanIn ( // @[:example.TestHarness.MediumBoomConfig.fir@73952.2]
input [1:0] io_prio_0, // @[:example.TestHarness.MediumBoomConfig.fir@73955.4]
input [1:0] io_prio_1, // @[:example.TestHarness.MediumBoomConfig.fir@73955.4]
input [1:0] io_ip, // @[:example.TestHarness.MediumBoomConfig.fir@73955... | 7.32121 |
module DMIToTL ( // @[:example.TestHarness.MediumBoomConfig.fir@80091.2]
input auto_out_a_ready, // @[:example.TestHarness.MediumBoomConfig.fir@80094.4]
output [ 8:0] auto_out_a_bits_address, // @[:example.TestHarness.MediumBoomConfig.fir@80094.4]
input auto_out_d_valid, //... | 6.634693 |
module AsyncResetRegVec_w1_i0 ( // @[:example.TestHarness.MediumBoomConfig.fir@82179.2]
input clock, // @[:example.TestHarness.MediumBoomConfig.fir@82180.4]
input reset, // @[:example.TestHarness.MediumBoomConfig.fir@82181.4]
input io_d, // @[:example.TestHarness.MediumBoomConfig.fir@82182.4]
ou... | 6.68936 |
module IntSyncCrossingSource ( // @[:example.TestHarness.MediumBoomConfig.fir@82778.2]
input auto_in_0, // @[:example.TestHarness.MediumBoomConfig.fir@82781.4]
output auto_out_sync_0 // @[:example.TestHarness.MediumBoomConfig.fir@82781.4]
);
assign auto_out_sync_0 = auto_in_0; // @[LazyModule.scala 173:49:... | 6.689384 |
module AsyncResetSynchronizerShiftReg_w1_d3_i0( // @[:example.TestHarness.MediumBoomConfig.fir@84307.2]
input clock, // @[:example.TestHarness.MediumBoomConfig.fir@84308.4]
input reset, // @[:example.TestHarness.MediumBoomConfig.fir@84309.4]
input io_d, // @[:example.TestHarness.MediumBoomConfig.fir@... | 6.605499 |
module AsyncValidSync ( // @[:example.TestHarness.MediumBoomConfig.fir@84555.2]
input clock, // @[:example.TestHarness.MediumBoomConfig.fir@84556.4]
input reset, // @[:example.TestHarness.MediumBoomConfig.fir@84557.4]
output io_out // @[:example.TestHarness.MediumBoomConfig.fir@84558.4]
);
wire sou... | 6.70336 |
module AsyncResetSynchronizerShiftReg_w1_d1_i0( // @[:example.TestHarness.MediumBoomConfig.fir@84601.2]
input clock, // @[:example.TestHarness.MediumBoomConfig.fir@84602.4]
input reset, // @[:example.TestHarness.MediumBoomConfig.fir@84603.4]
input io_d, // @[:example.TestHarness.MediumBoomConfig.fir@... | 6.605499 |
module AsyncValidSync_1 ( // @[:example.TestHarness.MediumBoomConfig.fir@84617.2]
input clock, // @[:example.TestHarness.MediumBoomConfig.fir@84618.4]
input reset, // @[:example.TestHarness.MediumBoomConfig.fir@84619.4]
input io_in, // @[:example.TestHarness.MediumBoomConfig.fir@84620.4]
output i... | 6.70336 |
module AsyncValidSync_2 ( // @[:example.TestHarness.MediumBoomConfig.fir@84753.2]
input clock, // @[:example.TestHarness.MediumBoomConfig.fir@84754.4]
input reset, // @[:example.TestHarness.MediumBoomConfig.fir@84755.4]
input io_in, // @[:example.TestHarness.MediumBoomConfig.fir@84756.4]
output i... | 6.70336 |
module SynchronizerShiftReg_w43_d1 ( // @[:example.TestHarness.MediumBoomConfig.fir@85015.2]
input clock, // @[:example.TestHarness.MediumBoomConfig.fir@85016.4]
input [42:0] io_d, // @[:example.TestHarness.MediumBoomConfig.fir@85018.4]
output [42:0] io_q // @[:example.TestHarness.MediumBoom... | 6.820992 |
module SynchronizerShiftReg_w55_d1 ( // @[:example.TestHarness.MediumBoomConfig.fir@109379.2]
input clock, // @[:example.TestHarness.MediumBoomConfig.fir@109380.4]
input [54:0] io_d, // @[:example.TestHarness.MediumBoomConfig.fir@109382.4]
output [54:0] io_q // @[:example.TestHarness.MediumB... | 6.820992 |
module SynchronizerShiftReg_w14_d1 ( // @[:example.TestHarness.MediumBoomConfig.fir@111030.2]
input clock, // @[:example.TestHarness.MediumBoomConfig.fir@111031.4]
input [13:0] io_d, // @[:example.TestHarness.MediumBoomConfig.fir@111033.4]
output [13:0] io_q // @[:example.TestHarness.MediumB... | 6.820992 |
module packageanon2 ( // @[:example.TestHarness.MediumBoomConfig.fir@121677.2]
input [19:0] io_x_ppn, // @[:example.TestHarness.MediumBoomConfig.fir@121680.4]
input io_x_u, // @[:example.TestHarness.MediumBoomConfig.fir@121680.4]
input io_x_ae, // @[:example.TestHarness.MediumBoomCon... | 8.116079 |
module IntSyncCrossingSink_2 ( // @[:example.TestHarness.MediumBoomConfig.fir@170027.2]
input auto_in_sync_0, // @[:example.TestHarness.MediumBoomConfig.fir@170030.4]
output auto_out_0 // @[:example.TestHarness.MediumBoomConfig.fir@170030.4]
);
assign auto_out_0 = auto_in_sync_0; // @[LazyModule.scala 173:... | 6.689384 |
module packageanon2_60 ( // @[:example.TestHarness.MediumBoomConfig.fir@170202.2]
input [2:0] io_x, // @[:example.TestHarness.MediumBoomConfig.fir@170205.4]
output [2:0] io_y // @[:example.TestHarness.MediumBoomConfig.fir@170205.4]
);
assign io_y = io_x; // @[package.scala 217:12:example.TestHarness.Med... | 7.431734 |
module packageanon2_61 ( // @[:example.TestHarness.MediumBoomConfig.fir@170212.2]
input [53:0] io_x_ppn, // @[:example.TestHarness.MediumBoomConfig.fir@170215.4]
input io_x_d, // @[:example.TestHarness.MediumBoomConfig.fir@170215.4]
input io_x_a, // @[:example.TestHarness.MediumBoom... | 7.431734 |
module AsyncResetRegVec_w2_i0 ( // @[:example.TestHarness.MediumBoomConfig.fir@321847.2]
input clock, // @[:example.TestHarness.MediumBoomConfig.fir@321848.4]
input reset, // @[:example.TestHarness.MediumBoomConfig.fir@321849.4]
input [1:0] io_d, // @[:example.TestHarness.MediumBoomConfi... | 6.68936 |
module IntSyncCrossingSource_2 ( // @[:example.TestHarness.MediumBoomConfig.fir@321880.2]
input clock, // @[:example.TestHarness.MediumBoomConfig.fir@321881.4]
input reset, // @[:example.TestHarness.MediumBoomConfig.fir@321882.4]
input auto_in_0, // @[:example.TestHarness.MediumBoomConfig.fir@321883.4]
... | 6.689384 |
module IntSyncCrossingSource_3 ( // @[:example.TestHarness.MediumBoomConfig.fir@321937.2]
input clock, // @[:example.TestHarness.MediumBoomConfig.fir@321938.4]
input reset, // @[:example.TestHarness.MediumBoomConfig.fir@321939.4]
input auto_in_0, // @[:example.TestHarness.MediumBoomConfig.fir@321940.4]
... | 6.689384 |
module SynchronizerShiftReg_w2_d3 ( // @[:example.TestHarness.MediumBoomConfig.fir@322023.2]
input clock, // @[:example.TestHarness.MediumBoomConfig.fir@322024.4]
input [1:0] io_d, // @[:example.TestHarness.MediumBoomConfig.fir@322026.4]
output [1:0] io_q // @[:example.TestHarness.MediumBoomC... | 6.820992 |
module PLICFanIn ( // @[:example.TestHarness.RocketConfig.fir@70722.2]
input [1:0] io_prio_0, // @[:example.TestHarness.RocketConfig.fir@70725.4]
input [1:0] io_prio_1, // @[:example.TestHarness.RocketConfig.fir@70725.4]
input [1:0] io_prio_2, // @[:example.TestHarness.RocketConfig.fir@70725.4]
inpu... | 7.32121 |
module DMIToTL ( // @[:example.TestHarness.RocketConfig.fir@76889.2]
input auto_out_a_ready, // @[:example.TestHarness.RocketConfig.fir@76892.4]
output [ 8:0] auto_out_a_bits_address, // @[:example.TestHarness.RocketConfig.fir@76892.4]
input auto_out_d_valid, // @[:example.... | 6.634693 |
module AsyncResetRegVec_w32_i0 ( // @[:example.TestHarness.RocketConfig.fir@78254.2]
input clock, // @[:example.TestHarness.RocketConfig.fir@78255.4]
input reset, // @[:example.TestHarness.RocketConfig.fir@78256.4]
input [31:0] io_d, // @[:example.TestHarness.RocketConfig.fir@78257.4]
... | 6.68936 |
module AsyncResetRegVec_w1_i0 ( // @[:example.TestHarness.RocketConfig.fir@78284.2]
input clock, // @[:example.TestHarness.RocketConfig.fir@78285.4]
input reset, // @[:example.TestHarness.RocketConfig.fir@78286.4]
input io_d, // @[:example.TestHarness.RocketConfig.fir@78287.4]
output io_q // ... | 6.68936 |
module IntSyncCrossingSource ( // @[:example.TestHarness.RocketConfig.fir@79303.2]
input auto_in_0, // @[:example.TestHarness.RocketConfig.fir@79306.4]
output auto_out_sync_0 // @[:example.TestHarness.RocketConfig.fir@79306.4]
);
assign auto_out_sync_0 = auto_in_0; // @[LazyModule.scala 173:49:example.Test... | 6.689384 |
module AsyncResetSynchronizerShiftReg_w1_d3_i0( // @[:example.TestHarness.RocketConfig.fir@80768.2]
input clock, // @[:example.TestHarness.RocketConfig.fir@80769.4]
input reset, // @[:example.TestHarness.RocketConfig.fir@80770.4]
input io_d, // @[:example.TestHarness.RocketConfig.fir@80771.4]
out... | 6.605499 |
module AsyncResetSynchronizerShiftReg_w1_d4_i0( // @[:example.TestHarness.RocketConfig.fir@80886.2]
input clock, // @[:example.TestHarness.RocketConfig.fir@80887.4]
input reset, // @[:example.TestHarness.RocketConfig.fir@80888.4]
output io_q // @[:example.TestHarness.RocketConfig.fir@80889.4]
);
wi... | 6.605499 |
module AsyncValidSync ( // @[:example.TestHarness.RocketConfig.fir@80920.2]
input clock, // @[:example.TestHarness.RocketConfig.fir@80921.4]
input reset, // @[:example.TestHarness.RocketConfig.fir@80922.4]
output io_out // @[:example.TestHarness.RocketConfig.fir@80923.4]
);
wire source_valid_clock; ... | 6.70336 |
module AsyncResetSynchronizerShiftReg_w1_d1_i0( // @[:example.TestHarness.RocketConfig.fir@80950.2]
input clock, // @[:example.TestHarness.RocketConfig.fir@80951.4]
input reset, // @[:example.TestHarness.RocketConfig.fir@80952.4]
input io_d, // @[:example.TestHarness.RocketConfig.fir@80953.4]
out... | 6.605499 |
module AsyncValidSync_1 ( // @[:example.TestHarness.RocketConfig.fir@80966.2]
input clock, // @[:example.TestHarness.RocketConfig.fir@80967.4]
input reset, // @[:example.TestHarness.RocketConfig.fir@80968.4]
input io_in, // @[:example.TestHarness.RocketConfig.fir@80969.4]
output io_out // @[:exa... | 6.70336 |
module AsyncValidSync_2 ( // @[:example.TestHarness.RocketConfig.fir@81054.2]
input clock, // @[:example.TestHarness.RocketConfig.fir@81055.4]
input reset, // @[:example.TestHarness.RocketConfig.fir@81056.4]
input io_in, // @[:example.TestHarness.RocketConfig.fir@81057.4]
output io_out // @[:exa... | 6.70336 |
module SynchronizerShiftReg_w43_d1 ( // @[:example.TestHarness.RocketConfig.fir@81252.2]
input clock, // @[:example.TestHarness.RocketConfig.fir@81253.4]
input [42:0] io_d, // @[:example.TestHarness.RocketConfig.fir@81255.4]
output [42:0] io_q // @[:example.TestHarness.RocketConfig.fir@81255... | 6.820992 |
module SynchronizerShiftReg_w55_d1 ( // @[:example.TestHarness.RocketConfig.fir@106118.2]
input clock, // @[:example.TestHarness.RocketConfig.fir@106119.4]
input [54:0] io_d, // @[:example.TestHarness.RocketConfig.fir@106121.4]
output [54:0] io_q // @[:example.TestHarness.RocketConfig.fir@10... | 6.820992 |
module SynchronizerShiftReg_w15_d1 ( // @[:example.TestHarness.RocketConfig.fir@107226.2]
input clock, // @[:example.TestHarness.RocketConfig.fir@107227.4]
input [14:0] io_d, // @[:example.TestHarness.RocketConfig.fir@107229.4]
output [14:0] io_q // @[:example.TestHarness.RocketConfig.fir@10... | 6.820992 |
module IntXbar_4 ( // @[:example.TestHarness.RocketConfig.fir@112626.2]
input auto_int_in_3_0, // @[:example.TestHarness.RocketConfig.fir@112629.4]
input auto_int_in_2_0, // @[:example.TestHarness.RocketConfig.fir@112629.4]
input auto_int_in_1_0, // @[:example.TestHarness.RocketConfig.fir@112629.4]
... | 6.635383 |
module SynchronizerShiftReg_w1_d3 ( // @[:example.TestHarness.RocketConfig.fir@141142.2]
input clock, // @[:example.TestHarness.RocketConfig.fir@141143.4]
input io_d, // @[:example.TestHarness.RocketConfig.fir@141145.4]
output io_q // @[:example.TestHarness.RocketConfig.fir@141145.4]
);
reg sync_... | 6.820992 |
module IntSyncCrossingSink ( // @[:example.TestHarness.RocketConfig.fir@141158.2]
input clock, // @[:example.TestHarness.RocketConfig.fir@141159.4]
input auto_in_sync_0, // @[:example.TestHarness.RocketConfig.fir@141161.4]
output auto_out_0 // @[:example.TestHarness.RocketConfig.fir@141161.4]
);
wire ... | 6.689384 |
module IntSyncCrossingSink_1 ( // @[:example.TestHarness.RocketConfig.fir@141186.2]
input auto_in_sync_0, // @[:example.TestHarness.RocketConfig.fir@141189.4]
input auto_in_sync_1, // @[:example.TestHarness.RocketConfig.fir@141189.4]
output auto_out_0, // @[:example.TestHarness.RocketConfig.fir@141189.4... | 6.689384 |
module IntSyncCrossingSink_2 ( // @[:example.TestHarness.RocketConfig.fir@141202.2]
input auto_in_sync_0, // @[:example.TestHarness.RocketConfig.fir@141205.4]
output auto_out_0 // @[:example.TestHarness.RocketConfig.fir@141205.4]
);
assign auto_out_0 = auto_in_sync_0; // @[LazyModule.scala 173:49:example.T... | 6.689384 |
module _1_79 ( // @[:example.TestHarness.RocketConfig.fir@148834.2]
input [53:0] io_x_ppn, // @[:example.TestHarness.RocketConfig.fir@148837.4]
input io_x_d, // @[:example.TestHarness.RocketConfig.fir@148837.4]
input io_x_a, // @[:example.TestHarness.RocketConfig.fir@148837.4]
i... | 7.160361 |
module AsyncResetRegVec_w2_i0 ( // @[:example.TestHarness.RocketConfig.fir@160614.2]
input clock, // @[:example.TestHarness.RocketConfig.fir@160615.4]
input reset, // @[:example.TestHarness.RocketConfig.fir@160616.4]
input [1:0] io_d, // @[:example.TestHarness.RocketConfig.fir@160617.4]
... | 6.68936 |
module IntSyncCrossingSource_2 ( // @[:example.TestHarness.RocketConfig.fir@160629.2]
input clock, // @[:example.TestHarness.RocketConfig.fir@160630.4]
input reset, // @[:example.TestHarness.RocketConfig.fir@160631.4]
input auto_in_0, // @[:example.TestHarness.RocketConfig.fir@160632.4]
input auto_i... | 6.689384 |
module IntSyncCrossingSource_3 ( // @[:example.TestHarness.RocketConfig.fir@160670.2]
input clock, // @[:example.TestHarness.RocketConfig.fir@160671.4]
input reset, // @[:example.TestHarness.RocketConfig.fir@160672.4]
input auto_in_0, // @[:example.TestHarness.RocketConfig.fir@160673.4]
output auto_... | 6.689384 |
module SynchronizerShiftReg_w2_d3 ( // @[:example.TestHarness.RocketConfig.fir@193597.2]
input clock, // @[:example.TestHarness.RocketConfig.fir@193598.4]
input [1:0] io_d, // @[:example.TestHarness.RocketConfig.fir@193600.4]
output [1:0] io_q // @[:example.TestHarness.RocketConfig.fir@193600... | 6.820992 |
module names
module module_name #(
// use CAPITAL_CASE for parameters
parameter PARAM_NAME = 0
) (
// prefix i_ for inputs
input i_my_input,
input i_clk,
// prefix o_ for outputs
output reg o_my_output
// use output reg for outputs, input wire is optional
// note this doesn't always ... | 9.051182 |
module and_gate
(
input_1,
input_2,
and_result
);
initial
begin
input input_1;
input input_2;
output and_result;
wire and_temp;
assign and_temp = input_1 & input_2;
assign and_result = and_temp;
$display( and_result);
$finish
end
endmodule
| 8.041953 |
module Example12 (
counter,
clk,
set
);
output [3:0] counter;
input clk, set;
reg [3:0] counter_reg;
always @(posedge clk) begin
if (set) counter_reg <= 4'b1111;
else counter_reg <= counter_reg - 4'b0001;
end
assign counter = counter_reg;
endmodule
| 7.184659 |
module Example13 (
counter,
Input,
clk,
load
);
output [3:0] counter;
input [3:0] Input;
input clk, load;
reg [3:0] counter_reg;
always @(posedge clk or posedge load) begin
if (load) counter_reg <= Input;
else counter_reg <= counter_reg + 4'b0001;
end
assign counter = counter_re... | 7.392317 |
module Example14 (
counter,
clk,
load
);
output [3:0] counter;
input clk, load;
reg [3:0] counter_reg;
always @(posedge clk) begin
if (load) counter_reg <= 4'b0110;
else counter_reg <= counter_reg + 4'b0001;
end
assign counter = counter_reg;
endmodule
| 7.535702 |
module Example15 (
counter,
clk,
clear,
enable
);
output [3:0] counter;
input clk, clear, enable;
reg [3:0] counter_reg;
always @(posedge clk or posedge clear) begin
if (clear) counter_reg <= 4'b0000;
else if (enable) counter_reg <= counter_reg + 4'b0001;
end
assign counter = coun... | 6.910504 |
module Example17 (
counter,
clk,
reset
);
output signed [4:0] counter;
input clk, reset;
reg signed [4:0] counter_reg;
always @(posedge clk or posedge reset) begin
if (reset) counter_reg <= 5'b00000;
else counter_reg <= counter_reg + 5'b00001;
end
assign counter = counter_reg;
endmod... | 7.338222 |
module Example19 (
counter,
accumulator,
clk,
clear
);
output [3:0] counter;
input [3:0] accumulator;
input clk, clear;
reg [3:0] counter_reg;
always @(posedge clk or posedge clear) // Sensitivity list
begin
if (clear) counter_reg <= 4'b0000;
else counter_reg <= counter_reg + acc... | 6.914512 |
module Example2 (
Q,
D,
clk,
clear
);
output Q;
input D, clk, clear;
reg Q;
always @(negedge clk or posedge clear) begin
if (clear) Q <= 1'b0;
else Q <= D;
end
endmodule
| 6.788044 |
module Example20 (
sout,
sin,
clk
);
output sout;
input sin, clk;
reg [7:0] temp;
always @(posedge clk) begin
temp = temp << 1;
temp[0] = sin;
end
assign sout = temp[7];
endmodule
| 7.022836 |
module Example21 (
sout,
sin,
clk,
enable
);
output sout;
input sin, clk, enable;
reg [7:0] temp;
always @(negedge clk) begin
if (enable) begin
temp = temp << 1;
temp[0] = sin;
end
end
assign sout = temp[7];
endmodule
| 6.949531 |
module Example25 (
sout,
sin,
in,
clk,
load
);
output sout;
input sin, clk, load;
input [7:0] in;
reg [7:0] temp;
always @(posedge clk or posedge load) begin
if (load) begin
temp = in;
end else begin
temp = temp << 1;
temp[0] = sin;
end
end
assign sout... | 6.831288 |
module Example28 (
res,
a,
b,
c,
oper
);
output reg [7:0] res;
input [7:0] a, b, c;
input oper;
always @(a or b or c or oper) begin
if (oper) res <= a + b;
else res <= a - c;
end
endmodule
| 7.209825 |
module counts how many seconds have passed until the seconds register
// overflows back to 0 after it hits 15. Uses two counters, the first counter
// just counts the positive edges of the clock, the second counts the seconds.
// When the first counter has reached half the clock cycles in a second (half
// because it's... | 7.024981 |
module moore (
input clk,
input in,
output reg out
);
// Define states as parameters
parameter S0 = 0, S1 = 1;
// Create a register for the current state, initialize it to S0
reg state_now = S0;
// Create a register for the next state
reg state_next;
// Process 1: Determine next state
alw... | 6.557094 |
module Example3 (
Q,
D,
clk,
set
);
output Q;
input D, clk, set;
reg Q;
always @(posedge clk) begin
if (set) Q <= 1'b1;
else Q <= D;
end
endmodule
| 6.583597 |
module mealy (
input clk,
input in,
output reg out
);
// Define states as parameters
parameter S0 = 0, S1 = 1;
// Create a register for the current state, initialize it to S0
reg state_now = S0;
// Create a register for the next state
reg state_next;
// Process 1: Determine next state
alw... | 7.666702 |
module mealy (
input clk,
input in,
output reg out
);
// Define states as parameters
parameter S0 = 0, S1 = 1;
// Create a register for the current state, initialize it to S0
reg state_now = S0;
// Create a register for the next state
reg state_next;
// Process 1: Determine next state and o... | 7.666702 |
module clk_div (
input clk,
input reset,
input [31:0] scale,
output reg clk_out = 0
);
// f = (100 MHz)/(4*scale)
// scale = 1000 --> f = 25 kHz
reg [15:0] count = 16'b0;
always @(posedge clk)
if (reset) begin
count <= 16'b0;
clk_out <= 1'b0;
end else if (count == scale - ... | 7.520262 |
module uses a 21 bit register as a refresh counter for the display. It uses the
// first 19 bits of this register for creating a 190 Hz refresh rate for the segment
// display, and uses the last two bits cycle through each of the four possible digits
// and refresh its display.
mo... | 7.298694 |
module Example5 (
Q,
D,
clk,
set,
enable
);
output [3:0] Q;
input [3:0] D;
input clk, set, enable;
reg [3:0] Q;
always@(posedge clk or posedge set) // Change on negative edge always
begin
if (set == 1'b1) Q <= 4'b1111;
else if (enable == 1'b1) Q <= D;
end
endmodule
| 6.790669 |
module was coded for a 100 MHz clock, meaning that there should be 100
// million ticks in one second. That means that after the counter has counted
// 100 million ticks / 16 we know that 1/16th of a second has passed. Another
// counter works simultaneously to count the number of positive edges from the
// input comin... | 8.076021 |
module Example8 (
Q,
D,
posgt,
preset
);
output [3:0] Q;
input [3:0] D;
input posgt, preset;
reg [3:0] Q;
always @(D or posgt or preset) begin
if (preset) Q <= 4'b1111;
else if (~posgt) Q <= D;
end
endmodule
| 7.00656 |
module examplemealy (
Clock,
Resetn,
w,
z
);
input Clock, Resetn, w;
output reg z;
reg [3:1] y, Y;
parameter S0 = 3'b000, S1 = 3'b001, S2 = 3'b010, S3 = 3'b011, S4 = 3'b100, S5 = 3'b101;
//Define the next state and output combinational circuits
always @(w, y)
case (y)
S0:
i... | 7.239322 |
module examplenioscrc (
input CLOCK2_50,
input CLOCK3_50,
input CLOCK4_50,
input CLOCK_50,
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX4,
output [6:0] HEX5,
input [3:0] KEY,
output [9:0] LEDR
);
... | 6.78172 |
module BufferCC (
input io_initial,
input io_dataIn,
output io_dataOut,
input clk_cpu,
input clk_cpu_reset_
);
reg buffers_0;
reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge clk_cpu) begin
if (!clk_cpu_reset_) begin
buffers_0 <= io_initial;
buffers_1 <= io... | 6.712921 |
module StreamFifoLowLatency (
input io_push_valid,
output io_push_ready,
input io_push_payload_error,
input [31:0] io_push_payload_inst,
output reg io_pop_valid,
input io_pop_ready,
output reg io_pop_payload_error,
output ... | 7.046487 |
module CCMasterArbiter (
input io_iBus_cmd_valid,
output reg io_iBus_cmd_ready,
input [31:0] io_iBus_cmd_payload_pc,
output io_iBus_rsp_valid,
output io_iBus_rsp_payload_error,
output [31:0] io_iBus_rsp_payload_inst,
input io_dBus... | 8.403271 |
module CCPipelinedMemoryBusRam (
input io_bus_cmd_valid,
output io_bus_cmd_ready,
input io_bus_cmd_payload_write,
input [31:0] io_bus_cmd_payload_address,
input [31:0] io_bus_cmd_payload_data,
input [ 3:0] io_bus_cmd_payload_mask,
output io_bus_rsp_valid,
... | 6.751552 |
module Timer (
input io_tick,
input io_clear,
input [15:0] io_limit,
output io_full,
output [15:0] io_value,
input clk_cpu,
input clk_cpu_reset_
);
wire [ 0:0] _zz_Timer_1_;
wire [15:0] _zz_Timer_2_;
reg [15:0] counter;
wire limitHit;
... | 6.729771 |
module Timer_1_ (
input io_tick,
input io_clear,
input [15:0] io_limit,
output io_full,
output [15:0] io_value,
input clk_cpu,
input clk_cpu_reset_
);
wire [ 0:0] _zz_Timer_1__1_;
wire [15:0] _zz_Timer_1__2_;
reg [15:0] counter;
wire li... | 6.570036 |
module InterruptCtrl (
input [1:0] io_inputs,
input [1:0] io_clears,
input [1:0] io_masks,
output [1:0] io_pendings,
input clk_cpu,
input clk_cpu_reset_
);
reg [1:0] pendings;
assign io_pendings = (pendings & io_masks);
always @(posedge clk_cpu) begin
if (!clk_cpu_res... | 7.510624 |
module BufferCC_1_ (
input [2:0] io_dataIn,
output [2:0] io_dataOut,
input clk_cpu,
input clk_cpu_reset_
);
reg [2:0] buffers_0;
reg [2:0] buffers_1;
assign io_dataOut = buffers_1;
always @(posedge clk_cpu) begin
buffers_0 <= io_dataIn;
buffers_1 <= buffers_0;
end
end... | 7.044402 |
module Apb3Gpio (
input [ 3:0] io_apb_PADDR,
input [ 0:0] io_apb_PSEL,
input io_apb_PENABLE,
output io_apb_PREADY,
input io_apb_PWRITE,
input [31:0] io_apb_PWDATA,
output reg [31:0] io_apb_PRDATA,
output io_apb_PSLVERROR,
i... | 6.706229 |
module ExampleTopLevel_tb;
//
// Parameter Declarations
//
localparam NUM_CYCLES = 50000; //Simulate this many clock cycles. Max. 1 billion
localparam CLOCK_FREQ = 50000000; //Clock frequency (in Hz)
localparam RST_CYCLES = 2; //Number of cycles of reset at beginning.
//
// Test Bench Generated Sig... | 6.942883 |
module ExampleTopModuleWithBB (
input clock,
input reset,
input [14:0] io_a,
input [14:0] io_b,
input [13:0] io_c,
output [15:0] io_x,
output [15:0] io_y,
output [15:0] io_z,
inout [ 2:0] io_analog1,
inout [ 2:0] io_analog2,
output [ 4:0] io_v_0,
outp... | 7.228255 |
module exampleV1TopModule (
input clk50MHz,
input rst,
input [3:0] switches,
input select_button,
output [2:0] red,
output [2:0] green,
output [1:0] blue,
output hsync,
output vsync
);
wire clk25MHz;
wire [2:0] variety;
wire [2:0] match;
wire enable;
wire [1:0] sifirla... | 7.221548 |
module priority_decoder_1
(input wire [3:0] select,
output reg [2:0] priority // "priority" is not a keyword
);
// return bit number of highest bit set, or 7 if none set
always @(select) begin
casez (select) // synthesis full_case
4'b1???: priority = 4'h3;
4'b01??: priority = 4'h2;
4'b00... | 6.546663 |
module example_3_1 (
A,
B,
C,
D,
E
);
output D, E;
input A, B, C;
wire w1;
and G1 (w1, A, B);
not G2 (E, C);
or G3 (D, w1, E);
endmodule
| 6.734123 |
module example_3_1_tb;
wire A, B, C, D, E;
integer k = 0;
assign {A, B, C} = k;
example_3_1 the_circuit (
A,
B,
C,
D,
E
);
initial begin
$dumpfile("example_3_1.vcd");
$dumpvars(0, example_3_1_tb);
for (k = 0; k < 8; k = k + 1) #10 $display("done testing case %d... | 6.856538 |
module example_3_4 (
E,
F,
A,
B,
C,
D
);
output E, F;
input A, B, C, D;
assign E = A || (B && C) || ((!B) && D);
assign F = ((!B) && C) || (B && (!C) && (!D));
endmodule
| 7.213919 |
module example_3_4_tb;
wire A, B, C, D, E, F;
integer k = 0;
assign {A, B, C, D} = k;
example_3_4 the_circuit (
E,
F,
A,
B,
C,
D
);
initial begin
$dumpfile("example_3_4.vcd");
$dumpvars(0, example_3_4_tb);
for (k = 0; k < 16; k = k + 1) #10 $display("done... | 6.725391 |
module example_3_5_tb;
wire A, B, C, D;
integer k = 0;
assign {A, B, C} = k;
example_3_5 the_circuit (
D,
A,
B,
C
);
initial begin
$dumpfile("example_3_5.vcd");
$dumpvars(0, example_3_5_tb);
for (k = 0; k < 8; k = k + 1) #10 $display("done testing case %d", k);
... | 6.742911 |
module example_and2 (
input clk,
input wire data_a,
input wire data_b,
output reg data_o
);
always @(posedge clk) begin
data_o <= data_a & data_b;
end
endmodule
| 6.593557 |
module example_and2 (
x1,
x2,
z1
);
input x1, x2;
output z1;
wire x1, x2;
wire z1;
assign z1 = x1 | x2;
endmodule
| 6.593557 |
module example_and_gate (
input_1,
input_2,
and_result
);
input input_1;
input input_2;
output and_result;
wire and_temp;
assign and_temp = input_1 & input_2;
assign and_result = and_temp;
endmodule
| 7.297126 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.