code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module example_a_m_axi_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire sclk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:0] m_d... | 7.841883 |
module example_a_m_axi_fifo #(
parameter DATA_BITS = 8,
DEPTH = 16,
DEPTH_BITS = 4
) (
input wire sclk,
input wire reset,
input wire sclk_en,
output reg empty_n,
output reg full... | 7.841883 |
module example_a_m_axi_buffer #(
parameter MEM_STYLE = "block",
DATA_WIDTH = 32,
ADDR_WIDTH = 5,
DEPTH = 32
) (
// system signal
input wire clk,
input wire reset,
input wire sclk_en,
// write
output wire if_full_n,
input ... | 7.841883 |
module example_a_m_axi_decoder #(
parameter DIN_WIDTH = 3
) (
input wire [ DIN_WIDTH-1:0] din,
output reg [2**DIN_WIDTH-1:0] dout
);
integer i;
always @(din) begin
dout = {2 ** DIN_WIDTH{1'b0}};
for (i = 0; i < din; i = i + 1) dout[i] = 1'b1;
end
endmodule
| 7.841883 |
module bcd_count_tb_example;
// Inputs
reg [6:0] max_count;
reg clk, run;
// Outputs
wire [3:0] digit_1, digit_2;
// UUT - BCD Counter
bcd_count_7 uut (
.max_count(max_count),
.run(run),
.CLK(clk),
.digit_1(digit_1),
.digit_2(digit_2)
);
// Clock Generator
always be... | 6.588494 |
module example_chipscope_icon ();
//-----------------------------------------------------------------
// Local Signals
//-----------------------------------------------------------------
wire [35:0] control0;
wire [35:0] control1;
wire [35:0] control2;
wire [35:0] control3;
//-----------------------... | 7.313348 |
module example_count (
input clk,
output done,
output [11:0] bin_cnt
);
parameter c_reg_size = 34;
reg [c_reg_size - 1:0] count = 0;
reg fin = 0;
reg old_b = 0;
always @(posedge clk) begin
count <= count + 1;
if ((old_b && !count[c_reg_size-12... | 6.562661 |
module example_ibert_7series_gtp_0 (
// GT top level ports
output wire [ 1:0] tx_en,
output [(4*`C_NUM_QUADS)-1:0] TXN_O,
output [(4*`C_NUM_QUADS)-1:0] TXP_O,
input [(4*`C_NUM_QUADS)-1:0] RXN_I,
input [(4*`C_NUM_QUADS)-1:0] RXP_I,
input ... | 7.560214 |
module x_lut4_0xf000 (
i2,
i3,
o
);
input i2, i3;
output o;
supply0 VSS;
supply1 VDD;
an2 inst296161 (
.b(i2),
.a(i3),
.z(o)
);
endmodule
| 6.556095 |
module x_lut4_0xbf15 (
i0,
i1,
i2,
i3,
o
);
input i0, i1, i2, i3;
output o;
supply0 VSS;
supply1 VDD;
na2 inst235450 (
.b (i1),
.a (i2),
.zn(n35)
);
mx21 inst235451 (
.sb(i0),
.b (i3),
.a (n35),
.z (o)
);
endmodule
| 6.514143 |
module x_lut4_0x0808 (
i0,
i1,
i2,
o
);
input i0, i1, i2;
output o;
supply0 VSS;
supply1 VDD;
an3 inst008463 (
.c(i1),
.b(n36),
.a(i0),
.z(o)
);
i1 inst008464 (
.a (i2),
.zn(n36)
);
endmodule
| 6.526512 |
module x_lut4_0x0f88 (
i0,
i1,
i2,
i3,
o
);
input i0, i1, i2, i3;
output o;
supply0 VSS;
supply1 VDD;
mx21i inst016519 (
.sb(i3),
.b (i2),
.a (n35),
.zn(o)
);
na2 inst016520 (
.b (i0),
.a (i1),
.zn(n35)
);
endmodule
| 6.518473 |
module ethernet_100m (
`ifdef USE_POWER_PINS
inout vccd1, // User area 1 1.8V supply
inout vssd1, // User area 1 digital ground
`endif
/*
* Clock: 125MHz
* Synchronous reset
*/
input wire clk,
input wire rst,
/*
* Ethernet: 100BASE-T MII
*/
input wire ... | 6.532797 |
module ethernet_100m_tb;
reg clock;
reg RSTB;
reg CSB;
reg power1, power2;
reg power3, power4;
wire gpio;
wire [37:0] mprj_io;
reg rst;
wire [3:0] phy_txd;
wire phy_tx_en;
wire phy_tx_clk;
wire phy_rx_clk;
wire [3:0] phy_rxd;
wire phy_rx_dv;
wire phy_rx_er;
integer clock_counter = 0;
... | 6.532797 |
module ethernet_altera_merlin_traffic_limiter_181_qwneafy #(
parameter IMPL = "reg",
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 4,
parameter FIFO_DEPTH = 4,
parameter CHANNEL_WIDTH = 0,
parameter ERROR_WIDTH = 0,
param... | 6.868407 |
module contains two main blocks :
// physical layer block and media access control (MAC)
//
// (MAC) has interfaces with => 1- PHY module by (MII interface)
// 2- Soc AXI BUS by (AXI4-Lite)
// 3- direct memo... | 6.942464 |
module contains two main blocks :
// physical layer block and media access control (MAC)
//
// (MAC) has interfaces with => 1- PHY module by (MII interface)
// 2- Soc AXI BUS by (AXI4-Lite)
// 3- direct memo... | 6.942464 |
module ethernet_parser #(
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = DATA_WIDTH / 8,
parameter NUM_IQ_BITS = 3,
parameter INPUT_ARBITER_STAGE_NUM = 2
) ( // --- Interface to the previous stage
input [DATA_WIDTH-1:0] in_data,
input [CTRL_WIDTH-1:0] in_ctrl,
input in_w... | 7.369521 |
module ethernet_parser_32bit #(
parameter DATA_WIDTH = 32,
parameter CTRL_WIDTH = DATA_WIDTH / 8,
parameter NUM_IQ_BITS = 3,
parameter INPUT_ARBITER_STAGE_NUM = 2
) ( // --- Interface to the previous stage
input [DATA_WIDTH-1:0] in_data,
input [CTRL_WIDTH-1:0] in_ctrl,
input ... | 7.369521 |
module ethernet_parser_64bit #(
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = DATA_WIDTH / 8,
parameter NUM_IQ_BITS = 3,
parameter INPUT_ARBITER_STAGE_NUM = 2
) ( // --- Interface to the previous stage
input [DATA_WIDTH-1:0] in_data,
input [CTRL_WIDTH-1:0] in_ctrl,
input ... | 7.369521 |
module to simplify the timing where a pattern
// generator and address swap module can be muxed into the data path
//
//------------------------------------------------------------------------------
`timescale 1 ps/1 ps
module ethernet_rgmii_axi_pipe (
input axi_tclk,
input a... | 6.900006 |
module: TENBASET_TxD
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module ethernet_tb;
// Inputs
reg reset;
reg clk;
// Outputs
wire [3:0] out;
wire ctrl;
wire phy_reset;
wire T... | 6.95246 |
module ethernet_test (
input reset_n,
input fpga_gclk,
output e_reset,
// output CLK_25_ASIC,
output e_mdc,
inout e_mdio,
input e_rxc, //125Mhz ethernet gmii rx clock
input e_rxdv,
input e_rxer,
input [7:0] e_rxd,
input e_txc, ... | 7.043526 |
module ethernet_tx (
input wire clk125MHz,
input wire clk125MHz90,
input wire [7:0] raw_data,
input wire raw_data_valid,
input wire raw_data_enable,
input wire phy_ready,
// output
output wire [3:0] eth_txd,
output wire eth_txck,
output wire eth_txctl
);
wire [7:0] with_crc;... | 6.656028 |
module rxClkgen (
rxclk_in,
reset,
rxclk,
rxclk_180,
locked
);
input rxclk_in;
input reset;
output rxclk;
output rxclk_180;
output locked;
// 2x clock should be provided with dcm
wire rxclk;
wire rxclk_180;
// wire rxclk_2x;
/*dcm0 rx_dcm(.CLKIN_IN(rxclk_in),
.R... | 6.819799 |
module rxRSIO (
rxclk,
rxclk_180,
rxclk_2x,
reset,
rxd_in,
rxc_in,
rxd64,
rxc8,
local_fault,
remote_fault
);
input rxclk;
input rxclk_180;
input rxclk_2x;
input reset;
input [31:0] rxd_in;
input [3:0] rxc_in;
output [63:0] rxd64;
output [7:0] rxc8;
output local_... | 7.067817 |
module rxRSLayer (
rxclk,
rxclk_180,
rxclk_2x,
reset,
link_fault,
rxd64,
rxc8,
rxd_in,
rxc_in
);
input rxclk;
input rxclk_180;
input rxclk_2x;
input reset;
input [31:0] rxd_in;
input [3:0] rxc_in;
output [1:0] link_fault;
output [63:0] rxd64;
output [7:0] rxc8;
w... | 6.612035 |
module SwitchAsyncFIFO (
inReset,
iWClk,
iWEn,
ivDataIn,
qWFull,
qvWCount,
iRClk,
iREn,
ovDataOut,
qREmpty,
qvRNumberLeft
);
// Default address and data width
parameter pDepthWidth = 5;
parameter pWordWidth = 16;
input inReset;
input iWClk;
input iWEn;
input [... | 8.02377 |
module DualPortRAM_ASYN (
// Generic synchronous two-port RAM interface
WriteClock,
MemWEn,
MemWAddr,
MemDataIn,
ReadClock,
MemRAddr,
MemDataOut
);
// Default address and data width
parameter pDepthWidth = 5;
parameter pWordWidth = 16;
// Generic synchronous two-port RAM interf... | 8.984598 |
module SwitchSyncFIFO (
nReset,
iClk,
iWEn,
ivDataIn,
iREn,
ovDataOut,
qEmpty,
qFull,
qvCount
);
// Default address and data width
parameter pDepthWidth = 5;
parameter pWordWidth = 16;
input nReset;
input iClk;
input iWEn;
input [pWordWidth-1:0] ivDataIn;
input iREn... | 8.40197 |
module DualPortRAM (
clock,
MemWEn,
qvWAddr,
vDataIn,
qvRAddr,
vDataOut
);
// Default address and data width
parameter pDepthWidth = 5;
parameter pWordWidth = 16;
// Generic synchronous two-port RAM interface
input clock; // clock
input MemWEn; // write enable input
input [pDep... | 8.237962 |
module ack_counter (
clock, // 156 MHz clock
reset, // active high, asynchronous Reset input
ready,
tx_start, // Active high tx_start signal for counter
max_count, //16 bit reg for the maximum count to generate the ack signal
tx_ack // Active high signal
);
// Ports declaration
input c... | 7.485899 |
module ethrx_realign (
input clk,
input reset,
input clear,
input [35:0] datain,
input src_rdy_i,
output dst_rdy_o,
output [35:0] dataout,
output src_rdy_o,
input dst_rdy_i
);
reg [1:0] state;
reg [15:0] held;
reg [1:0] held_occ;
wire xfer_in = src_rdy_i & dst_r... | 7.158761 |
module ethtx_realign (
input clk,
input reset,
input clear,
input [35:0] datain,
input src_rdy_i,
output dst_rdy_o,
output [35:0] dataout,
output src_rdy_o,
input dst_rdy_i
);
reg [ 1:0] state;
reg [15:0] held;
reg [ 1:0] held_occ;
reg held_sof;
wire xfe... | 7.116766 |
module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be ... | 7.379264 |
module eth_controller (
input wire in_txen, // mcu/cpu to mac transmit enable
input wire [7:0] in_txd, // mcu/cpu to mac transmit data
input wire in_rxen, // wire to phy receive enable
input wire [7:0] in_rxd, // wire to phy receive data
output wire out_tx_ready, // mac to mcu/cpu transmit read... | 9.135858 |
module eth_encode #(
parameter MAC = 48'h010203040506,
parameter TYPE = 16'habcd
) (
input clk,
input rst,
output reg ack_rd_en_out,
input [63:0] ack_rd_d_in,
input ack_rd_empty_in,
output reg ps2_rd_en_out,
input [63:0] ps2_rd_d_in,
input ps2_rd_empty_in,
output reg ctl_wr_en_out,
output reg [15:0] c... | 6.57817 |
module eth_fifo (
data_in,
data_out,
clk,
reset,
write,
read,
clear,
almost_full,
full,
almost_empty,
empty,
cnt
);
parameter DATA_WIDTH = 32;
parameter DEPTH = 8;
parameter CNT_WIDTH = 4;
parameter Tp = 1;
input clk;
input reset;
input write;
input rea... | 7.753817 |
module eth_simple_dual_port_ram #(
parameter Dw = 8,
parameter Aw = 6
) (
data,
read_addr,
write_addr,
we,
clk,
q
);
input [Dw-1 : 0] data;
input [Aw-1 : 0] read_addr;
input [Aw-1 : 0] write_addr;
input we;
input clk;
output reg [Dw-1 : 0] q;
// Declare the RAM variable
... | 8.346598 |
module eth_single_port_ram #(
parameter Dw = 8,
parameter Aw = 6
) (
data,
addr,
we,
clk,
q
);
input [(Dw-1):0] data;
input [(Aw-1):0] addr;
input we, clk;
output [(Dw-1):0] q;
// Declare the RAM variable
reg [Dw-1:0] ram[2**Aw-1:0];
// Variable to hold the registered read a... | 7.991995 |
module eth_gtx_hook #(
parameter JUMBO_DW = 14, // Not used, just holdover for compatibility with older eth_gtx_bridge
parameter EVENINIT = 0,
parameter ENC_DISPINIT = 1'b0,
parameter GTX_DW = 20
) // Parallel GTX data width; Supported values are 10b and 20b
(
input gtx_tx_clk, // ... | 6.721636 |
module eth_host (
// WISHBONE common
wb_clk_i,
wb_rst_i,
// WISHBONE master
wb_adr_o,
wb_sel_o,
wb_we_o,
wb_dat_i,
wb_dat_o,
wb_cyc_o,
wb_stb_o,
wb_ack_i,
wb_err_i
);
parameter Tp = 1;
input wb_clk_i, wb_rst_i;
input [31:0] wb_dat_i;
input wb_ack_i, wb_err... | 6.705477 |
module eth_l3_checksum (
MRxClk,
Reset,
RxData,
ByteCnt,
CheckSum,
CSready
);
input MRxClk;
input Reset;
input [7:0] RxData;
input [15:0] ByteCnt;
output [15:0] CheckSum;
output CSready;
reg [15:0] CheckSum;
reg [31:0] Sum;
reg CSready;
reg [ 1:0] StartCalc;
reg ... | 6.506276 |
module
// by liam davey (29/4/11)
//
module eth_loop (
input clk,
input rst,
output reg rd_en_out,
input rd_end_in,
input [8:0] rd_d_in,
input rd_empty_in,
output reg wr_chk_out,
output reg wr_clr_out,
output reg wr_en_out,
output reg [8:0] wr_d_out,
input wr_full_in
);
reg [1:0] state;
reg [1:0] su... | 6.972959 |
module eth_mac_conf #(
parameter SRC_MAC = 48'h001122334455
) (
output wire [79:0] mac_tx_configuration_vector,
output wire [79:0] mac_rx_configuration_vector
);
// TX Configuration
assign mac_tx_configuration_vector[79:32] = SRC_MAC;
assign mac_tx_configuration_vector[30:16] = 1518;
assign mac_tx_... | 7.941077 |
module eth_mac_mii #(
// target ("SIM", "GENERIC", "XILINX", "ALTERA")
parameter TARGET = "GENERIC",
// Clock input style ("BUFG", "BUFR", "BUFIO", "BUFIO2")
// Use BUFR for Virtex-5, Virtex-6, 7-series
// Use BUFG for Ultrascale
// Use BUFIO2 for Spartan-6
parameter CLOCK_INPUT_STYLE = "BUF... | 7.854696 |
module eth_mac_phy_10g_rx #(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH / 8),
parameter HDR_WIDTH = (DATA_WIDTH / 32),
parameter PTP_PERIOD_NS = 4'h6,
parameter PTP_PERIOD_FNS = 16'h6666,
parameter PTP_TS_ENABLE = 0,
parameter PTP_TS_WIDTH = 96,
parameter USER_WIDTH = ... | 6.816642 |
module eth_mac_phy_10g_tx #(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH / 8),
parameter HDR_WIDTH = (DATA_WIDTH / 32),
parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter PTP_PERIOD_NS = 4'h6,
parameter PTP_PERIOD_FNS = 16... | 6.816642 |
module
// by liam davey (30/4/11)
//
// reads data and addresses from a fifo and
// writes them to the dram mcb fifo's.
//
module eth_mcb_if (
input clk,
input rst,
output reg rd_en_out,
input [35:0] rd_d_in,
input rd_empty_in,
output reg mcb_cmd_en_out,
output [2:0] mcb_cmd_instr_out,
output [5:0] mcb_cmd... | 6.972959 |
module eth_memory (
wb_clk_i,
wb_rst_i,
wb_adr_i,
wb_sel_i,
wb_we_i,
wb_cyc_i,
wb_stb_i,
wb_ack_o,
wb_err_o,
wb_dat_o,
wb_dat_i
);
parameter Tp = 1;
input wb_clk_i, wb_rst_i;
input [31:0] wb_adr_i, wb_dat_i;
input [3:0] wb_sel_i;
input wb_we_i, wb_cyc_i, wb_stb_i;... | 6.615497 |
module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be ... | 7.379264 |
module eth_parser #(
parameter C_S_AXIS_DATA_WIDTH = 256,
parameter C_S_AXIS_TUSER_WIDTH = 128,
parameter SRC_PORT_POS = 16,
parameter NUM_QUEUES = 8
) (
// --- Interface to the previous stage
input [ C_S_AXIS_DATA_WIDTH-1:0] tdata,
input [C_S_AXIS_TUSER_WIDTH-1:0] tuser,
... | 8.673171 |
module eth_phy_10g #(
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = (DATA_WIDTH / 8),
parameter HDR_WIDTH = 2,
parameter BIT_REVERSE = 0,
parameter SCRAMBLER_DISABLE = 0,
parameter PRBS31_ENABLE = 0,
parameter TX_SERDES_PIPELINE = 0,
parameter RX_SERDES_PIPELINE = 0,
parameter BI... | 8.261117 |
module eth_phy_10g_rx #(
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = (DATA_WIDTH / 8),
parameter HDR_WIDTH = 2,
parameter BIT_REVERSE = 0,
parameter SCRAMBLER_DISABLE = 0,
parameter PRBS31_ENABLE = 0,
parameter SERDES_PIPELINE = 0,
parameter BITSLIP_HIGH_CYCLES = 1,
parameter B... | 7.902033 |
module eth_phy_10g_rx_ber_mon #(
parameter HDR_WIDTH = 2,
parameter COUNT_125US = 125000 / 6.4
) (
input wire clk,
input wire rst,
/*
* SERDES interface
*/
input wire [HDR_WIDTH-1:0] serdes_rx_hdr,
/*
* Status
*/
output wire rx_high_ber
);
// bus width assertio... | 7.902033 |
module eth_phy_10g_rx_frame_sync #(
parameter HDR_WIDTH = 2,
parameter BITSLIP_HIGH_CYCLES = 1,
parameter BITSLIP_LOW_CYCLES = 8
) (
input wire clk,
input wire rst,
/*
* SERDES interface
*/
input wire [HDR_WIDTH-1:0] serdes_rx_hdr,
output wire serdes_rx_bitsli... | 7.902033 |
module eth_phy_10g_rx_watchdog #(
parameter HDR_WIDTH = 2,
parameter COUNT_125US = 125000 / 6.4
) (
input wire clk,
input wire rst,
/*
* SERDES interface
*/
input wire [HDR_WIDTH-1:0] serdes_rx_hdr,
output wire serdes_rx_reset_req,
/*
* Monitor inputs
... | 7.902033 |
module eth_phy_10g_tx #(
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = (DATA_WIDTH / 8),
parameter HDR_WIDTH = 2,
parameter BIT_REVERSE = 0,
parameter SCRAMBLER_DISABLE = 0,
parameter PRBS31_ENABLE = 0,
parameter SERDES_PIPELINE = 0
) (
input wire clk,
input wire rst,
/*
... | 7.609146 |
module eth_reframe #(
parameter WORDS = 4
) (
input [64*WORDS-1:0] din_data,
input [ 2*WORDS-1:0] din_frame,
output [66*WORDS-1:0] dout
);
genvar i;
generate
for (i = 0; i < WORDS; i = i + 1) begin : lp
// merge the framing and data bits
assign dout[(i+1)*66-1:i*66] = {din_data[(i... | 7.019177 |
module eth_register (
DataIn,
DataOut,
Write,
Clk,
Reset,
SyncReset
);
parameter WIDTH = 8; // default parameter of the register width
parameter RESET_VALUE = 0;
input [WIDTH-1:0] DataIn;
input Write;
input Clk;
input Reset;
input SyncReset;
output [WIDTH-1:0] DataOut;
reg... | 7.59973 |
module eth_rx (
input clk_mac,
input rst_n,
input eth_crsdv,
input eth_rxerr,
input [1:0] eth_rxd,
output reg rx_vld,
output reg [7:0] rx_dat,
output reg rx_sof,
output reg rx_eof,
output reg rx_err
);
`include "util.vh"
reg eth_c... | 7.701743 |
module eth_rxaddrcheck (
MRxClk,
Reset,
RxData,
Broadcast,
r_Bro,
r_Pro,
ByteCntEq2,
ByteCntEq3,
ByteCntEq4,
ByteCntEq5,
ByteCntEq6,
ByteCntEq7,
HASH0,
HASH1,
CrcHash,
CrcHashGood,
StateData,
RxEndFrm,
Multicast,
MAC,
RxAbort,
Addre... | 7.924255 |
module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be ... | 7.379264 |
module eth_smi (
input clk_mac,
input rst_n,
output ready,
input valid,
input write,
input [ 4:0] phyaddr,
input [ 4:0] register,
output [15:0] read_value,
input [15:0] write_value,
output reg eth_mdc,
inout eth_mdio
);
reg [3:0] counter;
... | 7.549756 |
module eth_config (
input clk_mac,
input rst_n,
input eth_intn,
output eth_mdc,
inout eth_mdio,
input reg_vld,
input [ 4:0] reg_addr,
input reg_write,
input [15:0] reg_wval,
output reg [15:0] reg_rval,
output reg reg_ack,
outp... | 6.850916 |
module eth_top_tb;
reg clk, resetn;
reg eth_col;
reg eth_crs;
wire eth_ref_clk;
wire eth_rx_clk;
reg eth_rxdv;
reg eth_rxerr;
wire eth_tx_clk;
reg [3:0] eth_rx_data;
wire eth_tx_en;
wire [3:0] eth_tx_data;
wire eth_rst_n;
reg s... | 6.571508 |
module eth_tx_scheduler (
input wire clk,
input wire rst_n,
input wire [7:0] rx_error,
input wire dim_error,
input wire data_available,
input wire read,
output wire [2:0] frame,
output wire frame_available
);
/* Frame types */
localparam [2:0] FRAME_NONE = 3'b000;
localparam [2:0]... | 7.180213 |
module eth_unframe #(
parameter WORDS = 4,
parameter LATENCY = 2
) (
input clk,
input [66*WORDS-1:0] din,
output [2*WORDS-1:0] dout_frame_lag,
output [64*WORDS-1:0] dout_data
);
wire [2*WORDS-1:0] dout_frame;
genvar i;
generate
for (i = 0; i < WORDS; i = i + 1) begin : lp
// s... | 6.886556 |
module ha_0 (
A,
B,
S,
C
);
input A, B;
output S, C;
XOR2X1 U1 (
.A(B),
.B(A),
.Y(S)
);
AND2X1 U2 (
.A(A),
.B(B),
.Y(C)
);
endmodule
| 7.918671 |
module ha_238 (
A,
B,
S,
C
);
input A, B;
output S, C;
XOR2X1 U1 (
.A(B),
.B(A),
.Y(S)
);
AND2X1 U2 (
.A(A),
.B(B),
.Y(C)
);
endmodule
| 7.767256 |
module ha_239 (
A,
B,
S,
C
);
input A, B;
output S, C;
XOR2X1 U1 (
.A(B),
.B(A),
.Y(S)
);
AND2X1 U2 (
.A(A),
.B(B),
.Y(C)
);
endmodule
| 7.466803 |
module fa_0 (
A,
B,
Cin,
S,
Cout
);
input A, B, Cin;
output S, Cout;
wire s1, c1, c2;
ha_239 HA1 (
.A(A),
.B(B),
.S(s1),
.C(c1)
);
ha_238 HA2 (
.A(s1),
.B(Cin),
.S(S),
.C(c2)
);
OR2X1 U1 (
.A(c1),
.B(c2),
.Y(Cout)
)... | 7.346768 |
module ha_35 (
A,
B,
S,
C
);
input A, B;
output S, C;
XOR2X1 U1 (
.A(B),
.B(A),
.Y(S)
);
AND2X1 U2 (
.A(A),
.B(B),
.Y(C)
);
endmodule
| 7.976383 |
module ha_1 (
A,
B,
S,
C
);
input A, B;
output S, C;
XOR2X1 U1 (
.A(B),
.B(A),
.Y(S)
);
AND2X1 U2 (
.A(A),
.B(B),
.Y(C)
);
endmodule
| 8.251464 |
module ha_2 (
A,
B,
S,
C
);
input A, B;
output S, C;
XOR2X1 U1 (
.A(B),
.B(A),
.Y(S)
);
AND2X1 U2 (
.A(A),
.B(B),
.Y(C)
);
endmodule
| 8.820539 |
module fa_1 (
A,
B,
Cin,
S,
Cout
);
input A, B, Cin;
output S, Cout;
wire s1, c1, c2;
ha_2 HA1 (
.A(A),
.B(B),
.S(s1),
.C(c1)
);
ha_1 HA2 (
.A(s1),
.B(Cin),
.S(S),
.C(c2)
);
OR2X1 U1 (
.A(c1),
.B(c2),
.Y(Cout)
);
en... | 7.561253 |
module ha_3 (
A,
B,
S,
C
);
input A, B;
output S, C;
XOR2X1 U1 (
.A(B),
.B(A),
.Y(S)
);
AND2X1 U2 (
.A(A),
.B(B),
.Y(C)
);
endmodule
| 8.241723 |
module ha_4 (
A,
B,
S,
C
);
input A, B;
output S, C;
XOR2X1 U1 (
.A(B),
.B(A),
.Y(S)
);
AND2X1 U2 (
.A(A),
.B(B),
.Y(C)
);
endmodule
| 8.54402 |
module fa_2 (
A,
B,
Cin,
S,
Cout
);
input A, B, Cin;
output S, Cout;
wire s1, c1, c2;
ha_4 HA1 (
.A(A),
.B(B),
.S(s1),
.C(c1)
);
ha_3 HA2 (
.A(s1),
.B(Cin),
.S(S),
.C(c2)
);
OR2X1 U1 (
.A(c1),
.B(c2),
.Y(Cout)
);
en... | 7.487957 |
module ha_5 (
A,
B,
S,
C
);
input A, B;
output S, C;
XOR2X1 U1 (
.A(B),
.B(A),
.Y(S)
);
AND2X1 U2 (
.A(A),
.B(B),
.Y(C)
);
endmodule
| 8.445306 |
module ha_6 (
A,
B,
S,
C
);
input A, B;
output S, C;
XOR2X1 U1 (
.A(B),
.B(A),
.Y(S)
);
AND2X1 U2 (
.A(A),
.B(B),
.Y(C)
);
endmodule
| 8.462988 |
module fa_3 (
A,
B,
Cin,
S,
Cout
);
input A, B, Cin;
output S, Cout;
wire s1, c1, c2;
ha_6 HA1 (
.A(A),
.B(B),
.S(s1),
.C(c1)
);
ha_5 HA2 (
.A(s1),
.B(Cin),
.S(S),
.C(c2)
);
OR2X1 U1 (
.A(c1),
.B(c2),
.Y(Cout)
);
en... | 7.622918 |
module ha_7 (
A,
B,
S,
C
);
input A, B;
output S, C;
XOR2X1 U1 (
.A(B),
.B(A),
.Y(S)
);
AND2X1 U2 (
.A(A),
.B(B),
.Y(C)
);
endmodule
| 8.192229 |
module ha_8 (
A,
B,
S,
C
);
input A, B;
output S, C;
XOR2X1 U1 (
.A(B),
.B(A),
.Y(S)
);
AND2X1 U2 (
.A(A),
.B(B),
.Y(C)
);
endmodule
| 8.302319 |
module fa_4 (
A,
B,
Cin,
S,
Cout
);
input A, B, Cin;
output S, Cout;
wire s1, c1, c2;
ha_8 HA1 (
.A(A),
.B(B),
.S(s1),
.C(c1)
);
ha_7 HA2 (
.A(s1),
.B(Cin),
.S(S),
.C(c2)
);
OR2X1 U1 (
.A(c1),
.B(c2),
.Y(Cout)
);
en... | 7.659597 |
module ha_9 (
A,
B,
S,
C
);
input A, B;
output S, C;
XOR2X1 U1 (
.A(B),
.B(A),
.Y(S)
);
AND2X1 U2 (
.A(A),
.B(B),
.Y(C)
);
endmodule
| 8.400956 |
module ha_10 (
A,
B,
S,
C
);
input A, B;
output S, C;
XOR2X1 U1 (
.A(B),
.B(A),
.Y(S)
);
AND2X1 U2 (
.A(A),
.B(B),
.Y(C)
);
endmodule
| 8.137426 |
module fa_5 (
A,
B,
Cin,
S,
Cout
);
input A, B, Cin;
output S, Cout;
wire s1, c1, c2;
ha_10 HA1 (
.A(A),
.B(B),
.S(s1),
.C(c1)
);
ha_9 HA2 (
.A(s1),
.B(Cin),
.S(S),
.C(c2)
);
OR2X1 U1 (
.A(c1),
.B(c2),
.Y(Cout)
);
e... | 7.197287 |
module ha_11 (
A,
B,
S,
C
);
input A, B;
output S, C;
XOR2X1 U1 (
.A(B),
.B(A),
.Y(S)
);
AND2X1 U2 (
.A(A),
.B(B),
.Y(C)
);
endmodule
| 7.861981 |
module ha_12 (
A,
B,
S,
C
);
input A, B;
output S, C;
XOR2X1 U1 (
.A(B),
.B(A),
.Y(S)
);
AND2X1 U2 (
.A(A),
.B(B),
.Y(C)
);
endmodule
| 8.559907 |
module fa_6 (
A,
B,
Cin,
S,
Cout
);
input A, B, Cin;
output S, Cout;
wire s1, c1, c2;
ha_12 HA1 (
.A(A),
.B(B),
.S(s1),
.C(c1)
);
ha_11 HA2 (
.A(s1),
.B(Cin),
.S(S),
.C(c2)
);
OR2X1 U1 (
.A(c1),
.B(c2),
.Y(Cout)
);
... | 7.296649 |
module ha_13 (
A,
B,
S,
C
);
input A, B;
output S, C;
XOR2X1 U1 (
.A(B),
.B(A),
.Y(S)
);
AND2X1 U2 (
.A(A),
.B(B),
.Y(C)
);
endmodule
| 8.04693 |
module ha_14 (
A,
B,
S,
C
);
input A, B;
output S, C;
XOR2X1 U1 (
.A(B),
.B(A),
.Y(S)
);
AND2X1 U2 (
.A(A),
.B(B),
.Y(C)
);
endmodule
| 8.180543 |
module fa_7 (
A,
B,
Cin,
S,
Cout
);
input A, B, Cin;
output S, Cout;
wire s1, c1, c2;
ha_14 HA1 (
.A(A),
.B(B),
.S(s1),
.C(c1)
);
ha_13 HA2 (
.A(s1),
.B(Cin),
.S(S),
.C(c2)
);
OR2X1 U1 (
.A(c1),
.B(c2),
.Y(Cout)
);
... | 6.995727 |
module ha_15 (
A,
B,
S,
C
);
input A, B;
output S, C;
XOR2X1 U1 (
.A(B),
.B(A),
.Y(S)
);
AND2X1 U2 (
.A(A),
.B(B),
.Y(C)
);
endmodule
| 8.279878 |
module ha_16 (
A,
B,
S,
C
);
input A, B;
output S, C;
XOR2X1 U1 (
.A(B),
.B(A),
.Y(S)
);
AND2X1 U2 (
.A(A),
.B(B),
.Y(C)
);
endmodule
| 8.36379 |
module fa_8 (
A,
B,
Cin,
S,
Cout
);
input A, B, Cin;
output S, Cout;
wire s1, c1, c2;
ha_16 HA1 (
.A(A),
.B(B),
.S(s1),
.C(c1)
);
ha_15 HA2 (
.A(s1),
.B(Cin),
.S(S),
.C(c2)
);
OR2X1 U1 (
.A(c1),
.B(c2),
.Y(Cout)
);
... | 7.194293 |
module ha_17 (
A,
B,
S,
C
);
input A, B;
output S, C;
XOR2X1 U1 (
.A(B),
.B(A),
.Y(S)
);
AND2X1 U2 (
.A(A),
.B(B),
.Y(C)
);
endmodule
| 7.929076 |
module ha_18 (
A,
B,
S,
C
);
input A, B;
output S, C;
XOR2X1 U1 (
.A(B),
.B(A),
.Y(S)
);
AND2X1 U2 (
.A(A),
.B(B),
.Y(C)
);
endmodule
| 7.952132 |
module fa_9 (
A,
B,
Cin,
S,
Cout
);
input A, B, Cin;
output S, Cout;
wire s1, c1, c2;
ha_18 HA1 (
.A(A),
.B(B),
.S(s1),
.C(c1)
);
ha_17 HA2 (
.A(s1),
.B(Cin),
.S(S),
.C(c2)
);
OR2X1 U1 (
.A(c1),
.B(c2),
.Y(Cout)
);
... | 7.177852 |
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