code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module ha_84 (
A,
B,
S,
C
);
input A, B;
output S, C;
XOR2X1 U1 (
.A(B),
.B(A),
.Y(S)
);
AND2X1 U2 (
.A(A),
.B(B),
.Y(C)
);
endmodule
| 8.292642 |
module fa_41 (
A,
B,
Cin,
S,
Cout
);
input A, B, Cin;
output S, Cout;
wire s1, c1, c2;
ha_84 HA1 (
.A(A),
.B(B),
.S(s1),
.C(c1)
);
ha_83 HA2 (
.A(s1),
.B(Cin),
.S(S),
.C(c2)
);
OR2X1 U1 (
.A(c1),
.B(c2),
.Y(Cout)
);... | 7.449543 |
module ha_85 (
A,
B,
S,
C
);
input A, B;
output S, C;
XOR2X1 U1 (
.A(B),
.B(A),
.Y(S)
);
AND2X1 U2 (
.A(A),
.B(B),
.Y(C)
);
endmodule
| 8.218039 |
module ha_86 (
A,
B,
S,
C
);
input A, B;
output S, C;
XOR2X1 U1 (
.A(B),
.B(A),
.Y(S)
);
AND2X1 U2 (
.A(A),
.B(B),
.Y(C)
);
endmodule
| 8.213562 |
module fa_42 (
A,
B,
Cin,
S,
Cout
);
input A, B, Cin;
output S, Cout;
wire s1, c1, c2;
ha_86 HA1 (
.A(A),
.B(B),
.S(s1),
.C(c1)
);
ha_85 HA2 (
.A(s1),
.B(Cin),
.S(S),
.C(c2)
);
OR2X1 U1 (
.A(c1),
.B(c2),
.Y(Cout)
);... | 7.314371 |
module ha_87 (
A,
B,
S,
C
);
input A, B;
output S, C;
XOR2X1 U1 (
.A(B),
.B(A),
.Y(S)
);
AND2X1 U2 (
.A(A),
.B(B),
.Y(C)
);
endmodule
| 8.476511 |
module ha_88 (
A,
B,
S,
C
);
input A, B;
output S, C;
XOR2X1 U1 (
.A(B),
.B(A),
.Y(S)
);
AND2X1 U2 (
.A(A),
.B(B),
.Y(C)
);
endmodule
| 8.150541 |
module fa_43 (
A,
B,
Cin,
S,
Cout
);
input A, B, Cin;
output S, Cout;
wire s1, c1, c2;
ha_88 HA1 (
.A(A),
.B(B),
.S(s1),
.C(c1)
);
ha_87 HA2 (
.A(s1),
.B(Cin),
.S(S),
.C(c2)
);
OR2X1 U1 (
.A(c1),
.B(c2),
.Y(Cout)
);... | 7.901968 |
module ha_89 (
A,
B,
S,
C
);
input A, B;
output S, C;
XOR2X1 U1 (
.A(B),
.B(A),
.Y(S)
);
AND2X1 U2 (
.A(A),
.B(B),
.Y(C)
);
endmodule
| 7.908548 |
module ha_90 (
A,
B,
S,
C
);
input A, B;
output S, C;
XOR2X1 U1 (
.A(B),
.B(A),
.Y(S)
);
AND2X1 U2 (
.A(A),
.B(B),
.Y(C)
);
endmodule
| 8.102715 |
module fa_44 (
A,
B,
Cin,
S,
Cout
);
input A, B, Cin;
output S, Cout;
wire s1, c1, c2;
ha_90 HA1 (
.A(A),
.B(B),
.S(s1),
.C(c1)
);
ha_89 HA2 (
.A(s1),
.B(Cin),
.S(S),
.C(c2)
);
OR2X1 U1 (
.A(c1),
.B(c2),
.Y(Cout)
);... | 7.754823 |
module ha_91 (
A,
B,
S,
C
);
input A, B;
output S, C;
XOR2X1 U1 (
.A(B),
.B(A),
.Y(S)
);
AND2X1 U2 (
.A(A),
.B(B),
.Y(C)
);
endmodule
| 8.048826 |
module ha_92 (
A,
B,
S,
C
);
input A, B;
output S, C;
XOR2X1 U1 (
.A(B),
.B(A),
.Y(S)
);
AND2X1 U2 (
.A(A),
.B(B),
.Y(C)
);
endmodule
| 8.186683 |
module fa_45 (
A,
B,
Cin,
S,
Cout
);
input A, B, Cin;
output S, Cout;
wire s1, c1, c2;
ha_92 HA1 (
.A(A),
.B(B),
.S(s1),
.C(c1)
);
ha_91 HA2 (
.A(s1),
.B(Cin),
.S(S),
.C(c2)
);
OR2X1 U1 (
.A(c1),
.B(c2),
.Y(Cout)
);... | 7.894232 |
module ha_93 (
A,
B,
S,
C
);
input A, B;
output S, C;
XOR2X1 U1 (
.A(B),
.B(A),
.Y(S)
);
AND2X1 U2 (
.A(A),
.B(B),
.Y(C)
);
endmodule
| 7.97532 |
module ha_94 (
A,
B,
S,
C
);
input A, B;
output S, C;
XOR2X1 U1 (
.A(B),
.B(A),
.Y(S)
);
AND2X1 U2 (
.A(A),
.B(B),
.Y(C)
);
endmodule
| 8.138507 |
module fa_46 (
A,
B,
Cin,
S,
Cout
);
input A, B, Cin;
output S, Cout;
wire s1, c1, c2;
ha_94 HA1 (
.A(A),
.B(B),
.S(s1),
.C(c1)
);
ha_93 HA2 (
.A(s1),
.B(Cin),
.S(S),
.C(c2)
);
OR2X1 U1 (
.A(c1),
.B(c2),
.Y(Cout)
);... | 7.835702 |
module
// DEPARTMENT: communication and electronics department
// AUTHOR: Mina Hanna
// AUTHOR EMAIL: mina.hannaone@gmail.com
//------------------------------------------------
// Release history
// VERSION DATE AUTHOR DESCRIPTION
// 1.0 4/9/2022 Mina Hanna final version
//----------------------------------------------... | 8.923686 |
module adder_8 (
input clk,
input rst_n,
output reg [7:0] counter,
output C,
input en,
input clr
);
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
counter <= 0;
end else begin
if (clr) begin
counter <= 0;
end else begin
if (en) begin
... | 7.047398 |
module Counter_32 (
input clk,
input rst_n,
input clr,
input en,
input [31:0] cmp_data,
output [31:0] data_out,
output full
);
wire [31:0] counter;
wire C_7_8;
wire C_15_16;
wire C_23_24;
adder_8 inst_adder_7_0 (
.clk(clk),
.rst_n(rst_n),
.counter(counter[7:0]),... | 7.041723 |
module ETS_Adder (
input clk,
input reset,
input [31:0] Average,
input data_in,
output [31:0] data,
input en_count,
input start,
output reg done
);
localparam IDLE = 2'b00;
localparam BUSY = 2'b01;
localparam DONE = 2'b10;
localparam CLR = 2'b11;
reg clr;
reg en;
wire ... | 6.988033 |
module etx_arbiter ( /*AUTOARG*/
// Outputs
txwr_wait,
txrd_wait,
txrr_wait,
etx_access,
cfg_access,
etx_packet,
// Inputs
clk,
nreset,
txwr_access,
txwr_packet,
txrd_access,
txrd_packet,
txrr_access,
txrr_packet,
etx_wait,
etx_cfg_wait
);
para... | 7.325843 |
module serial_tx (
serial_br_i,
serial_clock_i,
serial_reset_i_b,
serial_scon7_sm0_i,
serial_scon1_ti_i,
serial_serial_tx_i,
serial_data_sbuf_i,
serial_scon3_tb8_i,
serial_p3en_0_o,
serial_p3en_1_o,
serial_scon1_ti_o,
serial_send_o,
serial_data_en_o,
serial_data_t... | 7.116969 |
module top_timer2 (
top_timer2_reset_i,
top_timer2_clock_i_d,
top_timer2_pht_i,
top_timer2_sfr_tcon2_dfp_i,
top_timer2_sfr_tcon2_dfsel_i,
top_timer2_sfr_tcon2_edsel_i,
top_timer2_sfr_tacph_i,
top_timer2_sfr_tacpl_i,
top_timer2_sfr_tcon2_tf2_i,
timers_sfr_tcon2_tr2_i,
top_time... | 7.422483 |
module euclidean_loop (
clk,
reset_n,
start_compute,
a,
b,
d_out,
a_out,
done
);
input clk;
input reset_n;
input start_compute;
input [63:0] a;
input [63:0] b;
output [63:0] a_out;
output [63:0] d_out;
output done;
wire clk;
wire reset_n;
wire start_compute;
wi... | 6.877395 |
modules with logic that will be instantiated
// through the Datapath_Unit
// 2-input Multiplexer to be used for B input reg.
module Mux2in#( parameter W = 16 )
( in0,
in1,
sel,
out
);
input [W-1:0] in0;
input [W-1:0] in1;
input sel;
output [W-1:0] out;
reg... | 8.365714 |
module Mux3in #(
parameter W = 16
) (
in0,
in1,
in2,
sel,
out
);
input [W-1:0] in0;
input [W-1:0] in1;
input [W-1:0] in2;
input [1:0] sel;
output [W-1:0] out;
reg [W-1:0] out;
always @(*) begin
casex (sel)
2'b00: out = in0;
2'b01: out = in1;
2'b10: ou... | 9.049411 |
module ED_FF #(
parameter W = 16
) (
clk,
en,
d,
q
);
input clk;
input en;
input [W-1:0] d;
output [W-1:0] q;
reg [W-1:0] q;
always @(posedge clk) begin
if (en) q <= d;
end
endmodule
| 6.895216 |
module EQ_zero #(
parameter W = 16
) (
in0,
in1,
out
);
input [W-1:0] in0;
input [W-1:0] in1;
output out;
assign out = (in0 == in1);
endmodule
| 8.066027 |
modules.
module Less_than#( parameter W = 16 )
( in0,
in1,
out
);
input [W-1:0] in0;
input [W-1:0] in1;
output out;
assign out = ( in0 < in1 );
endmodule
| 8.949802 |
module Subtractor #(
parameter W = 16
) (
in0,
in1,
out
);
input [W-1:0] in0;
input [W-1:0] in1;
output [W-1:0] out;
assign out = in0 - in1;
endmodule
| 7.524266 |
modules
// Datapath Unit to instantiate together submodules.
module Datapath_Unit#( parameter W = 16 )
( clk,
operand_A,
operand_B,
result_data,
A_en,
B_en,
A_mux_sel,
B_mux_sel,
B_zero,
A_lt_B
);
input clk;
// Data signals
inp... | 6.881003 |
module Euclid_GCD #(
parameter W = 16
) (
clk,
reset,
operand_A,
operand_B,
result_data,
input_available,
result_rdy,
result_taken,
state,
nstate
);
input clk;
// Data signals
input [W-1:0] operand_A;
input [W-1:0] operand_B;
output [W-1:0] result_data;
// Cont... | 7.897897 |
module eu_rom (
input wire clk,
input wire clka,
input wire [11:0] addra,
output reg [31:0] douta
);
reg [31:0] memory[3961:0];
initial $readmemb("microcode.mem", memory);
always @(posedge clka) douta <= memory[addra];
endmodule
| 6.539755 |
module ev21g1_decode_tb;
/*****************************/
/* Variables for Input Ports */
/*****************************/
reg [31:0] instruction;
reg [31:0] input_port0;
reg [31:0] input_port1;
reg clk;
/******************************/
/* Variables for Output Ports */
/*****************************... | 7.923206 |
module ev2_irs (
inout [`EV2IF_SIZE-1:0] interface_io,
input irsclk_i,
input [15:0] dat_i,
output [15:0] count_o,
input wr_i,
output full_o,
input rst_i,
output rst_ack_o
);
assign interface_io[0] = irsclk_i;
assign interface_io[16:1] = dat_i;
assign count_o = interface_io[32:17];... | 6.694919 |
module ev2_irs_reassign (
A_i,
B_o
);
inout [`EV2IF_SIZE-1:0] A_i;
inout [`EV2IF_SIZE-1:0] B_o;
assign B_o[0] = A_i[0];
assign B_o[16:1] = A_i[16:1];
assign A_i[32:17] = B_o[32:17];
assign B_o[33] = A_i[33];
assign A_i[34] = B_o[34];
assign B_o[35] = A_i[35];
assign A_i[36] = B_o[36];
endmodu... | 6.740008 |
module ev2_debug (
inout [`EV2IF_SIZE-1:0] interface_io,
output irsclk_o,
output [15:0] dat_o,
output [15:0] count_o,
output wr_o,
output full_o,
output rst_o,
output rst_ack_o
);
assign irsclk_o = interface_io[0];
assign dat_o = interface_io[16:1];
assign count_o = interface_io[3... | 7.315649 |
module evaluate_branch (
ir,
cx,
zf,
cf,
sf,
vf,
pf,
take_br
);
input [7:0] ir;
input [15:0] cx;
input zf, cf, sf, vf, pf;
output take_br;
reg take_br;
wire cxo = cx == 16'h0001; // CX is one
wire cxz = cx == 16'h0000; // CX is zero
always @(ir or cx or cxz or cxo or... | 7.646968 |
module EVA_ArgSort (
clk,
rst,
start,
in,
done_sorting,
sorted_index_1D
);
parameter bit_len = 18;
parameter Number = 16;
input clk;
input rst;
input start;
input [bit_len*Number-1 : 0] in;
output done_sorting;
output [4*Number-1 : 0] sorted_index_1D;
wire done;
wire [3:0... | 7.04153 |
module EvE #(
parameter num_PE = 8
) (
parent1,
parent2,
input_clk,
wr_en,
reset,
cfg1,
cfg2,
cfg3,
out1,
out2,
out3
);
input [63:0] parent1;
input [63:0] parent2;
input input_clk, reset, wr_en;
output [64*num_PE-1:0] out1, out2, out3;
input wr_en;
input [31:0... | 6.753352 |
module even (
clk,
out,
N,
reset,
not_zero,
enable
);
input clk; // fast input clock
output out; // slower divided clock
input [`SIZE-1:0] N; // divide by factor 'N'
input reset; // asynchronous reset
input not_zero; // if !not_zero divide by 1
input enable; // enable the even... | 7.063318 |
module EvenParityChecker (
i_data,
i_parity,
o_error
);
parameter width = 1;
input [width - 1:0] i_data;
input i_parity;
output o_error;
assign o_error = ^{i_data, i_parity};
endmodule
| 7.407047 |
module EvenParityGenerator (
i_data,
o_parity
);
parameter width = 1;
input [width - 1:0] i_data;
output o_parity;
assign o_parity = ^{i_data};
endmodule
| 7.942596 |
module m (
a,
x
);
input [31:0] a;
output [31:0] x;
reg [31:0] x;
event e2;
always @e2 begin
#1 x <= a;
#2->et1.e1;
end
endmodule
| 6.590707 |
module events_tb;
reg rst = 0;
reg clk = 0;
wire uart_ready;
wire [7:0] uart_data_in;
wire uart_write;
wire uart_data_out;
uart_tx #(
.BDIV(2)
) uart (
.rst(rst),
.clk(clk),
.ready(uart_ready),
.data_in(uart_data_in),
.write(uart_wri... | 6.844678 |
module event_and_trigger_flag_generator #(
parameter NUM_TRIGGERS = 4
) (
input g_trigger_i,
input [NUM_TRIGGERS-1:0] triggers_i,
input clk_i,
input rst_i,
output event_flag_o,
output [NUM_TRIGGERS-1:0] trig_flag_o
);
reg g_trigger_latched = 0;
reg [NUM_TRIGGERS-1:0] trig_latched = {NUM... | 6.615009 |
module event_counter #(
parameter integer TARGET_WIDTH = 4,
parameter integer EVENT_IS_CLOCK = 0,
parameter integer HAS_ENABLE = 0,
parameter integer RESET_IF_REACHED = 1
) (
input wire ACLK,
input wire ARESETN,
input wire ENABLE,
input wire [TARGET_WIDTH-1 : 0] INIT_VAL,
... | 6.864007 |
module event_counter_tb;
reg ACLK;
reg ARESETN;
wire REACHED;
wire [3:0] COUNTER;
reg TICK;
reg ENABLE;
localparam HALF_CORE_PERIOD = 5; // 100Mhz
localparam PERIOD = HALF_CORE_PERIOD * 2;
localparam TARGET_WIDTH = 4;
wire [TARGET_WIDTH-1 : 0] INIT;
wire [TARGE... | 6.864007 |
module ndFF (
nset,
reset,
Q
);
input nset; // clk negedge set Q=1
input reset; // reset posedge set Q=0
output Q; // Q output
reg Q;
always @(negedge nset or posedge reset) begin
if (nset == 1'b0) Q = 1'b1;
else if (reset == 1'b1) Q = 1'b0;
end
endmodule
| 6.899502 |
module
* All inputs are defined in TUBOSIM spec
*
* PARAMETERS:
* data_wd: width of single Q entry.
* q_add_wd: address width of event q store element (RAM). for example
* q_add_wd=5 => maximal numbers of entries in q is 32.
* q_max_len: maximal length of Event Q
* lo: bit select. TIME low bit offset.... | 7.43345 |
module event_sent_fsm (
input reset,
input clk,
input [1:0] ddl_event_send_i,
input [1:0] ddl_xoff,
output reg ddl_event_send = 1'b0
);
reg ddl_event_send_ii = 1'b0;
parameter IDLE_st = 5'b00001;
parameter Check_st = 5'b00010;
parameter AllSent_st = 5'b00100;
parameter LowSent_st = 5'b0... | 8.781312 |
module CAE #(
parameter FLOAT = "no",
parameter SIGNED = "no",
parameter DATW = 64,
parameter KEYW = 32
) (
input wire CLK,
input wire [DATW-1:0] DIN0,
input wire [DATW-1:0] DIN1,
output wire [DATW-1:0] DOT0,
output wire [DATW-1:0] DOT1
);
function [DATW-1:0] mu... | 8.364113 |
module K_CAE #(
parameter FLOAT = "no",
parameter SIGNED = "no",
parameter KEYW = 32
) (
input wire CLK,
input wire [KEYW-1:0] DIN0,
input wire [KEYW-1:0] DIN1,
output wire [KEYW-1:0] DOT0,
output wire [KEYW-1:0] DOT1,
output wire COMP
);
function [KEYW... | 7.97929 |
module P_EXCHANGE #(
parameter PAYW = 32
) (
input wire COMP,
input wire [PAYW-1:0] DIN0,
input wire [PAYW-1:0] DIN1,
output wire [PAYW-1:0] DOT0,
output wire [PAYW-1:0] DOT1
);
function [PAYW-1:0] mux;
input [PAYW-1:0] a;
input [PAYW-1:0] b;
input sel;
begin
... | 7.504532 |
module EVEN_ODD #(
parameter P_LOG = 4,
parameter FLOAT = "no",
parameter SIGNED = "no",
parameter DATW = 64,
parameter KEYW = 32
) (
input wire CLK,
input wire RST,
input wire [(DATW<<P_LOG)-1:0] DIN,
input wire D... | 7.858464 |
module even_parity_tb ();
wire parity;
reg [15:0] in;
reg clock;
integer myseed;
even_parity e0 (
parity,
in,
clock
);
initial begin
clock = 1'b0;
forever #5 clock = ~clock;
end
initial begin
$dumpfile("even_parity_tb.vcd");
$dumpvars(0, even_parity_tb);
myse... | 7.083399 |
module everloop #(
parameter SYS_FREQ_HZ = "mandatory",
parameter DATA_WIDTH = "mandatory",
parameter DATA_PERIOD = 833_000,
parameter ZERO_HIGH_TIME = 300,
parameter ONE_HIGH_TIME = 600,
parameter [8:0] DATA_PERIOD_COUNTER = $cei... | 6.835799 |
module everloop_ram #(
parameter MEM_FILE_NAME = "none",
parameter ADDR_WIDTH = "mandatory",
parameter DATA_WIDTH = "mandatory"
) (
input clk,
input we_a,
output reg ack_a,
input [ADDR_WIDTH-1:0] adr_a,
input [DATA_WI... | 6.81884 |
module everloop_fsm #(
parameter SYS_FREQ_HZ = "mandatory",
parameter N_LEDS = "mandatory",
parameter RESET_COUNTER = 12000 // uS
) (
input clk, // Clock
input resetn, // Asynchronous reset active low
input send_complete,
output reg ... | 6.582761 |
module EvE_PE (
genomeID,
parent1,
parent2,
clk,
wr_en,
rst,
cfg1,
cfg2,
cfg3,
out1,
out2,
out3
);
wire [35:0] s_out;
input [7:0] genomeID;
wire [63:0] crossover_out, perturbaiton_out, deleteGene_out;
input [63:0] parent1;
input [63:0] parent2;
wire [63:0] par... | 6.523311 |
module EvE_Perturbation_Engine (
Crossover,
ChildGene,
Rand,
Config
);
input [63:0] Crossover;
output [63:0] ChildGene;
input [35:0] Rand;
input [31:0] Config;
wire [ 3:0] Select;
wire [31:0] Mutated;
wire [31:0] Perturbation;
assign Perturbation[31:27] = 5'd0;
assign Perturbation[26... | 7.19595 |
module EvE_tb ();
reg clk;
reg rst;
reg wr_en;
parameter num_PE = 8;
// Changed the following
//reg [7:0] genomeNum;
reg [31:0] cnfg1;
reg [31:0] cnfg2;
reg [31:0] cnfg3;
reg [63:0] parentA;
reg [63:0] parentB;
wire [num_PE *64 - 1:0] gene1;
wire [num_PE *64 - 1:0] gene2;
wire [num_PE *64... | 6.618066 |
module eviction_ctr (
clk,
rst,
update_EVA,
evict_data,
evict_addr,
age_1D,
classificationBit,
evictionCtr_R_1D,
evictionCtr_NR_1D
);
parameter k = 3; /////////////age counter width//////////
parameter j = 2; /////////////set counter width- will be used for Age Granularity///... | 7.13227 |
module eSYNCERR_213 (
error,
stage,
we,
metric,
reset,
clock
);
output error;
input [3:0] stage;
input we;
input [2:0] metric;
input reset;
input clock;
wire N48;
FDC error_reg (
.CLR(reset),
.Q (error),
.C (clock),
.D (N48)
);
GND C35 (.G(N48));... | 6.627565 |
module XORCY (
O,
LI,
CI
);
output O;
input LI;
input CI;
assign O = (LI ^ CI);
endmodule
| 6.992694 |
module BUFE (
O,
I,
E
);
output O;
input I;
input E;
reg O;
always @(I or E) begin
if (E) O = (I);
else O = 1'bz;
end
endmodule
| 6.515199 |
module mode_control (
input clock,
input reset,
input mode,
input valid_vote_casted,
input [7:0] candidate1_votes,
input [7:0] candidate2_votes,
input [7:0] candidate3_votes,
input [7:0] candidate4_votes,
input [7:0] candidate5_votes,
input [7:0] candidate6_votes,
input candi... | 6.590285 |
module evm (
input clock,
input reset,
input mode,
input candidate1_button,
input candidate2_button,
input candidate3_button,
input candidate4_button,
input candidate5_button,
input candidate6_button,
output [7:0] result
);
wire anyValid_vote;
wire valid_vote1;
wire valid_... | 8.556759 |
module evolve_key_128 (
key_in,
rconst,
key_out
);
input [127:0] key_in;
input [7:0] rconst; // the low order 24 bits are all 0
output [127:0] key_out;
wire [127:0] key_out;
wire [ 31:0] rot_key;
wire [ 31:0] subrot_key;
rot_word rw (
.in (key_in[31:0]),
.out(rot_key)
... | 8.254898 |
module evrSROC #(
parameter SYSCLK_FREQUENCY = -1,
parameter SROC_DIVIDER = -1,
parameter DEBUG = "false"
) (
input sysClk,
input evrClk,
(*mark_debug=DEBUG*) input evrHeartbeatMarker,
(*mark_debug=DEBUG*) input evrPulsePerSecondMarker,
output wire heartBeatValid,
out... | 6.914691 |
module evrSROC_tb;
localparam SIM_SYS_CLK_FREQ = 133333333 / 1e4;
real SYS_CLK_PER = 7.5; // ns
localparam SIM_EVR_CLK_FREQ = 125000000 / 1e4;
real EVR_CLK_PER = 8;
localparam SIM_TIME = 1e6;
reg fail = 1;
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("evrSROC.vcd");
$dumpva... | 7.553343 |
module evt_capture_oq_plugin #(
parameter NUM_OUTPUT_QUEUES = 8,
parameter PKT_WORDS_WIDTH = 8,
parameter SRAM_ADDR_WIDTH = 19,
parameter NUM_OQ_WIDTH = log2(NUM_OUTPUT_QUEUES),
parameter SIG_VALUE_SIZE = 8,
parameter ALL_SIG_VALUES_SIZE = 3 * SIG_VALUE_SIZE,
parameter ... | 7.050815 |
module event_sync #(
parameter DATA_WIDTH = 65,
parameter TOTAL_CLUSTERS = 17,
parameter TOTAL_OUTPUT_BOARDS = 4,
parameter FIFO_DEPTH_BITS = 6,
parameter BOARD_ID = 0
) (
input logic es_clk,
input logic es_rst_n,
input logic es_srst_n,
input logic [DATA_WIDTH-1:0] cluster_data[TOT... | 8.523131 |
module: envolve_ctrl
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module ev_test;
// Inputs
reg clk;
reg rst;
reg [7:0] envo_ctrl_cmd;
reg mode;
reg [7:0] cur_x;
reg [7:0] cur_y;... | 6.847047 |
module top;
logic [3:0] a;
logic [7:0] b;
initial begin
// casez statement
a = 4'b0100;
casez (a)
4'b0000: b = 8'd0;
4'b???1: b = 8'd1;
4'b??10: b = 8'd2;
4'b?100: b = 8'd3;
4'b1000: b = 8'd4;
default: b = 8'hxx;
endcase
$display("a = 4'b0100, b = %x... | 7.3094 |
module top;
logic [7:0] a;
logic [7:0] b;
logic sel;
initial begin
// if statement
a = 8'd30;
b = 8'd16;
if (a == b) begin
$display("30 == 16");
end
if (a != b) begin
$display("30 != 16");
end
// if else statement
sel = 1'b1;
if (sel == 1'b0) be... | 7.3094 |
module top;
logic [7:0] A;
logic [7:0] B;
logic [7:0] C;
initial begin
// Basic arithmetic with no overflow or underflow
A = 8'd28;
B = 8'd15;
C = A + B;
$display("8'd28 + 8'd15 = %d", C);
C = A - B;
$display("8'd28 + 8'd15 = %d", C);
// Basic arithmetic with overflow and u... | 7.3094 |
module top;
logic [ 3:0] A; // 4-bit logic variable
logic [ 3:0] B; // 4-bit logic variable
logic [ 3:0] C; // 4-bit logic variable
logic [ 7:0] D; // 18-bit logic variable
logic [11:0] E; // 12-bit logic variable
initial begin
// Basic concatenation
A = 4'ha;
B = 4'hb;
C = 4'hc;... | 7.3094 |
module top;
logic [7:0] A;
logic [7:0] B;
logic [7:0] C;
initial begin
// Fixed shift amount for logical shifts
A = 8'b1110_0101;
C = A << 1;
$display("8'b1110_0101 << 1 = %b", C);
C = A << 2;
$display("8'b1110_0101 << 2 = %b", C);
C = A << 3;
$display("8'b1110_0101 << 3 = %... | 7.3094 |
module top;
logic [7:0] a;
logic [7:0] b;
logic [7:0] c;
logic [1:0] sel;
initial begin
// ternary statement
a = 8'd30;
b = 8'd16;
c = (a < b) ? 15 : 14;
$display("c = %d", c);
c = (b < a) ? 15 : 14;
$display("c = %d", c);
// nested ternary statement
sel = 2'b01;
... | 7.3094 |
module ex_gcd_GcdUnitDpath (
input logic clk,
input logic reset,
// Data signals
input logic [15:0] req_a,
input logic [15:0] req_b,
output logic [15:0] resp_result,
// Control signals
input logic a_reg_en, // Enable for A register
input logic b_reg_en, // Enabl... | 8.225528 |
module ex_gcd_GcdUnitCtrl (
input logic clk,
input logic reset,
// Dataflow signals
input logic req_val,
output logic req_rdy,
output logic resp_val,
input logic resp_rdy,
// Control signals
output logic a_reg_en, // Enable for A register
output logic b_reg_en... | 8.225528 |
module ex_gcd_GcdUnit (
input logic clk,
input logic reset,
input logic req_val,
output logic req_rdy,
input logic [15:0] req_a,
input logic [15:0] req_b,
output logic resp_val,
input logic resp_rdy,
output logic [15:0] resp_result
);
//----------... | 8.225528 |
module ex_gcd_GcdUnitFL (
input logic clk,
input logic reset,
input logic req_val,
output logic req_rdy,
input logic [15:0] req_a,
input logic [15:0] req_b,
output logic resp_val,
input logic resp_rdy,
output logic [15:0] resp_result
);
//--------... | 8.225528 |
module Ex_mem_register (
IAlu,
IZero,
IAdder,
IWB,
IM,
IReadRegister2,
IInstruction,
OAlu,
OZero,
OAdder,
OWB,
OM,
OReadRegister2,
OInstruction,
Clk
);
input [63:0] IAlu;
input IZero;
input [63:0] IAdder;
input [1:0] IWB;
input [2:0] IM;
input [63... | 8.22845 |
module top;
`VC_TEST_SUITE_BEGIN( "ex-regincr-RegIncr" )
//----------------------------------------------------------------------
// Test ex_regincr_RegIncr
//----------------------------------------------------------------------
logic [7:0] t1_in;
logic [7:0] t1_out;
ex_regincr_RegIncr t1_reg_incr
(... | 6.838355 |
module for a registered incrementer
// which combines a positive edge triggered register with a combinational
// +2 incrementer. We use flat register-transfer-level modeling.
`ifndef EX_REGINCR_REG_INCR_V
`define EX_REGINCR_REG_INCR_V
module ex_regincr_RegIncr
(
input logic clk,
input logic [7:0] in,
ou... | 7.928079 |
module takes two inputs, compares them, and outputs the larger
// via the "max" output port and the smaller via the "min" output port.
`ifndef EX_SORTER_MIN_MAX_UNIT_V
`define EX_SORTER_MIN_MAX_UNIT_V
module ex_sorter_MinMaxUnit
#(
parameter p_nbits = 1
)(
input logic [p_nbits-1:0] in0,
input logic [p_nbits-1... | 8.291986 |
module buffer (
output s,
input p
);
assign s = p; // criar vinculo permanente
// (dependencia)
endmodule
| 6.861394 |
module testbuffer;
// ------------------------- dados locais
reg a; // definir registrador
// (variavel independente)
wire s; // definir conexao (fio)
// (variavel dependente )
// ------------------------- instancia
buffer BF1 (
s,
a
);
// ------------------------- preparacao
i... | 7.153545 |
module notgate (
output s,
input p
);
assign s = ~p; // criar vinculo permanente
// (dependencia)
endmodule
| 7.575943 |
module testnotgate;
// ------------------------- dados locais
reg a; // definir registrador
// (variavel independente)
wire s; // definir conexao (fio)
// (variavel dependente )
// ------------------------- instancia
notgate NOT1 (
s,
a
);
// ------------------------- preparacao
... | 7.480879 |
module testandgate;
// ------------------------- dados locais
reg a, b; // definir registradores
wire s; // definir conexao (fio)
// ------------------------- instancia
andgate AND1 (
s,
a,
b
);
// ------------------------- preparacao
initial begin : start
// atribuicao simu... | 6.553783 |
module xorgate (
output [0:3] s,
input [0:3] p,
input [0:3] q
);
assign s = p ^ q;
endmodule
| 7.421731 |
module testxorgate;
// ------------------------- dados locais
reg [0:3] a, b; // definir registrador
wire [0:3] s; // definir conexao (fio)
// ------------------------- instancia
xorgate XOR1 (
s,
a,
b
);
// ------------------------- preparacao
initial begin : start
a = 4'b0... | 6.716539 |
module testandgate;
// ------------------------- dados locais
reg a, b; // definir registradores
wire s; // definir conexao (fio)
// ------------------------- instancia
andgate AND1 (
s,
a,
b
);
// ------------------------- preparacao
initial begin : start
// atribuicao simu... | 6.553783 |
module testnorgate;
// ------------------------- dados locais
reg a, b; // definir registradores
wire s; // definir conexao (fio)
// ------------------------- instancia
norgate NOR1 (
s,
a,
b
);
// ------------------------- preparacao
initial begin : start
// atribuicao simu... | 6.695863 |
module xnorgate (
output [0:3] s,
input [0:3] p,
input [0:3] q
);
assign s = ~(p ^ q);
endmodule
| 6.74222 |
module testxnorgate;
// ------------------------- dados locais
reg [0:3] a, b; // definir registrador
wire [0:3] s; // definir conexao (fio)
// ------------------------- instancia
xnorgate XNOR1 (
s,
a,
b
);
// ------------------------- preparacao
initial begin : start
a = 4... | 7.028584 |
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