code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module nandgate (
output s,
input p,
input q
);
assign s = (~p | ~q);
endmodule
| 7.298658 |
module operacoes;
reg [4:0] a;
reg [4:0] b;
reg [2:0] c;
reg [3:0] d;
reg [4:0] e;
initial begin
a = 2 + 14;
b = 3 * 9;
c = 32 / 5;
d = 24 - 11;
e = 2 * 6 + 7 - 1;
$display("a = %d = %5b", a, a);
$display("b = %d = %5b", b, b);
$display("c = %d = %3b", c, c);
$display... | 6.570498 |
module testnorgate;
// ------------------------- dados locais
reg a, b; // definir registradores
wire s; // definir conexao (fio)
// ------------------------- instancia
norgate NOR1 (
s,
a,
b
);
// ------------------------- preparacao
initial begin : start
// atribuicao simu... | 6.695863 |
module xorgate (
output [0:3] s,
input [0:3] p,
input [0:3] q
);
assign s = (~p & q | p & ~q);
endmodule
| 7.421731 |
module testxorgate;
// ------------------------- dados locais
reg [0:3] a, b; // definir registrador
wire [0:3] s; // definir conexao (fio)
// ------------------------- instancia
xorgate XOR1 (
s,
a,
b
);
// ------------------------- preparacao
initial begin : start
a = 4'b0... | 6.716539 |
module xnorgate (
output [0:3] s,
input [0:3] p,
input [0:3] q
);
assign s = (p & q | ~p & ~q);
endmodule
| 6.74222 |
module testxnorgate;
// ------------------------- dados locais
reg [0:3] a, b; // definir registrador
wire [0:3] s; // definir conexao (fio)
// ------------------------- instancia
xnorgate XNOR1 (
s,
a,
b
);
// ------------------------- preparacao
initial begin : start
a = 4... | 7.028584 |
module testandgate;
// ------------------------- dados locais
reg a, b, c; // definir registradores
wire s; // definir conexao (fio)
// ------------------------- instancia
andgate AND1 (
s,
a,
b,
c
);
// ------------------------- preparacao
initial begin : start
// atr... | 6.553783 |
module andgate2 (
output s,
input p,
input q,
input r
);
wire s1;
andgate AND1 (
s1,
p,
q
);
andgate AND2 (
s,
r,
s1
);
endmodule
| 7.731959 |
module testandgate;
reg a, b, c;
wire s;
andgate2 AND3 (
s,
a,
b,
c
);
//---------parte principal
initial begin : start
a = 0;
b = 0;
c = 0;
end
initial begin : main
$display("Exemplo0014 - Leonardo Machado Decina 451588");
$display("test andgate");
$disp... | 6.553783 |
module orgate2 (
output s,
input p,
input q,
input r
);
wire s1;
orgate OR1 (
s1,
p,
q
);
orgate OR2 (
s,
r,
s1
);
endmodule
| 7.349649 |
module
module counter(input clk, rst, output reg [2:0] q);
always @(posedge clk) begin
if (rst)
q = 3'b000;
else
q = q+1;
end
endmodule
| 6.958653 |
module norGate (
s0,
a,
b
);
output s0;
input a, b;
assign s0 = ~(a | b);
endmodule
| 7.000763 |
module meiasoma (
s0,
s1,
a,
b
);
output s0, s1;
input a, b;
xor XOR1 (s0, a, b);
and AND1 (s1, a, b);
endmodule
| 7.813544 |
module somacompleta (
s0,
s1,
vaium,
a,
b
);
output s0, s1;
input vaium, a, b;
wire w1, w2, w3;
meiasoma MS1 (
w1,
w2,
a,
b
);
meiasoma MS2 (
s0,
w3,
w1,
vaium
);
or (s1, w3, w2);
endmodule
| 7.045629 |
module soma3 (
s3,
s2,
s1,
s0,
a0,
a1,
a2,
b0,
b1,
b2
);
input a0, a1, a2, b0, b1, b2;
output s3, s2, s1, s0;
meiasoma MS1 (
s0,
c1,
a0,
b0
);
somacompleta SC1 (
s1,
c2,
a1,
b1,
c1
);
somacompleta SC2 (
s... | 7.00292 |
module testesoma;
reg a0, a1, a2, b0, b1, b2;
wire s3, s2, s1, s0;
soma3 S1 (
s3,
s2,
s1,
s0,
a0,
a1,
a2,
b0,
b1,
b2
);
initial begin : start
a0 = 0;
a1 = 0;
a2 = 0;
b0 = 0;
b1 = 0;
b2 = 0;
end
initial begin : main
... | 6.76879 |
module meiaDiferenca (
s0,
s1,
a,
b
);
output s0, s1;
input a, b;
wire w1;
xor (s0, a, b);
not (w1, a);
and (s1, w1, b);
endmodule
| 8.132121 |
module diferenca (
s0,
s1,
a0,
a1,
b0,
b1
);
input a0, a1, b0, b1;
output s0, s1;
wire w0, w1;
meiaDiferenca DC1 (
s0,
w0,
a0,
b0
);
DiferencaCompleta DC2 (
s1,
w1,
a1,
b1,
w0
);
endmodule
| 6.853547 |
module testediferenca;
reg a0, a1, b0, b1;
wire s0, s1;
diferenca D1 (
s0,
s1,
a0,
a1,
b0,
b1
);
initial begin : start
a0 = 0;
a1 = 0;
b0 = 0;
b1 = 0;
end
initial begin : main
$display("Exercicio 05-02 - Julio Cezar Taveira Araujo - 380776")... | 7.035536 |
module meiasoma (
s0,
s1,
a,
b
);
output s0, s1;
input a, b;
xor (s0, a, b);
and (s1, a, b);
endmodule
| 7.813544 |
module somaCompleta (
s0,
s1,
a,
b,
vaium
);
input a, b, vaium;
output s0, s1;
wire w1, w2, w3;
meiasoma MS1 (
w2,
w1,
a,
b
);
meiasoma MS2 (
s0,
w3,
r,
vaium
);
or (s1, w3, w1);
endmodule
| 7.146397 |
module produto (
s0,
cout,
e0,
e1,
e2,
e3,
cin
);
input e0, e1, e2, e3, cin;
output s0, cout;
and AND1 (p1, e0, e1);
and AND2 (p2, e2, e3);
somaCompleta soma (
s0,
cout,
p1,
p2,
cin
);
endmodule
| 7.220624 |
module produtoCompleto (
s3,
s2,
s1,
s0,
a0,
a1,
b0,
b1
);
input a0, a1, b0, b1;
output s3, s2, s1, s0;
reg p = 0;
produto P1 (
s0,
cout1,
p,
p,
a0,
b0,
p
);
produto P2 (
s1,
cout2,
a0,
b1,
a1,
b0,... | 6.528498 |
module meiasoma (
s0,
s1,
a,
b
);
output s0, s1;
input a, b;
wire w1, w2, w3, w4;
nand NAND1 (w1, a, b);
nand NAND2 (w2, b, w1);
nand NAND3 (w3, a, w1);
nand NAND4 (s0, w3, w2);
nand NAND5 (w4, a, b);
nand NAND6 (s1, w4, w4);
endmodule
| 7.813544 |
module somaCompleta (
s0,
s1,
a,
b,
vaium
);
input a, b, vaium;
output s0, s1;
wire w1, w2, w3, w4, w5;
meiasoma MS1 (
w1,
w2,
a,
b
);
meiasoma MS2 (
s0,
w3,
w1,
vaium
);
nand NAND1 (w4, w2, w2);
nand NAND2 (w5, w3, w3);
nand NAND... | 7.146397 |
module soma (
s2,
s1,
s0,
a0,
a1,
b0,
b1
);
input a0, a1, b0, b1;
output s2, s1, s0;
wire w1;
meiasoma MS1 (
s0,
w1,
a0,
b0
);
somaCompleta SC1 (
s1,
s2,
a1,
b1,
w1
);
endmodule
| 7.154378 |
module testesoma;
reg a0, a1, b0, b1;
wire s2, s1, s0;
soma SOMA1 (
s2,
s1,
s0,
a0,
a1,
b0,
b1
);
initial begin : start
a0 = 0;
a1 = 0;
b0 = 0;
b1 = 0;
end
initial begin : main
$display("Exercicio 05-04 - Julio Cezar Taveira Araujo - 380... | 6.76879 |
module meiaDiferenca (
s0,
s1,
a,
b
);
output s0, s1;
input a, b;
wire w1, w2, w3, w4, w5;
nor NAND1 (s0, w1, w1);
nor NAND2 (w1, w2, w3);
nor NAND3 (w2, a, w4);
nor NAND4 (w3, b, w4);
nor NAND5 (w4, a, b);
nor NAND6 (s1, a, w5);
nor NAND7 (w5, b, b);
endmodule
| 8.132121 |
module diferenca (
s0,
s1,
a0,
a1,
b0,
b1
);
input a0, a1, b0, b1;
output s0, s1;
wire w1, w2;
meiaDiferenca d1 (
s0,
w1,
a0,
b0
);
diferencaCompleta d2 (
s1,
w2,
a1,
b1,
w1
);
endmodule
| 6.853547 |
module testediferenca;
reg a0, a1, b0, b1;
wire s0, s1;
diferenca D1 (
s0,
s1,
a0,
a1,
b0,
b1
);
initial begin : start
a0 = 0;
a1 = 0;
b0 = 0;
b1 = 0;
end
initial begin : main
$display("Exercicio 05-05 - Julio Cezar Taveira Araujo - 380776");
... | 7.035536 |
module ex05_1 (
//////////// CLOCK //////////
input CLOCK_50,
//////////// SW //////////
input [9:0] SW,
//////////// LED //////////
output [9:0] LEDR,
//////////// Seg7 //////////
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0... | 6.510833 |
module ex05_2 (
//////////// CLOCK //////////
input CLOCK_50,
//////////// KEY //////////
input [3:0] KEY,
//////////// SW //////////
input [9:0] SW,
//////////// LED //////////
output [9:0] LEDR,
//////////// Seg7 //////////
output [6:0] HEX0,
output [6:0] HEX1,
out... | 8.002701 |
module meiasoma (
s0,
s1,
a,
b
);
output s0, s1;
input a, b;
xor (s0, a, b);
and (s1, a, b);
endmodule
| 7.813544 |
module somaCompleta (
s0,
s1,
a,
b,
vaium
);
input a, b, vaium;
output s0, s1;
wire w1, w2;
meiasoma MS1 (
w1,
w2,
a,
b
);
meiasoma MS2 (
s0,
w3,
w1,
vaium
);
or (s1, w3, w2);
endmodule
| 7.146397 |
module soma (
s,
a,
b,
op
);
input [3:0] a, b;
input op;
output [3:0] s;
xor XOR1 (n0, b[0], op);
somaCompleta FA1 (
s[0],
c1,
a[0],
n0,
op
);
xor XOR2 (n1, b[1], op);
somaCompleta FA2 (
s[1],
c2,
a[1],
n1,
c1
);
xor XOR... | 7.074089 |
module comparador (
s,
a,
b
);
input [3:0] a, b;
output s;
wire [3:0] c;
xnor XNOR1 (c[0], a[0], b[0]);
xnor XNOR2 (c[1], a[1], b[1]);
xnor XNOR3 (c[2], a[2], b[2]);
xnor XNOR4 (c[3], a[3], b[3]);
and AND1 (s, c[3], c[2], c[1], c[0]);
endmodule
| 7.425908 |
module alu (
s,
i,
a,
b,
op
);
input [3:0] a, b;
input op;
output [3:0] s;
output i;
soma SOMA1 (
s,
a,
b,
op
);
comparador COMPARADOR1 (
i,
a,
b
);
endmodule
| 6.774878 |
module meiasoma (
s0,
s1,
a,
b
);
output s0, s1;
input a, b;
xor (s0, a, b);
and (s1, a, b);
endmodule
| 7.813544 |
module somaCompleta (
s0,
s1,
a,
b,
c
);
input a, b, c;
output s0, s1;
meiasoma MS1 (
r,
c1,
a,
b
);
meiasoma MS2 (
s0,
c2,
r,
c
);
or (s1, c2, c1);
endmodule
| 7.146397 |
module soma (
s,
a,
b,
op
);
input [3:0] a, b;
input op;
output [3:0] s;
xor XOR1 (n0, b[0], op);
somaCompleta FA1 (
s[0],
c1,
a[0],
n0,
op
);
xor XOR2 (n1, b[1], op);
somaCompleta FA2 (
s[1],
c2,
a[1],
n1,
c1
);
xor XOR... | 7.074089 |
module comparadorA (
c1,
c2,
c3,
a,
b
);
input [3:0] a, b;
output c1, c2, c3;
wire [3:0] s;
soma SOMA1 (
s,
a,
b,
1
);
comparadorL COMPARADOR1 (
c2,
a,
b
);
nor NOR1 (c1, c2, s[3]);
assign c3 = s[3];
endmodule
| 7.101731 |
module alu (
s,
c1,
c2,
c3,
a,
b,
op
);
input [3:0] a, b;
input op;
output [3:0] s;
output c1, c2, c3;
soma SOMA1 (
s,
a,
b,
op
);
comparadorA COMPARADOR1 (
c1,
c2,
c3,
a,
b
);
endmodule
| 6.774878 |
module meiasoma (
s0,
s1,
a,
b
);
output s0, s1;
input a, b;
xor (s0, a, b);
and (s1, a, b);
endmodule
| 7.813544 |
module somaCompleta (
s0,
s1,
a,
b,
c
);
input a, b, c;
output s0, s1;
meiasoma HA1 (
r,
c1,
a,
b
);
meiasoma HA2 (
s0,
c2,
r,
c
);
or (s1, c2, c1);
endmodule
| 7.146397 |
module soma (
s,
c4,
a,
b,
op
);
input [3:0] a, b;
input op;
output [3:0] s;
output c4;
xor XOR1 (n0, b[0], op);
somaCompleta FA1 (
s[0],
c1,
a[0],
n0,
op
);
xor XOR2 (n1, b[1], op);
somaCompleta FA2 (
s[1],
c2,
a[1],
n1,
... | 7.074089 |
module comparadorA (
c1,
c2,
c3,
a,
b
);
input [3:0] a, b;
output c1, c2, c3;
wire [3:0] s;
soma SOMA1 (
s,
c,
a,
b,
1
);
comparadorL COMPARADOR1 (
c2,
a,
b
);
nor NOR1 (c1, c2, s[3]);
assign c3 = s[3];
endmodule
| 7.101731 |
module carry (
c,
a,
b,
op
);
input [3:0] a, b;
input op;
output c;
output [3:0] s;
soma SOMA1 (
s,
c,
a,
b,
op
);
endmodule
| 6.743084 |
module alu (
s,
o,
c1,
c2,
c3,
z,
c,
a,
b,
op,
p
);
input [3:0] a, b, p;
input op;
output [3:0] s;
output c1, c2, c3, o, z, c;
soma SOMA1 (
s,
c,
a,
b,
op
);
comparadorA COMPARADOR1 (
c1,
c2,
c3,
a,
b... | 6.774878 |
module continuous_assign (
input [3:0] a,
b,
input [4:0] c,
input add,
output [4:0] y
);
assign y = (add == 1) ? (a + b) : c;
endmodule
| 7.105309 |
module procedural_assign (
input [3:0] a,
b,
input [4:0] c,
input add,
output [4:0] y
);
always @* begin
y = (add == 1) ? (a + b) : c;
end
endmodule
| 6.956289 |
module gatedois (
output s,
input p,
input q
);
assign s = p | q;
endmodule
| 7.710131 |
module gate (
output s,
input p,
input q,
input r
);
wire x, z;
gatedois AND1 (
x,
p,
q
);
gatedois AND2 (
z,
x,
r
);
assign s = z;
endmodule
| 8.03527 |
module testgate;
reg a, b, c; // definir registradores
wire s; // definir conexao (fio)
gate AND1 (
s,
a,
b,
c
);
initial begin : start
// atribuicao simultanea
// dos valores iniciais
a = 0;
b = 0;
end
initial begin
$display("\na & b = s\n");
a = 0;
... | 6.897752 |
module SRlatch (
qn,
q,
r,
s
);
input r, s;
output qn, q;
nor NOR1 (q, s, qn);
nor NOR2 (qn, r, q);
endmodule
| 6.865912 |
module SRlatch (
qn,
q,
r,
s
);
input r, s;
output qn, q;
nand NAND1 (q, s, qn);
nand NAND2 (qn, r, q);
endmodule
| 6.865912 |
module dlatch (
qn,
q,
en,
d
);
input d, en;
output qn, q;
nand NAND1 (s1, en, d);
not NOT1 (s2, d);
nand NAND2 (s3, en, s2);
nand NAND3 (qn, s1, q);
nand NAND4 (q, s3, qn);
endmodule
| 6.890541 |
module dLatch
//----------------------
module test;
reg d, en;
wire nq, q;
dlatch Latch1( qn, q, en, d );
initial begin:start
d = 1; en=1;
end
initial begin: main
$display("\nExercicio 10-03 - Julio Cezar Taveira Araujo - 380776");
$display("\n En [b] | D [b] | Q = [b] |Q = [b]\n");
$monitor("En ... | 6.827805 |
module SRlatch (
qn,
q,
r,
s
);
input r, s;
output qn, q;
nand NAND1 (q, s, qn);
nand NAND2 (qn, r, q);
endmodule
| 6.865912 |
module SRlatch (
qn,
q,
r,
s
);
input r, s;
output qn, q;
nand NAND1 (q, s, qn);
nand NAND2 (qn, r, q);
endmodule
| 6.865912 |
module dlatch (
qn,
q,
en,
d
);
input d, en;
output qn, q;
nand NAND1 (s1, en, d);
not NOT1 (s2, d);
nand NAND2 (s3, en, s2);
SRlatch C1 (
qn,
q,
s1,
s3
);
endmodule
| 6.890541 |
module dLatch
//----------------------
module test;
reg d, en;
wire nq, q;
dlatch Latch1( qn, q, en, d );
initial begin:start
d = 1; en=1;
end
initial begin: main
$display("\nExercicio 10-05 - Julio Cezar Taveira Araujo - 380776");
$display("\n En [b] | D [b] | Q = [b] |Q = [b]\n");
$monitor("En... | 6.827805 |
module gate (
output s,
input [0:7] p
);
assign s = p[0] & p[1] & p[2] & p[3] & p[4] & p[5] & p[6] & p[7];
endmodule
| 8.03527 |
module testgate;
reg [0:7] a; // definir registrador
wire s; // definir conexao (fio)
gate XOR1 (
s,
a
);
initial begin : start
a = 8'b11111111; // 4 valores binarios
end
initial begin : main
$display("\n a ^ b = s\n");
$monitor("%b = %b", a, s);
#1 a = 8'... | 6.897752 |
module testeMF;
reg clk, reset, x;
wire e01;
Ex1101 Teste (
e01,
x,
clk,
reset
);
initial begin
$display("Exercicio 11-01 - Julio Cezar Taveira Araujo - 380776");
$display("Test Maquina de Estado Finito - Mealy");
// initial values
clk = 1;
reset = 0;
x ... | 7.5378 |
module TesteMF;
reg clk, reset, x;
wire e02;
Ex1102 Teste (
e02,
x,
clk,
reset
);
initial begin
$display("Exercicio 11-02 - Julio Cezar Taveira Araujo - 380776");
$display("Test Maquina de Estado Finito - Moore");
// initial values
clk = 1;
reset = 0;
x ... | 6.889872 |
module testeMF;
reg clk, reset, x;
wire w1;
Ex1103 Teste (
e03,
x,
clk,
reset
);
initial begin
$display("Exercicio 11-03 - Julio Cezar Taveira Araujo - 380776");
$display("Test Maquina de Estado Finito - Mealy");
// initial values
clk = 1;
reset = 0;
x ... | 7.821702 |
module gate (
output s,
input [0:7] p
);
assign s = p[0] & p[1] & p[2] & p[3] & p[4] & p[5] & p[6] & p[7];
endmodule
| 8.03527 |
module testgate;
reg [0:7] a; // definir registrador
wire s; // definir conexao (fio)
gate XOR1 (
s,
a
);
initial begin : start
a = 8'b11111111; // 4 valores binarios
end
initial begin : main
$display("\n a ^ b = s\n");
$monitor("%b = %b", a, s);
#1 a = 8... | 6.897752 |
module ex12_top (
SW,
HEX0,
HEX1,
HEX2,
CLOCK_50
);
input CLOCK_50;
input [9:0] SW;
output [6:0] HEX0, HEX1, HEX2;
wire [9:0] sin;
rom SINWAVE (
.address(SW),
.clock(CLOCK_50),
.q(sin)
);
hex_2_7seg SEG0 (
sin[3:0],
HEX0
);
hex_2_7seg SEG1 (
... | 7.006726 |
module ex14_top (
CLOCK_50,
SW,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
DAC_CS,
DAC_SDI,
DAC_SCK,
DAC_LD,
PWM_OUT
);
input wire CLOCK_50; //input clock
input wire [9:0] SW; //switch control frequency
output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4; //frequency display, in unit... | 8.128068 |
module ex15_top (
CLOCK_50,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
DAC_CS,
DAC_SDI,
DAC_SCK,
DAC_LD,
PWM_OUT,
ADC_SDI,
ADC_SCK,
ADC_CS,
ADC_SDO
);
input wire CLOCK_50; //input clock
input ADC_SDO; // potentiometer control frequency
output ADC_SCK, ADC_CS, ADC... | 7.011192 |
module - pass audio input to output directly
// Creator: Peter Cheung
// Version: 2.0
// Date: 10 Nov 2016
//------------------------------
module ex16_top (CLOCK_50, SW, HEX0, HEX1, HEX2,
DAC_SDI, DAC_SCK, DAC_CS, DAC_LD,
ADC_SDI, ADC_SCK, ADC_CS, ADC_SDO, PWM_OUT);
input CLOCK_50; // DE0 50MHz ... | 6.996927 |
module ex17_top (
CLOCK_50,
SW,
HEX0,
HEX1,
HEX2,
DAC_SDI,
DAC_SCK,
DAC_CS,
DAC_LD,
ADC_SDI,
ADC_SCK,
ADC_CS,
ADC_SDO,
PWM_OUT
);
input CLOCK_50; // DE0 50MHz system clock
input [9:0] SW; // 10 slide switches to specify address to ROM
output [6:0] HEX0, H... | 7.315193 |
module ex18_top (
CLOCK_50,
SW,
HEX0,
HEX1,
HEX2,
DAC_SDI,
DAC_SCK,
DAC_CS,
DAC_LD,
ADC_SDI,
ADC_SCK,
ADC_CS,
ADC_SDO,
PWM_OUT
);
input CLOCK_50; // DE0 50MHz system clock
input [9:0] SW; // 10 slide switches to specify address to ROM
output [6:0] HEX0, H... | 7.220322 |
module ex19_top (
CLOCK_50,
SW,
HEX0,
HEX1,
HEX2,
HEX3,
DAC_SDI,
DAC_SCK,
DAC_CS,
DAC_LD,
ADC_SDI,
ADC_SCK,
ADC_CS,
ADC_SDO,
PWM_OUT
);
input CLOCK_50; // DE0 50MHz system clock
input [9:0] SW; // 10 slide switches to specify address to ROM
output [6:... | 7.321205 |
module ex1_1 (
y1_1,
a,
b
);
input a, b;
output y1_1;
wire w3, w2, w1, w0;
or or_1 (w0, a, b);
and and_1 (w1, a, b);
and and_2 (w2, w0, w1);
nor nor_1 (w3, w0, w1);
or or_2 (y1_1, w3, w2);
endmodule
| 6.942516 |
module adderN #(
parameter N = 4
) (
input [N-1:0] a,
input [N-1:0] b,
input cin,
output cout,
output [N-1:0] sum
);
assign {cout, sum} = a + b + cin;
endmodule
| 7.016561 |
module ex1 (
A,
B,
S,
C
);
input A, B;
output S, C;
wire N0, n3;
assign C = N0;
AND_GATE U4 (
.I1(A),
.I2(B),
.O (N0)
);
NOR_GATE U5 (
.I1(A),
.I2(B),
.O (n3)
);
NOR_GATE U6 (
.I1(N0),
.I2(n3),
.O (S)
);
endmodule
| 6.644659 |
module AndGate (
s0,
e1,
e2
);
input e1, e2;
output s0;
assign s0 = e1 & e2;
// and AND1 (s0, e1,e2);
endmodule
| 7.746256 |
module XorGate (
s0,
e1,
e2
);
input e1, e2;
output s0;
assign s0 = (~e1 & e2) | (e1 & ~e2);
// xor XOR1 (s0, e1,e2);
endmodule
| 7.413558 |
module OrGate (
s0,
e1,
e2
);
input e1, e2;
output s0;
assign s0 = e1 | e2;
// or OR1 ( s0, e1, e2);
endmodule
| 6.50457 |
module ex2_4 (
SW,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4
);
input [2:0] SW;
output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4;
wire [2:0] o0, o1, o2, o3, o4;
wire [2:0] h = 3'b000, e = 3'b001, l = 3'b010, o = 3'b011, blk = 3'b100;
mux_3bit_5to1 m4 (
SW,
h,
e,
l,
l,
... | 7.463323 |
module mux_3bit_5to1 (
s,
u,
v,
w,
x,
y,
m
);
input [2:0] s;
input [2:0] u, v, w, x, y;
output [2:0] m;
wire [2:0] o0, o1, o2;
mux_3bit_2to1 m0 (
s[0],
u,
v,
o0
);
mux_3bit_2to1 m1 (
s[0],
w,
x,
o1
);
mux_3bit_2to1 m2 (
... | 6.507838 |
module mux_3bit_2to1 (
s,
x,
y,
m
);
input s;
input [2:0] x, y;
output [2:0] m;
assign m = ({3{~s}} & x) | ({3{s}} & y);
endmodule
| 7.545338 |
module ex2_5 (
SW,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5
);
input [2:0] SW;
output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;
wire [2:0] o0, o1, o2, o3, o4, o5;
wire [2:0] h = 3'b000, e = 3'b001, l = 3'b010, o = 3'b011, blk = 3'b100;
mux_3bit_6to1 m5 (
SW,
blk,
h,
... | 7.312593 |
module mux_3bit_2to1 (
s,
x,
y,
m
);
input s;
input [2:0] x, y;
output [2:0] m;
assign m = ({3{~s}} & x) | ({3{s}} & y);
endmodule
| 7.545338 |
module alu #(
parameter N = 8
) (
input [ 2:0] opcode, //
input [N-1:0] a, //
input [N-1:0] b, //
output reg [N-1:0] out //
);
localparam add = 3'd0;
localparam minus = 3'd1;
localparam band = 3'd2;
localparam bor = 3'd3;
localparam bnot = 3'd4;
... | 6.7799 |
module mux #(
parameter N = 2
) (
input [N-1:0] a,
input [N-1:0] b,
input [N-1:0] c,
input [N-1:0] d,
input [ 1:0] sel,
output [N-1:0] mux_out
);
reg [N-1:0] mux_temp;
assign mux_out = mux_temp;
//always_comb
always @(a or b or c or d or sel)
case (sel)
0: mux_temp ... | 8.575874 |
module ex2_top (
SW, //input switches
HEX0 //Hex output to 7 segment display
);
input [3:0] SW;
output [6:0] HEX0;
hex_2_7seg SEG0 (
HEX0,
SW
);
endmodule
| 7.565325 |
module bcd_7seg (
c,
display
);
input [3:0] c;
output [6:0] display;
assign display[0] = ~c[3] & ~c[2] & ~c[1] & c[0] | c[2] & ~c[1] & ~c[0];
assign display[1] = c[2] & ~c[1] & c[0] | c[2] & c[1] & ~c[0];
assign display[2] = ~c[2] & c[1] & ~c[0];
assign display[3] = ~c[3] & ~c[2] & ~c[1] & c[0] | c... | 6.710996 |
module ckt_b (
c,
display
);
input c;
output [6:0] display;
wire [6:0] one = 7'b1111001, zero = 7'b1000000;
assign display = ({7{~c}} & zero) | ({7{c}} & one);
endmodule
| 8.19927 |
module bcd_7seg (
c,
display
);
input [3:0] c;
output [6:0] display;
assign display[0] = ~c[3] & ~c[2] & ~c[1] & c[0] | c[2] & ~c[1] & ~c[0];
assign display[1] = c[2] & ~c[1] & c[0] | c[2] & c[1] & ~c[0];
assign display[2] = ~c[2] & c[1] & ~c[0];
assign display[3] = ~c[3] & ~c[2] & ~c[1] & c[0] | c... | 6.710996 |
module mux_1bit_2to1 (
s,
x,
y,
m
);
input s;
input x, y;
output m;
assign m = (~s & x) | (s & y);
endmodule
| 6.742175 |
module ex3_4 (
SW,
LEDR,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5
);
input [8:0] SW;
output [9:0] LEDR;
output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;
assign LEDR[8:0] = SW[8:0];
wire [3:0] a = SW[7:4], b = SW[3:0];
wire cin = SW[8];
wire cout;
wire [3:0] result;
bin_to_d... | 6.872125 |
module full_adder_4bits (
a,
b,
cin,
o,
cout
);
input [3:0] a, b;
input cin;
output [4:0] o;
output cout;
wire c1, c2, c3;
full_adder fa0 (
a[0],
b[0],
cin,
o[0],
c1
);
full_adder fa1 (
a[1],
b[1],
c1,
o[1],
c2
);
full_... | 6.62292 |
module ckt_b (
c,
display
);
input c;
output [6:0] display;
wire [6:0] one = 7'b1111001, zero = 7'b1000000;
assign display = ({7{~c}} & zero) | ({7{c}} & one);
endmodule
| 8.19927 |
module bcd_7seg (
c,
display
);
input [3:0] c;
output [6:0] display;
assign display[0] = ~c[3] & ~c[2] & ~c[1] & c[0] | c[2] & ~c[1] & ~c[0];
assign display[1] = c[2] & ~c[1] & c[0] | c[2] & c[1] & ~c[0];
assign display[2] = ~c[2] & c[1] & ~c[0];
assign display[3] = ~c[3] & ~c[2] & ~c[1] & c[0] | c... | 6.710996 |
module mux_1bit_2to1 (
s,
x,
y,
m
);
input s;
input x, y;
output m;
assign m = (~s & x) | (s & y);
endmodule
| 6.742175 |
module DFF (
input D,
input CLK,
output reg Q
);
always @(posedge CLK) Q <= D;
endmodule
| 7.464833 |
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