code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module DFF1 (
input clk,
input reset,
input d,
output reg q
);
always @(posedge clk or negedge reset)
if (!reset) q <= 0; //첽 0͵ƽЧ
else q <= d;
endmodule
| 7.650406 |
module DFF1 (
input clk,
input reset,
input d,
output reg q
);
always @(posedge clk)
if (!reset) q <= 0; //ͬ 0͵ƽЧ
else q <= d;
endmodule
| 7.650406 |
module ex3_top (
SW, //input 10 bit switch, RHS is the LSB
HEX0, //LSB
HEX1,
HEX2 //MSB
);
input [9:0] SW;
output [6:0] HEX0;
output [6:0] HEX1;
output [6:0] HEX2;
hex_2_7seg SEG0 (
HEX0,
SW[3:0]
);
hex_2_7seg SEG1 (
HEX1,
SW[7:4]
);
hex_2_7seg SEG2 (
... | 7.367031 |
module RS_latch (
Clk,
R,
S,
Q
);
input Clk, R, S;
output Q;
wire R_g, S_g, Qa, Qb;
and (R_g, R, Clk);
and (S_g, S, Clk);
nor (Qa, R_g, Qb);
nor (Qb, S_g, Qa);
assign Q = Qa;
endmodule
| 6.53356 |
module RS_latch (
Clk,
R,
S,
Q
);
input Clk, R, S;
output Q;
wire R_g, S_g, Qa, Qb;
and (R_g, R, Clk);
and (S_g, S, Clk);
nor (Qa, R_g, Qb);
nor (Qb, S_g, Qa);
assign Q = Qa;
endmodule
| 6.53356 |
module D_filp_flop (
Clk,
D,
Q
);
input Clk, D;
output Q;
wire Qm;
D_latch m (
~Clk,
D,
Qm
);
D_latch s (
Clk,
Qm,
Q
);
endmodule
| 7.180337 |
module MAC #(
parameter N = 8
) (
input clk,
input reset,
input [ N-1:0] opa,
input [ N-1:0] opb,
output reg [2*N-1:0] out
);
function [2*N-1:0] mult; //壬mult ɳ˷
input [N-1:0] opa; //ֻܶ
input [N-1:0] opb; //˿Ϊ
reg [2*N-1:0] result;
... | 7.246867 |
module ex4_mac_direct #(
parameter N = 8
) (
input clk,
input reset,
input [ N-1:0] opa,
input [ N-1:0] opb,
output reg [2*N-1:0] out
);
reg [2*N-1:0] mult;
reg [2*N-1:0] result;
integer i;
always @(*) begin
result = opa[0] ? opb : 0;
f... | 6.715134 |
module combo (
out1,
in1,
in2
);
output out1;
input in1;
input in2;
wire w1, w2, w3;
nand nand1 (w1, in1, in2);
nand nand2 (w2, in1, w1);
nand nand3 (w3, w1, in2);
nand nand4 (out1, w2, w3);
endmodule
| 7.020323 |
module ex4_top (
SW[9:0],
HEX0[6:0],
HEX1[6:0],
HEX2[6:0],
HEX3[6:0]
);
input [9:0] SW;
output [6:0] HEX0;
output [6:0] HEX1;
output [6:0] HEX2;
output [6:0] HEX3;
wire [3:0] w1, w2, w3, w4, w5, w6, w7, w8, w9, w10, w11, w12; //input
wire [3:0] a1, a2, a3, a4, a5, a6, a7, a8, a9, a1... | 6.862991 |
module gate (
output s,
input p,
input q
);
assign s = (~p & ~q);
endmodule
| 8.03527 |
module testgate;
reg a, b; // definir registradores
wire s; // definir conexao (fio)
gate AND1 (
s,
a,
b
);
initial begin : start
// atribuicao simultanea
// dos valores iniciais
a = 0;
b = 0;
end
initial begin
$display("\na & b = s\n");
a = 0;
b = 0;
... | 6.897752 |
module meiasoma (
s0,
s1,
a,
b
);
output s0, s1;
input a, b;
xor (s0, a, b);
and (s1, a, b);
endmodule
| 7.813544 |
module somaCompleta (
s0,
s1,
a,
b,
c
);
input a, b, c;
output s0, s1;
meiasoma HA1 (
r,
c1,
a,
b
);
meiasoma HA2 (
s0,
c2,
r,
c
);
or (s1, c2, c1);
endmodule
| 7.146397 |
module soma (
s3,
s2,
s1,
s0,
a0,
a1,
a2,
b0,
b1,
b2
);
input a0, a1, a2, b0, b1, b2;
output s3, s2, s1, s0;
meiasoma HA1 (
s0,
c1,
a0,
b0
);
somaCompleta FA1 (
s1,
c2,
a1,
b1,
c1
);
somaCompleta FA2 (
s2... | 6.889397 |
module testesoma ();
reg a0, a1, a2, b0, b1, b2;
wire s3, s2, s1, s0;
soma SOMA1 (
s3,
s2,
s1,
s0,
a0,
a1,
a2,
b0,
b1,
b2
);
initial begin : start
a0 = 0;
a1 = 0;
a2 = 0;
b0 = 0;
b1 = 0;
b2 = 0;
end
initial begin : mai... | 6.525332 |
module meiaDiferenca (
s0,
s1,
a,
b
);
output s0, s1;
input a, b;
xor (s0, a, b);
not (a1, a);
and (s1, a1, b);
endmodule
| 8.132121 |
module difCompleta (
s0,
s1,
a,
b,
c
);
input a, b, c;
output s0, s1;
meiaDiferenca d1 (
d,
v,
a,
b
);
meiaDiferenca d2 (
s0,
v2,
d,
c
);
or (s1, v2, v);
endmodule
| 6.867628 |
module diferenca (
s0,
s1,
a0,
a1,
b0,
b1
);
input a0, a1, b0, b1;
output s0, s1;
meiaDiferenca d1 (
s0,
c1,
a0,
b0
);
difCompleta d2 (
s1,
c2,
a1,
b1,
c1
);
endmodule
| 6.853547 |
module testediferenca ();
reg a0, a1, b0, b1;
wire s0, s1;
diferenca d (
s0,
s1,
a0,
a1,
b0,
b1
);
initial begin : start
a0 = 0;
a1 = 0;
b0 = 0;
b1 = 0;
end
initial begin : main
$display("Exercicio 02");
$display("Celso R Franca Jr - 404590... | 7.035536 |
module meiasoma (
s0,
s1,
a,
b
);
output s0, s1;
input a, b;
xor (s0, a, b);
and (s1, a, b);
endmodule
| 7.813544 |
module somaCompleta (
s0,
s1,
a,
b,
c
);
input a, b, c;
output s0, s1;
meiasoma HA1 (
r,
c1,
a,
b
);
meiasoma HA2 (
s0,
c2,
r,
c
);
or (s1, c2, c1);
endmodule
| 7.146397 |
module produto (
s0,
cout,
e0,
e1,
e2,
e3,
cin
);
input e0, e1, e2, e3, cin;
output s0, cout;
and AND1 (p1, e0, e1);
and AND2 (p2, e2, e3);
somaCompleta soma (
s0,
cout,
p1,
p2,
cin
);
endmodule
| 7.220624 |
module produtoCompleto (
s3,
s2,
s1,
s0,
a0,
a1,
b0,
b1
);
input a0, a1, b0, b1;
output s3, s2, s1, s0;
reg p = 0;
produto P1 (
s0,
cout1,
p,
p,
a0,
b0,
p
);
produto P2 (
s1,
cout2,
a0,
b1,
a1,
b0,... | 6.528498 |
module meiasoma (
s0,
s1,
a,
b
);
output s0, s1;
input a, b;
nand NAND1 (s4, a, b);
nand NAND2 (s3, b, s4);
nand NAND3 (s2, a, s4);
nand NAND4 (s0, s2, s3);
nand NAND5 (s5, a, b);
nand NAND6 (s1, s5, s5);
endmodule
| 7.813544 |
module somaCompleta (
s0,
s1,
a,
b,
c
);
input a, b, c;
output s0, s1;
meiasoma HA1 (
r,
c1,
a,
b
);
meiasoma HA2 (
s0,
c2,
r,
c
);
nand NAND1 (t1, c1, c1);
nand NAND2 (t2, c2, c2);
nand NAND3 (s1, t1, t2);
endmodule
| 7.146397 |
module soma (
s2,
s1,
s0,
a0,
a1,
b0,
b1
);
input a0, a1, b0, b1;
output s2, s1, s0;
meiasoma HA1 (
s0,
c1,
a0,
b0
);
somaCompleta FA1 (
s1,
s2,
a1,
b1,
c1
);
endmodule
| 7.154378 |
module testesoma ();
reg a0, a1, b0, b1;
wire s2, s1, s0;
soma SOMA1 (
s2,
s1,
s0,
a0,
a1,
b0,
b1
);
initial begin : start
a0 = 0;
a1 = 0;
b0 = 0;
b1 = 0;
end
initial begin : main
$display("Exercicio 04");
$display("Celso R Franca Jr -... | 6.525332 |
module meiaDiferenca (
s0,
s1,
a,
b
);
output s0, s1;
input a, b;
nor NAND1 (s0, s2, s2);
nor NAND2 (s2, s3, s4);
nor NAND3 (s3, a, s5);
nor NAND4 (s4, b, s5);
nor NAND5 (s5, a, b);
nor NAND6 (s1, a, s6);
nor NAND7 (s6, b, b);
endmodule
| 8.132121 |
module difCompleta (
s0,
s1,
a,
b,
c
);
input a, b, c;
output s0, s1;
meiaDiferenca d1 (
d,
v,
a,
b
);
meiaDiferenca d2 (
s0,
v2,
d,
c
);
nor NOR1 (t, v2, v);
nor NOR2 (s1, t, t);
//or (s1,v2,v);
endmodule
| 6.867628 |
module diferenca (
s0,
s1,
a0,
a1,
b0,
b1
);
input a0, a1, b0, b1;
output s0, s1;
meiaDiferenca d1 (
s0,
c1,
a0,
b0
);
difCompleta d2 (
s1,
c2,
a1,
b1,
c1
);
endmodule
| 6.853547 |
module testediferenca ();
reg a0, a1, b0, b1;
wire s0, s1;
diferenca d (
s0,
s1,
a0,
a1,
b0,
b1
);
initial begin : start
a0 = 0;
a1 = 0;
b0 = 0;
b1 = 0;
end
initial begin : main
$display("Exercicio 05");
$display("Celso R Franca Jr - 404590... | 7.035536 |
module ex5_1 (
KEY,
SW,
HEX0,
HEX1,
HEX2,
HEX3
);
input [3:0] KEY;
input [1:0] SW;
output [6:0] HEX0, HEX1, HEX2, HEX3;
wire [15:0] Q;
counter_16bits c0 (
Q,
KEY[0],
SW[1],
SW[0]
);
display_4bits d0 (
HEX0,
Q[3:0]
);
display_4bits d1 (
... | 7.822871 |
module counter_16bits (
Q,
Clk,
En,
Res
);
input Clk, En, Res;
output [15:0] Q;
wire [3:0] Trig;
counter_4bits c0 (
Q[3:0],
Clk,
En,
Res,
Trig[0]
);
counter_4bits c1 (
Q[7:4],
Clk,
En & Trig[0],
Res,
Trig[1]
);
counter_4bits c... | 6.674368 |
module counter_4bits (
Q,
Clk,
En,
Res,
Trig
);
input Clk, En, Res;
output [3:0] Q;
output Trig;
T_flip_flop t0 (
Q[0],
Clk,
En,
Res
);
T_flip_flop t1 (
Q[1],
Clk,
En & Q[0],
Res
);
T_flip_flop t2 (
Q[2],
Clk,
En & Q[... | 7.309351 |
module T_flip_flop (
Q,
Clk,
T,
Res
);
input Clk, Res;
input T;
output reg Q = 0;
always @(posedge Clk) begin
if (~Res) Q <= 1'b0;
else Q <= Q ^ T;
end
endmodule
| 7.050804 |
module display_4bits (
disp,
c
);
input [3:0] c;
output reg [6:0] disp;
always @(c) begin
case (c)
0: disp = 7'b1000000;
1: disp = 7'b1111001;
2: disp = 7'b0100100;
3: disp = 7'b0110000;
4: disp = 7'b0011001;
5: disp = 7'b0010010;
6: disp = 7'b0000010;
... | 7.050021 |
module ex5_2 (
KEY,
SW,
HEX0,
HEX1,
HEX2,
HEX3
);
input [3:0] KEY;
input [1:0] SW;
output [6:0] HEX0, HEX1, HEX2, HEX3;
wire [15:0] Q;
counter_16bits c0 (
Q,
KEY[0],
SW[1],
SW[0]
);
display_4bits d0 (
HEX0,
Q[3:0]
);
display_4bits d1 (
... | 7.802977 |
module counter_16bits (
Q,
Clk,
En,
Res
);
input Clk, En, Res;
output reg [15:0] Q = 16'b0;
always @(posedge Clk) begin
if (~Res | Q == {16{1'b1}}) Q <= 16'b0;
else if (En) Q <= Q + 1;
end
endmodule
| 6.674368 |
module display_4bits (
disp,
c
);
input [3:0] c;
output reg [6:0] disp;
always @(c) begin
case (c)
0: disp = 7'b1000000;
1: disp = 7'b1111001;
2: disp = 7'b0100100;
3: disp = 7'b0110000;
4: disp = 7'b0011001;
5: disp = 7'b0010010;
6: disp = 7'b0000010;
... | 7.050021 |
module ex5_3 (
KEY,
SW,
HEX0,
HEX1,
HEX2,
HEX3
);
input [3:0] KEY;
input [1:0] SW;
output [6:0] HEX0, HEX1, HEX2, HEX3;
wire [15:0] Q;
counter c0 (
KEY[0],
SW[1],
~SW[0],
Q
);
display_4bits d0 (
HEX0,
Q[3:0]
);
display_4bits d1 (
HEX1... | 8.087567 |
module display_4bits (
disp,
c
);
input [3:0] c;
output reg [6:0] disp;
always @(c) begin
case (c)
0: disp = 7'b1000000;
1: disp = 7'b1111001;
2: disp = 7'b0100100;
3: disp = 7'b0110000;
4: disp = 7'b0011001;
5: disp = 7'b0010010;
6: disp = 7'b0000010;
... | 7.050021 |
module ex5_4 (
HEX0,
CLOCK_50
);
output [6:0] HEX0;
input CLOCK_50;
wire [3:0] Q;
counter c0 (
Q,
CLOCK_50
);
display_4bits d0 (
HEX0,
Q
);
endmodule
| 7.496616 |
module display_4bits (
disp,
c
);
input [3:0] c;
output reg [6:0] disp;
always @(c) begin
case (c)
0: disp = 7'b1000000;
1: disp = 7'b1111001;
2: disp = 7'b0100100;
3: disp = 7'b0110000;
4: disp = 7'b0011001;
5: disp = 7'b0010010;
6: disp = 7'b0000010;
... | 7.050021 |
module FSM (
input clk,
input reset,
input start,
input step2,
input step3,
output reg [2:0] fsm_out
);
localparam state0 = 2'b00;
localparam state1 = 2'b01;
localparam state2 = 2'b11;
localparam state3 = 2'b10;
//ʽ룬ÿڸµǰ״̬
reg [1:0] state;
reg [1:0] next_state;
always @(posedge... | 8.007563 |
module FSM (
input clk,
input reset,
input start,
input step2,
input step3,
input step4,
output reg [2:0] fsm_out
);
localparam fsm_width = 3;
localparam state0 = 3'b000;
localparam state1 = 3'b001;
localparam state2 = 3'b011;
localparam state3 = 3'b010;
localparam state4 = 3'b10... | 8.007563 |
module gate (
output s,
input p,
input q
);
assign s = (~p & q) | (p & ~q);
endmodule
| 8.03527 |
module testgate;
reg a, b; // definir registradores
wire s; // definir conexao (fio)
gate AND1 (
s,
a,
b
);
initial begin : start
// atribuicao simultanea
// dos valores iniciais
a = 0;
b = 0;
end
initial begin
$display("\na & b = s\n");
a = 0;
b = 0;
... | 6.897752 |
module ex6_1 (
KEY,
HEX0,
HEX1,
HEX2,
CLOCK_50
);
input [3:0] KEY;
input CLOCK_50;
output [6:0] HEX0, HEX1, HEX2;
wire clk;
wire [9:0] Q;
clock c (
clk,
CLOCK_50
);
counter c0 (
Q,
clk,
KEY[0]
);
display_4bits d0 (
HEX0,
Q % 10
);
... | 7.878746 |
module display_4bits (
disp,
c
);
input [3:0] c;
output reg [6:0] disp;
always @(c) begin
case (c)
0: disp = 7'b1000000;
1: disp = 7'b1111001;
2: disp = 7'b0100100;
3: disp = 7'b0110000;
4: disp = 7'b0011001;
5: disp = 7'b0010010;
6: disp = 7'b0000010;
... | 7.050021 |
module ex6_2 (
SW,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
CLOCK_50
);
input [9:0] SW;
input CLOCK_50;
output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;
wire clk;
wire [5:0] sec, min, hr;
wire C[2:0];
clock c (
clk,
CLOCK_50
);
timer t (
hr,
min,
... | 7.238093 |
module display_4bits (
disp,
c
);
input [3:0] c;
output reg [6:0] disp;
always @(c) begin
case (c)
0: disp = 7'b1000000;
1: disp = 7'b1111001;
2: disp = 7'b0100100;
3: disp = 7'b0110000;
4: disp = 7'b0011001;
5: disp = 7'b0010010;
6: disp = 7'b0000010;
... | 7.050021 |
module ex6_3 (
SW,
KEY,
HEX0,
HEX1,
HEX2,
HEX3,
LEDR,
CLOCK_50
);
input [3:0] SW;
input [3:0] KEY;
input CLOCK_50;
output [7:0] LEDR;
output [6:0] HEX0, HEX1, HEX2, HEX3;
wire clk;
wire [9:0] ms;
wire [1:0] set_time;
clock c (
clk,
CLOCK_50
);
bin2dec ... | 8.210879 |
module display_4bits (
disp,
c
);
input [3:0] c;
output reg [6:0] disp;
always @(c) begin
case (c)
0: disp = 7'b1000000;
1: disp = 7'b1111001;
2: disp = 7'b0100100;
3: disp = 7'b0110000;
4: disp = 7'b0011001;
5: disp = 7'b0010010;
6: disp = 7'b0000010;
... | 7.050021 |
module ex6_top (
CLOCK_50, //50 Mhz clk
KEY, //key0 => press to enable counter; key1 => press to reset counter
SW, //sw0 => turn on to enable counter
HEX0,
HEX1,
HEX2,
HEX3,
HEX4
);
input CLOCK_50;
input [1:0] KEY;
input [0:0] SW;
output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4;
... | 6.961304 |
module gate (
output s,
input p,
input q
);
assign s = (p & q) | (~p & ~q);
endmodule
| 8.03527 |
module testgate;
reg a, b; // definir registradores
wire s; // definir conexao (fio)
gate AND1 (
s,
a,
b
);
initial begin : start
// atribuicao simultanea
// dos valores iniciais
a = 0;
b = 0;
end
initial begin
$display("\na & b = s\n");
a = 0;
b = 0;
... | 6.897752 |
module ex7_1 (
KEY,
SW,
LEDR,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5
);
input [1:0] KEY;
input [8:0] SW;
output [8:0] LEDR;
output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;
wire [7:0] a, b;
storage_8bits s0 (
a,
SW[7:0],
SW[8],
KEY[0],
KEY[1]
... | 7.195195 |
module adder_8bits (
sum,
overflow,
a,
b,
cin
);
input [7:0] a, b;
input cin;
output [7:0] sum;
output overflow;
wire [8:0] c;
genvar i;
generate
for (i = 0; i <= 7; i = i + 1) begin : add
full_adder f (
c[i+1],
sum[i],
a[i],
b[i],
... | 7.981077 |
module display_4bits (
disp,
c
);
input [3:0] c;
output reg [6:0] disp;
always @(c) begin
case (c)
0: disp = 7'b1000000;
1: disp = 7'b1111001;
2: disp = 7'b0100100;
3: disp = 7'b0110000;
4: disp = 7'b0011001;
5: disp = 7'b0010010;
6: disp = 7'b0000010;
... | 7.050021 |
module ex7_2 (
KEY,
SW,
LEDR,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5
);
input [1:0] KEY;
input [9:0] SW;
output [8:0] LEDR;
output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;
wire [7:0] a, b;
storage_8bits s0 (
a,
SW[7:0],
SW[8],
KEY[0],
KEY[1]
... | 7.4918 |
module adder_8bits (
sum,
overflow,
a,
b,
cin
);
input [7:0] a, b;
input cin;
output [7:0] sum;
output overflow;
wire [8:0] c;
genvar i;
generate
for (i = 0; i <= 7; i = i + 1) begin : add
full_adder f (
c[i+1],
sum[i],
a[i],
b[i],
... | 7.981077 |
module display_4bits (
disp,
c
);
input [3:0] c;
output reg [6:0] disp;
always @(c) begin
case (c)
0: disp = 7'b1000000;
1: disp = 7'b1111001;
2: disp = 7'b0100100;
3: disp = 7'b0110000;
4: disp = 7'b0011001;
5: disp = 7'b0010010;
6: disp = 7'b0000010;
... | 7.050021 |
module ex7_3 (
KEY,
SW,
LEDR,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5
);
input [1:0] KEY;
input [8:0] SW;
output [8:0] LEDR;
output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;
wire [7:0] a, b;
storage_8bits s0 (
a,
SW[7:0],
SW[8],
KEY[0],
KEY[1]
... | 7.224313 |
module display_4bits (
disp,
c
);
input [3:0] c;
output reg [6:0] disp;
always @(c) begin
case (c)
0: disp = 7'b1000000;
1: disp = 7'b1111001;
2: disp = 7'b0100100;
3: disp = 7'b0110000;
4: disp = 7'b0011001;
5: disp = 7'b0010010;
6: disp = 7'b0000010;
... | 7.050021 |
module ex7_4 (
SW,
HEX0,
HEX1,
HEX4,
HEX5
);
input [7:0] SW;
output [6:0] HEX0, HEX1, HEX4, HEX5;
wire [3:0] a, b;
assign a = SW[7:4];
assign b = SW[3:0];
wire [7:0] product;
multiplier_4bits m (
product,
a,
b
);
display_4bits d0 (
HEX0,
product[3:... | 6.730084 |
module multiplier_4bits (
product,
a,
b
);
input [3:0] a, b;
output [7:0] product;
wire [3:0] sum [2:0];
wire [2:0] cout;
assign product[0] = a[0] & b[0];
adder_4bits a0 (
sum[0],
cout[0],
{1'b0, a[3:1] & {3{b[0]}}},
a[3:0] & {4{b[1]}},
0
);
assign product[1]... | 6.715547 |
module adder_4bits (
sum,
overflow,
a,
b,
cin
);
input [3:0] a, b;
input cin;
output [3:0] sum;
output overflow;
wire [4:0] c;
genvar i;
generate
for (i = 0; i <= 3; i = i + 1) begin : add
full_adder f (
c[i+1],
sum[i],
a[i],
b[i],
... | 8.00499 |
module display_4bits (
disp,
c
);
input [3:0] c;
output reg [6:0] disp;
always @(c) begin
case (c)
0: disp = 7'b1000000;
1: disp = 7'b1111001;
2: disp = 7'b0100100;
3: disp = 7'b0110000;
4: disp = 7'b0011001;
5: disp = 7'b0010010;
6: disp = 7'b0000010;
... | 7.050021 |
module ex7_5 (
SW,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5
);
input [8:0] SW;
output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;
reg [7:0] a, b;
always @(SW[8]) begin
if (SW[8]) b = SW[7:0];
else if (~SW[8]) a = SW[7:0];
end
wire [15:0] product;
multiplier_8bits m (
p... | 6.565951 |
module multiplier_8bits (
product,
a,
b
);
input [7:0] a, b;
output [15:0] product;
wire [7:0] sum [6:0];
wire [7:0] cout;
assign product[0] = a[0] & b[0];
adder_8bits a0 (
sum[0],
cout[0],
{1'b0, a[7:1] & {7{b[0]}}},
a[7:0] & {8{b[1]}},
0
);
assign product[1... | 6.514288 |
module adder_8bits (
sum,
overflow,
a,
b,
cin
);
input [7:0] a, b;
input cin;
output [7:0] sum;
output overflow;
wire [8:0] c;
genvar i;
generate
for (i = 0; i <= 7; i = i + 1) begin : add
full_adder f (
c[i+1],
sum[i],
a[i],
b[i],
... | 7.981077 |
module display_4bits (
disp,
c
);
input [3:0] c;
output reg [6:0] disp;
always @(c) begin
case (c)
0: disp = 7'b1000000;
1: disp = 7'b1111001;
2: disp = 7'b0100100;
3: disp = 7'b0110000;
4: disp = 7'b0011001;
5: disp = 7'b0010010;
6: disp = 7'b0000010;
... | 7.050021 |
module ex7_6 (
KEY,
SW,
LEDR,
HEX0,
HEX1,
HEX2,
HEX3
);
input [3:0] KEY;
input [9:0] SW;
output [9:9] LEDR;
output [6:0] HEX0, HEX1, HEX2, HEX3;
wire [7:0] a, b, c, d;
storage_8bits s0 (
a,
SW[7:0],
~KEY[2] & ~SW[8] & SW[9],
KEY[0],
KEY[1]
);
s... | 7.434684 |
module display_4bits (
disp,
c
);
input [3:0] c;
output reg [6:0] disp;
always @(c) begin
case (c)
0: disp = 7'b1000000;
1: disp = 7'b1111001;
2: disp = 7'b0100100;
3: disp = 7'b0110000;
4: disp = 7'b0011001;
5: disp = 7'b0010010;
6: disp = 7'b0000010;
... | 7.050021 |
module gate (
output s,
input p,
input q,
input r
);
assign s = (p & q) & r;
endmodule
| 8.03527 |
module testgate;
reg a, b, c; // definir registradores
wire s; // definir conexao (fio)
gate AND1 (
s,
a,
b,
c
);
initial begin : start
// atribuicao simultanea
// dos valores iniciais
a = 0;
b = 0;
end
initial begin
$display("\na & b = s\n");
a = 0;
... | 6.897752 |
module D_flip_flop (
q,
d,
reset,
r_value,
clk
);
input d, reset, r_value, clk;
output reg q;
always @(posedge clk) begin
if (~reset) q <= r_value;
else q <= d;
end
endmodule
| 7.315668 |
module ex8_2 (
KEY,
SW,
LEDR
);
input [1:0] SW;
input [0:0] KEY;
output [9:0] LEDR;
parameter A = 4'b0000, B = 4'b0001, C = 4'b0010, D = 4'b0011,
E = 4'b0100, F = 4'b0101, G = 4'b0110, H = 4'b0111,
I = 4'b1000;
reg [3:0] state;
reg z;
always @(posedge KEY[0])... | 6.649114 |
module ex8_4 (
KEY,
SW,
HEX0
);
input [2:0] SW;
input [0:0] KEY;
output [6:0] HEX0;
reg [3:0] count;
always @(posedge KEY[0]) begin
if (~SW[0]) count = 0;
else
case (SW[2:1])
2'b00: count = count;
2'b01: count = (count + 1) % 10;
2'b10: count = (count + 2) %... | 7.270291 |
module display_4bits (
disp,
c
);
input [3:0] c;
output reg [6:0] disp;
always @(c) begin
case (c)
0: disp = 7'b1000000;
1: disp = 7'b1111001;
2: disp = 7'b0100100;
3: disp = 7'b0110000;
4: disp = 7'b0011001;
5: disp = 7'b0010010;
6: disp = 7'b0000010;
... | 7.050021 |
module ex8_top(CLOCK_50,KEY,LEDR,HEX0,HEX1,HEX2,HEX3,HEX4);
input CLOCK_50;
input [3:3] KEY;
output [9:0] LEDR;
output [6:0] HEX0,HEX1,HEX2,HEX3,HEX4;
// ---- submodule interface
wire tick_ms;//every 1ms
wire tick_hs;//every 0.5s
reg time_out;//is 1 if countdown finish
reg en_lfsr;//enable LFSR
reg [... | 7.807127 |
module gatedois (
output s,
input p,
input q
);
assign s = p & q;
endmodule
| 7.710131 |
module gate (
output s,
input p,
input q,
input r
);
wire x, z;
gatedois AND1 (
x,
p,
q
);
gatedois AND2 (
z,
x,
r
);
assign s = z;
endmodule
| 8.03527 |
module testgate;
reg a, b, c; // definir registradores
wire s; // definir conexao (fio)
gate AND1 (
s,
a,
b,
c
);
initial begin : start
// atribuicao simultanea
// dos valores iniciais
a = 0;
b = 0;
end
initial begin
$display("\na & b = s\n");
a = 0;
... | 6.897752 |
module ex9_top(CLOCK_50,KEY,LEDR,HEX0,HEX1,HEX2,HEX4,HEX5);
input CLOCK_50;
input [3:3] KEY;
output [9:0] LEDR;
output [6:0] HEX0,HEX1,HEX2,HEX5,HEX4;
// ---- submodule interface
wire tick_ms;//every 1ms
wire tick_hs;//every 0.5s
reg time_out;//is 1 if countdown finish
reg en_lfsr;//enable LFSR
reg [... | 7.715163 |
module Exact_4_to_2_Comp (
input IN1,
IN2,
IN3,
IN4,
input Cin,
output wire Cout,
output wire Ccy,
Csum
);
assign Csum = Cin ^ IN1 ^ IN2 ^ IN3 ^ IN4;
assign Cout = (IN1 && !(IN2 ^ IN1)) || (IN3 && (IN2 ^ IN1));
assign Ccy = (IN4 && (!(IN4 ^ IN3 ^ IN2 ^ IN1))) || (Cin &... | 6.71995 |
module exam (
LEDR,
LEDG,
SW,
KEY,
CLOCK_50,
HEX3,
HEX2,
HEX1,
HEX0
);
input [9:0] SW;
input [3:0] KEY;
input CLOCK_50;
output [7:0] LEDG;
output [9:0] LEDR;
output [6:0] HEX3, HEX2, HEX1, HEX0;
wire Enable, Reset, Preset, Clock, Co;
wire [25:0] C;
wire [3:0] bcd3,... | 6.586131 |
module exam1_A (
input wire clk,
input wire rst,
input wire signed [`WIDTH-1:0] A,
input wire signed [`WIDTH-1:0] B,
input wire [1:0] ctrl,
output reg signed [`WIDTH*2-1:0] out // You can modify "reg" to "wire" if needed
);
//Your design here
always @(posedge clk or posedge rst) begin
i... | 8.348546 |
module SevenSegment (
output reg [6:0] display,
output reg [3:0] digit,
input wire [15:0] nums, // four 4-bits BCD number
input wire rst,
input wire clk // Input 100Mhz clock
);
reg [15:0] clk_divider;
reg [ 3:0] display_num;
always @(posedge clk, posedge rst) begin
if (rst) begin
... | 7.922915 |
module clock_divider (
clk,
clk_div
);
parameter n = 26;
input clk;
output clk_div;
reg [n-1:0] num;
wire [n-1:0] next_num;
always @(posedge clk) begin
num <= next_num;
end
assign next_num = num + 1;
assign clk_div = num[n-1];
endmodule
| 6.818038 |
module ExamenDSD #(
parameter WORD_LENGTH = 8
) (
// Input Ports
input clk,
input reset,
input start,
input [WORD_LENGTH-1:0] x_input,
output error,
output [WORD_LENGTH-1:0] y_output
);
//---------------Internal signals-----------------------
wire [1:0] Constant_control;
wire [1... | 6.902614 |
module examine (
input clk,
input reset,
input rd,
input examine,
input [7:0] lo_addr,
input [7:0] hi_addr,
output reg [7:0] data_out,
output examine_latch
);
reg [2:0] state = 3'b000;
reg prev_rd = 1'b0;
reg en_lt = 1'b0;
always @(posedge clk) begin
if (reset) begin
... | 7.385846 |
module examine_next (
input clk,
input reset,
input rd,
input examine,
output reg [7:0] data_out,
output examine_latch
);
reg [2:0] state = 3'b000;
reg prev_rd = 1'b0;
reg en_lt = 1'b0;
always @(posedge clk) begin
if (reset) begin
en_lt <= 1'b0;
end else if (examine) begi... | 6.664421 |
module AHB_BUS (
input wire HCLK,
input wire HRESETn,
`AHB_MASTER_BUS_IFC( ),
`AHB_SLAVE_BUS_IFC(S0),
`AHB_SLAVE_BUS_IFC(S1),
`AHB_SLAVE_BUS_IFC(S2),
`AHB_SLAVE_BUS_IFC(S3)
);
// The salves bases addresses
localparam S0_PAGE = 8'h40;
localparam S1_PAGE = 8'h41;
localpa... | 8.588355 |
module top (
input clk,
output LED1,
output LED2,
output LED3,
output LED4,
output LED5
);
localparam BITS = 5;
localparam LOG2DELAY = 22;
function [BITS-1:0] bin2gray(input [BITS-1:0] in);
integer i;
reg [BITS-1:0] temp;
begin
temp = in;
for (i = 0; i < BITS; i ... | 7.233807 |
module AHB_SLAVE_0(
input wire HCLK,
input wire HRESETn,
`AHB_SLAVE_IFC
);
`AHB_SLAVE_EPILOGUE
// R1 is a 20-bit register @ offset 0x20
// It has 3 fields:
// F1 (bit 0), F2 (bit 1), F3 (bits 2:19)
`AHB_REG(R1, 20, 8'h20, 0)
`REG_FIELD(R1, F1, 0, 0)
`REG_FIELD(R1, F2, 1, 1)
... | 6.796919 |
module AHB_SLAVE_1(
input wire HCLK,
input wire HRESETn,
`AHB_SLAVE_IFC
);
`AHB_SLAVE_EPILOGUE
// R1 is a 8-bit register @ offset 0x0
// It has 1 field: F1 (bits 7:0)
// F1 (bit 0), F2 (bit 1), F3 (bits 19:2)
`AHB_REG(R1, 8, 8'h0, 0)
`REG_FIELD(R1, F1, 0, 7)
`AHB_READ
... | 6.745746 |
module AHB_SYS (
input wire HCLK,
input wire HRESETn,
`AHB_MASTER_BUS_IFC()
);
`AHB_SLAVE_SIGNALS(S0)
`AHB_SLAVE_SIGNALS(S1)
`AHB_SLAVE_SIGNALS(S2)
`AHB_SLAVE_SIGNALS(S3)
AHB_BUS BUS (
.HCLK(HCLK),
.HRESETn(HRESETn),
`AHB_MASTER_CONN,
`AHB_SLAVE_BUS_CONN(S0),
`AH... | 6.519246 |
module APB_SYS (
input wire HCLK,
input wire HRESETn,
`AHB_SLAVE_IFC
);
wire PCLK;
wire PRESETn;
`APB_MASTER_SIGNALS
AHB_APB_BRIDGE #(
.SLOW_PCLK(0)
) APB_BR (
.HCLK(HCLK),
.HRESETn(HRESETn),
`AHB_SLAVE_INST_CONN_NP,
// APB Master Port
.PCLK(PCLK),
... | 6.54701 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.