code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module x_lut4_0xa000 (
i0,
i2,
i3,
o
);
input i0, i2, i3;
output o;
supply0 VSS;
supply1 VDD;
an3 inst197025 (
.c(i3),
.b(i0),
.a(i2),
.z(o)
);
endmodule
| 6.526929 |
module x_lut4_0xc505 (
i0,
i1,
i2,
i3,
o
);
input i0, i1, i2, i3;
output o;
supply0 VSS;
supply1 VDD;
mx21i inst242237 (
.sb(i2),
.b (n35),
.a (i0),
.zn(o)
);
na2 inst242238 (
.b (i1),
.a (i3),
.zn(n35)
);
endmodule
| 6.509103 |
module x_lut4_0xccf0 (
i1,
i2,
i3,
o
);
input i1, i2, i3;
output o;
supply0 VSS;
supply1 VDD;
mx21 inst251815 (
.sb(i3),
.b (i1),
.a (i2),
.z (o)
);
endmodule
| 6.536031 |
module Example (
output wire F,
input wire A,
B,
C
);
wire An;
assign An = !A;
assign F = (An && B) || C;
endmodule
| 7.067607 |
module example_por (
`ifdef USE_POWER_PINS
inout vdd3v3,
inout vdd1v8,
inout vss,
`endif
output porb_h,
output porb_l,
output por_l
);
wire mid, porb_h;
reg inode;
// This is a behavioral model! Actual circuit is a resitor dumping
// current (slowly) from vdd3v3 onto a capacitor, a... | 6.694907 |
module example_sys (
input wire i_sysclk, // 125MHz board clock
input wire i_rst, // active high board button
// HDMI interface
output wire [3:0] o_TMDS_N,
output wire [3:0] o_TMDS_P
);
wire rstn;
wire clk_25MHz;
wire clk_250MHz;
wire vsync, hsync, active;
wire [9:0] counterX, coun... | 6.555307 |
module: example
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module example_test;
// Inputs
reg CLK;
reg nRST;
reg [1:0] state;
reg [12:0] info_node_1;
reg [12:0] info_node_2;
re... | 6.932076 |
module top_module (
input [4:1] x,
output f
);
wire not_x1, not_x2, not_x4, w1, w2, w3;
not (not_x1, x[1]);
not (not_x2, x[2]);
not (not_x4, x[4]);
and (w1, not_x4, not_x2);
and (w2, not_x1, x[3]);
and (w3, x[2], x[3], x[4]);
or (f, w1, w2, w3);
endmodule
| 7.203305 |
module top_module (
input [4:1] x,
output f
);
assign f = ~((~x[2] & ~x[3] & x[4]) | (~x[1] & x[2] & ~x[3] & x[4]) | (x[1] & x[2] & x[3] & ~x[4]) | (~x[1] & x[2] & ~x[3] & ~x[4]));
endmodule
| 7.203305 |
module top_module (
input [4:1] x,
output f
);
assign f = (!x[1] & x[3]) | (!x[2] & !x[4]) | &x;
endmodule
| 7.203305 |
module top_module (
input clk,
input w,
R,
E,
L,
output Q
);
wire m1, m2;
mymux u_mymux_1 (
Q,
w,
E,
m1
);
mymux u_mymux_2 (
m1,
R,
L,
m2
);
mydff u_mydff_1 (
m2,
clk,
Q
);
endmodule
| 7.203305 |
module mydff (
input d,
clk,
output reg q
);
always @(posedge clk) begin
q <= d;
end
endmodule
| 7.474227 |
module mymux (
input in0,
in1,
sel,
output out
);
assign out = sel ? in1 : in0;
endmodule
| 7.768112 |
module top_module (
input [3:0] SW,
input [3:0] KEY,
output [3:0] LEDR
); //
wire mux[7:0];
mymux u_mymux_11 (
LEDR[3],
KEY[3],
KEY[1],
mux[0]
);
mymux u_mymux_12 (
mux[0],
SW[3],
KEY[2],
mux[1]
);
mydff u_mydff_1 (
mux[1],
KEY[0],... | 7.203305 |
module mydff (
input d,
clk,
output reg q
);
always @(posedge clk) begin
q <= d;
end
endmodule
| 7.474227 |
module mymux (
input in0,
in1,
sel,
output out
);
assign out = sel ? in1 : in0;
endmodule
| 7.768112 |
module top_module (
input clk,
input enable,
input S,
input A,
B,
C,
output Z
);
reg [7:0] shiftreg;
initial shiftreg = 8'd0;
// 我去，还能这样做
assign Z = shiftreg[{A, B, C}];
always @(posedge clk) begin
if (enable) begin
shiftreg <= {shiftreg[6:0], S};
end
end
en... | 7.203305 |
module top_module (
input a,
input b,
input c,
input d,
output out_sop,
output out_pos
);
assign out_sop = (c & d) | (~a & ~b & c);
assign out_pos = (~a & ~b & c) | (b & c & d) | (a & c & d);
endmodule
| 7.203305 |
module top_module (
input clk,
input j,
input k,
output Q
);
always @(posedge clk) begin
case ({
j, k
})
2'b00: Q <= Q;
2'b01: Q <= 0;
2'b10: Q <= 1;
2'b11: Q <= !Q;
endcase
end
endmodule
| 7.203305 |
module top_module (
input [7:0] a,
input [7:0] b,
output [7:0] s,
output overflow
); //
// assign s = ...
// assign overflow = ...
assign s = a + b;
// hint: 两负相加变正、两正相加变负表示溢出
assign overflow = a[7] & b[7] & ~s[7] | ~a[7] & ~b[7] & s[7];
endmodule
| 7.203305 |
module top_module (
input c,
input d,
output [3:0] mux_in
);
assign mux_in[0] = c | d;
assign mux_in[1] = 0;
assign mux_in[2] = (c & d);
assign mux_in[3] = !d;
endmodule
| 7.203305 |
module top_module (
input clk,
input x,
output z
);
wire q1, q2, q3;
assign z = !(q1 | q2 | q3);
mydff u_mydff_1 (
q1 ^ x,
clk,
q1
);
mydff u_mydff_2 (
!q2 & x,
clk,
q2
);
mydff u_mydff_3 (
!q3 | x,
clk,
q3
);
endmodule
| 7.203305 |
module mydff (
input d,
clk,
output reg q
);
always @(posedge clk) begin
q <= d;
end
endmodule
| 7.474227 |
module top_module (
input clk, // posedge
input reset, // sync rst
input enable, // hi-enable
output [3:0] Q,
output c_enable,
output c_load,
output [3:0] c_d
); //
assign c_enable = enable;
// c_load决定什么时候从d锁存数据至q，两个情况：复位或计数到达最大
assign c_load = reset | (Q == 4'd12 && enable);
/... | 7.203305 |
module top_module (
input clk,
input reset,
output OneHertz,
output [2:0] c_enable
); //
reg [3:0] l, m, h;
initial l = 4'b0;
initial m = 4'b0;
initial h = 4'b0;
assign OneHertz = (h == 4'd9 && m == 4'd9 && l == 4'd9);
assign c_enable = {m == 4'd9 && l == 4'd9, l == 4'd9, 1'b1};
bcdcou... | 7.203305 |
module top_module (
input [4:1] x,
output f
);
assign f = (x[3] & !x[1]) | (x[1] & x[2] & !x[3]);
endmodule
| 7.203305 |
module top_module (
input d,
input ena,
output q
);
always @(*) begin
if (ena) q = d;
end
endmodule
| 7.203305 |
module top_module (
input clk,
input d,
input ar, // asynchronous reset
output q
);
always @(posedge clk or posedge ar) begin
if (ar) q <= 1'b0;
else q <= d;
end
endmodule
| 7.203305 |
module top_module (
input clk,
input d,
input r, // synchronous reset
output q
);
always @(posedge clk) begin
if (r) q <= 1'b0;
else q <= d;
end
endmodule
| 7.203305 |
module top_module (
input clk,
input in,
output out
);
always @(posedge clk) begin
out <= (out ^ in);
end
endmodule
| 7.203305 |
module top_module (
input in1,
input in2,
output out
);
assign out = !(in1 | in2);
endmodule
| 7.203305 |
module top_module (
input in1,
input in2,
output out
);
assign out = in1 & (!in2);
endmodule
| 7.203305 |
module top_module (
input in1,
input in2,
input in3,
output out
);
assign out = (!(in1 ^ in2) ^ in3);
endmodule
| 7.203305 |
module top_module (
input in,
output out
);
assign out = in;
endmodule
| 7.203305 |
module top_module (
output out
);
assign out = 1'b0;
endmodule
| 7.203305 |
module top_module (
input [3:0] x,
input [3:0] y,
output [4:0] sum
);
wire [2:0] carry;
full_adder u_full_adder_1 (
x[0],
y[0],
0,
carry[0],
sum[0]
);
full_adder u_full_adder_2 (
x[1],
y[1],
carry[0],
carry[1],
sum[1]
);
full_adder ... | 7.203305 |
module top_module (
input clk,
input resetn, // synchronous reset
input in,
output out
);
reg [3:0] shiftreg;
assign out = shiftreg[0];
always @(posedge clk) begin
if (!resetn) begin
shiftreg <= 4'd0;
end else begin
shiftreg <= {in, shiftreg[3:1]};
end
end
endmodul... | 7.203305 |
module data_path #(
parameter DATA_WIDTH = 8
) (
clk,
rst,
SUM_SEL,
NEXT_SEL,
A_SEL,
LD_SUM,
LD_NEXT,
NEXT_ZERO,
ans
);
input clk;
input rst;
input SUM_SEL;
input NEXT_SEL;
input A_SEL;
input LD_SUM;
input LD_NEXT;
output NEXT_ZERO;
output ans;
wire [DATA_WID... | 7.155626 |
module somacompleta (
s,
fao1,
fai0,
a,
b
);
output s, fao1;
input fai0, a, b;
wire w0, w1, w2;
meiasoma HALFADD1 (
w0,
w1,
fai0,
a
);
meiasoma HALFADD2 (
fao0,
w2,
w0,
b
);
or OR1 (fao1, w1, w2);
endmodule
| 7.045629 |
module somacompleta (
fao0,
fao1,
fai0,
fai1,
fai2
);
output fao0, fao1;
input fai0, fai1, fai2;
wire faw0, faw1, faw2, faw3, faw4;
meiasoma HALFADD1 (
faw0,
faw1,
fai0,
fai1
);
meiasoma HALFADD2 (
fao0,
faw2,
faw0,
fai2
);
nand NAND9 ... | 7.045629 |
module Exercicio0504;
reg [3:0] A, B;
wire [3:0] S;
wire [1:0] W;
somacompleta FULLADD1 (
S[0],
W[0],
A[0],
B[0],
0
);
somacompleta FULLADD2 (
S[1],
W[1],
A[1],
B[1],
W[0]
);
somacompleta FULLADD3 (
S[2],
S[3],
A[2],
B... | 7.280671 |
module except( clk, opa, opb, inf, ind, qnan, snan, opa_nan, opb_nan,
opa_00, opb_00, opa_inf, opb_inf, opa_dn, opb_dn);
input clk;
input [31:0] opa, opb;
output inf, ind, qnan, snan, opa_nan, opb_nan;
output opa_00, opb_00;
output opa_inf, opb_inf;
output opa_dn;
output opb_dn;
///////////////////////////////... | 6.521738 |
module exceptiondec (
input wire [31:0] pcE, // 地址错误，MEM阶段写入异常
input wire [31:0] memAddrE, // 访存地址（数据存储器）
input wire [31:0] cp0cause, // cp数据
input wire [31:0] cp0status, // status 寄存器
// exception signal
input wire isSy... | 7.808788 |
module ExceptionGen (
input [ `INST_BUS] inst,
input [ `INST_OP_BUS] op,
input [`REG_ADDR_BUS] rs,
input [`REG_ADDR_BUS] rt,
input [ `FUNCT_BUS] funct,
output eret_flag,
output syscall_flag,
output break_flag,
output overflow_flag,
output reg invalid_inst_fl... | 7.093775 |
module ExceptionModule (
Z,
NegE,
R,
S,
InputExc,
EOF,
P,
Flags
);
// Input ports
input [31:0] Z; // Final product
input NegE; // Negative exponent?
input R; // Round bit
input S; // Sticky bit
input [4:0] InputExc; // Exceptions in inputs A and B
input EOF;
// Out... | 7.368018 |
module exceptions_1 (
Ex,
Ey,
Mx,
My,
zero_mantessa_x,
zero_mantessa_y,
max_exponent_x,
max_exponent_y
);
input [7:0] Ex, Ey;
input [22:0] Mx, My;
output reg zero_mantessa_x, zero_mantessa_y, max_exponent_x, max_exponent_y;
always @(*) begin
zero_mantessa_x = ~|Mx;
zero_m... | 8.024155 |
module exceptions_2 (
zero_mantessa_x,
zero_mantessa_y,
max_exponent_x,
max_exponent_y,
max_exponent_z,
overflow_case,
x_is_inf,
y_is_inf
);
input zero_mantessa_x, zero_mantessa_y, max_exponent_x, max_exponent_y, max_exponent_z;
output reg overflow_case, x_is_inf, y_is_inf;
always ... | 7.393287 |
module exceptions_new (
Ex,
Ey,
Mx,
My,
EOP,
max_exponent_z,
invalid_flag,
overflow_flag
);
input [7:0] Ex, Ey;
input [22:0] Mx, My;
input EOP, max_exponent_z;
output wire invalid_flag, overflow_flag;
//internal signals
wire zero_mantessa_x , zero_mantessa_y , max_exponent_x ... | 6.521835 |
module ExceptionUnit (
input clk,
rst,
input csr_rw_in,
input [1:0] csr_wsc_mode_in,
input csr_w_imm_mux,
input [11:0] csr_rw_addr_in,
input [31:0] csr_w_data_reg,
input [4:0] csr_w_data_imm,
output [31:0] csr_r_data_out,
input interrupt,
input illegal_inst,
input l_acce... | 6.910599 |
module exception_gen (
input ctrl_alu,
input ctrl_addi,
input ovf,
input [4:0] aluop,
output reg ctrl_ex,
output reg [31:0] data_excode
);
always @(*) begin
ctrl_ex = 1'b0;
data_excode = 32'h00000000;
if (ovf) begin
if (ctrl_addi) begin
ctrl_ex = 1'b1;
d... | 6.71594 |
module exception_type (
input rst,
input [31:0] pcM,
input [7:0] exceptioncollectM,
input wire [31:0] cp0_status,
cp0_cause,
aluoutM,
output reg [31:0] excepttype_i,
bad_addr
);
//0:eret,1:syscall,2:break,3:reserve,4:orveflow,5:adelM,6:adesM
always @(*) begin
if (rst) excepttype_... | 7.154899 |
module exceptions (
input clk,
input dmiss,
input imiss,
input dfill,
input ifill,
input jump,
input remaining_stores,
output IFID_we,
output IDEX_we,
output EX_WBTL_we,
output TLC_we,
output CWB_we,
output EXS1_we,
output S12_we,
output S23_we,
output S3... | 6.504684 |
module except_detect1 (
input syscall_i,
input eret_i,
input invalid_inst_i,
input break_i,
input [31:0] excepttype_i,
output reg [31:0] excepttype_o
);
always @(*) begin
excepttype_o = excepttype_i;
if (syscall_i == 1'b1) begin
excepttype_o[`bit_Sys]... | 7.397355 |
module except_detect2 (
input alu_lf,
input alu_of,
input alu_zf,
input trap,
input overflow_detect,
input [31:0] excepttype_i,
input [ 2:0] condition,
output reg [31:0] excepttype_o
);
always @(*) begin
excepttype_o = excepttype_i;
if (overf... | 7.397355 |
module except_detect_if (
input [31:0] pc_i,
output reg [31:0] excepttype_o
);
always @(*) begin
excepttype_o = 32'h00000000;
end
endmodule
| 7.397355 |
module except_detect_mem (
input [31:0] excepttype_i,
input [31:0] access_addr_i,
input load_en_i,
input store_en_i,
input [ 2:0] load_sel_i,
input [ 2:0] store_sel_i,
input [31:0] branch_target,
input branch_state,
output reg [31:0] excepttype_o
);
always @(... | 7.397355 |
module excep_ctrl (
//from rob
input rob_commit_valid,
input [PC_WIDTH-1:0] rob_cm_exp_pc,
input rob_cm_mret,
input rob_cm_wfi,
input [3:0] rob_cm_ecause,
input rob_cm_exp,
// from csr
input sip, // software interrupt pending
input tip, // timer
input eip, // external
... | 7.221159 |
module excess_ram_32x16bit (
input clk,
input [4:0] excess_addr, //对应的block
input [15:0] excess_wr_data,
input excess_wren,
//同时读4位
input excess_4block_rden,
input [4:0] excess_addr_rd1,
input [4:0] excess_addr_rd2,
input [4:0] excess_addr_rd3,
input [4:0] excess_addr_rd4,
... | 6.881392 |
module exciting (
input clk,
input rst,
input switch,
output signal
);
reg lag1, lag2;
always @(posedge clk or posedge rst) begin
if (rst) begin
lag1 <= switch;
lag2 <= lag1;
end else begin
lag1 <= switch;
lag2 <= lag1;
end
end
//输出为一个时钟周期的信号
assign si... | 7.352703 |
module Excuteunit #(parameter width=32)(
input[width-1:0] PC,RD1,RD2,immediatevalue,
input [4:0] Rd,[3:0]ALUcontrolinput,[8:0] controlsignal,
input [4:0] Rs1,Rs2,Rd1,Rd2,
input [width-1:0] ALUIN,Writedatain,
output zero,[width-1:0] ALUresult,branchaddress,ReadData22,
output [4:0] rd, [5:0] contr... | 7.070735 |
module EXE_EXC (
overflow,
flow_sus,
ExcCode_E,
ExcCode
);
//interface
input overflow;
input flow_sus; //add/sub/addi
input [6:2] ExcCode_E;
output reg [6:2] ExcCode;
//Ov
always @(*) begin
if (overflow && flow_sus) ExcCode = `Ov;
else ExcCode = ExcCode_E;
end
endmodule
| 6.550097 |
module Exc_i (
instr_d,
pc8_i,
bd_i,
exccode_i,
b_d
);
input [31:0] pc8_i, instr_d;
input b_d;
output bd_i;
output [4:0] exccode_i;
wire [31:0] pc;
assign pc = pc8_i - 8;
assign bd_i = (instr_d[31:26] ==
`beq
|| instr_d[31:26] ==
`j
|| instr_d[31:26] ==
... | 6.91895 |
module EXE (
input [31:0] rda_EX,
input [31:0] rdb_EX,
input [31:0] imm_EX,
input ALUsrc, //control
input [1:0] ALUOP,
input funct7,
input [2:0] funct3,
//forwarding part
input forwardA,
forwardB,
input [31:0] wdata_WB,
output wire [31:0] alu_result
);
reg [... | 7.594385 |
module registres;
reg [5:0] a;
reg [4:0] b;
reg [6:0] c;
reg [4:0] d;
reg [4:0] e;
reg [5:0] f;
reg [9:0] g;
reg [5:0] h;
reg [3:0] i;
reg [8:0] j;
reg [8:0] k;
reg [6:0] l;
reg [4:0] m;
reg [5:0] n;
reg [6:0] o;
reg [9:0] p;
// ------------------------- Main
initial begin
$disp... | 7.009924 |
module registres;
reg [5:0] a;
reg [4:0] b;
reg [4:0] c;
reg [5:0] d;
reg [3:0] e;
reg [5:0] f;
reg [4:0] g;
reg [5:0] h;
reg [3:0] i;
// ------------------------- Main
initial begin
$display("Guia02 Ex03 - Marden Santos Batista- 388613");
//Operations
$display("Operaoes");
a = 6'... | 7.009924 |
module registres;
reg [ 5:0] a;
reg [10:0] b;
reg [ 4:0] c;
reg [ 3:0] d;
reg [ 4:0] e;
reg [ 8:0] f;
reg [ 6:0] g;
reg [ 5:0] h;
reg [ 4:0] i;
reg [ 7:0] j;
// ------------------------- Main
initial begin
$display("Guia02 Ex04 - Marden Santos Batista- 388613");
//Operations
$displa... | 7.009924 |
module registres;
reg [5:0] a;
reg [3:0] b;
reg [7:0] c;
reg [7:0] c2;
reg [4:0] d;
reg [3:0] e;
reg [7:0] f;
reg [7:0] f2;
reg [4:0] g;
reg [3:0] h;
reg [7:0] i;
reg [7:0] i2;
reg [7:0] j;
reg [7:0] k;
reg [7:0] l;
reg [7:0] l2;
reg [7:0] m;
reg [7:0] n;
reg [7:0] o;
reg [7:0] o... | 7.009924 |
module EXE2MEM (
clk,
rst,
WB_EN_IN,
MEM_R_EN_IN,
MEM_W_EN_IN,
PCIn,
ALUResIn,
STValIn,
destIn,
WB_EN,
MEM_R_EN,
MEM_W_EN,
PC,
ALURes,
STVal,
dest
);
input clk, rst;
// TO BE REGISTERED FOR ID STAGE
input WB_EN_IN, MEM_R_EN_IN, MEM_W_EN_IN;
input [... | 6.691158 |
module meiasoma (
s0,
s1,
a,
b
);
output s0, s1;
input a, b;
xor (s0, a, b);
and (s1, a, b);
endmodule
| 7.813544 |
module somaCompleta (
s0,
s1,
a,
b,
c
);
input a, b, c;
output s0, s1;
meiasoma HA1 (
r,
c1,
a,
b
);
meiasoma HA2 (
s0,
c2,
r,
c
);
or (s1, c2, c1);
endmodule
| 7.146397 |
module soma (
s,
a,
b,
op
);
input [3:0] a, b;
input op;
output [3:0] s;
xor XOR1 (n0, b[0], op);
somaCompleta FA1 (
s[0],
c1,
a[0],
n0,
op
);
xor XOR2 (n1, b[1], op);
somaCompleta FA2 (
s[1],
c2,
a[1],
n1,
c1
);
xor XOR... | 7.074089 |
module comparador (
s,
a,
b
);
input [3:0] a, b;
output s;
wire [3:0] c;
xnor XNOR1 (c[0], a[0], b[0]);
xnor XNOR2 (c[1], a[1], b[1]);
xnor XNOR3 (c[2], a[2], b[2]);
xnor XNOR4 (c[3], a[3], b[3]);
and AND1 (s, c[3], c[2], c[1], c[0]);
endmodule
| 7.425908 |
module alu (
s,
i,
a,
b,
op
);
input [3:0] a, b;
input op;
output [3:0] s;
output i;
soma SOMA1 (
s,
a,
b,
op
);
comparador COMPARADOR1 (
i,
a,
b
);
endmodule
| 6.774878 |
module meiasoma (
s0,
s1,
a,
b
);
output s0, s1;
input a, b;
xor (s0, a, b);
and (s1, a, b);
endmodule
| 7.813544 |
module somaCompleta (
s0,
s1,
a,
b,
c
);
input a, b, c;
output s0, s1;
meiasoma HA1 (
r,
c1,
a,
b
);
meiasoma HA2 (
s0,
c2,
r,
c
);
or (s1, c2, c1);
endmodule
| 7.146397 |
module soma (
s,
a,
b,
op
);
input [3:0] a, b;
input op;
output [3:0] s;
xor XOR1 (n0, b[0], op);
somaCompleta FA1 (
s[0],
c1,
a[0],
n0,
op
);
xor XOR2 (n1, b[1], op);
somaCompleta FA2 (
s[1],
c2,
a[1],
n1,
c1
);
xor XOR... | 7.074089 |
module comparadorA (
c1,
c2,
c3,
a,
b
);
input [3:0] a, b;
output c1, c2, c3;
wire [3:0] s;
soma SOMA1 (
s,
a,
b,
1
);
comparadorL COMPARADOR1 (
c2,
a,
b
);
nor NOR1 (c1, c2, s[3]);
assign c3 = s[3];
endmodule
| 7.101731 |
module alu (
s,
c1,
c2,
c3,
a,
b,
op
);
input [3:0] a, b;
input op;
output [3:0] s;
output c1, c2, c3;
soma SOMA1 (
s,
a,
b,
op
);
comparadorA COMPARADOR1 (
c1,
c2,
c3,
a,
b
);
endmodule
| 6.774878 |
module meiasoma (
s0,
s1,
a,
b
);
output s0, s1;
input a, b;
xor (s0, a, b);
and (s1, a, b);
endmodule
| 7.813544 |
module somaCompleta (
s0,
s1,
a,
b,
c
);
input a, b, c;
output s0, s1;
meiasoma HA1 (
r,
c1,
a,
b
);
meiasoma HA2 (
s0,
c2,
r,
c
);
or (s1, c2, c1);
endmodule
| 7.146397 |
module soma (
s,
c4,
a,
b,
op
);
input [3:0] a, b;
input op;
output [3:0] s;
output c4;
xor XOR1 (n0, b[0], op);
somaCompleta FA1 (
s[0],
c1,
a[0],
n0,
op
);
xor XOR2 (n1, b[1], op);
somaCompleta FA2 (
s[1],
c2,
a[1],
n1,
... | 7.074089 |
module comparadorA (
c1,
c2,
c3,
a,
b
);
input [3:0] a, b;
output c1, c2, c3;
wire [3:0] s;
soma SOMA1 (
s,
c,
a,
b,
1
);
comparadorL COMPARADOR1 (
c2,
a,
b
);
nor NOR1 (c1, c2, s[3]);
assign c3 = s[3];
endmodule
| 7.101731 |
module carry (
c,
a,
b,
op
);
input [3:0] a, b;
input op;
output c;
output [3:0] s;
soma SOMA1 (
s,
c,
a,
b,
op
);
endmodule
| 6.743084 |
module alu (
s,
o,
c1,
c2,
c3,
z,
c,
a,
b,
op,
p
);
input [3:0] a, b, p;
input op;
output [3:0] s;
output c1, c2, c3, o, z, c;
soma SOMA1 (
s,
c,
a,
b,
op
);
comparadorA COMPARADOR1 (
c1,
c2,
c3,
a,
b... | 6.774878 |
module meiasoma (
s0,
s1,
a,
b
);
output s0, s1;
input a, b;
xor (s0, a, b);
and (s1, a, b);
endmodule
| 7.813544 |
module somaCompleta (
s0,
s1,
a,
b,
c
);
input a, b, c;
output s0, s1;
meiasoma HA1 (
r,
c1,
a,
b
);
meiasoma HA2 (
s0,
c2,
r,
c
);
or (s1, c2, c1);
endmodule
| 7.146397 |
module soma (
s,
c4,
a,
b,
op
);
input [3:0] a, b;
input op;
output [3:0] s;
output c4;
wire [3:0] n;
complemento1 COMP1 (
n,
b
);
somaCompleta FA1 (
s[0],
c1,
a[0],
n[0],
op
);
somaCompleta FA2 (
s[1],
c2,
a[1],
... | 7.074089 |
module comparadorA (
c1,
c2,
c3,
a,
b
);
input [3:0] a, b;
output c1, c2, c3;
wire [3:0] s;
soma SOMA1 (
s,
c,
a,
b,
op
);
comparadorL COMPARADOR1 (
c2,
a,
b
);
nor NOR1 (c1, c2, s[3]);
assign c3 = s[3];
endmodule
| 7.101731 |
module carry (
c,
a,
b,
op
);
input [3:0] a, b;
input op;
output c;
output [3:0] s;
soma SOMA1 (
s,
c,
a,
b,
op
);
endmodule
| 6.743084 |
module meiasoma (
s0,
s1,
a,
b
);
output s0, s1;
input a, b;
xor (s0, a, b);
and (s1, a, b);
endmodule
| 7.813544 |
module somaCompleta (
s0,
s1,
a,
b,
c
);
input a, b, c;
output s0, s1;
meiasoma HA1 (
r,
c1,
a,
b
);
meiasoma HA2 (
s0,
c2,
r,
c
);
or (s1, c2, c1);
endmodule
| 7.146397 |
module soma (
s,
c4,
a,
b,
op
);
input [3:0] a, b;
input op;
output [3:0] s;
output c4;
wire [3:0] n;
complemento1 COMP1 (
n,
b
);
somaCompleta FA1 (
s[0],
c1,
a[0],
n[0],
op
);
somaCompleta FA2 (
s[1],
c2,
a[1],
... | 7.074089 |
module comparadorA (
c1,
c2,
c3,
a,
b
);
input [3:0] a, b;
output c1, c2, c3;
wire [3:0] s;
soma SOMA1 (
s,
c,
a,
b,
op
);
comparadorL COMPARADOR1 (
c2,
a,
b
);
nor NOR1 (c1, c2, s[3]);
assign c3 = s[3];
endmodule
| 7.101731 |
module carry (
c,
a,
b,
op
);
input [3:0] a, b;
input op;
output c;
output [3:0] s;
soma SOMA1 (
s,
c,
a,
b,
op
);
endmodule
| 6.743084 |
module alu (
s,
o,
c1,
c2,
c3,
z,
c,
d1a,
d1b,
n,
r,
a,
b,
op,
p
);
input [3:0] a, b, p;
input op;
output [3:0] s, d1a, d1b, n, r;
output c1, c2, c3, o, z, c;
soma SOMA1 (
s,
c,
a,
b,
op
);
comparadorA COMPARADOR1 ... | 6.774878 |
module f4 (
output s,
input a,
input b,
input [2:0] key
);
wire temp0, temp1, temp2, temp3,temp4, temp5, temp6, temp7, temp8, temp9, temp10, temp11, temp12, temp13, temp14;
wire [2:0] keytemp;
//--portas
and AND0 (temp0, a, b);
or OR0 (temp1, a, b);
xor XOR0 (temp2, a, b);
not NOT0 (temp3,... | 6.784298 |
module test_f4;
// ------------------------- definir dados
reg x;
reg y;
reg [2:0] v;
wire z;
f4 Teste (
z,
x,
y,
v
);
// ------------------------- parte principal
initial begin
$display("Exemplo0035 - Matheus de Souza Castro Santos - 466516");
$display("Test LU's mo... | 6.629466 |
module exercicio;
// definir dados
reg [7:0] a;
reg [7:0] b;
reg [9:0] g;
reg [8:0] i;
reg [8:0] h;
reg [6:0] sa;
reg [5:0] sb;
reg [3:0] sc;
reg [6:0] sd;
reg [8:0] se;
// ------------------------- parte principal
initial begin
$display("Exemplo0015 - Ana Carolina - 449517");
$displ... | 6.815543 |
module execute (
input clk,
// Inputs
input [ 2:0] E_stat,
input [ 3:0] E_icode,
input [ 3:0] E_ifun,
input [63:0] E_valC,
input [63:0] E_valA,
input [63:0] E_valB,
input [ 3:0] E_dstE,
input [ 3:0] E_dstM,
input [ 2:0] W_stat,
input [ 2:0] m_stat,
// Outputs
ou... | 6.624963 |
module execute (
input wire [31:0] A,
input wire [31:0] B,
input wire [ 5:0] func_code,
output wire [31:0] out
);
//assume 6'b111111 is mult
reg out_sel;
reg doMult;
always @*
case (func_code)
6'h0e: begin
out_sel = 1;
doMult = 1;
end
default: begin
... | 6.624963 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.