code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module testbench;
reg clock;
reg reset;
wire [05:00] reg_rd1;
wire [05:00] reg_rd2;
wire [05:00] reg_rd3;
wire [08:00] data_rd1;
wire [08:00] data_rd2;
wire [08:00] data_rd3;
wire [08:00] data_rd4;
wire [15:00] reg_rd1_out;
wire [15:00] reg_rd2_out;
wire [15:00] reg_rd3_ou... | 7.015571 |
module execute_alu (
input wire [ 5:0] alu_op,
input wire [`REGSZ-1:0] in_a,
input wire [`REGSZ-1:0] in_b,
input wire [`REGSZ-1:0] in_c,
input wire carry_in,
output wire carry_out,
output wire overflow,
output wire [`REGSZ-1:0] out
);
... | 7.06956 |
module execute_alu_adder (
input wire [`REGSZ-1:0] A,
input wire [`REGSZ-1:0] B,
output wire [`REGSZ-1:0] OUT,
input wire CI,
output wire CO,
output wire OV
);
reg [`REGSZ:0] res; /* Note 1 bit larger */
always @(*) begin
res = A + B + CI;
e... | 7.768825 |
module execute_br_cond (
input wire [4:0] instr_cr_field,
input wire input_valid,
input wire [3:0] input_fault,
input wire [ 3:0] exe_brcond,
input wire [31:0] cond_reg,
input wire br_ctr_z,
output wire branch_taken
);
reg br_taken; // Wire
reg br_cr_bit; // Wire
//... | 6.666047 |
module execute_clz (
input wire [31:0] in,
output wire [ 5:0] count
);
// Approach: cascade 4 8-bit clz8 blocks
// and generate a priority decode from all of them?
wire [3:0] a;
wire [3:0] b;
wire [3:0] c;
wire [3:0] d;
reg [5:0] num; // Wire
clz8 CLZA (
.in(in[31:24]),
.coun... | 7.49918 |
module clz8 (
input wire [7:0] in,
output wire [3:0] count
);
reg [3:0] num;
always @(*) begin
casez (in)
8'b1???????: num = 0;
8'b01??????: num = 1;
8'b001?????: num = 2;
8'b0001????: num = 3;
8'b00001???: num = 4;
8'b000001??: num = 5;
8'b0000001?: num = 6;... | 7.764332 |
module operand_select_ex (
output [31:0] b,
output [31:0] count,
input CLK,
input PRE,
input CLR,
input CS_IS_CMPS_FIRST_UOP_ALL,
input CS_IS_CMPS_SECOND_UOP_ALL,
input CS_REPNE_INTERNAL_COUNT_WB,
input [31:0] EX_A,
input [31:0] EX_B,
input [31:0] EX_C,
input [31:0] saved... | 6.554126 |
module cmpxchg_decision_ex (
output ex_ld_gpr1,
output ex_ld_gpr2,
output ex_dcache_write,
input CS_IS_CMPXCHG_EX,
input EX_de_ld_gpr1_ex,
input CS_LD_GPR2_EX,
input EX_de_dcache_write_ex,
input [31:0] alu32_flags
);
wire ZF;
assign ZF = alu32_flags[6];
wire ZF_not;
wire equal... | 7.295963 |
module functional_unit_ex (
output [31:0] alu32_result,
output [31:0] alu32_flags,
output [63:0] alu64_result,
output [31:0] shift_result,
output [31:0] shift_flags,
output [31:0] count_minus_one,
output [31:0] stack_pointer_pop,
output [31:0] cmps_pointer_updated,
input [ 2:0] EX_d... | 7.159461 |
module stall_and_bubble_ex (
output WB_ld_latches,
output WB_V_next,
input WB_Stall,
input WB_de_repne_all,
input EX_V,
input wb_repne_terminate_all
);
inv1$ not_wb_stall (
WB_ld_latches,
WB_Stall
);
wire wb_repne_terminate_all_not;
wire valid_terminate_not;
inv1$ no... | 6.794877 |
module repne_support (
output [31:0] repne_count,
input [31:0] count,
input [31:0] count_minus_one,
input [31:0] ex_flags
);
wire ZF;
wire repne_zero_terminate;
wire repene_final_terminate;
assign ZF = ex_flags[6];
equal_to_zero u_zero_count (
repne_zero_terminate,
count
);... | 7.30861 |
module result_select_ex (
output [31:0] WB_RESULT_A_next,
output [31:0] WB_RESULT_B_next,
output [31:0] WB_RESULT_C_next,
output [31:0] WB_FLAGS_next,
output [63:0] WB_RESULT_MM_next,
input CS_IS_ALU32_EX,
input CS_IS_CMPS_FIRST_UOP_ALL,
input CS_IS_XCHG_EX,
input CS_PASS_A_EX,
i... | 6.839128 |
module execute_crf (
input wire [`REGSZ-1:0] in,
input wire co,
input wire ov,
input wire SO,
output wire [ 3:0] crf,
output wire [ 3:0] crf_compare_signed,
output wire [ 3:0] crf_compare_unsigned
);
reg EQ;
reg LT;
reg G... | 6.852448 |
module execute_memory (
i_clk,
i_rst_n,
i_alures,
i_busB,
i_Rw,
i_M,
i_WB,
o_alures,
o_busB,
o_Rw,
o_M,
o_WB
);
input wire i_clk, i_rst_n;
input wire [31:0] i_alures;
input wire [31:0] i_busB;
input wire [4:0] i_Rw;
input wire [1:0] i_M;
input wire i_WB;
o... | 6.622698 |
module execute_memory_access (
clk
);
input clk;
wire clk;
reg [31:0] instruction, pc_current, branchtarget, op2, aluresult1;
reg isst, isld, isbeq, Isbgt, isret, isimmediate, iswb, isubranch, iscall;
reg [4:0] alusignal;
always @(negedge clk) begin
#9.99
instruction <= p.pr2.i... | 6.622698 |
module XOR (
x,
y,
z
);
input [63:0] x, y;
output [63:0] z;
genvar i;
generate
for (i = 0; i < 64; i = i + 1) begin
xor (z[i], x[i], y[i]);
end
endgenerate
endmodule
| 7.095291 |
module AND (
x,
y,
z
);
input [0:63] x, y;
output [0:63] z;
genvar i;
generate
for (i = 0; i < 64; i = i + 1) begin
and (z[i], x[i], y[i]);
end
endgenerate
endmodule
| 6.925853 |
module ADD (
x,
y,
sum,
OF
);
input signed [63:0] x, y;
output signed [63:0] sum;
output signed OF;
wire signed [63:0] ci;
wire carry_in;
assign carry_in = 1'b0;
full_adder FA1 (
x[0],
y[0],
carry_in,
sum[0],
ci[0]
);
genvar i;
generate
for (i = 1... | 6.891749 |
module SUB (
x,
y,
z,
OF
);
input signed [63:0] x, y;
output signed [63:0] z;
output OF;
wire signed [63:0] u, v, w;
wire signed [63:0] k;
twocomp comp (
y,
u
);
ADD sub_add (
x,
u,
w,
OF
);
assign z = w;
endmodule
| 6.850044 |
module twocomp (
x,
y
);
input signed [63:0] x;
output signed [63:0] y;
wire signed [63:0] w;
wire c_out;
genvar i;
generate
for (i = 0; i < 64; i = i + 1) begin
not (w[i], x[i]);
end
endgenerate
ADD twocomp1 (
w,
64'b1,
y,
c_out
);
endmodule
| 6.570209 |
module execute_pipe_reg #(
parameter data_width = 32,
alu_ctrl_width = 3,
op_width = 5
) (
input clk,
input reset,
input clr,
//control_unit_in
input reg_write_d,
input mem2reg_d,
input mem_wr_d,
input [alu_ctrl_width-1:0] alu_control_d,
input alu_src_d,
input reg_dst... | 7.013014 |
module execute_reg (
input wire clk_i,
input wire rstn_i,
input wire E_bubble_i,
input wire [`NIBBLE] D_stat_i,
input wire [`NIBBLE] D_icode_i,
input wire [`NIBBLE] D_ifun_i,
input wire [`D_WORD] D_valC_i,
input wire [`D_WORD] d_valA_i,
input wi... | 7.319482 |
module execute_register (
clk,
D_stat,
D_icode,
D_ifun,
D_valP,
D_valC,
d_valA,
d_valB,
d_rA,
d_rB,
E_stat,
E_icode,
E_ifun,
E_valC,
E_valA,
E_valB,
E_rA,
E_rB,
E_valP
);
input clk;
input [2:0] D_stat;
input [3:0] D_icode;
input [3:0] D... | 6.728157 |
module mask (
input wire [ 4:0] start_bit,
input wire [ 4:0] stop_bit,
output wire [31:0] out
);
reg [31:0] res; // Wire
reg [3:0] s1, e1; // Wire
reg [3:0] s0, e0; // Wire
wire [15:0] m0, m1;
wire w0, w1;
mask16 masker1 (
.start_bit(s1),
.stop_bit(e1),
.out(m1),
... | 7.715093 |
module mask16 (
input wire [ 3:0] start_bit,
input wire [ 3:0] stop_bit,
output wire [15:0] out,
output wire wrapped
);
reg [15:0] res; // Wire
reg w; // Wire
reg [2:0] s1, e1; // Wire
reg [2:0] s0, e0; // Wire
wire [7:0] m0, m1;
wire w0, w1;
mask8 masker1 (
.s... | 7.756101 |
module mask8 (
input wire [2:0] start_bit,
input wire [2:0] stop_bit,
output wire [7:0] out,
output wire wrapped
);
reg [7:0] r; // Wire
reg w; // Wire
reg [1:0] s1, e1; // Wire
reg [1:0] s0, e0; // Wire
wire [3:0] m0, m1;
wire w0, w1;
mask4 masker1 (
.start_bit(... | 7.680658 |
module mask4 (
input wire [1:0] start_bit,
input wire [1:0] stop_bit,
output wire [3:0] out,
output wire wrapped
);
reg [3:0] r; // Wire
reg w; // Wire
always @(*) begin
casez ({
start_bit, stop_bit
})
4'b0000: begin
r = 4'b0001;
w = 1'b0;
... | 7.647111 |
module Execute_TestCase;
// Inputs
reg clockPulse;
reg [31:0] ALU_Read_DataOne;
reg [31:0] ALU_Read_DataTwo;
reg [31:0] Immediate;
reg [5:0] Function;
reg [2:0] ALU_Operation;
reg ALU_Source;
// Outputs
wire [31:0] ALU_Result;
wire Zero;
// Instantiate the Unit Under Test (UUT)
Execute uut ... | 6.522358 |
module Execute_to_Memory_Register #(
parameter ALUOut_width = 32,
WriteData_width = 32,
WriteReg_width = 5
) (
input wire CLK,
input wire RST,
input wire RegWriteE,
input wire MemtoRegE,
input wire ... | 8.758502 |
module
// DEPARTMENT: communication and electronics department
// AUTHOR: Mina Hanna
// AUTHOR EMAIL: mina.hannaone@gmail.com
//------------------------------------------------
// Release history
// VERSION DATE AUTHOR DESCRIPTION
// 1.0 4/9/2022 Mina Hanna final version
//----------------------------------------------... | 8.923686 |
module execute (
input wire clock,
input wire [ 4:0] sa,
input wire [15:0] im,
input wire [25:0] instr_idx,
input wire [ 5:0] alu_op,
input wire br,
input wire jp,
input wire g_t,
input wire sign_x,
input wire nop,
input wire mem_op,
input wire enable,
input ... | 6.624963 |
module ExecutionBlock (
ans_ex,
DM_data,
data_out,
flag_ex,
A,
B,
data_in,
op_dec,
clk,
reset
);
input [7:0] A, B, data_in;
input [4:0] op_dec;
input clk, reset;
output reg [7:0] ans_ex, DM_data, data_out;
output wire [3:0] flag_ex;
wire [7:0] ans_tmp, data_out_buff;... | 7.128925 |
module execution_block (
ans_ex,
DM_data,
data_out,
flag_ex,
A,
B,
data_in,
op_dec,
clk,
reset
);
output reg [15:0] ans_ex, DM_data, data_out;
output [1:0] flag_ex;
input [15:0] A, B;
input [15:0] data_in;
input [5:0] op_dec;
input clk, reset;
reg [1:0] flag_prv;
... | 7.569451 |
module rsa (
ans_rsa,
A,
B
);
output [15:0] ans_rsa;
input signed [15:0] A; //Inbuilt RSA works only if the operand is signed
input [15:0] B;
assign ans_rsa = A >>> B;
endmodule
| 8.67374 |
module booth (
ans_mul,
mul_overflow,
A,
B
);
input signed [15:0] A, B;
output reg signed [15:0] ans_mul;
output reg mul_overflow;
reg signed [31:0] copy_z;
reg signed [31:0] Z;
reg [1:0] temp;
integer i;
reg E1;
reg [15:0] B1;
always @(A, B) begin
Z = 32'd0;
E1 = 1'd0;
... | 6.567276 |
module: execution_block
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module execution_block_tb;
// Inputs
reg [15:0] A;
reg [15:0] B;
reg [15:0] data_in;
reg [5:0] op_dec;
reg clk... | 6.831293 |
module execution_register (
input clk,
input rst,
input wb_en_in,
input mem_r_en_in,
input mem_w_en_in,
input [31:0] alu_result_in,
input [31:0] st_val_in,
input [3:0] dest_in,
output reg wb_en,
output reg mem_r_en,
output reg mem_w_en,
output reg [31:0] alu_result,
o... | 7.484162 |
module : execution_unit
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the ... | 9.708111 |
module execution_unit_result_selection (
input [31:0] mem_mux_out,
input [31:0] mac_out,
input mac_control_mem,
output reg [31:0] mem_final_mux
);
always @(*) begin
if (mac_control_mem == 1) begin
mem_final_mux = mac_out;
end else mem_final_mux = mem_mux_out;
end
endmodule
| 8.45822 |
module executor_ALU (
en,
opcode,
op1,
op2,
c_in,
result,
N,
Z,
C,
V
);
input en;
input [3:0] opcode;
input [31:0] op1, op2;
input c_in;
output [31:0] result;
output N, Z, C, V;
wire [32: 0] result_OP1, result_OP2, result_AND, result_ORR, result_EOR, ... | 6.7937 |
module Executs32 (
input [31:0] Read_data_1,
input [31:0] Read_data_2,
input [31:0] Sign_extend,
input [5:0] Function_opcode,
input [5:0] Exe_opcode,
input [1:0] ALUOp,
input [4:0] Shamt,
input Sftmd,
input ALUSrc,
input I_format,
input Jr,
output Zero,
//the ALU calc... | 7.947204 |
module exec_rom (
input clk,
input rst,
// Wishbone slave interface
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input [19:1] wb_adr_i,
input wb_we_i,
input wb_tga_i,
input wb_stb_i,
input wb_cyc_i,
input [ 1:0] wb_sel_i,
output ... | 7.301565 |
module alu_muxa (
input [31:0] spc,
input [31:0] pc,
input [31:0] fw_mem,
input [31:0] rs,
input [31:0] fw_alu,
input [31:0] ext,
input [1:0] ctl,
input [2:0] fw_ctl,
output reg [31:0] a_o
);
always @(*) begin
case (ctl)
`MUXA_RS: a_o = (fw_ctl == `FW_ALU) ? fw_alu : (f... | 8.379566 |
module alu_muxb (
input [31:0] rt,
input [31:0] ext,
input [1:0] ctl,
output reg [31:0] b_o
);
always @(*)
case (ctl)
// `MUXB_RT :b_o =rt; //(fw_ctl ==`FW_ALU )?fw_alu:(fw_ctl==`FW_MEM)?fw_mem:rt;
`MUXB_EXT: b_o = ext;
default b_o = rt;
endcase
endmodule
| 7.707778 |
module shifter_ff (
input [31:0] a,
output reg [31:0] shift_out,
input [4:0] shift_func, //connect to alu_func_ctl
input [31:0] shift_amount //connect to b
);
always @(*) begin
case (shift_func)
`ALU_SLL: shift_out = a << shift_amount;
`ALU_SRL: shift_out = a >> shift_amount;
... | 7.506042 |
module EXEC_Stage_Reg (
input clk,
rst,
input wb_en_in,
mem_r_en_in,
mem_w_en_in,
input [31:0] alu_result_in,
st_val_in,
input [3:0] dest_in,
output reg wb_en,
mem_r_en,
mem_w_en,
output reg [31:0] alu_result,
st_val,
output reg [3:0] dest
);
always @(posedge c... | 7.960162 |
module Exec_tb;
// Inputs
reg [31:0] Operand1;
reg [31:0] Operand2;
reg [4:0] Operation;
// Outputs
wire [31:0] Out;
wire bcond;
reg [31:0] Operands[0:5];
reg [4:0] alu_op[0:17];
integer index1, index2, index3;
integer read_op, read_alu;
// Instantiate the Unit Under Test (UUT)
Exec uut ... | 6.869631 |
module EXMEM (
output reg [31:0] branchAddress,
alu,
writeToMemory,
output reg [4:0] rd,
output reg [1:0] wb,
output reg regwrite,
output reg memtoreg,
output reg [2:0] mem,
output reg br,
output reg zero,
input [106:0] exeMem,
input clk
);
initial begin
branchAddr... | 7.862259 |
module EXEMEM_register (
input clk_i,
input rst_i,
input [31:0] instr_i,
input [2:0] WB_i,
input [2:0] Mem_i,
input zero_i,
input [31:0] alu_ans_i,
input [31:0] rtdata_i,
input [4:0] WBreg_i,
input [31:0] pc_add4_i,
output reg [31:0] instr_o,
output reg [2:0] WB_o,
o... | 7.298557 |
module subcircuitoMeia (
s0,
s1,
a,
b
);
output s0, s1;
input a, b;
and AND1 (s1, a, b);
xor XOR1 (s0, a, b);
endmodule
| 6.9654 |
module subcircuitoComp (
s0,
s1,
a,
b,
c
);
output s0, s1;
input a, b, c;
wire s2, s3, s4;
subcircuitoMeia SUB1 (
s2,
s3,
a,
b
);
subcircuitoMeia SUB2 (
s0,
s4,
c,
s2
);
or OR1 (s1, s3, s4);
endmodule
| 7.454893 |
module circuito (
s0,
s1,
s2,
s3,
s4,
a3,
a2,
a1,
a0,
b3,
b2,
b1,
b0
);
output s0, s1, s2, s3, s4;
input a3, a2, a1, a0, b3, b2, b1, b0;
wire s5, s6, s7;
subcircuitoMeia SUBM1 (
s0,
s5,
a0,
b0
);
subcircuitoComp SUBC1 (
s1,
... | 6.7052 |
module testcircuito;
reg a3, a2, a1, a0, b3, b2, b1, b0;
wire s0, s1, s2, s3, s4;
circuito CIRCUITO1 (
s0,
s1,
s2,
s3,
s4,
a3,
a2,
a1,
a0,
b3,
b2,
b1,
b0
);
initial begin
$display("Exemplo 01 - Bruno Rafael Nicolletti - 380752... | 6.943425 |
module subcircuitoMeia (
s0,
s1,
a,
b
);
output s0, s1;
input a, b;
wire s2;
xor XOR1 (s0, a, b);
not NOT1 (s2, a);
and AND1 (s1, s2, b);
endmodule
| 6.9654 |
module subcircuitoComp (
s0,
s1,
a,
b,
c
);
output s0, s1;
input a, b, c;
wire s2, s3, s4;
subcircuitoMeia SUB1 (
s2,
s3,
a,
b
);
subcircuitoMeia SUB2 (
s0,
s4,
s2,
c
);
or OR1 (s1, s3, s4);
endmodule
| 7.454893 |
module circuito (
s0,
s1,
s2,
s3,
a2,
a1,
a0,
b2,
b1,
b0
);
output s0, s1, s2, s3;
input a2, a1, a0, b2, b1, b0;
wire s4, s5;
subcircuitoMeia SUBM1 (
s0,
s4,
a0,
b0
);
subcircuitoComp SUBC1 (
s1,
s5,
a1,
b1,
s4
... | 6.7052 |
module testcircuito;
reg a2, a1, a0, b2, b1, b0;
wire s0, s1, s2, s3;
circuito CIRCUITO1 (
s0,
s1,
s2,
s3,
a2,
a1,
a0,
b2,
b1,
b0
);
initial begin
$display("Exemplo 02 - Bruno Rafael Nicolletti - 380752");
$display("Test Circuito Diferenca ... | 6.943425 |
module subcircuitoMeia (
s0,
s1,
a,
b
);
output s0, s1;
input a, b;
and AND1 (s1, a, b);
xor XOR1 (s0, a, b);
endmodule
| 6.9654 |
module subcircuitoComp (
s0,
s1,
a,
b,
c
);
output s0, s1;
input a, b, c;
wire s2, s3, s4;
subcircuitoMeia SUB1 (
s2,
s3,
a,
b
);
subcircuitoMeia SUB2 (
s0,
s4,
c,
s2
);
or OR1 (s1, s3, s4);
endmodule
| 7.454893 |
module circuito (
s0,
s1,
s2,
s3,
a1,
a0,
b1,
b0
);
output s0, s1, s2, s3;
input a1, a0, b1, b0;
wire s4, s5, s6, s7, s8, s9;
and AND1 (s4, a0, b0);
and AND2 (s5, a0, b1);
and AND3 (s6, a1, b0);
and AND4 (s7, a1, b1);
subcircuitoMeia SUBM1 (
s0,
s8,
0,
... | 6.7052 |
module testcircuito;
reg a1, a0, b1, b0;
wire s0, s1, s2, s3;
circuito CIRCUITO1 (
s0,
s1,
s2,
s3,
a1,
a0,
b1,
b0
);
initial begin
$display("Exemplo 03 - Bruno Rafael Nicolletti - 380752");
$display("Test Circuito Produto de 2 Binarios com 3 bits cada"... | 6.943425 |
module f4 (
output [3:0] s,
input [3:0] a,
input [3:0] b
);
// descrever por portas
endmodule
| 6.784298 |
module test_f4;
// ------------------------- definir dados
reg [3:0] x;
reg [3:0] y;
wire [3:0] z;
f4 modulo (
z,
x,
y
);
// ------------------------- parte principal
initial begin
$display("Exemplo0031 - Rafael Tadeu - 451609");
$display("Test LU's module");
x = 4'b001... | 6.629466 |
module LU (
output s,
input a,
input b,
input chave
);
wire tmp1, tmp2, notchave, tmp3, tmp4;
and AND1 (tmp1, a, b);
or OR1 (tmp2, a, b);
not NOT1 (notchave, chave);
// parte do mux
and AND2 (tmp3, tmp1, notchave);
and AND3 (tmp4, tmp2, chave);
// parte da saida
or OR2 (s, tmp3, tm... | 8.04132 |
module teste;
reg a;
reg b;
reg chave;
wire s;
LU test(s,a,b,chave);
initial begin:main
$display("Exemplo0032 - Rafael Tadeu - 451609");
$display("Test exercicio02's module");
a=0; b=0; chave=0;
$display("\nchave = 0 (operacao and) chave = 1 (operacao or)");
#1 $monitor("a = %b ... | 6.583866 |
module LU (
output s,
input a,
input b,
input chave
);
wire tmp1, tmp2, notchave, tmp3, tmp4;
and AND1 (tmp1, a, b);
or OR1 (tmp2, a, b);
nand NAND1 (tmp3, a, b);
nor NOR1 (tmp4, a, b);
not NOT1 (notchave, chave);
// parte do mux
and AND2 (tmp5, tmp1, tmp2, notchave);
and AND3 (tmp... | 8.04132 |
module teste;
reg a;
reg b;
reg chave;
wire s;
LU test(s,a,b,chave);
initial begin:main
$display("Exemplo0033 - Rafael Tadeu - 451609");
$display("Test exercicio02's module");
a=0; b=0; chave=0;
$display("\nchave = 0 (operacao and) chave = 1 (operacao or)");
#1 $monitor("a = %b ... | 6.583866 |
module LU (
output s,
input a,
input b,
input [1:0] chave
);
wire tmp1, tmp2, tmp3, tmp4, tmp5, tmp8, tmp9, tmp10, tmp11, tmp12, tmp13, tmp14, tmp15, tmp16;
or OR1 (tmp1, a, b);
nor NOR1 (tmp2, a, b);
xor XOR1 (tmp3, a, b);
xnor XNOR1 (tmp4, a, b);
not NOT1 (tmp11, chave[1]);
not NOT2 (tm... | 8.04132 |
module teste;
reg a;
reg b;
reg [1:0]chave;
wire s;
LU test(s,a,b,chave);
initial begin:main
$display("Exemplo0034 - Rafael Tadeu - 451609");
$display("Test exercicio02's module");
a=0; b=0; chave[0]=0; chave[1]=0;
$display("\nchave 00 - XNOR , chave 01 - XOR , chave 10 - NOR , ch... | 6.583866 |
module LU (
output s,
input a,
input b,
input [2:0] chave
);
wire s1, s2, s3, s4, s5, s6, s7, s8;
wire tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7, tmp8;
wire notchave0, notchave1, notchave2;
not NOT1 (s1, a);
or OR1 (s2, a, b);
nor NOR1 (s3, a, b);
and AND1 (s4, a, b);
nand NAND1 (s5, a,... | 8.04132 |
module teste;
reg a;
reg b;
reg [2:0]chave;
wire s;
LU test(s,a,b,chave);
initial begin:main
$display("Exemplo0035 - Rafael Tadeu - 451609");
$display("Test exercicio02's module");
a=0; b=0; chave[0]=0; chave[1]=0; chave[2]=0;
$display("\nchave 000 - NOT , chave 001 - OR , chave ... | 6.583866 |
module LU (
output s0,
s1,
input a,
input b
);
wire s0, s1;
xnor XNOR1 (s0, a, b);
not NOT1 (s1, s0);
endmodule
| 8.04132 |
module LU (
output s0,
s1,
s2,
input a,
input b
);
wire s0, s1, s2;
wire nota, notb;
xnor XNOR1 (s0, a, b);
not NOT1 (nota, a);
not NOT2 (notb, b);
and AND1 (s1, a, notb);
and AND2 (s2, nota, b);
endmodule
| 8.04132 |
module buffer (
output s,
input p
);
assign s = p; // criar vinculo permanente
// (dependencia)
endmodule
| 6.861394 |
module testbuffer;
// ------------------------- dados locais
reg a; // definir registrador
// (variavel independente)
wire s; // definir conexao (fio)
// (variavel dependente )
// ------------------------- instancia
buffer BF1 (
s,
a
);
// ------------------------- preparacao
initial ... | 7.153545 |
module buffer (
output s,
input p
);
assign s = p; // criar vinculo permanente (dependencia)
endmodule
| 6.861394 |
module testbuffer;
//dados locais
reg a; //definir registrador (variavel independente)
wire s; //definir conexao (fio) (variavel dependente)
//instancia
buffer BF1 (
s,
a
);
//preparacao
initial begin : start
a = 0; //valor inicial
end
//parte principal
initial begin : main... | 7.153545 |
module buffer (
output s,
input p
);
assign s = p; // criar vinculo permanente
// (dependencia)
endmodule
| 6.861394 |
module testbuffer;
// ------------------------- dados locais
reg a; // definir registrador
// (variavel independente)
wire s; // definir conexao (fio)
// (variavel dependente )
// ------------------------- instancia
buffer BF1 (
s,
a
);
// ------------------------- preparacao
initial... | 7.153545 |
module buffer (
output s,
input p
);
assign s = p; // criar vinculo permanente
// (dependencia)
endmodule
| 6.861394 |
module testbuffer;
// ------------------------- dados locais
reg a; // definir registrador
// (variavel independente)
wire s; // definir conexao (fio)
// (variavel dependente )
// ------------------------- instancia
buffer BF1 (
s,
a
);
// ------------------------- preparacao
initial... | 7.153545 |
module testeorgate;
// ----------------------- dados locais
reg a, b, c; //definir registrador
//(variavel independente)
wire s; //definir conexao(fio)
//(variavel dependente)
// --------------- instancia
orgate OR1 (
s,
a,
b,
c
);
// --------------- preparacao
initial begi... | 7.079751 |
module test_base_01;
// ------------------------- definir dados
reg [2:0] a;
reg [3:0] b;
reg [4:0] c;
reg [4:0] d;
// ------------------------- parte principal
initial begin
$display("Exemplo0011 - Julio Miranda Machado");
$display("Test number system");
a = 5;
b = 10;
c = 15;
d... | 6.932753 |
module notgate (
output s,
input p
);
assign s = ~p;
endmodule
| 7.575943 |
module testnotgate;
//dados locais
reg a; //definir registrador (variavel independente)
wire s; //definir conexao (fio) (variavel dependente)
//instancia
notgate NOT1 (
s,
a
);
//preparacao
initial begin : start
a = 0; //valor inicial
end
//parte principal
initial begin
... | 7.480879 |
module notgate (
output s,
input p
);
assign s = ~p;
endmodule
| 7.575943 |
module testnotgate;
// ------------------------- dados locais
reg a; // definir registrador
// (variavel independente)
wire s; // definir conexao (fio)
// (variavel dependente )
// ------------------------- instancia
notgate NOT1 (
s,
a
);
// ------------------------- preparacao
init... | 7.480879 |
module notgate (
output s,
input p
);
assign s = ~p;
endmodule
| 7.575943 |
module testnotgate;
// ------------------------- dados locais
reg a; // definir registrador
// (variavel independente)
wire s; // definir conexao (fio)
// (variavel dependente )
// ------------------------- instancia
notgate NOT1 (
s,
a
);
// ------------------------- preparacao
init... | 7.480879 |
module testandgate;
//dados locais
reg a, b; //definir registradores
wire s; //definir conexao (fio)
//instancia
andgate AND1 (
s,
a,
b
);
//preparacao
initial begin : start
a = 0;
b = 0; //atribuicao simultanea dos valores iniciais
end
//parte principal
initial be... | 6.553783 |
module testandgate;
// ------------------------- dados locais
reg a, b; // definir registradores
wire s; // definir conexao (fio)
// ------------------------- instancia
andgate AND1 (
s,
a,
b
);
// ------------------------- preparacao
initial begin : start
// atribuicao simultane... | 6.553783 |
module testandgate;
// ------------------------- dados locais
reg a, b; // definir registradores
wire s; // definir conexao (fio)
// ------------------------- instancia
andgate AND1 (
s,
a,
b
);
// ------------------------- preparacao
initial begin : start
// atribuicao simultane... | 6.553783 |
module testandgate;
// ------------------------- dados locais
reg a, b; // definir registradores
wire s; // definir conexao (fio)
// ------------------------- instancia
andgate AND1 (
s,
a,
b
);
// ------------------------- preparacao
initial begin : start
// atribuicao simultane... | 6.553783 |
module xorgate (
output [0:3] s,
input [0:3] p,
input [0:3] q
);
assign s = p ^ q;
endmodule
| 7.421731 |
module testxorgate;
//dados locais
reg [0:3] a, b; //definir registradores
wire [0:3] s; //definir conexao (fio)
//instancia
xorgate XOR1 (
s,
a,
b
);
//preparacao
initial begin : start
a = 4'b0011; //4 valores binarios
b = 4'b0101; //4 valores binarios
end
//parte p... | 6.716539 |
module xorgate (
output [0:3] s,
input [0:3] p,
input [0:3] q
);
assign s = p ^ q;
endmodule
| 7.421731 |
module testxorgate;
// ------------------------- dados locais
reg [0:3] a, b; // definir registrador
wire [0:3] s; // definir conexao (fio)
// ------------------------- instancia
xorgate XOR1 (
s,
a,
b
);
// ------------------------- preparacao
initial begin : start
a = 4'b0011; ... | 6.716539 |
module xorgate (
output [0:3] s,
input [0:3] p,
input [0:3] q
);
assign s = p ^ q;
endmodule
| 7.421731 |
module testxorgate;
// ------------------------- dados locais
reg [0:3] a, b; // definir registrador
wire [0:3] s; // definir conexao (fio)
// ------------------------- instancia
xorgate XOR1 (
s,
a,
b
); // ------------------------- preparacao
initial begin : start
a = 4'b0011; ... | 6.716539 |
module nandgate (
output s,
input p,
input q
);
assign s = ~(p & q);
endmodule
| 7.298658 |
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