code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module testnorgate;
// ------------------------- dados locais
reg a, b; // definir registradores
wire s; // definir conexao (fio)
// ------------------------- instancia
norgate NOR1 (
s,
a,
b
);
// ------------------------- preparacao
initial begin : start
// atribuicao simultane... | 6.695863 |
module xnorgate (
output s,
input p,
q
);
assign s = ~(p ^ q);
endmodule
| 6.74222 |
module testxnorgate;
// ------------------------- dados locais
reg a, b; // definir registradores
wire s; // definir conexao (fio)
// ------------------------- instancia
xnorgate XNOR1 (
s,
a,
b
);
// ------------------------- preparacao
initial begin : start
// atribuicao simult... | 7.028584 |
module nandgate (
output s,
input p,
input q
);
assign s = ~p | ~q; //nand por de morgan
endmodule
| 7.298658 |
module buffer (
output s,
input p
);
assign s = p; // criar vinculo permanente
// (dependencia)
endmodule
| 6.861394 |
module testbuffer;
// ------------------------- dados locais
reg a; // definir registrador
// (variavel independente)
wire s; // definir conexao (fio)
// (variavel dependente )
// ------------------------- instancia
buffer BF1 (
s,
a
);
// ------------------------- preparacao
i... | 7.153545 |
module testnorgate;
// ------------------------- dados locais
reg a, b; // definir registradores
wire s; // definir conexao (fio)
// ------------------------- instancia
norgate NOR1 (
s,
a,
b
);
// ------------------------- preparacao
initial begin : start
// atribuicao simultane... | 6.695863 |
module test_base_01;
// ------------------------- definir dados
reg [2:0] a;
reg [3:0] b;
reg [4:0] c;
reg [4:0] d;
// ------------------------- parte principal
initial begin
$display("Exemplo0011 - xxx yyy zzz - 999999");
$display("Test number system");
a = 5;
b = 10;
c = 15;
d = ... | 6.932753 |
module test_base_01;
// ------------------------- definir dados
reg [2:0] a;
reg [3:0] b;
reg [4:0] c;
reg [4:0] d;
// ------------------------- parte principal
initial begin
$display("Exemplo0012 - xxx yyy zzz - 999999");
$display("Test number system");
a = 5;
b = 10;
c = 15;
d = ... | 6.932753 |
module test_base_01;
// ------------------------- definir dados
reg [2:0] a;
reg [3:0] b;
reg [4:0] c;
reg [4:0] d;
// ------------------------- parte principal
initial begin
$display("Exemplo0013 - xxx yyy zzz - 999999");
$display("Test number system");
a = 5;
b = 10;
c = 15;
d = ... | 6.932753 |
module test_base_01;
// ------------------------- definir dados
reg [2:0] a;
reg [3:0] b;
reg [4:0] c;
reg [4:0] d;
// ------------------------- parte principal
initial begin
$display("Exemplo0014 - xxx yyy zzz - 999999");
$display("Test number system");
a = 5;
b = 10;
c = 15;
d = ... | 6.932753 |
module test_base_01;
// ------------------------- definir dados
reg [2:0] a;
reg [3:0] b;
reg [4:0] c;
reg [4:0] d;
// ------------------------- parte principal
initial begin
$display("Exemplo0014 - Luiz Marques de Oliveira - 417138");
$display("Test number system");
a = 5;
b = 10;
c... | 6.932753 |
module test_base_01;
// ------------------------- definir dados
reg [2:0] a;
reg [3:0] b;
reg [4:0] c;
reg [4:0] d;
// ------------------------- parte principal
initial begin
$display("Exemplo0015 - Marden Santos Batista- 388613");
$display("Test number system");
a = 5;
b = 10;
c = ... | 6.932753 |
module test_base_01;
// ------------------------- definir dados
reg [2:0] a;
reg [3:0] b;
reg [4:0] c;
reg [4:0] d;
// ------------------------- parte principal
initial begin
$display("Exemplo0015 - xxx yyy zzz - 999999");
$display("Test number system");
a = 5;
b = 10;
c = 15;
d = ... | 6.932753 |
module test_base_01;
// ------------------------- definir dados
reg [2:0] a;
reg [3:0] b;
reg [4:0] c;
reg [4:0] d;
// ------------------------- parte principal
initial begin
$display("Exemplo0015 - Raphael Quintao - 445171");
$display("Test number system");
a = 5;
b = 10;
c = 15;
... | 6.932753 |
module nandgate (
output s,
input m,
n
);
assign s = ~(m & n);
endmodule
| 7.298658 |
module test_base_01;
//-------------------------definir dados
reg [4:0] a;
reg [5:0] b;
reg [2:0] c;
reg [3:0] d;
reg [4:0] e;
//-------------------------parte principal
initial begin
$display("Exemplo0016 - Wellington Santos Correa - 472047");
$display("Test number system");
a = 3 + 14;... | 6.932753 |
module test_base_01;
//-------------------------definir dados
reg [6:0] a;
reg [5:0] b;
reg [9:0] c;
reg [6:0] d;
reg [9:0] e;
//-------------------------parte principal
initial begin
$display("Exemplo0017 - Wellington Santos Correa - 472047");
$display("Test number system");
a = 6'b10... | 6.932753 |
module test_base_01;
// ------------------------- definir dados
reg [ 5:0] a;
reg [ 4:0] b;
reg [ 6:0] c;
reg [ 5:0] d;
reg [ 9:0] e;
reg [10:0] f;
reg [ 8:0] g;
reg [ 4:0] h;
// ------------------------- parte principal
initial begin
$display("Exemplo0017 - Lucas Cardoso - 441694");
a... | 6.932753 |
module test_base_01;
//-------------------------definir dados
reg [6:0] a;
reg [5:0] b;
reg [5:0] c;
reg [6:0] d;
reg [6:0] e;
//-------------------------parte principal
initial begin
$display("Exemplo0018 - Wellington Santos Correa - 472047");
$display("Test number system");
a = ~7'b101... | 6.932753 |
module test_base_01;
//-------------------------definir dados
reg [7:0] a;
reg [6:0] b;
reg [5:0] c;
reg [4:0] d;
reg [6:0] e;
//-------------------------parte principal
initial begin
$display("Exemplo0019 - Wellington Santos Correa - 472047");
$display("Test number system");
a = ~7'b101... | 6.932753 |
module notgate (
output s,
input p
);
assign s = ~p;
endmodule
| 7.575943 |
module testnotgate;
// ------------------------- dados locais
reg a; // definir registrador
// (variavel independente)
wire s; // definir conexao (fio)
// (variavel dependente )
// ------------------------- instancia
notgate NOT1 (
s,
a
);
// ------------------------- preparacao
... | 7.480879 |
module test_base_01;
//-------------------------definir dados
reg [7:0] a;
reg [7:0] b;
reg [7:0] c;
reg [7:0] d;
reg [7:0] e;
//-------------------------parte principal
initial begin
$display("Exemplo0020 - Wellington Santos Correa - 472047");
$display("Test number system");
a = 6'b1010... | 6.932753 |
module test_base_01;
// ---------------- definir dados
reg [2:0] a;
reg [3:0] b;
reg [4:0] c;
reg [4:0] d;
// --------------- parte principal
initial begin
a = 0;
b = 0;
c = 0;
end
// --------------- parte principal
initial begin : main
$display("Exemplo 0021 - Izabela Caldeira Bo... | 6.932753 |
module HA (
output s,
output s1,
input a,
input b
);
xor (s, a, b);
and (s1, a, b);
endmodule
| 8.105131 |
module FA (
output s,
output carry,
input a,
input b,
input carryIn
);
wire w1, w0, w3;
HA h1 (
w1,
w0,
a,
b
);
HA h2 (
s,
w3,
carryIn,
w1
);
or (carry, w3, w0);
endmodule
| 7.885402 |
module XorEntrada (
output s,
input a,
input b
);
xor (s, a, b);
endmodule
| 7.915596 |
module Somando (
output [5:0] soma,
input [5:0] a,
input [5:0] b,
input carryIn
);
// ------------------------- definir dados
XorEntrada x1 (
bb,
b[0],
carryIn
);
XorEntrada x2 (
bc,
b[1],
carryIn
);
XorEntrada x3 (
bd,
b[2],
carryIn
... | 9.080118 |
module test_fullAdder;
// ------------------------- definir dados
reg [5:0] x;
reg [5:0] y;
reg C;
wire [5:0] soma;
Somando s1 (
soma,
x,
y,
C
);
// ------------------------- parte principal
initial begin
$display("Exemplo0022 - Felipe Ferreira Andrade do Carmo- 427402... | 7.258892 |
module test_base_01;
// ---------------- definir dados
reg [2:0] a;
reg [3:0] b;
reg [4:0] c;
reg [4:0] d;
// --------------- parte principal
initial begin : main
$display("Exemplo 0022 - Izabela Caldeira Borges - 463243");
$display("Test number system");
a = 5;
b = 10;
c = 15;
d ... | 6.932753 |
module S1 (
output soma,
output co,
input ci,
input a,
input b
);
wire xora, anda, andb;
xor X1 (xora, ci, a);
xor X2 (soma, xora, b);
and A1 (anda, xora, b);
and A2 (andb, ci, a);
or O1 (co, anda, andb);
endmodule
| 8.289865 |
module teste;
wire [2:0] subtracao;
wire co;
reg [2:0] entradaA, entradaB;
reg ci;
S3 SA (
subtracao,
co,
ci,
entradaA,
entradaB
);
initial begin
$display("Subtrator");
#1 entradaA = 3'b000;
entradaB = 3'b000;
#1 $monitor("A=%3b B=%3b RESULTADO=%3b", entradaA,... | 7.490834 |
module Sub1 (
output sub,
output co,
input ci,
input a,
input b
);
wire xora, anda, andb, notxora, nota;
xor X1 (xora, a, b);
xor X2 (sub, ci, xora);
not N1 (notxora, xora);
and A1 (anda, ci, notxora);
not N2 (nota, a);
and A2 (andb, b, nota);
or O1 (co, anda, andb);
endmodule
| 8.052205 |
module teste;
wire [2:0] subtracao;
wire co;
reg [2:0] entradaA, entradaB;
reg ci;
Sub3 SA (
subtracao,
co,
ci,
entradaA,
entradaB
);
initial begin
$display("Subtrator");
#1 entradaA = 3'b000;
entradaB = 3'b000;
ci = 1'b0;
#1 $monitor("A=%3b B=%3b RESULTAD... | 7.490834 |
module test_base_01;
// ---------------- definir dados
reg [2:0] a;
reg [3:0] b;
reg [4:0] c;
reg [4:0] d;
// --------------- parte principal
initial begin : main
$display("Exemplo 0023 - Izabela Caldeira Borges - 463243");
$display("Test number system");
a = 5;
b = 10;
c = 15;
d ... | 6.932753 |
module test_base_01;
// ---------------- definir dados
reg [2:0] a;
reg [3:0] b;
reg [4:0] c;
reg [4:0] d;
// --------------- parte principal
initial begin : main
$display("Exemplo 0024 - Izabela Caldeira Borges - 463243");
$display("Test number system");
a = 5;
b = 10;
c = 15;
d ... | 6.932753 |
module test_base_01;
// ---------------- definir dados
reg [2:0] a;
reg [3:0] b;
reg [4:0] c;
reg [4:0] d;
// --------------- parte principal
initial begin : main
$display("Exemplo 0025 - Izabela Caldeira Borges - 463243");
$display("Test number system");
a = 5;
b = 10;
c = 15;
d ... | 6.932753 |
module test_base_01;
// ---------------- definir dados
reg [4:0] a;
reg [4:0] b;
reg [2:0] c;
reg [3:0] d;
reg [4:0] e;
// --------------- parte principal
initial begin : main
$display("Exemplo 0026 - Izabela Caldeira Borges - 463243");
$display("Test number system");
a = 3 + 14;
b = 3... | 6.932753 |
module test_base_01;
// ---------------- definir dados
reg [6:0] a;
reg [5:0] b;
reg [3:0] c;
reg [6:0] d;
reg [5:0] e;
// --------------- parte principal
initial begin : main
$display("Exemplo 0027 - Izabela Caldeira Borges - 463243");
$display("Test number system");
a = 'b100110 + 'b1101... | 6.932753 |
module test_base_01;
// ---------------- definir dados
reg [6:0] a;
reg [5:0] b;
reg [2:0] c;
reg [6:0] d;
reg [3:0] e;
// --------------- parte principal
initial begin : main
$display("Exemplo 0028 - Izabela Caldeira Borges - 463243");
$display("Test number system");
a = ~'b101010 + 1;
... | 6.932753 |
module test_base_01;
// ---------------- definir dados
reg [7:0] a;
reg [6:0] b;
reg [5:0] c;
reg [4:0] d;
reg [7:0] e;
// --------------- parte principal
initial begin : main
$display("Exemplo 0029 - Izabela Caldeira Borges - 463243");
$display("Test number system");
a = 'b101011 + ~'b100... | 6.932753 |
module test_base_01;
// ---------------- definir dados
reg [5:0] a;
reg [2:0] b;
reg [4:0] c;
reg [0:0] d;
reg [3:0] e;
// --------------- parte principal
initial begin : main
$display("Exemplo 0030 - Izabela Caldeira Borges - 463243");
$display("Test number system");
a = 'b101011 + (~'b10... | 6.932753 |
module f4 (
output [3:0] s,
output [3:0] g,
input [3:0] a,
input [3:0] b
);
wire exe31[0:1];
and AND1 (exe31[0], a, b);
or OR1 (exe31[1], a, b);
assign s = exe31[0];
assign g = exe31[1];
// descrever por portas
endmodule
| 6.784298 |
module test_f4;
// ------------------------- definir dados
reg [3:0] x;
reg [3:0] y;
wire [3:0] z;
f4 modulo (
z,
x,
y
);
// ------------------------- parte principal
initial begin
$display("Exemplo0031 - Adamo Ludwig - 473319");
$display("Test LU's module");
x = 4'b0... | 6.629466 |
module fand4 (
output [3:0] s,
input [3:0] a,
input [3:0] b
);
and AND1 (s[0], a[0], b[0]);
and AND2 (s[1], a[1], b[1]);
and AND3 (s[2], a[2], b[2]);
and AND4 (s[3], a[3], b[3]);
endmodule
| 6.697017 |
module test_f4;
// ------------------------- definir dados
reg [3:0] x;
reg [3:0] y;
wire [3:0] w;
wire [3:0] z;
fand4 modulo1 (
w,
x,
y
);
for4 modulo2 (
z,
x,
y
);
initial begin : start
x = 4'b0000;
y = 4'b0000;
end
// ------------------------- ... | 6.629466 |
module f4 (
output [3:0] s,
output [3:0] s1,
input [3:0] a,
input [3:0] b
);
// ------------------------- descrever por portas
// operacoes logicas bit a bit
and AND1 (s[0], a[0], b[0]);
and AND2 (s[1], a[1], b[1]);
and AND3 (s[2], a[2], b[2]);
and AND4 (s[3], a[3], b[3]);
or OR1 (s1[0... | 6.784298 |
module test_f4;
// ------------------------- definir dados
reg [3:0] x;
reg [3:0] y;
wire [3:0] z;
wire [3:0] z1;
f4 modulo (
z,
z1,
x,
y
);
// ------------------------- parte principal
initial begin
$display("Exemplo 0031 - ANA CRISTINA - 427385");
$display("Test... | 6.629466 |
module f4 (
output [1:0] s,
input [1:0] a,
input [1:0] b,
input f
);
wire [1:0] saida_and;
wire [1:0] saida_or;
and AND1 (saida_and[0], a[0], b[0]);
and AND2 (saida_and[1], a[1], b[1]);
or OR1 (saida_or[0], a[0], b[0]);
or OR2 (saida_or[1], a[1], b[1]);
selecionador SEL1 (
s,
... | 6.784298 |
module f4 (
output [3:0] s,
input [1:0] a,
input [1:0] b,
input f
);
wire [1:0] saida_and;
wire [1:0] saida_or;
wire [1:0] saida_nand;
wire [1:0] saida_nor;
and AND1 (saida_and[0], a[0], b[0]);
and AND2 (saida_and[1], a[1], b[1]);
or OR1 (saida_or[0], a[0], b[0]);
or OR2 (saida_or[1],... | 6.784298 |
module test_f4;
reg [1:0] x, y;
reg flag;
wire [3:0] z;
f4 modulo (
z,
x,
y,
flag
);
// -- parte principal
initial begin
$display("Exemplo 0033 - ANA CRISTINA - 427385");
$display("Test LU's module");
$display("Legenda da chave: 0-OR/AND 1-NOR/NAND \n");
#1 x = ... | 6.878203 |
module f4 (
output s,
input a,
input b,
input c1,
input c2
);
wire temp[0:8];
or OR1 (temp[0], a, b);
nor NOR1 (temp[1], a, b);
xor XOR1 (temp[2], a, b);
xnor XNOR1 (temp[3], a, b);
and AND1 (temp[4], ~c1, ~c2, temp[0]);
and AND2 (temp[5], ~c1, c2, temp[1]);
and AND3 (temp[6],... | 6.784298 |
module test_f4;
// ------------------------- definir dados
reg a;
reg b;
reg c1;
reg c2;
wire s;
f4 modulo (
s,
a,
b,
c1,
c2
);
initial begin : start
a = 0;
b = 0;
c1 = 0;
c2 = 0;
end
// ------------------------- parte principal
initial b... | 6.616349 |
module f4 (
output [1:0] s,
input [1:0] a,
input [1:0] b,
input flag1,
input flag2
);
wire [1:0] saida_xor, saida_or, saida_xnor, saida_nor;
wire [1:0] s1, s2;
xor XOR1 (saida_xor[0], a[0], b[0]);
xor XOR2 (saida_xor[1], a[1], b[1]);
or OR1 (saida_or[0], a[0], b[0]);
or OR2 (saida_or[1... | 6.784298 |
module S1 (
output s,
output co,
input ci,
input a,
input b
);
wire xora, anda, andb;
xor X1 (xora, a, b);
and A1 (anda, a, b);
xor X2 (s, xora, ci);
and A2 (andb, xora, ci);
or O1 (co, anda, andb);
endmodule
| 8.289865 |
module SomaSub (
output [2:0] s,
output co,
output over,
output flag,
output [2:0] sinal,
input ci,
input [2:0] a,
input [2:0] b
);
wire co0, co1;
wire xora, xorb, xorc;
xor X1 (xora, ci, b[0]);
xor X2 (xorb, ci, b[1]);
xor X3 (xorc, ci, b[2]);
S1 SA (
s[0],
co0,
... | 8.63255 |
module comparador (
output s1,
output s2,
output s3,
input [2:0] a,
input [2:0] b
);
wire [2:0] sinal;
wire zero;
wire [2:0] resposta;
SomaSub SS (
resposta,
co,
over,
zero,
sinal,
1'b1,
a,
b
);
wire notA, notB, notS, notFlag;
not N1 (not... | 7.425908 |
module teste;
wire s1, s2, s3;
reg [2:0] entradaA, entradaB;
comparador C (
s1,
s2,
s3,
entradaA,
entradaB
);
initial begin
#1 entradaA = 3'b100;
entradaB = 3'b000;
#1 $display("Comparador\n(100)A>B, (010)A=B, (001)A<B");
$monitor("A=%3b B=%3b S=%b%b%b", entradaA,... | 7.490834 |
module f4 (
output s1,
output s2,
output s3,
output s4,
output s5,
output s6,
output s7,
output s8,
output [7:0] sFim,
input a,
input b
);
// Parte And/Or
assign s1 = a & b;
assign s2 = a | b;
// Parte Nand/Nor
assign s3 = ~(a & b);
assign s4 = ~(a | b);
// ... | 6.784298 |
module test_f4;
// ------------------------- definir dados
reg x;
reg y;
wire z1;
wire z2;
wire z3;
wire z4;
wire z5;
wire z6;
wire z7;
wire z8;
wire [7:0] zFim;
f4 modulo (
z1,
z2,
z3,
z4,
z5,
z6,
z7,
z8,
zFim,
x,
y
);
/... | 6.629466 |
module f4 (
output saida,
input x,
input y,
input [2:0] flag
);
wire saida_not1, saida_not2, saida_or, saida_nor, saida_and, saida_nand, saida_xor, saida_xnor;
not NOT1 (saida_not1, x);
not NOT2 (saida_not2, y);
or OR1 (saida_or, x, y);
nor NOR1 (saida_nor, x, y);
and AND1 (saida_and, x,... | 6.784298 |
module Comparador (
output s,
input a,
input b
);
wire s0, s1;
wire tmp0, tmp1;
not NOT1 (s0, a);
not NOT2 (s1, b);
and AND1 (tmp0, s0, b);
and AND2 (tmp1, a, s1);
or OR1 (s, tmp0, tmp1);
endmodule
| 8.21073 |
module Comparador (
output s,
input a,
input b
);
xor XOR1 (s, a, b);
endmodule
| 8.21073 |
module f4 (
output [3:0] saida,
input [3:0] a,
input [3:0] b,
input f
);
wire [3:0] saida_xor, saida_xnor;
xor XOR1 (saida_xor[0], a[0], b[0]);
xor XOR2 (saida_xor[1], a[1], b[1]);
xor XOR3 (saida_xor[2], a[2], b[2]);
xor XOR4 (saida_xor[3], a[3], b[3]);
xnor XNOR1 (saida_xnor[0], a[0], b... | 6.784298 |
module Comparador (
output s0,
output s1,
output s2,
input a,
input b
);
wire notb;
wire nota;
xnor XNOR1 (s0, a, b);
not NOT1 (notb, b);
and AND1 (s1, notb, a);
not NOT2 (nota, a);
and AND2 (s2, nota, b);
endmodule
| 8.21073 |
module f4 (
output [3:0] saida,
input [3:0] entrada1,
input [3:0] entrada2,
input chave
);
wire [3:0] saida_menor;
wire [3:0] saida_maior;
or OR1 (saida_menor[0], ~entrada1[0], entrada2[0]);
or OR2 (saida_menor[1], ~entrada1[1], entrada2[1]);
or OR3 (saida_menor[2], ~entrada1[2], entrada2[2]... | 6.784298 |
module compigual (
output s,
input a,
input b,
input c
);
// descrever por portas
wire h, g, d, f;
xnor XNOR1 (h, c, b);
xnor XNOR2 (g, c, a);
xnor XNOR3 (d, a, b);
and AND1 (f, h, g);
and AND2 (s, d, f);
endmodule
| 6.688785 |
module test_compigual;
// ------------------------- definir dados
reg x;
reg y;
reg k;
wire comp;
compigual modulo (
comp,
x,
y,
k
);
initial begin : start
x = 1;
y = 0;
k = 0;
end
// ------------------------- parte principal
initial begin
$display("Ex... | 7.472686 |
module compde2 (
output s,
input a,
input b,
input c
);
// descrever por portas
wire h, g, d, f;
xor XOR1 (h, c, b);
xor XOR2 (g, c, a);
xor XOR3 (d, a, b);
or OR1 (f, h, g);
or OR2 (s, d, f);
endmodule
| 7.721964 |
module EXERCICIO1;
// ------------------------- definir dados
reg [4:0] a;
reg [4:0] b;
reg [3:0] c;
reg [3:0] d;
reg [3:0] e;
// ------------------------- parte principal
initial begin
$display("\nExercicio0031 - Lucas Cassiano Ferraz Paolilo");
$display("Matricula: 420125");
a = 2 + 14;
... | 7.831328 |
module EXERCICIO3;
// ------------------------- definir dados
reg [5:0] a;
reg [5:0] b;
reg [3:0] c;
reg [4:0] d;
reg [3:0] e;
// ------------------------- parte principal
initial begin
$display("\nExercicio0033 - Lucas Cassiano Ferraz Paolilo");
$display("Matricula: 420125");
a = 6'b10011... | 7.037054 |
module EXERCICIO4;
// ------------------------- definir dados
reg [7:0] a;
reg [6:0] b;
reg [5:0] c;
reg [4:0] d;
reg [3:0] e;
// ------------------------- parte principal
initial begin
$display("\nExercicio0034 -Lucas Cassiano Ferraz Paolilo");
$display("Matricula: 420125");
a = 8'b110101... | 7.257924 |
module EXERCICIO5;
// ------------------------- definir dados
reg [7:0] a;
reg [6:0] b;
reg [5:0] c;
reg [4:0] d;
reg [3:0] e;
// ------------------------- parte principal
initial begin
$display("\nExercicio0035 - Lucas Cassiano Ferraz Paolilo");
$display("Matricula: 420125");
a = 8'b10001... | 7.758722 |
module EXERCICIO6;
// ------------------------- definir dados
reg [7:0] a;
wire [7:0] ac;
wire [7:0] ac2;
assign ac = ~a;
assign ac2 = ac + 1;
// ------------------------- parte principal
initial begin
$display("\nExercicio0036 - Lucas Cassiano Ferraz Paolillo");
$display("Matricula: 420125"... | 7.232675 |
module comparar (
output s,
input [3:0] a,
input [3:0] b
);
// descrever por portas
wire s0;
wire s1;
wire s2;
wire s3;
xnor XNOR1 (s0, a[0], b[0]);
xnor XNOR2 (s1, a[1], b[1]);
xnor XNOR3 (s2, a[2], b[2]);
xnor XNOR3 (s3, a[3], b[3]);
and AND1 (s, s0, s1, s2, s3);
// descrever p... | 6.646357 |
module test_comparar;
// ------------------------- definir dados
reg [3:0] x;
reg [3:0] y;
wire comp;
comparar modulo (
comp,
x,
y
);
// ------------------------- parte principal
initial begin
$display("Exemplo00040 - Flavio Andrade Amaral Motta- 392001");
$display("Test ALU... | 8.247729 |
module Exemplo0042;
wire clock;
clock clk (clock);
reg p;
wire p1, t1;
pulse pulse1 (
p1,
clock
);
trigger trigger1 (
t1,
p,
clock
);
initial begin
p = 1'b0;
end
initial begin
$dumpfile("Exemplo0042.vcd");
$dumpvars(1, clock, p1, p, t1);
#060 p = 1'b1;... | 6.608834 |
module pulse2 (
signal,
clock
);
input clock;
output signal;
reg signal;
initial begin
signal = 1'b0;
end
always @(posedge clock) begin
signal = 1'b1;
#5 signal = 1'b0;
end
endmodule
| 6.524618 |
module pulse3 (
signal,
clock
);
input clock;
output signal;
reg signal;
initial begin
signal = 1'b0;
end
always @(negedge clock) begin
signal = 1'b1;
#15 signal = 1'b0;
#15 signal = 1'b1;
end
endmodule
| 6.545395 |
module Exemplo0043;
wire clock;
clock clk (clock);
wire p1, p2, p3, p4;
pulse1 pls1 (
p1,
clock
);
pulse2 pls2 (
p2,
clock
);
pulse3 pls3 (
p3,
clock
);
pulse4 pls4 (
p4,
clock
);
initial begin
$dumpfile("Exemplo0043.vcd");
$dumpvars(1, clo... | 6.51954 |
module Exemplo0044;
wire clock;
clock clk (clock);
wire p;
pulse3fk p3fk (
p,
clock
);
initial begin
$dumpfile("Exemplo0044.vcd");
$dumpvars(1, clock, p);
#480 $finish;
end
endmodule
| 6.799566 |
module pulseMfk (
signal,
clock
);
input clock;
output signal;
reg signal;
initial begin
signal = 1'b0;
end
always @(posedge clock) begin
signal = 1'b1;
#24 signal = 1'b0;
#24 signal = 1'b0;
end
endmodule
| 6.999873 |
module Exemplo0043;
wire clock;
clock clk (clock);
wire p1;
pulse1 pls1 (
p1,
clock
);
initial begin
$dumpfile(" Exemplo0043.vcd");
$dumpvars(1, clock, p1);
#480 $finish;
end
endmodule
| 6.51954 |
module pulse5 (
signal,
clock
);
input clock;
output signal;
reg signal;
initial begin
signal = 1'b0;
end
always @(posedge clock) begin
signal = 1'b1;
#5 signal = 1'b0;
#5 signal = 1'b1;
#5 signal = 1'b0;
#5 signal = 1'b1;
#5 signal = 1'b0;
#5 signal = 1'b1;
#5 si... | 6.552822 |
module pulse5 (
signal,
clock
);
input clock;
output signal;
reg signal;
initial begin
signal = 1'b0;
end
always @(negedge clock) begin
signal = 1'b1;
#5 signal = 1'b0;
#5 signal = 1'b1;
#5 signal = 1'b0;
#5 signal = 1'b1;
#5 signal = 1'b0;
#5 signal = 1'b1;
#5 si... | 6.552822 |
module halfAdder (
s0,
s1,
a,
b
);
input a, b;
output s0, s1;
xor XOR1 (s0, a, b);
and AND1 (s1, a, b);
endmodule
| 7.256462 |
module fullAdder4 (
output [3:0] s,
output carryOut,
input [3:0] a,
input [3:0] b
);
// descrever por portas
wire vaiUm;
wire vaiUm1;
wire vaiUm2;
halfAdder HA1 (
s[0],
vaiUm,
a[0],
b[0]
);
fullAdder FA1 (
s[1],
vaiUm1,
a[1],
b[1],
... | 7.492542 |
module halfSub (
s0,
s1,
a,
b
);
input a, b;
output s0, s1;
xor XOR1 (s0, a, b);
and AND1 (s1, ~a, b);
endmodule
| 6.504659 |
module fullSub (
s0,
s1,
a,
b,
c
);
input a, b, c;
output s0, s1;
wire q0, q1, q2;
halfSub HS1 (
q0,
q1,
a,
b
);
halfSub HS2 (
s0,
q2,
q0,
c
);
or OR1 (s1, q2, q1);
endmodule
| 6.562172 |
module fullSub4 (
output [4:0] s,
output carryOut,
input [3:0] a,
input [3:0] b
);
// descrever por portas
wire vemUm;
wire vemUm1;
wire vemUm2;
halfSub HS (
s[0],
vemUm,
a[0],
b[0]
);
fullSub FS1 (
s[1],
vemUm1,
a[1],
b[1],
vemUm
... | 7.71966 |
module xorgate (
output [0:3] s,
input [0:3] p,
input [0:3] q
);
assign s = p ^ q;
endmodule
| 7.421731 |
module testxorgate;
// ------------------------- dados locais
reg [0:3] a, b; // definir registrador
wire [0:3] s; // definir conexao (fio)
// ------------------------- instancia
xorgate XOR1 (
s,
a,
b
);
// ------------------------- preparacao
initial begin : start
a = 4'b0... | 6.716539 |
module Exemplo0051;
reg clk, reset, x;
wire m1, m2;
mealy1101 mealy1 (
m1,
x,
clk,
reset
);
moore1101 moore1 (
m2,
x,
clk,
reset
);
initial begin
$display("Time X Mealy Moore");
//initial values
clk = 1;
reset = 0;
x = 0;
//input... | 7.137628 |
module Exemplo0052;
reg x, reset;
wire clk, m;
//instncia
clock clock1 (clk);
mealy1001 mealy1 (
m,
x,
clk,
reset
);
initial begin
$display("Exemplo0052 - Mealy FSM - Guilherme Diniz de Assumpcao - 462269");
$display("Time x Mealy");
//initial values
reset =... | 7.133815 |
module Exemplo0052test;
reg clk, reset, x;
wire m1;
exemplo0052 mealy101 (
m1,
x,
clk,
reset
);
initial begin
$display("Time X Mealy ");
// initial values
clk = 1;
reset = 0;
x = 0;
// input signal changing
#5 reset = 1;
#10 x = 1;
#10 x =... | 7.34658 |
module Exemplo0052;
reg clk, reset, x;
wire m1;
mealy1001 mealy1 (
m1,
x,
clk,
reset
);
initial begin
$display("Time X Mealy");
// initial values
clk = 1;
reset = 0;
x = 0;
// input signal changing
#5 reset = 1;
#10 x = 1;
#10 x = 0;
#10 x = ... | 7.133815 |
module Exemplo0053;
reg x, reset;
wire clk, m;
//instncia
clock clock1 (clk);
moore1001 moore1 (
m,
x,
clk,
reset
);
initial begin
$display("Exemplo0053 - Moore FSM - Guilherme Diniz de Assumpcao - 462269");
$display("Time x Moore");
//initial values
reset =... | 6.866159 |
module Exemplo0053test;
reg clk, reset, x;
wire m1;
exemplo0053 moore1010 (
m1,
x,
clk,
reset
);
initial begin
$display("Time X Mealy ");
// initial values
clk = 1;
reset = 0;
x = 0;
// input signal changing
#5 reset = 1;
#10 x = 1;
#10 x ... | 6.91538 |
module Exemplo0053;
reg clk, reset, x;
wire m2;
moore1001 moore1 (
m2,
x,
clk,
reset
);
initial begin
$display("Time X Moore");
// initial values
clk = 1;
reset = 0;
x = 0;
// input signal changing
#5 reset = 1;
#10 x = 1;
#10 x = 0;
#10 x = ... | 6.866159 |
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