code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module FFTLinearbar #(
////////////////////////////////////////////////////
// Parameters
parameter bw_input = 17
) (
////////////////////////////////////////////////////
// Ports
input Clock,
Reset,
Start,
input [bw_input-1:0] In,
output reg [6:0] Out,
output reg Busy,
E... | 7.524638 |
module FFTLoader #(
////////////////////////////////////////////////////
// Parameters
parameter bw_fftp = 12
) (
////////////////////////////////////////////////////
// Ports
input Clock,
Reset,
Start,
// For Cacher
input [12:0] LastWriteAddr,
//For FFTC
output FFTCSta... | 7.091795 |
module FFTLogbar #(
////////////////////////////////////////////////////
// Parameters
parameter bw_input = 17
) (
////////////////////////////////////////////////////
// Ports
input Clock,
Reset,
Start,
input [bw_input-1:0] In,
output reg [6:0] Out,
output reg Busy,
End
... | 7.203027 |
module FFTLogbar2 #(
////////////////////////////////////////////////////
// Parameters
parameter bw_input = 18
) (
////////////////////////////////////////////////////
// Ports
input Clock,
Reset,
Start,
input [bw_input-1:0] In,
output reg [6:0] Out,
output reg Busy,
End... | 6.972757 |
module FFTLogbar2 #(
////////////////////////////////////////////////////
// Parameters
parameter bw_input = 18
) (
////////////////////////////////////////////////////
// Ports
input Clock,
Reset,
Start,
input [bw_input-1:0] In,
output reg [6:0] Out,
output reg Busy,
End... | 6.972757 |
module fftpga (
input sys_clk,
input sys_rst,
//////////////
//audio part//
//////////////
//WM978 interface
input aud_bclk, //bit clk
input aud_lrc, //synchronize signal
input aud_adcdat, //audio_input
input key0,
output aud_mclk, //main clk signal for WM897... | 6.645669 |
module ComplexAdd (
input [31:0] io_op1_re,
input [31:0] io_op1_im,
input [31:0] io_op2_re,
input [31:0] io_op2_im,
output [31:0] io_res_re,
output [31:0] io_res_im
);
assign io_res_re = $signed(io_op1_re) + $signed(io_op2_re); // @[Butterfly.scala 21:13]
assign io_res_im = $signed(io_o... | 8.602364 |
module ComplexSub (
input [31:0] io_op1_re,
input [31:0] io_op1_im,
input [31:0] io_op2_re,
input [31:0] io_op2_im,
output [31:0] io_res_re,
output [31:0] io_res_im
);
assign io_res_re = $signed(io_op1_re) - $signed(io_op2_re); // @[Butterfly.scala 35:13]
assign io_res_im = $signed(io_o... | 8.653321 |
module ComplexMul (
input [31:0] io_op1_re,
input [31:0] io_op1_im,
input [31:0] io_op2_re,
input [31:0] io_op2_im,
output [31:0] io_res_re,
output [31:0] io_res_im
);
wire [63:0] _T = $signed(io_op1_re) * $signed(io_op2_re); // @[Butterfly.scala 57:28]
wire [63:0] _T_1 = $signed(io_op1... | 7.643712 |
module Butterfly (
input [31:0] io_in1_re,
input [31:0] io_in1_im,
input [31:0] io_in2_re,
input [31:0] io_in2_im,
input [31:0] io_wn_re,
input [31:0] io_wn_im,
output [31:0] io_out1_re,
output [31:0] io_out1_im,
output [31:0] io_out2_re,
output [31:0] io_out2_im
);
wire ... | 7.053425 |
module Switch (
input [31:0] io_in1_re,
input [31:0] io_in1_im,
input [31:0] io_in2_re,
input [31:0] io_in2_im,
input io_sel,
output [31:0] io_out1_re,
output [31:0] io_out1_im,
output [31:0] io_out2_re,
output [31:0] io_out2_im
);
assign io_out1_re = io_sel ? $signed(
... | 8.637434 |
module FFTResOptimize (
////////////////////////////////////////////////////
// Ports
input Clock,
Reset,
Start,
AudioInputSel,
input [17:0] Re,
Im,
output [6:0] Spectol,
output End,
output reg Busy
);
////////////////////////////////////////////////////
// Registers
... | 6.719688 |
module FFTScramblerTB ();
reg clk, reset;
reg [19:0] inputscrambler0, inputscrambler1, inputscrambler2, inputscrambler3;
wire [19:0] outputscrambler0, outputscrambler1, outputscrambler2, outputscrambler3;
FFTScramblerBit Inst2 (
inputscrambler0,
inputscrambler1,
inputscrambler2,
input... | 6.80431 |
module FFTSequenser
#(
////////////////////////////////////////////////////
// Parameters
parameter bw_fftp = 6
)
(
////////////////////////////////////////////////////
// Ports
input Clock,Reset,obstart,outvalid,Busy_SW,Busy_SL,
output reg CGate,Start_SL,Start_SW
);
wire [3:0] Opcode;
///////////////////////... | 6.551731 |
module FFTSequenser2 #(
////////////////////////////////////////////////////
// Parameters
parameter bw_fftp = 12
) (
////////////////////////////////////////////////////
// Ports
input Clock,
Reset,
input StartFFT,
input FFTEnd, // = FFTEnd
input FFTCReadAddrValid,
output ... | 6.814616 |
module FFTSeq_Loader #(
////////////////////////////////////////////////////
// Parameters
parameter bw_dpram = 12,
parameter bw_data = 16
) (
////////////////////////////////////////////////////
// Ports
input Clock,
Reset,
Start,
rfib,
ibend,
input [bw_data-1:0] RAM_Q,... | 6.719304 |
module FFTSpectolWriterOld (
////////////////////////////////////////////////////
// Ports
input Clock,
ClockEn,
Reset,
Start,
LRChange,
input [6:0] Bar, //スペクトルの高さ 0~96
output Screen,
output reg [8:0] X, //座標。左上からx0,y0
output reg [6:0] Y,
output reg [14:0] Color, //MS... | 7.148612 |
module FFTSpectolWriter (
////////////////////////////////////////////////////
// Ports
input Clock,
Reset,
LRChange,
NewFrame,
input [1:0] ActiveScreen,
// For FFTSequenser
input Start,
input [6:0] Bar,
input DrawTop,
output End,
output reg Busy,
// For SRAMCt... | 7.148612 |
module FFTVisualisator (
input CLOCK_50,
input AUD_ADCDAT,
input AUD_ADCLRCK,
input AUD_BCLK,
output AUD_XCK,
inout I2C_SCLK,
inout I2C_SDAT,
input [3:0] KEY,
output [8:0] LEDG,
output [17:0] LEDR,
input [17:0] SW,
output [7:0] VGA_R,
output [7:0] VGA_G,
output [7... | 7.139415 |
module fftx82048 (
input wire clock,
reset,
input wire [7:0] input_data_in,
input wire [10:0] input_addr,
input wire input_we,
input wire input_enable,
output reg done,
output wire [31:0] data_out
);
//To start off the FFT, assert input_enable for 1 cycle
wire mem_we;
wire [10:0] m... | 7.051319 |
module: FFT_20150605
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module FFT_20150605_tb;
parameter DataWidth = 12;
// Inputs
reg clk;
reg rst;
reg [11:0] sample_Re_data;
reg [11:0]... | 6.826009 |
module FFT_2_8_DIF_TB;
reg clk;
reg rst_n;
reg valid;
reg [15:0] data_in;
wire [36:0] data_out;
FFT_2_8_DIF u_FFT_2_8_DIF (
.clk (clk),
.rst_n(rst_n),
.valid(valid),
.data_in (data_in),
.data_out(data_out)
);
initial begin
clk = 0;
forever #(10) clk = ~c... | 6.682678 |
module real_imaginary_interchange_0 (
A32,
Swap,
R32
);
input [31:0] A32;
output [31:0] R32;
input Swap;
mux_2_to_1_DATA_WIDTH16_0 mux_2_to_1_inst0 (
.D0(A32[31:16]),
.D1(A32[15:0]),
.S (Swap),
.Y (R32[31:16])
);
mux_2_to_1_DATA_WIDTH16_147 mux_2_to_1_inst1 (
.D0(... | 7.005496 |
module dff_hold_sync_high_reset_DATA_WIDTH32_180 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_251 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_inputsel_hold_sync_high_reset_DATA_WIDTH32_0 (
clk,
rst,
hold,
sel,
D0,
D1,
Q
);
input [31:0] D0;
input [31:0] D1;
output [31:0] Q;
input clk, rst, hold, sel;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_273 mux_2_to_1_inst0 (
.D0(D0),
.D1(D1),
.S (... | 7.41601 |
module dff_hold_sync_high_reset_DATA_WIDTH32_179 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_250 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_inputsel_hold_sync_high_reset_DATA_WIDTH32_74 (
clk,
rst,
hold,
sel,
D0,
D1,
Q
);
input [31:0] D0;
input [31:0] D1;
output [31:0] Q;
input clk, rst, hold, sel;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_272 mux_2_to_1_inst0 (
.D0(D0),
.D1(D1),
.S ... | 7.41601 |
module dff_hold_sync_high_reset_DATA_WIDTH32_178 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_249 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_inputsel_hold_sync_high_reset_DATA_WIDTH32_73 (
clk,
rst,
hold,
sel,
D0,
D1,
Q
);
input [31:0] D0;
input [31:0] D1;
output [31:0] Q;
input clk, rst, hold, sel;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_271 mux_2_to_1_inst0 (
.D0(D0),
.D1(D1),
.S ... | 7.41601 |
module dff_hold_sync_high_reset_DATA_WIDTH32_0 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_270 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset_D... | 7.383704 |
module dff_hold_sync_high_reset_DATA_WIDTH32_177 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_248 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_hold_sync_high_reset_DATA_WIDTH32_176 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_247 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_hold_sync_high_reset_DATA_WIDTH32_171 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_242 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_hold_sync_high_reset_DATA_WIDTH32_170 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_241 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_hold_sync_high_reset_DATA_WIDTH32_172 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_243 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_hold_sync_high_reset_DATA_WIDTH32_173 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_244 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_hold_sync_high_reset_DATA_WIDTH32_174 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_245 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_hold_sync_high_reset_DATA_WIDTH32_175 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_246 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_segment_for_input_DATA_WIDTH32_0 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] DFF_7_OUT;
wire [31:0] DFF_6_OUT;
wire [31:0] DFF_5_OUT;
wire [31:0] DFF_4_OUT;
wire [31:0] DFF_3_OUT;
wire [31:0] DFF_2_OUT;
wire [31:0] DFF_... | 7.230941 |
module dff_hold_sync_high_reset_DATA_WIDTH32_169 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_240 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_hold_sync_high_reset_DATA_WIDTH32_168 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_239 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_hold_sync_high_reset_DATA_WIDTH32_167 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_238 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_hold_sync_high_reset_DATA_WIDTH32_164 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_235 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_hold_sync_high_reset_DATA_WIDTH32_163 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_234 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_hold_sync_high_reset_DATA_WIDTH32_162 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_233 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_hold_sync_high_reset_DATA_WIDTH32_165 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_236 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_hold_sync_high_reset_DATA_WIDTH32_166 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_237 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_segment_for_input_DATA_WIDTH32_6 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] DFF_7_OUT;
wire [31:0] DFF_6_OUT;
wire [31:0] DFF_5_OUT;
wire [31:0] DFF_4_OUT;
wire [31:0] DFF_3_OUT;
wire [31:0] DFF_2_OUT;
wire [31:0] DFF_... | 7.230941 |
module dff_hold_sync_high_reset_DATA_WIDTH32_161 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_232 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_hold_sync_high_reset_DATA_WIDTH32_160 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_231 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_hold_sync_high_reset_DATA_WIDTH32_159 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_230 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_hold_sync_high_reset_DATA_WIDTH32_154 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_225 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_hold_sync_high_reset_DATA_WIDTH32_155 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_226 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_hold_sync_high_reset_DATA_WIDTH32_156 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_227 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_hold_sync_high_reset_DATA_WIDTH32_157 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_228 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_hold_sync_high_reset_DATA_WIDTH32_158 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_229 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_segment_for_input_DATA_WIDTH32_5 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] DFF_7_OUT;
wire [31:0] DFF_6_OUT;
wire [31:0] DFF_5_OUT;
wire [31:0] DFF_4_OUT;
wire [31:0] DFF_3_OUT;
wire [31:0] DFF_2_OUT;
wire [31:0] DFF_... | 7.230941 |
module dff_hold_sync_high_reset_DATA_WIDTH32_153 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_224 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_hold_sync_high_reset_DATA_WIDTH32_152 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_223 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_hold_sync_high_reset_DATA_WIDTH32_151 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_222 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_hold_sync_high_reset_DATA_WIDTH32_150 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_221 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_hold_sync_high_reset_DATA_WIDTH32_149 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_220 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_hold_sync_high_reset_DATA_WIDTH32_148 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_219 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_hold_sync_high_reset_DATA_WIDTH32_147 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_218 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_hold_sync_high_reset_DATA_WIDTH32_146 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_217 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_segment_for_input_DATA_WIDTH32_4 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] DFF_7_OUT;
wire [31:0] DFF_6_OUT;
wire [31:0] DFF_5_OUT;
wire [31:0] DFF_4_OUT;
wire [31:0] DFF_3_OUT;
wire [31:0] DFF_2_OUT;
wire [31:0] DFF_... | 7.230941 |
module dff_hold_sync_high_reset_DATA_WIDTH32_145 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_216 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_hold_sync_high_reset_DATA_WIDTH32_144 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_215 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_hold_sync_high_reset_DATA_WIDTH32_143 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_214 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_hold_sync_high_reset_DATA_WIDTH32_142 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_213 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_hold_sync_high_reset_DATA_WIDTH32_141 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_212 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_hold_sync_high_reset_DATA_WIDTH32_140 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_211 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_hold_sync_high_reset_DATA_WIDTH32_139 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_210 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_hold_sync_high_reset_DATA_WIDTH32_138 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_209 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_segment_for_input_DATA_WIDTH32_3 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] DFF_7_OUT;
wire [31:0] DFF_6_OUT;
wire [31:0] DFF_5_OUT;
wire [31:0] DFF_4_OUT;
wire [31:0] DFF_3_OUT;
wire [31:0] DFF_2_OUT;
wire [31:0] DFF_... | 7.230941 |
module dff_hold_sync_high_reset_DATA_WIDTH32_137 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_208 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_hold_sync_high_reset_DATA_WIDTH32_136 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_207 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_hold_sync_high_reset_DATA_WIDTH32_130 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_201 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_hold_sync_high_reset_DATA_WIDTH32_131 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_202 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_hold_sync_high_reset_DATA_WIDTH32_132 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_203 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_hold_sync_high_reset_DATA_WIDTH32_133 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_204 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_hold_sync_high_reset_DATA_WIDTH32_134 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_205 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_hold_sync_high_reset_DATA_WIDTH32_135 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_206 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_segment_for_input_DATA_WIDTH32_2 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire n1, n2;
wire [31:0] DFF_7_OUT;
wire [31:0] DFF_6_OUT;
wire [31:0] DFF_5_OUT;
wire [31:0] DFF_4_OUT;
wire [31:0] DFF_3_OUT;
wire [31:0] DFF_2_OUT;
wi... | 7.230941 |
module dff_hold_sync_high_reset_DATA_WIDTH32_123 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_194 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_hold_sync_high_reset_DATA_WIDTH32_122 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_193 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_hold_sync_high_reset_DATA_WIDTH32_124 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_195 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_hold_sync_high_reset_DATA_WIDTH32_125 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_196 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_hold_sync_high_reset_DATA_WIDTH32_126 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_197 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_hold_sync_high_reset_DATA_WIDTH32_127 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_198 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_hold_sync_high_reset_DATA_WIDTH32_128 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_199 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_hold_sync_high_reset_DATA_WIDTH32_129 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] MUX_OUT;
mux_2_to_1_DATA_WIDTH32_200 mux_2_to_1_inst0 (
.D0(D),
.D1(Q),
.S (hold),
.Y (MUX_OUT)
);
dff_sync_high_reset... | 7.383704 |
module dff_segment_for_input_DATA_WIDTH32_1 (
clk,
rst,
hold,
D,
Q
);
input [31:0] D;
output [31:0] Q;
input clk, rst, hold;
wire [31:0] DFF_7_OUT;
wire [31:0] DFF_6_OUT;
wire [31:0] DFF_5_OUT;
wire [31:0] DFF_4_OUT;
wire [31:0] DFF_3_OUT;
wire [31:0] DFF_2_OUT;
wire [31:0] DFF_... | 7.230941 |
module pg_0 (
i_a,
i_b,
o_p,
o_g
);
input i_a, i_b;
output o_p, o_g;
XOR2X1 U2 (
.A(i_b),
.B(i_a),
.Y(o_p)
);
AND2X1 U1 (
.A(i_a),
.B(i_b),
.Y(o_g)
);
endmodule
| 6.858155 |
module pg_9649 (
i_a,
i_b,
o_p,
o_g
);
input i_a, i_b;
output o_p, o_g;
XOR2X1 U2 (
.A(i_b),
.B(i_a),
.Y(o_p)
);
AND2X1 U1 (
.A(i_a),
.B(i_b),
.Y(o_g)
);
endmodule
| 6.584348 |
module pg_9650 (
i_a,
i_b,
o_p,
o_g
);
input i_a, i_b;
output o_p, o_g;
XOR2X1 U2 (
.A(i_b),
.B(i_a),
.Y(o_p)
);
AND2X1 U1 (
.A(i_a),
.B(i_b),
.Y(o_g)
);
endmodule
| 7.012663 |
module pg_9651 (
i_a,
i_b,
o_p,
o_g
);
input i_a, i_b;
output o_p, o_g;
XOR2X1 U2 (
.A(i_b),
.B(i_a),
.Y(o_p)
);
AND2X1 U1 (
.A(i_a),
.B(i_b),
.Y(o_g)
);
endmodule
| 7.089633 |
module pg_9652 (
i_a,
i_b,
o_p,
o_g
);
input i_a, i_b;
output o_p, o_g;
XOR2X1 U2 (
.A(i_b),
.B(i_a),
.Y(o_p)
);
AND2X1 U1 (
.A(i_a),
.B(i_b),
.Y(o_g)
);
endmodule
| 6.947289 |
module pg_9653 (
i_a,
i_b,
o_p,
o_g
);
input i_a, i_b;
output o_p, o_g;
XOR2X1 U2 (
.A(i_b),
.B(i_a),
.Y(o_p)
);
AND2X1 U1 (
.A(i_a),
.B(i_b),
.Y(o_g)
);
endmodule
| 6.93398 |
module pg_9655 (
i_a,
i_b,
o_p,
o_g
);
input i_a, i_b;
output o_p, o_g;
XOR2X1 U2 (
.A(i_b),
.B(i_a),
.Y(o_p)
);
AND2X1 U1 (
.A(i_a),
.B(i_b),
.Y(o_g)
);
endmodule
| 7.012655 |
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