code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module fetch_wb #(
parameter WIDTH = 32,
parameter ENABLES = WIDTH / 8,
parameter ADDRESS = 27,
parameter CNTBITS = 4,
parameter CNTMAX = (1 << CNTBITS) - 1,
parameter MSB = WIDTH - 1,
parameter ASB = ADDRESS - 1,
parameter TSB = ASB - 8,
parameter ESB = ENABLES - 1,
parameter CS... | 8.827769 |
module FeverLed (
clock,
masterState,
fever,
led
);
input clock;
input masterState; //Xbg̎s
input fever; //
output [7:0] led;
wire [7:0] led;
reg [1:0] disp; //LED]p
///ĂȂLED̓̐ݒ
function [7:0] RotateLed;
input [1:0] disp;
input masterState;
input fever;
begin
... | 6.866884 |
module 7 "fex7perm.v" #f)
Copyright (C) 2010-2012 Antti Karttunen, subject to the terms of the GPL v2.
*/
module fex7perm(input f1,
input [1:0] f2,
input [1:0] f3,
input [2:0] f4,
input [2:0] f5,
input [2:0] f6,
inp... | 7.493613 |
module gets generated NUM_CHANNELS times to give independent control to
// the individual channels.
//
module fe_control #(
parameter NUM_CHANNELS = 2,
parameter [7:0] SR_FE_CHAN_OFFSET = 16,
parameter [7:0] SR_TX_FE_BASE = 192,
parameter [7:0] SR_RX_FE_BASE = 200
)(
input clk, input reset,
// Commands fro... | 7.31747 |
module: fe
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_fe;
// Inputs
reg rst;
reg t0;
reg [15:0] pcnew;
reg [15:0] irnew;
reg jp;
reg t3;
// Outputs
wire irr;
wi... | 7.897227 |
module ff (
input wire CLK,
input wire RST_N,
input wire [7:0] D_IN,
input wire EN,
output wire RDY,
output wire [7:0] D_OUT
);
reg [7:0] dff;
assign D_OUT = dff;
assign RDY = 1;
always @(posedge CLK or negedge RST_N) begin
if (!RST_N) dff <= 0;
else if (EN) dff <= D_IN;
end... | 7.633266 |
module flip flop for ssolving debouncing problem
//clock>>>>clock divider>>>>slowclock>>>>flipflop>>>>counter
module ff(clk,d,q);
input clk , d;
output reg q;
always @(posedge clk)
q<=d;
endmodule
| 7.25863 |
module orGate (
output s,
input a,
input b
);
assign s = a | b;
endmodule
| 7.703609 |
module andGate (
output s,
input a,
input b,
input c,
input d
);
assign s = (a & b & c & d);
endmodule
| 9.12182 |
module notGate (
output s,
input a
);
assign s = ~a;
endmodule
| 8.310861 |
module nandaGate (
output s,
input a,
input b
);
assign s = ~(a & b);
endmodule
| 9.318514 |
module nandGate (
output s,
input a,
input b,
input c,
input d
);
assign s = ~(a & b & c & d);
endmodule
| 9.788452 |
module notGate (
output s,
input a
);
assign s = ~a;
endmodule
| 8.310861 |
module dff (
output q,
output qnot,
input d,
input clk,
input preset,
input clear
);
reg q, qnot;
always @(posedge clk) begin
if (clear == 1) begin
q <= 0;
qnot <= 1;
end else begin
if (preset == 1) begin
q <= 1;
qnot <= 0;
end else begin
... | 7.02102 |
module andGate (
output s,
input x,
input y
);
assign s = x & y;
endmodule
| 9.12182 |
module ff16 #(
parameter N = 16
) (
input CLK,
input en,
rst,
input [N-1:0] i,
output reg [N-1:0] o = 0
);
endmodule
| 8.647922 |
module ff16 #(
parameter N = 16
) (
input CLK,
input en,
rst,
input [N-1:0] i,
output reg [N-1:0] o = 0
);
always @(posedge CLK)
if (rst) o <= 0;
else if (en) o <= i;
endmodule
| 8.647922 |
module ff32 #(
parameter N = 32
) (
input CLK,
input en,
rst,
input [N-1:0] i,
output reg [N-1:0] o = 0
);
endmodule
| 8.946966 |
module ff32 #(
parameter N = 32
) (
input CLK,
input en,
rst,
input [N-1:0] i,
output reg [N-1:0] o = 0
);
always @(posedge CLK)
if (rst) o <= 0;
else if (en) o <= i;
endmodule
| 8.946966 |
module ff32_bwe #(
parameter N = 32
) (
input CLK,
input [N/8-1 : 0] en,
input rst,
input [N-1:0] i,
output reg [N-1:0] o = 0
);
endmodule
| 7.151696 |
module ff32_bwe #(
parameter N = 32
) (
input CLK,
input [N/8-1 : 0] en,
input rst,
input [N-1:0] i,
output reg [N-1:0] o = 0
);
genvar j;
generate
for (j = 0; j < N / 8; j = j + 1) begin : r
always @(posedge CLK)
if (rst) o[8*j+:8] <= 0;
else if (en[j]) o[8*j+:8]... | 7.151696 |
module FF7 (
input wire clk,
input wire rst,
//from FF6
input wire [`REG_ADDR_BUS7] iff7_rtaddr_e,
input wire iff7_wreg_e,
input wire [`REG_BUS128] iff7_rt_e,
input wire [0:2] iff7_uid_e,
input wire [`REG_ADDR_BUS7] iff7_rtaddr_o,
input wire iff7_wreg_o,
input wire [`REG_BUS12... | 6.600109 |
module FFD1 (
input [1:0] in
, output out
);
parameter NUM_GATES = 5;
wire [NUM_GATES - 1:0] LW;
wire [NUM_GATES - 1:0] w;
genvar i;
generate
for (i = 0; i < NUM_GATES; i++) begin : L
LCELL lcell_inst (
.in (LW[i])
, .out(w[i])
);
end
endgenerate
or (L... | 6.568556 |
module FFEDataMemoryMux (
input Select,
input [9:0] ReadAddressIn0,
input [9:0] ReadAddressIn1,
output [9:0] ReadAddressOut,
input [9:0] WriteAddressIn0,
input [9:0] WriteAddressIn1,
output [9:0] WriteAddressOut,
input [35:0] DataToMemoryIn0,
input [35:0] DataToMemoryIn1,
... | 7.915343 |
module fff (
clk,
fifo_rd_en,
fifo_r_data,
prog_full,
reseto
);
input fifo_rd_en;
input clk;
// input key;
output reseto;
output [31:0] fifo_r_data;
output prog_full;
reg [3:0] count;
reg reseto;
reg fifo_wr_en;
reg [31:0] fifo_w_data;
initial begin
reseto <= 0;
fifo... | 6.665247 |
module: fibonacci_lfsr
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module ffff;
// Inputs
reg clk;
reg rst_n;
// Outputs
wire [4:0] data;
// Instantiate the Unit Under Test (UU... | 6.790868 |
module FFJK_instanciamientos_tb ();
reg iJ;
reg iK;
reg iClk;
wire oQ;
wire oQn;
FFJK_instanciamientos moduloff (
.iJ (iJ),
.iK (iK),
.iClk(iClk),
.oQ (oQ),
.oQn (oQn)
);
initial begin
iJ = 0;
iK = 0; //estado 1
#100; //retardo
iJ = 0;
iK = 1... | 6.709173 |
module fflopx (
clk,
rst,
idat,
odat
);
parameter WIDTH = 8;
parameter RESET_VALUE = {WIDTH{1'b0}};
input clk, rst;
input [WIDTH-1:0] idat;
output [WIDTH-1:0] odat;
reg [WIDTH-1:0] odat;
always @(posedge clk) begin
if (rst) odat <= RESET_VALUE;
else odat <= idat;
end
endmod... | 6.741412 |
module ffoo (
clock,
data,
rdreq,
wrreq,
empty,
full,
q,
usedw
);
input clock;
input [7:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [7:0] q;
output [3:0] usedw;
wire [3:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [7:0] sub_wire3;
... | 7.180588 |
module ffr #(
parameter WIDTH = 32
) (
input [WIDTH-1:0] D,
input clk,
input reset,
output reg [WIDTH-1:0] Q
);
always @(posedge clk, posedge reset) begin
if (reset) Q <= 32'b0;
else Q <= D;
end
endmodule
| 8.252778 |
module ffre #(
parameter WIDTH = 32,
parameter RESET_VALUE = 32'h0
) (
input [WIDTH-1:0] D,
input clk,
input reset,
input enable,
output reg [WIDTH-1:0] Q
);
always @(posedge clk) begin
if (reset) Q <= RESET_VALUE;
else if (enable) Q <= D;
end
endmodule
| 7.974727 |
module dff (
output q,
output qnot,
input d,
input clk
);
reg q, qnot;
always @(posedge clk) begin
q <= d;
qnot <= ~d;
end
endmodule
| 7.02102 |
module ffsync #( // parameters
WIDTH = 9 // bitwidth to synchronize (must be fifoaddrwidth + 1)
) ( // ports
input [WIDTH-1:0] signal,
input clock,
reset,
output reg [WIDTH-1:0] signal_sync
);
// architecture
// signal --> meta --> signal_sync
// (clk) ^ ^
// first reg
reg [... | 7.662003 |
module FFT #(
parameter WIDTH = 32
) (
input clock, // Master Clock
input reset, // Active High Asynchronous Reset
input di_en, // Input Data Enable
input [WIDTH-1:0] di_re, // Input Data (Real)
input [WIDTH-1:0] di_im, // Input Data (Imag)
... | 6.736598 |
module FFT #(
parameter WIDTH = 16
) (
input clock, // Master Clock
input reset, // Active High Asynchronous Reset
input di_en, // Input Data Enable
input [WIDTH-1:0] di_re, // Input Data (Real)
input [WIDTH-1:0] di_im, // Input Data (Imag)
... | 6.736598 |
module rc39174 (
clk,
reset,
next,
next_out,
X0,
Y0,
X1,
Y1,
X2,
Y2,
X3,
Y3
);
output next_out;
input clk, reset, next;
input [15:0] X0, X1, X2, X3;
output [15:0] Y0, Y1, Y2, Y3;
wire [31:0] t0;
wire [31:0] s0;
assign t0 = {X0, X1};
wire [31:0] t1;
w... | 6.570469 |
module shiftRegFIFO (
X,
Y,
clk
);
parameter depth = 1, width = 1;
output [width-1:0] Y;
input [width-1:0] X;
input clk;
reg [width-1:0] mem [depth-1:0];
integer index;
assign Y = mem[depth-1];
always @(posedge clk) begin
for (index = 1; index < depth; index = index... | 7.124291 |
module memMod (
in,
out,
inAddr,
outAddr,
writeSel,
clk
);
parameter depth = 1024, width = 16, logDepth = 10;
input [width-1:0] in;
input [logDepth-1:0] inAddr, outAddr;
input writeSel, clk;
output [width-1:0] out;
reg [width-1:0] out;
// synthesis attribute ram_style of mem is ... | 7.262241 |
module memMod_dist (
in,
out,
inAddr,
outAddr,
writeSel,
clk
);
parameter depth = 1024, width = 16, logDepth = 10;
input [width-1:0] in;
input [logDepth-1:0] inAddr, outAddr;
input writeSel, clk;
output [width-1:0] out;
reg [width-1:0] out;
// synthesis attribute ram_style of me... | 7.680291 |
module switch (
ctrl,
x0,
x1,
y0,
y1
);
parameter width = 16;
input [width-1:0] x0, x1;
output [width-1:0] y0, y1;
input ctrl;
assign y0 = (ctrl == 0) ? x0 : x1;
assign y1 = (ctrl == 0) ? x1 : x0;
endmodule
| 6.864438 |
module rc39257 (
clk,
reset,
next,
next_out,
X0,
Y0,
X1,
Y1,
X2,
Y2,
X3,
Y3
);
output next_out;
input clk, reset, next;
input [15:0] X0, X1, X2, X3;
output [15:0] Y0, Y1, Y2, Y3;
wire [31:0] t0;
wire [31:0] s0;
assign t0 = {X0, X1};
wire [31:0] t1;
w... | 6.834462 |
module D8_39424 (
addr,
out,
clk
);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [0:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case (addr)
0: out3 <= 16'h0;
1: out3 <= 16'hc000;
default: out3 <= 0;
endcase
end
// synth... | 6.914181 |
module D6_39432 (
addr,
out,
clk
);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [0:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case (addr)
0: out3 <= 16'h4000;
1: out3 <= 16'h0;
default: out3 <= 0;
endcase
end
// synth... | 6.877833 |
module codeBlock39260 (
clk,
reset,
next_in,
next_out,
i2_in,
X0_in,
Y0,
X1_in,
Y1,
X2_in,
Y2,
X3_in,
Y3
);
output next_out;
input clk, reset, next_in;
reg next;
input [0:0] i2_in;
reg [0:0] i2;
input [15:0] X0_in, X1_in, X2_in, X3_in;
reg [15:0] X0,... | 6.517306 |
module rc39522 (
clk,
reset,
next,
next_out,
X0,
Y0,
X1,
Y1,
X2,
Y2,
X3,
Y3
);
output next_out;
input clk, reset, next;
input [15:0] X0, X1, X2, X3;
output [15:0] Y0, Y1, Y2, Y3;
wire [31:0] t0;
wire [31:0] s0;
assign t0 = {X0, X1};
wire [31:0] t1;
w... | 6.731533 |
module D4_39690 (
addr,
out,
clk
);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [1:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case (addr)
0: out3 <= 16'h0;
1: out3 <= 16'hd2bf;
2: out3 <= 16'hc000;
3: out3 <= 16'hd2bf;
... | 6.859419 |
module D2_39702 (
addr,
out,
clk
);
input clk;
output [15:0] out;
reg [15:0] out, out2, out3;
input [1:0] addr;
always @(posedge clk) begin
out2 <= out3;
out <= out2;
case (addr)
0: out3 <= 16'h4000;
1: out3 <= 16'h2d41;
2: out3 <= 16'h0;
3: out3 <= 16'hd2bf;
... | 7.087581 |
module rc39794 (
clk,
reset,
next,
next_out,
X0,
Y0,
X1,
Y1,
X2,
Y2,
X3,
Y3
);
output next_out;
input clk, reset, next;
input [15:0] X0, X1, X2, X3;
output [15:0] Y0, Y1, Y2, Y3;
wire [31:0] t0;
wire [31:0] s0;
assign t0 = {X0, X1};
wire [31:0] t1;
w... | 6.776218 |
module multfix (
clk,
rst,
a,
b,
q_sc,
q_unsc
);
parameter WIDTH = 35, CYCLES = 6;
input signed [WIDTH-1:0] a, b;
output [WIDTH-1:0] q_sc;
output [WIDTH-1:0] q_unsc;
input clk, rst;
reg signed [2*WIDTH-1:0] q [CYCLES-1:0];
wire signed [2*WIDTH-1:0] res;
integer ... | 7.660857 |
module addfxp (
a,
b,
q,
clk
);
(* use_dsp48 = "no" *)
parameter width = 16, cycles = 1;
input signed [width-1:0] a, b;
input clk;
output signed [width-1:0] q;
reg signed [width-1:0] res[cycles-1:0];
assign q = res[cycles-1];
integer i;
always @(posedge clk) begin
res[0] <= a +... | 6.519538 |
module shiftRegFIFO (
X,
Y,
clk
);
parameter depth = 1, width = 1;
output [width-1:0] Y;
input [width-1:0] X;
input clk;
reg [width-1:0] mem [depth-1:0];
integer index;
assign Y = mem[depth-1];
always @(posedge clk) begin
for (index = 1; index < depth; index = index... | 7.124291 |
module multfix (
clk,
rst,
a,
b,
q_sc,
q_unsc
);
(* use_dsp48 = "no" *)
parameter WIDTH = 35, CYCLES = 6;
input signed [WIDTH-1:0] a, b;
output [WIDTH-1:0] q_sc;
output [WIDTH-1:0] q_unsc;
input clk, rst;
reg signed [2*WIDTH-1:0] q [CYCLES-1:0];
wire signed [2*WIDTH-1:0] re... | 7.660857 |
module addfxp (
a,
b,
q,
clk
);
(* use_dsp48 = "no" *)
parameter width = 16, cycles = 1;
input signed [width-1:0] a, b;
input clk;
output signed [width-1:0] q;
reg signed [width-1:0] res[cycles-1:0];
assign q = res[cycles-1];
integer i;
always @(posedge clk) begin
res[0] <= a +... | 6.519538 |
module FFT4_LUT_tb_v;
reg Clk;
reg Reset, Start;
reg [ 3:0] address;
wire [16:0] coeff_real;
wire [16:0] coeff_imag;
// Instantiate the Unit Under Test (UUT)
FFT4_LUT_Re uut1 (
.k(address[3:2]),
.n(address[1:0]),
.twiddle(coeff_real)
);
FFT4_LUT_Im uut2 (
.k(address[3:2]),... | 6.849236 |
module FFT4_tb_v;
parameter PRE = 16;
reg Clk;
reg Reset, Start;
reg signed [PRE:0] X[3:0];
// Outputs
wire signed [2*PRE:0] Y_Re[3:0];
wire signed [2*PRE:0] Y_Im[3:0];
wire signed [PRE:0] X_out[3:0];
assign X_out[0] = X[0];
assign X_out[1] = X[1];
assign X_out[2] = X[2];
assign X_out[3] = X[3... | 6.983071 |
module FFT64 #(
parameter WIDTH = 16
) (
input clock, // Master Clock
input reset, // Active High Asynchronous Reset
input di_en, // Input Data Enable
input [WIDTH-1:0] di_re, // Input Data (Real)
input [WIDTH-1:0] di_im, // Input Data (Imag)
... | 6.892183 |
module fft64_tb ();
reg clk;
reg start;
reg rst_n;
wire [9:0] dinre;
wire [9:0] dinim;
wire [9:0] doutre;
wire [9:0] doutim;
wire doutvalid;
wire din_valid;
fft64_tb_fsm fsm (
.clk(clk),
.rst_n(rst_n),
.start(start),
.din_valid(din_valid),
.doutre(dinre),
.doutim... | 6.599973 |
module fft64_tb_fsm (
input clk,
input rst_n,
input start,
output reg din_valid,
output reg [9:0] doutre,
output reg [9:0] doutim
);
localparam idle = 1'b0, send = 1'b1;
reg state, nextstate;
always @(posedge clk, negedge rst_n)
if (!rst_n) state <= idle;
else state <= nextstate;
... | 8.094931 |
module FFT8_LUT (
n,
twiddle
);
input [9:0] n;
output reg [31:0] twiddle;
always @(n) begin
case (n)
3'd0: twiddle = {16'd32767, 16'd0}; //i=0 n=8 twiddle= 1 + i 0
3'd1:
twiddle = {16'd23170, -16'd23170}; //i=1 n=8 twiddle= 7.071068e-01 + i -7.071068e-01
... | 6.681016 |
module fftaddr2048 (
input wire clock,
reset,
input wire enable, //makes the addresser count up
input wire writemode, //read or write mode for addresser (asserted TRUE for writing to MEMORY)
output wire mem_we, //write enable for memory
output wire [10:0] mem_addr0, //memory addresses
ou... | 6.835212 |
module bitrev11 (
input wire [10:0] data_in,
output wire [10:0] data_out
);
assign data_out[0] = data_in[10];
assign data_out[1] = data_in[9];
assign data_out[2] = data_in[8];
assign data_out[3] = data_in[7];
assign data_out[4] = data_in[6];
assign data_out[5] = data_in[5];
assign data_out[... | 7.396518 |
module bitcirc_r11 (
input wire [ 3:0] n,
input wire [10:0] data_in,
output wire [10:0] data_out
);
//Bit circulates data_in to the right by n bits
wire [10:0] data_out3;
wire [10:0] data_out2;
wire [10:0] data_out1;
assign data_out3 = (n[3] == 1) ? {data_in[7:0], data_in[10:8]} : data_in;
ass... | 7.042309 |
module: DFF
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module DFF_tb;
// Inputs
reg D;
reg Clk;
reg Reset;
// Outputs
wire Q;
wire Qbar;
// Instantiate the Unit Under Te... | 7.075697 |
module fft(
rst_n,
clk,
data1,
fft_go,
fft_done,
fft_res
);
input rst_n;
input clk;
input signed[7:0]data1;
input fft_go;
output reg fft_done;
output reg signed[815:0]fft_res;
reg[4:0]current_state;
reg[4:0]next_state;
reg rad_data_en;//读取外部数据使能
reg[6:0]rd_cnt;
reg[6:0]rd_data_add;//RAM 从外部读取数据线
... | 7.57757 |
module me5334a_FFTC2048_16 (
clk,
rstn,
pfdd15f,
uk2bfe6,
neca54e,
tj9ba2b,
go7dcff
);
parameter ba99a50 = 16;
parameter ho69416 = 16;
parameter gq1a9ae = 1;
parameter med4d71 = "ECP";
localparam kqde610 = 1 << ho69416;
input clk;
input rstn;
input pfdd15f;
input [ho69416-1... | 6.732686 |
module do9c345_FFTC2048_16 (
clk,
rstn,
din,
dout
);
parameter fc2aae9 = 16;
input clk;
input rstn;
input [fc2aae9-1:0] din;
output [fc2aae9-1:0] dout;
reg [fc2aae9-1:0] dout;
always @(posedge clk or negedge rstn) begin
if (rstn == 1'b0) dout <= 'b0;
else dout <= din;
end
endmodu... | 7.237333 |
module osf5e4e_FFTC2048_16 (
clk,
rstn,
ph38443,
ri110f7,
wlbe0cb,
zm832e8,
hbd80ed,
ph3b7a
);
parameter pdin_widthr = 16;
parameter xj71cad = 16;
parameter phard_mac = 1;
parameter sw31626 = 0;
parameter ph8b130 = 1;
parameter zk58987 = 0;
parameter plog2_points = 10;
pa... | 6.621092 |
module lqee0f9_FFTC2048_16 (
rstn,
clk,
pfe9af9,
hdaa0f5
);
parameter gb707ca = 3;
parameter mg1f2a2 = 16;
input rstn;
input clk;
input [mg1f2a2-1:0] pfe9af9;
output [mg1f2a2-1:0] hdaa0f5;
reg [mg1f2a2-1:0] yz95d45 [0:gb707ca-1];
integer en75165;
always @(posedge clk ... | 6.757373 |
module sj12f6f_FFTC2048_16 (
clk,
rstn,
fft_mode,
dire,
diim,
dore,
doim
);
input clk;
input rstn;
input fft_mode;
input [`DATA_WIDTH-1:0] dire;
input [`DATA_WIDTH-1:0] diim;
output [`DATA_WIDTH-1:0] dore;
output [`DATA_WIDTH-1:0] doim;
reg [`DATA_WIDTH-1:0] dore;
reg [`DAT... | 7.032279 |
module epd4c0_FFTC2048_16 (
rstn,
clk,
aa98120,
`ifdef OUTVALID_SEL
ng14954,
`endif
rv2dca9,
dz6e54e,
su72a76,
oh953b0,
dore,
doim
);
input rstn;
input clk;
input aa98120;
`ifdef OUTVALID_SEL
input ng14954;
`endif
input [`DATA_WIDTH-1:0] rv2dca9;
input [`DATA_WIDT... | 6.653725 |
module sj232d3_FFTC2048_16 (
rstn,
clk,
uk3ea23,
end39ce,
tw9ce75,
rv2dca9,
dz6e54e,
su72a76,
oh953b0,
pf742a7,
qva153e,
ks34a7f,
hda53f9,
an29fcf,
xj4fe7c
);
input rstn;
input clk;
input uk3ea23;
input [`DATA_WIDTH-1:0] end39ce;
input [`DATA_WIDTH-1... | 6.880972 |
module me5334a_FFTC2048_18 (
clk,
rstn,
pfdd15f,
uk2bfe6,
neca54e,
tj9ba2b,
go7dcff
);
parameter ba99a50 = 16;
parameter ho69416 = 16;
parameter gq1a9ae = 1;
parameter med4d71 = "ECP";
localparam kqde610 = 1 << ho69416;
input clk;
input rstn;
input pfdd15f;
input [ho69416-1... | 6.732686 |
module do9c345_FFTC2048_18 (
clk,
rstn,
din,
dout
);
parameter fc2aae9 = 16;
input clk;
input rstn;
input [fc2aae9-1:0] din;
output [fc2aae9-1:0] dout;
reg [fc2aae9-1:0] dout;
always @(posedge clk or negedge rstn) begin
if (rstn == 1'b0) dout <= 'b0;
else dout <= din;
end
endmodu... | 7.237333 |
module osf5e4e_FFTC2048_18 (
clk,
rstn,
ph38443,
ri110f7,
wlbe0cb,
zm832e8,
hbd80ed,
ph3b7a
);
parameter pdin_widthr = 16;
parameter xj71cad = 16;
parameter phard_mac = 1;
parameter sw31626 = 0;
parameter ph8b130 = 1;
parameter zk58987 = 0;
parameter plog2_points = 10;
pa... | 6.621092 |
module lqee0f9_FFTC2048_18 (
rstn,
clk,
pfe9af9,
hdaa0f5
);
parameter gb707ca = 3;
parameter mg1f2a2 = 16;
input rstn;
input clk;
input [mg1f2a2-1:0] pfe9af9;
output [mg1f2a2-1:0] hdaa0f5;
reg [mg1f2a2-1:0] yz95d45 [0:gb707ca-1];
integer en75165;
always @(posedge clk ... | 6.757373 |
module sj12f6f_FFTC2048_18 (
clk,
rstn,
fft_mode,
dire,
diim,
dore,
doim
);
input clk;
input rstn;
input fft_mode;
input [`DATA_WIDTH-1:0] dire;
input [`DATA_WIDTH-1:0] diim;
output [`DATA_WIDTH-1:0] dore;
output [`DATA_WIDTH-1:0] doim;
reg [`DATA_WIDTH-1:0] dore;
reg [`DAT... | 7.032279 |
module epd4c0_FFTC2048_18 (
rstn,
clk,
aa98120,
`ifdef OUTVALID_SEL
ng14954,
`endif
rv2dca9,
dz6e54e,
su72a76,
oh953b0,
dore,
doim
);
input rstn;
input clk;
input aa98120;
`ifdef OUTVALID_SEL
input ng14954;
`endif
input [`DATA_WIDTH-1:0] rv2dca9;
input [`DATA_WIDT... | 6.653725 |
module sj232d3_FFTC2048_18 (
rstn,
clk,
uk3ea23,
end39ce,
tw9ce75,
rv2dca9,
dz6e54e,
su72a76,
oh953b0,
pf742a7,
qva153e,
ks34a7f,
hda53f9,
an29fcf,
xj4fe7c
);
input rstn;
input clk;
input uk3ea23;
input [`DATA_WIDTH-1:0] end39ce;
input [`DATA_WIDTH-1... | 6.880972 |
module me5334a_FFTC2048 (
clk,
rstn,
pfdd15f,
uk2bfe6,
neca54e,
tj9ba2b,
go7dcff
);
parameter ba99a50 = 16;
parameter ho69416 = 16;
parameter gq1a9ae = 1;
parameter med4d71 = "ECP";
localparam kqde610 = 1 << ho69416;
input clk;
input rstn;
input pfdd15f;
input [ho69416-1:0]... | 6.732686 |
module do9c345_FFTC2048 (
clk,
rstn,
din,
dout
);
parameter fc2aae9 = 16;
input clk;
input rstn;
input [fc2aae9-1:0] din;
output [fc2aae9-1:0] dout;
reg [fc2aae9-1:0] dout;
always @(posedge clk or negedge rstn) begin
if (rstn == 1'b0) dout <= 'b0;
else dout <= din;
end
endmodule
... | 7.237333 |
module osf5e4e_FFTC2048 (
clk,
rstn,
ph38443,
ri110f7,
wlbe0cb,
zm832e8,
hbd80ed,
ph3b7a
);
parameter pdin_widthr = 16;
parameter xj71cad = 16;
parameter phard_mac = 1;
parameter sw31626 = 0;
parameter ph8b130 = 1;
parameter zk58987 = 0;
parameter plog2_points = 10;
param... | 6.621092 |
module lqee0f9_FFTC2048 (
rstn,
clk,
pfe9af9,
hdaa0f5
);
parameter gb707ca = 3;
parameter mg1f2a2 = 16;
input rstn;
input clk;
input [mg1f2a2-1:0] pfe9af9;
output [mg1f2a2-1:0] hdaa0f5;
reg [mg1f2a2-1:0] yz95d45 [0:gb707ca-1];
integer en75165;
always @(posedge clk or ... | 6.757373 |
module sj12f6f_FFTC2048 (
clk,
rstn,
fft_mode,
dire,
diim,
dore,
doim
);
input clk;
input rstn;
input fft_mode;
input [`DATA_WIDTH-1:0] dire;
input [`DATA_WIDTH-1:0] diim;
output [`DATA_WIDTH-1:0] dore;
output [`DATA_WIDTH-1:0] doim;
reg [`DATA_WIDTH-1:0] dore;
reg [`DATA_W... | 7.032279 |
module epd4c0_FFTC2048 (
rstn,
clk,
aa98120,
`ifdef OUTVALID_SEL
ng14954,
`endif
rv2dca9,
dz6e54e,
su72a76,
oh953b0,
dore,
doim
);
input rstn;
input clk;
input aa98120;
`ifdef OUTVALID_SEL
input ng14954;
`endif
input [`DATA_WIDTH-1:0] rv2dca9;
input [`DATA_WIDTH-1... | 6.653725 |
module sj232d3_FFTC2048 (
rstn,
clk,
uk3ea23,
end39ce,
tw9ce75,
rv2dca9,
dz6e54e,
su72a76,
oh953b0,
pf742a7,
qva153e,
ks34a7f,
hda53f9,
an29fcf,
xj4fe7c
);
input rstn;
input clk;
input uk3ea23;
input [`DATA_WIDTH-1:0] end39ce;
input [`DATA_WIDTH-1:0]... | 6.880972 |
module me5334a_FFTC64 (
clk,
rstn,
pfdd15f,
uk2bfe6,
neca54e,
tj9ba2b,
go7dcff
);
parameter ba99a50 = 16;
parameter ho69416 = 16;
parameter gq1a9ae = 1;
parameter med4d71 = "ECP";
localparam kqde610 = 1 << ho69416;
input clk;
input rstn;
input pfdd15f;
input [ho69416-1:0] u... | 6.568454 |
module do9c345_FFTC64 (
clk,
rstn,
din,
dout
);
parameter fc2aae9 = 16;
input clk;
input rstn;
input [fc2aae9-1:0] din;
output [fc2aae9-1:0] dout;
reg [fc2aae9-1:0] dout;
always @(posedge clk or negedge rstn) begin
if (rstn == 1'b0) dout <= 'b0;
else dout <= din;
end
endmodule
| 7.080877 |
module rib7c8c_FFTC64 (
clk,
rstn,
pfdd15f,
uk2bfe6,
neca54e,
tj9ba2b,
go7dcff
);
parameter ba99a50 = 16;
parameter ho69416 = 16;
parameter gq1a9ae = 1;
parameter med4d71 = "ECP";
localparam kqde610 = 1 << ho69416;
input clk;
input rstn;
input pfdd15f;
input [ho69416-1:0] u... | 6.580233 |
module lqee0f9_FFTC64 (
rstn,
clk,
pfe9af9,
hdaa0f5
);
parameter gb707ca = 3;
parameter mg1f2a2 = 16;
input rstn;
input clk;
input [mg1f2a2-1:0] pfe9af9;
output [mg1f2a2-1:0] hdaa0f5;
reg [mg1f2a2-1:0] yz95d45 [0:gb707ca-1];
integer en75165;
always @(posedge clk or ne... | 6.955404 |
module sj12f6f_FFTC64 (
clk,
rstn,
fft_mode,
dire,
diim,
dore,
doim
);
input clk;
input rstn;
input fft_mode;
input [`DATA_WIDTH-1:0] dire;
input [`DATA_WIDTH-1:0] diim;
output [`DATA_WIDTH-1:0] dore;
output [`DATA_WIDTH-1:0] doim;
reg [`DATA_WIDTH-1:0] dore;
reg [`DATA_WID... | 7.435958 |
module epd4c0_FFTC64 (
rstn,
clk,
aa98120,
`ifdef OUTVALID_SEL
ng14954,
`endif
rv2dca9,
dz6e54e,
su72a76,
oh953b0,
dore,
doim
);
input rstn;
input clk;
input aa98120;
`ifdef OUTVALID_SEL
input ng14954;
`endif
input [`DATA_WIDTH-1:0] rv2dca9;
input [`DATA_WIDTH-1:0... | 6.606281 |
module sj232d3_FFTC64 (
rstn,
clk,
uk3ea23,
end39ce,
tw9ce75,
rv2dca9,
dz6e54e,
su72a76,
oh953b0,
pf742a7,
qva153e,
ks34a7f,
hda53f9,
an29fcf,
xj4fe7c
);
input rstn;
input clk;
input uk3ea23;
input [`DATA_WIDTH-1:0] end39ce;
input [`DATA_WIDTH-1:0] t... | 6.764963 |
module vxb030e_FFTC64 (
clk,
rstn,
din,
cz709f8,
`ifdef BFPU_PRESENT
`else
`ifdef SFACT_UNSCALE
`else
except,
`endif
`endif
dout
);
input clk;
input rstn;
input [`DATA_WIDTH+1:0] din;
input [1:0] cz709f8;
output [`DATA_WIDTH-1:0] dout;
`ifdef BFPU_PRESENT
`else
`ifdef SFACT_UNSCALE
`el... | 6.513134 |
module descram_FFTC64 (
din,
dout
);
parameter SIZE = 2047;
parameter SCRAMSTRING = 0;
localparam [31:0] zkdfd9d = SCRAMSTRING;
localparam zxf675a = SCRAMSTRING & 4'hf;
localparam [11:0] co9d6b8 = 'h7ff;
input [(1 << zxf675a) -1:0] din;
output [SIZE-1:0] dout;
reg [SIZE-1:0] dout;
reg [zxf... | 6.868042 |
module FFTC64_top (
clk, // system clock
rstn, // system reset
ibstart, // input block start indicator
dire, // real part of input data
diim, // imaginary part of input data
except, // exception signal
rfib, // ready for input block
ibend, // input block end
obstart, // out... | 6.869033 |
module fftclock_unq1 // fftclock
(
input clock_in,
output logic clock_out
);
// (DIV==1) => (clock_out == clock_in)
assign clock_out = clock_in;
endmodule
| 6.568653 |
module FFTCore #(
////////////////////////////////////////////////////
// Parameters
parameter bw_fftp = 12,
parameter bw_data = 18,
parameter bw_stage = 4, //bw_fftpが収まるビット幅
parameter ram_delay = 3 // Address - Q delay
) (
////////////////////////////////////////////////////
/... | 7.606672 |
module fftdisplay #(
parameter LOGFFTSIZE = 0,
LOGDSPSIZE = 0,
AUDIOWIDTH = 0,
DISPLWIDTH = 0
) (
input wire clk,
input wire rst,
output wire [2:0] pixel,
input wire [10:0] hcount,
input wire [9:0] vcount,
input wire hsync,
vsync,
blank,
output wire [ LOGDSPSIZE-1:... | 6.560843 |
module fftfifo (
input CLK,
input RST,
input wr_en,
input [21:0] din,
output full,
output reg valid_o,
output [21:0] dout,
input rd_en
);
localparam counter_top = 6'd63;
reg [5:0] counter;
wire rd_en_w;
assign rd_en_w = rd_en & v... | 7.126357 |
module
//A-B交互にIndexを出力
/*
FFTIndexer_R2 #(.bw_fftp(bw_fftp),.bw_stage(bw_stage))
indexer(.Clock(Clock),Reset(Reset),.Index(),Start(),.Busy(),.End());
*/
module FFTIndexer_R2 #(
////////////////////////////////////////////////////
// Parameters
parameter bw_fftp = 4, //Bit width of output index
parameter bw_stag... | 7.26952 |
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