code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module fec_rot_15 (
input [31:0] c,
output [31:0] co
);
assign co[0] = c[17] ^ c[26] ^ c[28];
assign co[1] = c[18] ^ c[27] ^ c[29];
assign co[2] = c[17] ^ c[19] ^ c[26] ^ c[30];
assign co[3] = c[18] ^ c[20] ^ c[27] ^ c[31];
assign co[4] = c[19] ^ c[21] ^ c[28];
assign co[5] = c[20] ^ c[... | 7.157879 |
module fec_rot_16 (
input [31:0] c,
output [31:0] co
);
assign co[0] = c[16] ^ c[25] ^ c[27];
assign co[1] = c[17] ^ c[26] ^ c[28];
assign co[2] = c[16] ^ c[18] ^ c[25] ^ c[29];
assign co[3] = c[17] ^ c[19] ^ c[26] ^ c[30];
assign co[4] = c[18] ^ c[20] ^ c[27] ^ c[31];
assign co[5] = c[... | 7.252311 |
module fec_rot_17 (
input [31:0] c,
output [31:0] co
);
assign co[0] = c[15] ^ c[24] ^ c[26];
assign co[1] = c[16] ^ c[25] ^ c[27];
assign co[2] = c[15] ^ c[17] ^ c[24] ^ c[28];
assign co[3] = c[16] ^ c[18] ^ c[25] ^ c[29];
assign co[4] = c[17] ^ c[19] ^ c[26] ^ c[30];
assign co[5] = c[... | 6.999481 |
module fec_rot_18 (
input [31:0] c,
output [31:0] co
);
assign co[0] = c[14] ^ c[23] ^ c[25];
assign co[1] = c[15] ^ c[24] ^ c[26];
assign co[2] = c[14] ^ c[16] ^ c[23] ^ c[27];
assign co[3] = c[15] ^ c[17] ^ c[24] ^ c[28];
assign co[4] = c[16] ^ c[18] ^ c[25] ^ c[29];
assign co[5] = c[... | 6.86421 |
module fec_rot_19 (
input [31:0] c,
output [31:0] co
);
assign co[0] = c[13] ^ c[22] ^ c[24] ^ c[31];
assign co[1] = c[14] ^ c[23] ^ c[25];
assign co[2] = c[13] ^ c[15] ^ c[22] ^ c[26] ^ c[31];
assign co[3] = c[14] ^ c[16] ^ c[23] ^ c[27];
assign co[4] = c[15] ^ c[17] ^ c[24] ^ c[28];
as... | 6.737921 |
module fec_rot_20 (
input [31:0] c,
output [31:0] co
);
assign co[0] = c[12] ^ c[21] ^ c[23] ^ c[30];
assign co[1] = c[13] ^ c[22] ^ c[24] ^ c[31];
assign co[2] = c[12] ^ c[14] ^ c[21] ^ c[25] ^ c[30];
assign co[3] = c[13] ^ c[15] ^ c[22] ^ c[26] ^ c[31];
assign co[4] = c[14] ^ c[16] ^ c[23... | 6.907428 |
module fec_rot_21 (
input [31:0] c,
output [31:0] co
);
assign co[0] = c[11] ^ c[20] ^ c[22] ^ c[29];
assign co[1] = c[12] ^ c[21] ^ c[23] ^ c[30];
assign co[2] = c[11] ^ c[13] ^ c[20] ^ c[24] ^ c[29] ^ c[31];
assign co[3] = c[12] ^ c[14] ^ c[21] ^ c[25] ^ c[30];
assign co[4] = c[13] ^ c[15... | 7.01538 |
module fec_rot_22 (
input [31:0] c,
output [31:0] co
);
assign co[0] = c[10] ^ c[19] ^ c[21] ^ c[28] ^ c[31];
assign co[1] = c[11] ^ c[20] ^ c[22] ^ c[29];
assign co[2] = c[10] ^ c[12] ^ c[19] ^ c[23] ^ c[28] ^ c[30] ^ c[31];
assign co[3] = c[11] ^ c[13] ^ c[20] ^ c[24] ^ c[29] ^ c[31];
assi... | 7.098314 |
module fec_rot_23 (
input [31:0] c,
output [31:0] co
);
assign co[0] = c[9] ^ c[18] ^ c[20] ^ c[27] ^ c[30] ^ c[31];
assign co[1] = c[10] ^ c[19] ^ c[21] ^ c[28] ^ c[31];
assign co[2] = c[9] ^ c[11] ^ c[18] ^ c[22] ^ c[27] ^ c[29] ^ c[30] ^ c[31];
assign co[3] = c[10] ^ c[12] ^ c[19] ^ c[23] ^ ... | 6.624752 |
module fec_rot_24 (
input [31:0] c,
output [31:0] co
);
assign co[0] = c[8] ^ c[17] ^ c[19] ^ c[26] ^ c[29] ^ c[30];
assign co[1] = c[9] ^ c[18] ^ c[20] ^ c[27] ^ c[30] ^ c[31];
assign co[2] = c[8] ^ c[10] ^ c[17] ^ c[21] ^ c[26] ^ c[28] ^ c[29] ^ c[30] ^ c[31];
assign co[3] = c[9] ^ c[11] ^ c[... | 6.910119 |
module fec_rot_25 (
input [31:0] c,
output [31:0] co
);
assign co[0] = c[7] ^ c[16] ^ c[18] ^ c[25] ^ c[28] ^ c[29];
assign co[1] = c[8] ^ c[17] ^ c[19] ^ c[26] ^ c[29] ^ c[30];
assign co[2] = c[7] ^ c[9] ^ c[16] ^ c[20] ^ c[25] ^ c[27] ^ c[28] ^ c[29] ^ c[30] ^ c[31];
assign co[3] = c[8] ^ c[10] ^... | 7.101847 |
module fec_rot_26 (
input [31:0] c,
output [31:0] co
);
assign co[0] = c[6] ^ c[15] ^ c[17] ^ c[24] ^ c[27] ^ c[28];
assign co[1] = c[7] ^ c[16] ^ c[18] ^ c[25] ^ c[28] ^ c[29];
assign co[2] = c[6] ^ c[8] ^ c[15] ^ c[19] ^ c[24] ^ c[26] ^ c[27] ^ c[28] ^ c[29] ^ c[30];
assign co[3] = c[7] ^ c[9] ^ ... | 6.625096 |
module fec_rot_27 (
input [31:0] c,
output [31:0] co
);
assign co[0] = c[5] ^ c[14] ^ c[16] ^ c[23] ^ c[26] ^ c[27];
assign co[1] = c[6] ^ c[15] ^ c[17] ^ c[24] ^ c[27] ^ c[28];
assign co[2] = c[5] ^ c[7] ^ c[14] ^ c[18] ^ c[23] ^ c[25] ^ c[26] ^ c[27] ^ c[28] ^ c[29];
assign co[3] = c[6] ^ c[8] ^ ... | 6.756367 |
module fec_rot_28 (
input [31:0] c,
output [31:0] co
);
assign co[0] = c[4] ^ c[13] ^ c[15] ^ c[22] ^ c[25] ^ c[26] ^ c[31];
assign co[1] = c[5] ^ c[14] ^ c[16] ^ c[23] ^ c[26] ^ c[27];
assign co[2] =
c[4] ^ c[6] ^ c[13] ^ c[17] ^ c[22] ^ c[24] ^
c[25] ^ c[26] ^ c[27] ^ c[28] ^ c[31];
assi... | 7.049159 |
module fec_rot_29 (
input [31:0] c,
output [31:0] co
);
assign co[0] = c[3] ^ c[12] ^ c[14] ^ c[21] ^ c[24] ^ c[25] ^ c[30];
assign co[1] = c[4] ^ c[13] ^ c[15] ^ c[22] ^ c[25] ^ c[26] ^ c[31];
assign co[2] =
c[3] ^ c[5] ^ c[12] ^ c[16] ^ c[21] ^ c[23] ^
c[24] ^ c[25] ^ c[26] ^ c[27] ^ c[30];... | 7.081183 |
module fec_rot_30 (
input [31:0] c,
output [31:0] co
);
assign co[0] = c[2] ^ c[11] ^ c[13] ^ c[20] ^ c[23] ^ c[24] ^ c[29] ^ c[31];
assign co[1] = c[3] ^ c[12] ^ c[14] ^ c[21] ^ c[24] ^ c[25] ^ c[30];
assign co[2] =
c[2] ^ c[4] ^ c[11] ^ c[15] ^ c[20] ^ c[22] ^
c[23] ^ c[24] ^ c[25] ^ c[26] ... | 6.892201 |
module fec_rot_31 (
input [31:0] c,
output [31:0] co
);
assign co[0] = c[1] ^ c[10] ^ c[12] ^ c[19] ^ c[22] ^ c[23] ^ c[28] ^ c[30] ^ c[31];
assign co[1] = c[2] ^ c[11] ^ c[13] ^ c[20] ^ c[23] ^ c[24] ^ c[29] ^ c[31];
assign co[2] =
c[1] ^ c[3] ^ c[10] ^ c[14] ^ c[19] ^ c[21] ^
c[22] ^ c[23] ... | 7.135121 |
module fec_rot_32 (
input [31:0] c,
output [31:0] co
);
assign co[0] = c[0] ^ c[9] ^ c[11] ^ c[18] ^ c[21] ^ c[22] ^ c[27] ^ c[29] ^ c[30] ^ c[31];
assign co[1] = c[1] ^ c[10] ^ c[12] ^ c[19] ^ c[22] ^ c[23] ^ c[28] ^ c[30] ^ c[31];
assign co[2] =
c[0] ^ c[2] ^ c[9] ^ c[13] ^ c[18] ^ c[20] ^
... | 7.182936 |
module fec_rot_4 (
input [31:0] c,
output [31:0] co
);
assign co[0] = c[28];
assign co[1] = c[29];
assign co[2] = c[28] ^ c[30];
assign co[3] = c[29] ^ c[31];
assign co[4] = c[0] ^ c[30];
assign co[5] = c[1] ^ c[31];
assign co[6] = c[2];
assign co[7] = c[3];
assign co[8] = c... | 6.904996 |
module fec_rot_5 (
input [31:0] c,
output [31:0] co
);
assign co[0] = c[27];
assign co[1] = c[28];
assign co[2] = c[27] ^ c[29];
assign co[3] = c[28] ^ c[30];
assign co[4] = c[29] ^ c[31];
assign co[5] = c[0] ^ c[30];
assign co[6] = c[1] ^ c[31];
assign co[7] = c[2];
assign c... | 6.885205 |
module fec_rot_6 (
input [31:0] c,
output [31:0] co
);
assign co[0] = c[26];
assign co[1] = c[27];
assign co[2] = c[26] ^ c[28];
assign co[3] = c[27] ^ c[29];
assign co[4] = c[28] ^ c[30];
assign co[5] = c[29] ^ c[31];
assign co[6] = c[0] ^ c[30];
assign co[7] = c[1] ^ c[31];
... | 6.548758 |
module fec_rot_8 (
input [31:0] c,
output [31:0] co
);
assign co[0] = c[24];
assign co[1] = c[25];
assign co[2] = c[24] ^ c[26];
assign co[3] = c[25] ^ c[27];
assign co[4] = c[26] ^ c[28];
assign co[5] = c[27] ^ c[29];
assign co[6] = c[28] ^ c[30];
assign co[7] = c[29] ^ c[31];
... | 7.001558 |
module fec_rot_9 (
input [31:0] c,
output [31:0] co
);
assign co[0] = c[23];
assign co[1] = c[24];
assign co[2] = c[23] ^ c[25];
assign co[3] = c[24] ^ c[26];
assign co[4] = c[25] ^ c[27];
assign co[5] = c[26] ^ c[28];
assign co[6] = c[27] ^ c[29];
assign co[7] = c[28] ^ c[30];
... | 6.550766 |
module fec_rot_n2112 (
input [31:0] c,
output [31:0] co
);
assign co[0] =
c[1] ^ c[5] ^ c[6] ^ c[8] ^ c[12] ^ c[14] ^
c[15] ^ c[16] ^ c[19] ^ c[21] ^ c[23] ^ c[24] ^ c[26] ^
c[27] ^ c[28];
assign co[1] =
c[0] ^ c[2] ^ c[6] ^ c[7] ^ c[9] ^ c[13] ^
c[15] ^ c[16] ^ c[17] ^ c[20] ^ c[2... | 6.788442 |
module FEdetect (
output fe, // Output of the detector (1 on falling edges)
input in, // intput to look for edges on
input clk, // clock Input
input reset // reset Input
);
reg [1:0] state;
//-------------Code Starts Here-------
always @(posedge clk) begin
if (reset) begin
... | 8.076015 |
module feedback_gate (
din,
clk,
aclr,
feedback,
dout
);
input [15:0] din;
input clk, aclr;
output [15:0] feedback, dout;
reg [15:0] dout;
reg [15:0] feedback;
reg [ 1:0] counter;
always @(negedge clk or posedge aclr) begin
if (aclr == 1'b1) begin
feedback <= 16'b00000000... | 6.930227 |
module fee_40dtc_top #(
parameter LGSEN_Init = 1'b1,
parameter FEEFMVer = 16'h5043
) (
input [39:0] dtc_clk_p, //output
input [39:0] dtc_clk_n, //output
input [39:0] dtc_trig_p, //output
input [39:0] dtc_trig_n, //output
output [39:0] dtc_data_p,
output [39:0] dtc_data_n,
outpu... | 6.803628 |
module feimen (
input a,
output b
);
assign b = !a;
endmodule
| 7.489324 |
module feimen2 (
input a,
output b
);
assign b = !a;
endmodule
| 7.438288 |
module Feistel (
input [0:31] right,
input [0:47] key,
output [0:31] fout
);
wire [0:47] expansion_out;
wire [0:47] sbox_in;
wire [0:31] sbox_out;
Expansion e (
.in (right),
.out(expansion_out)
);
assign sbox_in = expansion_out ^ key;
Sbox1 sbox1 (
.sin (sbox_in[0:5]),
... | 8.320606 |
module Fellow (
clk,
rst,
clkout
);
parameter N = 25000000;
input clk, rst;
output clkout;
reg [63:0] cnt;
reg clkout;
//计数
always @(posedge clk) begin
if (rst == 1) cnt <= 0;
else if (cnt == (N - 1)) cnt <= 0;
else cnt <= cnt + 1;
end
//新时钟
always @(posedge clk) begin
i... | 7.077579 |
module FEMB_GTH_example_bit_synchronizer #(
parameter INITIALIZE = 5'b00000,
parameter FREQUENCY = 512
) (
input wire clk_in,
input wire i_in,
output wire o_out
);
// Use 5 flip-flops as a single synchronizer, and tag each declaration with the appropriate synthesis attribute to
// enable... | 8.357856 |
module FEMB_GTH_example_reset_synchronizer #(
parameter FREQUENCY = 512
) (
input wire clk_in,
input wire rst_in,
output wire rst_out
);
// Use 5 flip-flops as a single synchronizer, and tag each declaration with the appropriate synthesis attribute to
// enable clustering. Each flip-flop in t... | 8.357856 |
module femtoPLL #(
parameter freq = 60
) (
input wire pclk,
output wire clk
);
assign clk = pclk;
endmodule
| 7.111655 |
module femul (
input wire clock,
start,
input wire [254:0] a_in,
b_in,
output reg ready = 1,
output reg done = 0,
output wire [254:0] out
);
parameter W = 17; // hardware multiplier input word size
parameter N = 15; // number of words used to represent one field element
parameter C =... | 7.600323 |
module fenotipo (
input [422:0] cromossomo,
input [7:0] chromIn,
output wire [7:0] chromOut
);
wire [24:0][14:0] descricao_les;
wire [ 7:0][ 5:0] descricao_outs;
assign descricao_les[0] = cromossomo[14:0];
assign descricao_les[1] = cromossomo[29:15];
assign descricao_les[2] = cromossomo[44:30... | 6.706761 |
module fenpin (
input clk,
output reg clk_out
);
reg [25:0] cnt = 26'b0;
always @(negedge clk) begin
cnt <= cnt + 1;
if (cnt == 26'b00000000000000000000000000) begin
clk_out <= 0;
end else if (cnt == 26'b01011011100011011000000000) begin
clk_out <= 1;
cnt <= 26'b0;
end
... | 7.193452 |
module fenpin1 (
clk_out,
clk_in,
SW
);
output clk_out;
input clk_in;
input [3:0] SW;
reg [13:0] cnt;
reg clk_out;
always @(posedge clk_in) begin
if (SW[0] == 1) begin
parameter N = 32;
begin
begin
if (cnt == N / 2 - 1) begin
clk_out <= ~clk_out;
... | 7.088806 |
module fenpin2 (
clk_out,
clk_in,
SW
);
output clk_out;
input clk_in;
input [3:0] SW;
reg [13:0] cnt;
reg clk_out;
always @(posedge clk_in) begin
if (SW[0] == 1) begin
parameter N = 16;
begin
begin
if (cnt == N / 2 - 1) begin
clk_out <= ~clk_out;
... | 6.717385 |
module fenqu (
input [7:0] data,
input clk,
input rst_n,
input i_h_sync,
input i_v_sync,
input i_data_en,
output [7:0] o_data,
output reg o_data_en
);
wire h_add_flag;
wire [11:0] yaddr;
//reg [5:0] h_count... | 6.618148 |
module fenweiqi (
input [31:0] instr,
output [ 5:0] op,
output [ 5:0] func,
output [ 4:0] rs,
output [ 4:0] rt,
output [ 4:0] rd,
output [15:0] imm16,
output [25:0] imm26
);
assign op = instr[31:26];
assign func = instr[5:0];
assign rs = instr[25:21];
assign rt = instr[20:16];
... | 6.818235 |
module fenweiqigai (
input [31:0] instr,
//output [31:0] instr_D,
output [ 4:0] rs,
output [ 4:0] rt,
output [ 4:0] rs_D,
output [ 4:0] rt_D,
output [ 4:0] rd_D,
output [15:0] imm16,
output [ 4:0] sp,
output [25:0] imm26
);
assign instr_D = instr;
assign rs = instr[25:21];
... | 7.532013 |
module fenweiqixugai (
input [31:0] instr,
//output [31:0] instr_D,
output [ 4:0] rs,
output [ 4:0] rt,
output [ 4:0] rs_D,
output [ 4:0] rt_D,
output [ 4:0] rd_D,
output [15:0] imm16
);
assign instr_D = instr;
assign rs = instr[25:21];
assign rt = instr[20:16];
assign rs_D = in... | 7.716111 |
module fenweiqi_2 (
input [31:0] instr,
output [31:0] instr_D,
output [ 4:0] rs,
output [ 4:0] rt,
output [ 4:0] rs_D,
output [ 4:0] rt_D,
output [ 4:0] rd_D,
output [15:0] imm16
);
assign instr_D = instr;
assign rs = instr[25:21];
assign rt = instr[20:16];
assign rs_D = instr[2... | 7.224631 |
module fen_wei_qi (
input [31:0] alu_m_level,
output [ 1:0] w_level_input
);
assign w_level_input = alu_m_level[1:0];
endmodule
| 6.7646 |
module fen_wei_qi_2 (
input [31:0] data_dm_M_level,
output [ 7:0] data_one,
output [ 7:0] data_two,
output [ 7:0] data_three,
output [ 7:0] data_four
);
assign data_one = data_dm_M_level[7:0];
assign data_two = data_dm_M_level[15:8];
assign data_three = data_dm_M_level[23:16];
assign da... | 6.516996 |
module fesub (
input wire clock,
start,
input wire [254:0] a_in,
b_in,
output reg done = 0,
output wire [254:0] out
);
parameter W = 17; // hardware multiplier input word size
parameter N = 15; // number of words used to represent one field element
parameter C = 19; // pseudo-Mersenne c... | 7.017779 |
module fetch (
// Inputs
input [63:0] F_predPC,
input [3:0] M_icode,
input M_Cnd,
input [63:0] M_valA,
input [3:0] W_icode,
input [63:0] W_valM,
// Outputs
output [2:0] f_stat,
output reg [3:0] f_icode,
output reg [3:0] f_ifun,
output reg [3:0] f_rA,
output reg [3:0]... | 7.133965 |
module fetch2 (
input wire clock_i,
input wire reset_i,
input wire frontend_we_i,
input wire [63:0] idata_i,
input wire branch_mispred_i,
input wire wasnt_branch_i,
input wire zero_1_i,
input wire pred_1_i,
output reg [31:0] inst0_o ... | 7.244472 |
module implements pipeline registers between Fetch2 and Decode
# stage.
# Author: FabGen
*******************************************************************************/
`timescale 1ns/100ps
module Fetch2Decode( input clk,
input instruction0Valid_i,
input [`SIZE_INS... | 7.143923 |
module fetch8x8 (
clk,
rstn,
enable,
cnt,
blockcnt,
finish,
rf_512bit,
md_ren_o,
md_sel_o,
md_size_o,
md_4x4_x_o,
md_4x4_y_o,
md_idx_o,
md_data_i
);
input clk;
input rstn;
input enable;
output [5:0] cnt;
output [6:0] blockcnt;
output [511:0] rf_512... | 7.556402 |
module file
// for simulation only
`timescale 1ns/1ps
module testbench;
reg clk;
reg rst;
riscv_top #(.SIM(1)) top(
.EXCLK(clk),
.btnC(rst),
.Tx(),
.Rx(),
.led()
);
initial begin
clk=0;
rst=0;
repeat(50) #1 clk=!clk;
$finish;
end
// my testbench. generate .vcd
initial begin ... | 6.792956 |
module icache_ram8 (
addr,
out,
din,
write
);
input [3:0] addr;
input write;
input [7:0] din;
output [7:0] out;
//--------------------------------------
// Condition Status
//--------------------------------------
// 2. select ram0
// if addr in (0-7) select ram0 0000 - 0111
// if... | 6.906594 |
module icache_ram16 (
addr,
out,
din,
update
);
input [3:0] addr;
input update;
input [15:0] din;
output [15:0] out;
icache_ram8 ram_0 (
addr,
out[7:0],
din[7:0],
update
);
icache_ram8 ram_1 (
addr,
out[15:8],
din[15:8],
update
);
endmodul... | 7.59689 |
module icache_ram32 (
addr,
out,
din,
update
);
input [4:0] addr;
input update;
input [31:0] din;
output [31:0] out;
icache_ram16 ram_0 (
addr,
out[15:0],
din[15:0],
update
);
icache_ram16 ram_1 (
addr,
out[31:16],
din[31:16],
update
);
en... | 7.647705 |
module ram32b16w (
A,
DIN,
OE,
WR,
DOUT
);
input [3:0] A;
input [31:0] DIN;
input OE;
input WR;
output [31:0] DOUT;
wire row_sel;
wire row_sel_n;
wire W0, W1;
// A[2:0] 000 --- 111
assign row_sel = A[3]; // sel 8-15
inv1$ inv_0 (
row_sel_n,
row_sel
);
or2$ ... | 6.836373 |
module fetch_stall_logic (
control_flow_change,
icache_miss,
other_stage_stall,
other_stage_flush,
instr_buf_empty,
exp_flag,
F2D_valid,
F2D_stall,
F2D_stall_n,
eip_stall,
F_flush
);
input control_flow_change;
input icache_miss;
input other_stage_stall;
input other_s... | 6.829887 |
module int_exp_logic (
pg_exp_flag,
ge_exp_flag,
int_flag,
mask_int,
serving_int_exp,
vector_num,
exp_occur,
int_occur,
upc,
upc_valid
);
input pg_exp_flag;
input ge_exp_flag;
input int_flag;
input mask_int; // when fetch is stalled, the instruction cannot be interrupt... | 6.894241 |
module fetchInstructionModule (
write_enable,
instruction_buf,
write_data,
clk,
rst,
write_addr
);
input write_enable, clk, rst;
input [15:0] write_data;
input [31:0] write_addr;
wire [15:0] instruction;
output wire [15:0] instruction_buf;
reg [31:0] pc = 32'b0100000;
instructio... | 7.439512 |
module FetchInstruction_tb ();
localparam addrBits = `ADDRESS_BITS;
localparam dataBits = `DATA_BITS;
reg reset = 0;
reg clk;
always #1 clk <= clk !== 1;
wire [addrBits-1:0] address;
wire [dataBits-1:0] dataIn;
wire [dataBits-1:0] dataOut;
wire rw = `RAM_READ;
IceRam #(
.add... | 7.427207 |
module fetchnum (
input wire clk,
rst_n,
read_en, //外部读使能，使能时候，可以读入数据
input wire [15:0] data_in[1:20],
output reg fetchnum_vld,
output reg [15:0] data_one[1:5], //取出(1x5)这样一帧数，通过移位寄存器实现
output reg empty //传递给外部，目前一帧（1x20）运算结束，请求输入下一帧
);
reg [2 : 0] cnt;
// reg status;//0表示空了，... | 6.79861 |
module fetchnum_tb;
reg clk;
reg rst_n;
reg read_en;
reg [15:0] data_in[1:20];
wire [15:0] data_one[1:5];
wire empty;
fetchnum fetchnum_u (
.clk(clk),
.rst_n(rst_n),
.read_en(read_en),
.data_in(data_in),
.data_one(data_one),
.empty(empty)
);
always #5 clk = !c... | 6.815306 |
module FetchReg (
clk,
rst,
Stall,
NextPCIn,
InstructIn,
NextPCOut,
InstructOut
);
input clk, rst, Stall;
input [15:0] NextPCIn, InstructIn;
output reg [15:0] NextPCOut, InstructOut;
parameter NOP = 16'b1110100000000000;
always @(posedge clk or posedge rst) begin
if (rst) beg... | 6.984664 |
module FetchStack #(parameter addrBits = `ADDRESS_BITS, parameter dataBits = `DATA_BITS) (
// Section: operational I/Os
input wire clk,
input wire reset,
input wire [dataBits-1:0] dataOut,
output wire [addrBits-1:0] address,
output wire finished,
... | 7.709431 |
module FetchStack_tb ();
localparam addrBits = `ADDRESS_BITS;
localparam dataBits = `DATA_BITS;
reg clk = 0;
always #1 clk <= ~clk;
wire [addrBits-1:0] address;
wire [dataBits-1:0] dataIn;
wire [dataBits-1:0] dataOut;
wire rw = `RAM_READ;
IceRam #(
.addrBits(addrBits),
.d... | 7.20605 |
module fetch (
input clk,
set,
reset,
input [31:0] EIP,
input [127:0] icache_data,
input icache_ready,
input [31:0] jmp_fp,
trap_fp,
input [15:0] CS,
input [1:0] fp_mux,
input load_eip,
output [31:0] EIP_OUT,
output [15:0] CS_OUT,
output icache_en,
output [31... | 6.580385 |
module FE_full_shifter (
input [127:0] A,
B,
C,
D,
input [ 5:0] address,
output [127:0] OutputA
);
assign dir = 0;
wire [127:0] AB_out, BC_out, CD_out, DA_out;
shift128$ AB (
A,
B,
dir,
address[3:0],
AB_out
);
shift128$ BC (
B,
C,
di... | 7.18601 |
module reg128e$ (
input CLK,
input [127:0] Din,
output [127:0] Q,
output [127:0] QBAR,
input CLR,
input PRE,
input en
);
reg64e$ low (
CLK,
Din[63:0],
Q[63:0],
QBAR[63:0],
CLR,
PRE,
en
);
reg64e$ high (
CLK,
Din[127:64],
Q[12... | 6.62108 |
module fetch_controller (
WF_dispatch_i,
fetch_valid,
wr,
inst_buff_rd,
wave_reserve_valid
);
input WF_dispatch_i;
input fetch_valid;
output wr;
output inst_buff_rd;
output wave_reserve_valid;
assign wr = WF_dispatch_i;
assign wave_reserve_valid = fetch_valid;
assign inst_buff_rd ... | 6.624969 |
module fetch_data (
num,
parity,
count
);
//get ripple counter data
input [3:0] count;
output [7:0] num;
output parity;
wire [7:0] num1, num2;
wire parity1, parity2;
//get data from mem1 & mem2
mem1 m1 (
num1,
parity1,
count[2:0]
);
mem2 m2 (
num2,
parity2... | 7.505286 |
module fetch_finn_AXI_CPU_s_axi_ram #(
parameter BYTES = 4,
DEPTH = 256,
AWIDTH = log2(DEPTH)
) (
input wire clk0,
input wire [ AWIDTH-1:0] address0,
input wire ce0,
input wire we0,
input wire [ BYTES-1:0] be0,
input wire [BYTES*8-1:0]... | 7.441899 |
module fetch_finn_regslice_both #(
parameter DataWidth = 32
) (
input ap_clk,
input ap_rst,
input [DataWidth-1:0] data_in,
input vld_in,
output ack_in,
output [DataWidth-1:0] data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire ... | 7.370153 |
module fetch_finn_regslice_both_w1 #(
parameter DataWidth = 1
) (
input ap_clk,
input ap_rst,
input data_in,
input vld_in,
output ack_in,
output data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire B_V_data_1_data_in;
re... | 7.370153 |
module fetch_hier_bench ();
// wires and reg
reg [15:0] pc;
wire [15:0] instr;
reg fail;
// DUT & memory (initializing same memory twice)
fetch_hier DUT ();
memory2c m0 (
.data_out(instr),
.data_in(16'b0),
.addr(pc),
.enable(1'b1),
.wr(1'b0),
.createdump(1'b0),
... | 6.756727 |
module fetch_ins_port_m_axi_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire sclk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:0... | 8.30549 |
module fetch_ins_port_m_axi_fifo #(
parameter DATA_BITS = 8,
DEPTH = 16,
DEPTH_BITS = 4
) (
input wire sclk,
input wire reset,
input wire sclk_en,
output reg empty_n,
output reg ... | 8.30549 |
module fetch_ins_port_m_axi_buffer #(
parameter MEM_STYLE = "block",
DATA_WIDTH = 32,
ADDR_WIDTH = 5,
DEPTH = 32
) (
// system signal
input wire clk,
input wire reset,
input wire sclk_en,
// write
output wire if_full_n,
in... | 8.30549 |
module fetch_ins_port_m_axi_decoder #(
parameter DIN_WIDTH = 3
) (
input wire [ DIN_WIDTH-1:0] din,
output reg [2**DIN_WIDTH-1:0] dout
);
integer i;
always @(din) begin
dout = {2 ** DIN_WIDTH{1'b0}};
for (i = 0; i < din; i = i + 1) dout[i] = 1'b1;
end
endmodule
| 8.30549 |
module : fetch_issue
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Sof... | 8.205111 |
module : fetch_issue_intr
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in th... | 8.205111 |
module Fetch_lame #(
parameter W_addr_pah = 5,
parameter W_data_pah = 32,
parameter W_addr_arh = 5,
parameter W_data_arh = 32
) (
//////////// output data flow
output wire [W_data_arh-1:0] instruct,
output wire [W_data_arh-1:0] pc_out,
output wire [W_data_arh-1:0] spec,
output wire b... | 7.303961 |
module fetch_latch (
output reg [31:0] instrout,
npcout,
input wire [31:0] instr,
npc
);
initial begin
instrout <= 0;
npcout <= 0;
end
always @* begin
#1 instrout <= instr;
npcout <= npc;
end
endmodule
| 6.541759 |
module
// Group 3
// Author: Ashan Shanaka Liyanage
// ashan8k@gmail.com
module fetch_mem_wr #(
parameter ADDR_WIDTH=12,
parameter REG_WIDTH=16)(
// System related sygnals
input wire clk,
input wire rst,
// decoder related
output wire [15:0] o_16_data_mem2cpu, // connected to register out of the memo... | 8.87926 |
module fetch_new_test_bench;
// Inputs
reg [31:0] BranchTarget;
reg PCSource;
reg clk;
// Outputs
wire [31:0] NextPC;
wire [31:0] Instruction;
wire Hit;
// Instantiate the Unit Under Test (UUT)
Fetch uut (
.BranchTarget(BranchTarget),
.PCSource(PCSource),
.clk(clk),
.NextP... | 7.684077 |
module Fetch_PC (
input clk,
input rst,
output reg [5:0] PC_code
);
reg [31:0] PC;
always @(posedge rst or negedge clk) begin
if (rst) begin
PC <= 32'h0;
end else begin
PC_code = PC[7:2];
PC <= PC + 32'h4;
end
end
endmodule
| 6.721113 |
module Fetch_Pipe_Reg //program counter with pipe reg
#(
parameter width = 32
) (
input clk,
input reset,
input en,
input [width-1:0] pc_in,
output reg [width-1:0] pc_out
);
always @(posedge clk, negedge reset) begin
if (!reset) pc_out <= {width{1'b0}};
else if (!en) pc_out <= pc_in... | 7.434813 |
module fetch_ram_1p_128x32 (
clk,
cen_i, // low active
oen_i, // low active
wen_i, // low active
addr_i,
data_i,
data_o
);
//*** PARAMETER DECLARATION ****************************************************
parameter Word_Width = 128;
parameter Addr_Width = 5;
//*** INPUT/OUTPUT ... | 8.560682 |
module fetch_ram_2p_128x16 (
clk,
wdata,
waddr,
we,
rd,
raddr,
rdata
);
// *****************************************************
//
// INPUT / OUTPUT DECLARATION
// ... | 7.784284 |
module fetch_ram_2p_128x64 (
clk,
wdata,
waddr,
we,
rd,
raddr,
rdata
);
// *****************************************************
//
// INPUT / OUTPUT DECLARATION
// ... | 7.784284 |
module fetch_ram_2p_64x144 (
clk_i,
wren,
wraddr,
wrdata,
rden,
rdaddr,
rddata
);
// *****************************************************
//
// INPUT / OUTPUT DECLARATION
// ... | 7.784284 |
module fetch_ram_2p_64x208 (
clk,
a_we, // write
a_addr, // write
a_data_i, // write
b_re, // read
b_addr,
b_data_o
);
// ********************************************
//
// Parameters DECLARATION
// ... | 7.784284 |
module : fetch_receive
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the S... | 9.660608 |
module fetch_reg (
input wire clk_i,
input wire rstn_i,
input wire F_stall_i,
input wire [`D_WORD] f_pred_pc_i,
output wire [`D_WORD] F_pred_pc_o
);
reg [`D_WORD] pred_pc_reg;
assign F_pred_pc_o = pred_pc_reg;
always @(posedge clk_i) begin
if (~rstn_i) ... | 7.422672 |
module fetch_rf_1p_128x512 (
clk,
rstn,
wrif_en_i,
wrif_addr_i,
wrif_data_i,
rdif_en_i,
rdif_addr_i,
rdif_pdata_o
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input [1-1:0] clk; ... | 8.149126 |
module fetch_rf_1p_64x256 (
clk,
rstn,
wrif_en_i,
wrif_addr_i,
wrif_data_i,
rdif_en_i,
rdif_addr_i,
rdif_pdata_o
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input [1-1:0] clk; /... | 8.122353 |
module tb;
parameter word_size = 32;
wire [word_size-1:0] instruction, PC_next_normal;
reg [word_size-1:0] PC_next_branch;
reg PCSrc, start;
reg clk, rst;
fetch_unit F0 (
instruction,
PC_next_normal,
PC_next_branch,
PCSrc,
start,
clk,
rst
);
always begin
... | 6.612288 |
module fetch_state_machine (
input f_bus_en,
input bus_ready,
input reset_n,
input clk,
input stopfetch,
output reg pc_incr,
output reg [1:0] current_state,
output reg wen_regs,
output reg sw_fetch_internal
);
parameter INTERNAL_FETCH = 2'b00;
parameter BUS_FETCH_LATCH = 2'b01... | 7.104224 |
module.
//
//////////////////////////////////////////////////////////////////////////////////
`ifndef FETCH_TESTBENCH
`define FETCH_TESTBENCH
`include "../fetch_stage.v"
module FetchTestbench;
reg dep_stall;
reg mem_stall;
reg v_de_br_stall;
reg v_agex_br_stall;
reg v_mem_br_... | 7.119381 |
module Fetch_to_Decode_Register #(
parameter Instr_width = 32,
PCPlus4_width = 32
) (
input wire CLK,
input wire RST,
input wire CLR,
input wire EN,
input wire [ Instr_width-1:0] InstrF,
input wire [PCPlus4_... | 7.491713 |
module fetch (
input clk,
output reg [23:0] instruction
);
integer fd;
reg [23:0] ic[99:0];
initial begin
//binary code is read from code.bin
$readmemb("code.bin", ic);
end
always @(posedge clk) begin
#8 instruction = ic[Program_Counter.PC];
Program_Counter.PC = Program_Counter.PC + ... | 6.580385 |
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