repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
olajep/oh | src/spi/hdl/spi.v | 5,189 | module MODULE1 #( parameter VAR29 = 32, parameter VAR15 = 104, parameter VAR14 = 13 )
( input VAR10, input clk, input VAR27, output VAR20, input VAR16, input [VAR15-1:0] VAR26, input VAR12, output VAR21, output [VAR15-1:0] VAR18, output VAR32, output VAR35, output VAR3, output VAR24, input VAR17, input VAR28, input VAR... | mit |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_mem/bsg_mem_1rw_sync_mask_write_byte.v | 5,583 | if (VAR6 == VAR21 && VAR43 == VAR44) \
begin: VAR8 \
wire [VAR43-1:0] VAR14; \
genvar VAR13; \
for(VAR13=0;VAR13<VAR30;VAR13++) \
assign VAR14[8*VAR13+:8] = {8{VAR46[VAR13]}}; \
VAR28 VAR32 \
(.VAR45 ( VAR25 ) \
,.VAR29 ( VAR17 ) \
,.VAR3 ( ~VAR14 ) \
,.VAR11 ( ~VAR22 ) \
,.VAR9 ( ~VAR24 ) \
,.VAR48 ( VAR1 ) \
,.VAR38 ... | bsd-3-clause |
cornell-zhang/datuner | designs/quartus/processor/cpu.v | 2,406 | module MODULE1(VAR45, VAR51, VAR27, VAR20, VAR29, VAR32, VAR1, VAR39, VAR21, VAR59, VAR12, VAR40);
input VAR45;
input VAR51;
input VAR27;
input [15:0] VAR20;
input [7:0] VAR29;
output [7:0] VAR32;
output [7:0] VAR1;
output [7:0] VAR39;
output [7:0] VAR21;
output [7:0] VAR59;
output [7:0] VAR12;
output VAR40;
reg [7:0] ... | bsd-3-clause |
aabdelfattah/alhaitham-hardware | v/VGA_Controller.v | 5,759 | module MODULE1( VAR22,
VAR27,
VAR4,
VAR19,
VAR2,
VAR26,
VAR17,
VAR14,
VAR7,
VAR11,
VAR34,
VAR32,
VAR36,
VAR3
);
parameter VAR16 = 96;
parameter VAR24 = 48;
parameter VAR21 = 640;
parameter VAR5= 16;
parameter VAR10= 800;
parameter VAR12 = 2;
parameter VAR29 = 33;
parameter VAR33 = 480;
parameter VAR13= 10;
parameter VA... | gpl-3.0 |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/ip/Erosion/acl_fp_custom_add_dbl_pumped.v | 3,691 | module MODULE1
(
input VAR10,
input VAR11,
input enable,
input VAR2,
input [VAR8-1:0] VAR17,
input [VAR8-1:0] b1,
input [VAR8-1:0] VAR1,
input [VAR8-1:0] VAR15,
output reg [VAR8-1:0] VAR16,
output reg [VAR8-1:0] VAR14
);
reg [VAR8-1:0] VAR3;
reg [VAR8-1:0] VAR7;
reg [VAR8-1:0] VAR9;
reg [VAR8-1:0] VAR5;
reg VAR13 ;
wir... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfbbp/sky130_fd_sc_lp__sdfbbp_1.v | 2,821 | module MODULE1 (
VAR5 ,
VAR10 ,
VAR8 ,
VAR11 ,
VAR14 ,
VAR7 ,
VAR9 ,
VAR3,
VAR4 ,
VAR2 ,
VAR12 ,
VAR6
);
output VAR5 ;
output VAR10 ;
input VAR8 ;
input VAR11 ;
input VAR14 ;
input VAR7 ;
input VAR9 ;
input VAR3;
input VAR4 ;
input VAR2 ;
input VAR12 ;
input VAR6 ;
VAR1 VAR13 (
.VAR5(VAR5),
.VAR10(VAR10),
.VAR8(VAR8),
... | apache-2.0 |
peteasa/oh | src/elink/hdl/elink_cfg.v | 3,909 | module MODULE1 (
VAR2, VAR23, VAR13, VAR37,
VAR25,
clk, VAR14, VAR7, VAR35
);
parameter VAR22 = 6; parameter VAR30 = 104; parameter VAR36 = 12'h000;
parameter VAR21 = 12'h808;
input clk;
input VAR14;
input VAR7;
input [VAR30-1:0] VAR35;
output VAR2;
output VAR23; output VAR13; output [15:0] VAR37; output [11:0] VAR25;
... | mit |
asicguy/gplgpu | hdl/de_temp/dex_smlablt.v | 11,701 | module MODULE1
(
input VAR2,
input VAR50,
input VAR73,
input VAR51,
input VAR1,
input VAR54,
input VAR28,
input VAR86,
input VAR26,
input VAR87,
input VAR12,
input [2:0] VAR88,
input VAR70,
input VAR90,
input VAR72,
input VAR60,
input VAR59,
output reg [21:0] VAR44,
output reg [4:0] VAR48,
output reg VAR38,
output reg ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkdlybuf4s18/sky130_fd_sc_lp__clkdlybuf4s18.functional.v | 1,343 | module MODULE1 (
VAR5,
VAR1
);
output VAR5;
input VAR1;
wire VAR2;
buf VAR4 (VAR2, VAR1 );
buf VAR3 (VAR5 , VAR2 );
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2_2.functional.v | 1,043 | module MODULE1( VAR10, VAR9, VAR2, VAR3 );
input VAR3, VAR9, VAR2;
output VAR10;
wire VAR12;
and VAR4( VAR12, VAR3, VAR9 );
wire VAR1;
not VAR11( VAR1, VAR2 );
wire VAR8;
and VAR5( VAR8, VAR1, VAR3 );
wire VAR6;
and VAR7( VAR6, VAR9, VAR2 );
or VAR13( VAR10, VAR12, VAR8, VAR6 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a41o/sky130_fd_sc_lp__a41o.symbol.v | 1,381 | module MODULE1 (
input VAR5,
input VAR6,
input VAR7,
input VAR4,
input VAR8,
output VAR10
);
supply1 VAR1;
supply0 VAR3;
supply1 VAR2 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
AntonovAlexander/activecore | designs/rtl/ram/ram_dual_memsplit_2banks.v | 23,378 | module MODULE1
parameter VAR113="VAR130", VAR123="VAR84.VAR130", VAR4=32, VAR87=32, VAR49=1024, VAR25="VAR39", VAR73="VAR39"
)
(
input VAR13,
input VAR6,
input [0:0] VAR97,
input [0:0] VAR120,
input [31:0] VAR106,
input [3:0] VAR72,
input [31:0] VAR101,
output reg [0:0] VAR126,
output reg [0:0] VAR121,
output reg [31:0... | apache-2.0 |
ShepardSiegel/ocpi | rtl/mkOCApp4B_scenario1.v | 52,119 | module MODULE1(VAR94,
VAR144,
VAR382,
VAR130,
VAR4,
VAR76,
VAR215,
VAR223,
VAR383,
VAR234,
VAR55,
VAR48,
VAR85,
VAR211,
VAR178,
VAR216,
VAR7,
VAR153,
VAR109,
VAR71,
VAR363,
VAR231,
VAR305,
VAR314,
VAR163,
VAR98,
VAR16,
VAR179,
VAR323,
VAR342,
VAR321,
VAR204,
VAR106,
VAR139,
VAR110,
VAR236,
VAR301,
VAR241,
VAR297,
VAR37... | lgpl-3.0 |
alexforencich/verilog-axis | rtl/axis_cobs_encode.v | 17,203 | module MODULE1 #
(
parameter VAR86 = 1
)
(
input wire clk,
input wire rst,
input wire [7:0] VAR66,
input wire VAR81,
output wire VAR7,
input wire VAR26,
input wire VAR17,
output wire [7:0] VAR24,
output wire VAR45,
input wire VAR21,
output wire VAR58,
output wire VAR53
);
localparam [1:0]
VAR61 = 2'd0,
VAR68 = 2'd1,
VA... | mit |
impedimentToProgress/ProbableCause | ddr2/cores/uart16550/bench/verilog/uart_wb_utilities.v | 13,320 | module MODULE1;
task VAR70;
input [VAR59-1:0] VAR38;
reg [3:0] VAR46;
reg VAR56 VAR5;
reg VAR6 VAR58;
integer VAR49;
integer VAR21;
integer VAR16;
reg VAR52;
begin
VAR46 = 4'hF;
VAR21 = 4;
VAR16 = 1;
VAR52 = 1'b0;
VAR19 = VAR49;
VAR48 = VAR21;
VAR43 = (VAR16 == 1);
VAR34 = VAR52;
if (VAR50 !== 1'b1)
begin
end
if (V... | mit |
FAST-Switch/fast | lib/hardware/pipeline/IPE_IF_OPENFLOW/mac_core/altera_tse_rgmii_out4.v | 5,146 | module MODULE1 (
VAR17,
VAR5,
VAR12,
VAR19,
VAR14);
input VAR17;
input [3:0] VAR5;
input [3:0] VAR12;
input VAR19;
output [3:0] VAR14;
wire [3:0] VAR8;
wire [3:0] VAR14 = VAR8[3:0];
VAR18 VAR9 (
.VAR19 (VAR19),
.VAR5 (VAR5),
.VAR17 (VAR17),
.VAR12 (VAR12),
.VAR14 (VAR8),
.VAR4 (1'b0),
.VAR11 (1'b1),
.VAR16 (1'b1));
VA... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/tieh/gf180mcu_fd_sc_mcu9t5v0__tieh.behavioral.pp.v | 1,084 | module MODULE1( VAR5, VAR2, VAR6 );
inout VAR2, VAR6;
output VAR5;
VAR1 VAR4(.VAR5(VAR5),.VAR2(VAR2),.VAR6(VAR6));
VAR1 VAR3(.VAR5(VAR5),.VAR2(VAR2),.VAR6(VAR6)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfbbn/sky130_fd_sc_hs__sdfbbn.symbol.v | 1,534 | module MODULE1 (
input VAR4 ,
output VAR2 ,
output VAR3 ,
input VAR1,
input VAR10 ,
input VAR7 ,
input VAR9 ,
input VAR6
);
supply1 VAR8;
supply0 VAR5;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfsbp/sky130_fd_sc_hd__sdfsbp.functional.pp.v | 2,306 | module MODULE1 (
VAR3 ,
VAR12 ,
VAR21 ,
VAR14 ,
VAR20 ,
VAR22 ,
VAR6,
VAR19 ,
VAR18 ,
VAR11 ,
VAR2
);
output VAR3 ;
output VAR12 ;
input VAR21 ;
input VAR14 ;
input VAR20 ;
input VAR22 ;
input VAR6;
input VAR19 ;
input VAR18 ;
input VAR11 ;
input VAR2 ;
wire VAR10 ;
wire VAR9 ;
wire VAR1;
not VAR7 (VAR9 , VAR6 );
VAR13... | apache-2.0 |
Murailab-arch/magukara | cores/ipexpress/asfifo9_4.v | 19,970 | module MODULE1 (VAR232, VAR341, VAR334, VAR98, VAR352, VAR308, VAR379, VAR11,
VAR125, VAR205);
input wire [8:0] VAR232;
input wire VAR341;
input wire VAR334;
input wire VAR98;
input wire VAR352;
input wire VAR308;
input wire VAR379;
output wire [8:0] VAR11;
output wire VAR125;
output wire VAR205;
wire VAR377;
wire VAR2... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o311a/sky130_fd_sc_ms__o311a.pp.blackbox.v | 1,406 | module MODULE1 (
VAR7 ,
VAR8 ,
VAR10 ,
VAR3 ,
VAR5 ,
VAR1 ,
VAR6,
VAR9,
VAR4 ,
VAR2
);
output VAR7 ;
input VAR8 ;
input VAR10 ;
input VAR3 ;
input VAR5 ;
input VAR1 ;
input VAR6;
input VAR9;
input VAR4 ;
input VAR2 ;
endmodule | apache-2.0 |
ipburbank/Raster-Laser-Projector | src/Raster_Laser_Projector/synthesis/submodules/altera_up_video_clipper_add.v | 6,837 | module MODULE1 (
clk,
reset,
VAR20,
VAR7,
VAR23,
VAR10,
VAR36,
VAR18,
VAR31,
VAR35,
VAR22,
VAR25,
VAR16,
VAR27
);
parameter VAR2 = 15; parameter VAR3 = 0;
parameter VAR1 = 640; parameter VAR30 = 480; parameter VAR37 = 9; parameter VAR4 = 8;
parameter VAR14 = 0;
parameter VAR34 = 0;
parameter VAR15 = 0;
parameter VAR8 =... | gpl-3.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_comm_link/bsg_source_sync_channel_control_master.v | 17,361 | module MODULE1 #(parameter VAR21( VAR25 )
, parameter VAR55 = 6
, parameter VAR64 = 6
, parameter VAR43 = 5'b0
, parameter VAR18 = 5
, parameter VAR49 = 1
)
( input VAR20
, input VAR41
, input [VAR51(VAR18+1)-1:0] VAR23
, input VAR65
, input VAR54
, output VAR12
, output [VAR25+1-1:0] VAR60
, input VAR28
, output [VAR1... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a32o/sky130_fd_sc_ls__a32o.pp.blackbox.v | 1,458 | module MODULE1 (
VAR4 ,
VAR10 ,
VAR7 ,
VAR8 ,
VAR1 ,
VAR3 ,
VAR9,
VAR6,
VAR2 ,
VAR5
);
output VAR4 ;
input VAR10 ;
input VAR7 ;
input VAR8 ;
input VAR1 ;
input VAR3 ;
input VAR9;
input VAR6;
input VAR2 ;
input VAR5 ;
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_k7_x4_250/source/pcie_7x_v1_3_axi_basic_rx_pipeline.v | 27,296 | module MODULE1 #(
parameter VAR65 = 128, parameter VAR67 = "VAR21", parameter VAR26 = 1,
parameter VAR45 = (VAR65 == 128) ? 2 : 1, parameter VAR77 = VAR65 / 8 ) (
output reg [VAR65-1:0] VAR64, output reg VAR28, input VAR9, output [VAR77-1:0] VAR12, output VAR56, output reg [21:0] VAR74,
input [VAR65-1:0] VAR20, input V... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfxbp/sky130_fd_sc_ls__sdfxbp.behavioral.v | 2,477 | module MODULE1 (
VAR26 ,
VAR12,
VAR27,
VAR24 ,
VAR7,
VAR2
);
output VAR26 ;
output VAR12;
input VAR27;
input VAR24 ;
input VAR7;
input VAR2;
supply1 VAR19;
supply0 VAR10;
supply1 VAR6 ;
supply0 VAR22 ;
wire VAR16 ;
wire VAR14 ;
reg VAR20 ;
wire VAR23 ;
wire VAR5;
wire VAR17;
wire VAR13;
wire VAR8 ;
wire VAR3 ;
wire VAR... | apache-2.0 |
cpulabs/mist1032sa | src/core/core.v | 4,951 | module MODULE1 #(
parameter VAR43 = 32'h0
)(
input wire VAR45,
input wire VAR28,
output wire VAR49,
output wire VAR50,
output wire [5:0] VAR20,
output wire VAR37,
output wire VAR5,
output wire [1:0] VAR18,
output wire VAR52,
input wire VAR23,
output wire [1:0] VAR9,
output wire [31:0] VAR39,
output wire [31:0] VAR26,
i... | bsd-2-clause |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/ASIC_NTNU/integracion_fisica/front_end/source/SVD_unit.v | 1,298 | module MODULE1(VAR4, VAR16, VAR10, VAR6, VAR13, VAR14, VAR7);
input [VAR15-1:0] VAR4;
output reg VAR16, VAR10, VAR6, VAR13, VAR14;
output reg [32:0] VAR7;
reg VAR12;
reg [VAR11-1:0] VAR2;
reg [VAR8-1:0] VAR9;
reg VAR5, VAR3, VAR1;
always @(VAR4) begin
VAR12 = VAR4[VAR15-1]; VAR2 = VAR4[(VAR15-2):(VAR15-VAR11-1)]; VAR9 ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/inputiso0n/sky130_fd_sc_lp__inputiso0n.pp.blackbox.v | 1,389 | module MODULE1 (
VAR6 ,
VAR7 ,
VAR4,
VAR2 ,
VAR3 ,
VAR1 ,
VAR5
);
output VAR6 ;
input VAR7 ;
input VAR4;
input VAR2 ;
input VAR3 ;
input VAR1 ;
input VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nand4/sky130_fd_sc_hd__nand4_2.v | 2,253 | module MODULE2 (
VAR1 ,
VAR9 ,
VAR5 ,
VAR3 ,
VAR11 ,
VAR6,
VAR2,
VAR7 ,
VAR10
);
output VAR1 ;
input VAR9 ;
input VAR5 ;
input VAR3 ;
input VAR11 ;
input VAR6;
input VAR2;
input VAR7 ;
input VAR10 ;
VAR8 VAR4 (
.VAR1(VAR1),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR11(VAR11),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR7(VAR7),
.VA... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_ddr_common/rtl/bw_io_ddr_4sig_clk_x2.v | 3,661 | module MODULE1(VAR3 ,VAR20 ,VAR33 ,
VAR28 ,VAR42 ,VAR24 ,VAR1 ,VAR36 ,
VAR21 ,VAR34 ,VAR10 ,VAR18 ,VAR9 ,VAR35
,VAR2 ,VAR12 ,VAR31 ,VAR32 ,VAR27 ,VAR26 ,
VAR38 ,VAR41 ,VAR39 ,VAR48 ,VAR22 ,
VAR44 ,VAR7 ,VAR13 ,VAR16 );
input [7:0] VAR28 ;
input [7:0] VAR42 ;
input [8:1] VAR10 ;
input [8:1] VAR35 ;
input [8:1] VAR26 ;
i... | gpl-2.0 |
nextseto/Verilog-Projects | Project 2 – Combinational Logic/four_bit_ripple_adder/four_bit_adder.v | 1,204 | module MODULE1
(
input [3:0] VAR4,
input [3:0] VAR9,
output [4:0] VAR10
);
wire VAR11;
assign VAR11 = 1'b0;
MODULE2 MODULE2 (VAR4[0], VAR9[0], VAR11, VAR10[0], VAR6);
MODULE2 MODULE1 (VAR4[1], VAR9[1], VAR6, VAR10[1], VAR2);
MODULE2 MODULE4 (VAR4[2], VAR9[2], VAR2, VAR10[2], VAR3);
MODULE2 MODULE3 (VAR4[3], VAR9[3], VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlclkp/sky130_fd_sc_hs__dlclkp.pp.blackbox.v | 1,216 | module MODULE1 (
VAR5,
VAR2,
VAR3 ,
VAR4,
VAR1
);
output VAR5;
input VAR2;
input VAR3 ;
input VAR4;
input VAR1;
endmodule | apache-2.0 |
chahuja/hilbert-fpga | mpuc541.v | 1,722 | module MODULE1 ( VAR5,VAR7 ,VAR13, VAR16,VAR21,VAR11 ,VAR2 ,VAR9 );
parameter VAR3 = 32;
input VAR5 ;
wire VAR5 ;
input VAR7 ;
wire VAR7 ;
input VAR13; input VAR16 ; wire VAR16 ;
input [VAR3-1:0] VAR21 ;
wire signed [VAR3-1:0] VAR21 ;
input [VAR3-1:0] VAR11 ;
wire signed [VAR3-1:0] VAR11 ;
output [VAR3-1:0] VAR2 ;
reg ... | gpl-2.0 |
EEorCS/Taximeter_on_Altera_DE2 | Verilog_sources/taxi_top.v | 1,824 | module MODULE1 (reset, pulse, clk,
VAR36, VAR40, VAR27,
VAR45, VAR31,
VAR30, VAR41, VAR37);
input reset;
input pulse,clk;
output [6:0] VAR36, VAR40, VAR27,
VAR45, VAR31,
VAR30, VAR41, VAR37;
wire [15:0] VAR14; wire [15:0] VAR33;
wire [15:0] VAR35;
wire [11:0] VAR44;
wire [11:0] VAR15; wire [11:0] VAR1;
wire VAR3;
wire ... | gpl-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_1/embedded_lab_1.cache/ip/2017.2/8a4f3f63fe715aee/zynq_design_1_xbar_0_stub.v | 5,932 | module MODULE1(VAR15, VAR78, VAR53, VAR12,
VAR59, VAR13, VAR10, VAR8, VAR3, VAR50,
VAR42, VAR64, VAR67, VAR66, VAR62, VAR26,
VAR60, VAR20, VAR40, VAR23, VAR51, VAR7, VAR38,
VAR76, VAR9, VAR27, VAR47, VAR16, VAR22,
VAR77, VAR30, VAR44, VAR65, VAR72, VAR55, VAR39,
VAR70, VAR32, VAR28, VAR25, VAR29, VAR37, VAR68,
VAR58, V... | mit |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/fetch/fetch_db.v | 9,296 | module MODULE1 (
clk ,
VAR55 ,
VAR43 ,
VAR31 ,
VAR57 ,
VAR52 ,
VAR20 ,
VAR13 ,
VAR30 ,
VAR33 ,
VAR17 ,
VAR49 ,
VAR1 ,
VAR47 ,
VAR64 ,
VAR58 ,
VAR50 ,
VAR46 ,
VAR3 ,
VAR44 ,
VAR54 ,
VAR22
);
input [1-1:0] clk ; input [1-1:0] VAR55 ;
input [1-1:0] VAR43 ;
input [1-1:0] VAR31 ; input [5-1:0] VAR57 ; input [5-1:0] VAR52 ; ... | gpl-3.0 |
rkrajnc/minimig-mist | rtl/minimig/gary.v | 6,994 | module MODULE1
(
input [23:1] VAR20, input [20:1] VAR3, output [18:1] VAR35, input [15:0] VAR39,
output [15:0] VAR8,
input [15:0] VAR1,
output [15:0] VAR18,
input [15:0] VAR36,
output [15:0] VAR24,
input VAR25,
input VAR17, input VAR11, input VAR27, input VAR33,
input VAR6, input VAR37, input VAR19, output VAR29, outpu... | gpl-3.0 |
fbalakirev/red-pitaya-notes | cores/axis_adder_v1_0/axis_adder.v | 1,384 | module MODULE1 #
(
parameter integer VAR6 = 32,
parameter VAR7 = "VAR9"
)
(
input wire VAR16,
output wire VAR5,
input wire [VAR6-1:0] VAR18,
input wire VAR13,
output wire VAR14,
input wire [VAR6-1:0] VAR15,
input wire VAR19,
input wire VAR17,
output wire [VAR6-1:0] VAR10,
output wire VAR1
);
wire [VAR6-1:0] VAR8;
wire ... | mit |
lloves/Sora | FPGA/MIMO/rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/old/RCB_FRL_STATUS_IN.v | 5,843 | module MODULE1(
input VAR13,
input VAR9,
output reg VAR1, output reg VAR16, output reg VAR14, input VAR7,
output reg VAR5 );
reg VAR8;
reg VAR12;
reg VAR4; reg [2:0] VAR17;
reg [7:0] VAR15;
parameter VAR10 = 2'b00;
parameter VAR6 = 2'b01;
parameter VAR3 = 2'b10;
parameter VAR11 = 2'b11;
reg [1:0] VAR2;
always @ ( neged... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlrbn/sky130_fd_sc_lp__dlrbn_2.v | 2,480 | module MODULE1 (
VAR2 ,
VAR4 ,
VAR9,
VAR11 ,
VAR5 ,
VAR6 ,
VAR10 ,
VAR7 ,
VAR8
);
output VAR2 ;
output VAR4 ;
input VAR9;
input VAR11 ;
input VAR5 ;
input VAR6 ;
input VAR10 ;
input VAR7 ;
input VAR8 ;
VAR3 VAR1 (
.VAR2(VAR2),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR11(VAR11),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR7(VAR7)... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfrbp/sky130_fd_sc_ms__sdfrbp.blackbox.v | 1,485 | module MODULE1 (
VAR10 ,
VAR9 ,
VAR6 ,
VAR5 ,
VAR11 ,
VAR4 ,
VAR2
);
output VAR10 ;
output VAR9 ;
input VAR6 ;
input VAR5 ;
input VAR11 ;
input VAR4 ;
input VAR2;
supply1 VAR1;
supply0 VAR8;
supply1 VAR3 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/isolatch/sky130_fd_sc_lp__isolatch_lp.v | 2,305 | module MODULE2 (
VAR1 ,
VAR6 ,
VAR4,
VAR10 ,
VAR2 ,
VAR7 ,
VAR9 ,
VAR8
);
output VAR1 ;
input VAR6 ;
input VAR4;
input VAR10 ;
input VAR2 ;
input VAR7 ;
input VAR9 ;
input VAR8 ;
VAR5 VAR3 (
.VAR1(VAR1),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR8(VAR8)
);
endmodule
module MODU... | apache-2.0 |
SymbiFlow/icestorm | icetime/cells.v | 13,863 | module MODULE52(VAR54, VAR60, VAR64);
input VAR54;
input VAR60;
output VAR64;
endmodule
module MODULE43(VAR10, VAR64);
input VAR10;
output VAR64;
endmodule
module MODULE121(VAR10, VAR64);
input VAR10;
output VAR64;
endmodule
module MODULE27(VAR10, VAR64);
input VAR10;
output VAR64;
endmodule
module MODULE80(VAR10, VAR6... | isc |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/system/synthesis/submodules/system_acl_iface_hps_hps_io.v | 6,777 | module MODULE1 (
output wire [14:0] VAR1, output wire [2:0] VAR26, output wire VAR22, output wire VAR37, output wire VAR29, output wire VAR42, output wire VAR33, output wire VAR41, output wire VAR3, output wire VAR2, inout wire [31:0] VAR15, inout wire [3:0] VAR31, inout wire [3:0] VAR19, output wire VAR8, output wire ... | mit |
Ribeiro/sd2snes | verilog/sd2snes_cx4/msu.v | 5,244 | module MODULE1(
input VAR4,
input enable,
input [13:0] VAR2,
input [7:0] VAR33,
input VAR7,
input [2:0] VAR27,
input [7:0] VAR12,
output [7:0] VAR46,
input VAR32,
input VAR29,
input VAR43,
output [6:0] VAR37,
output [7:0] VAR5,
output VAR22,
output [31:0] VAR1,
output [15:0] VAR39,
input [5:0] VAR11,
input [5:0] VAR20,... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | models/udp_dff_p_pp_pg_n/sky130_fd_sc_ms__udp_dff_p_pp_pg_n.symbol.v | 1,413 | module MODULE1 (
input VAR2 ,
output VAR1 ,
input VAR5 ,
input VAR6,
input VAR3 ,
input VAR4
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/mux2i/sky130_fd_sc_hd__mux2i.behavioral.v | 1,654 | module MODULE1 (
VAR4 ,
VAR2,
VAR9,
VAR7
);
output VAR4 ;
input VAR2;
input VAR9;
input VAR7 ;
supply1 VAR5;
supply0 VAR1;
supply1 VAR6 ;
supply0 VAR10 ;
wire VAR11;
VAR3 VAR12 (VAR11, VAR2, VAR9, VAR7 );
buf VAR8 (VAR4 , VAR11);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl.pp.symbol.v | 1,427 | module MODULE1 (
input VAR4 ,
output VAR1 ,
input VAR5,
input VAR3 ,
input VAR2 ,
input VAR6 ,
input VAR7
);
endmodule | apache-2.0 |
sh-chris110/chris | FPGA/chris.system_ok/db/ip/soc_design/submodules/soc_design_SystemID.v | 2,203 | module MODULE1 (
address,
VAR2,
VAR1,
VAR3
)
;
output [ 31: 0] VAR3;
input address;
input VAR2;
input VAR1;
wire [ 31: 0] VAR3;
assign VAR3 = address ? 1499934493 : 255;
endmodule | gpl-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig37/mig_37/example_design/rtl/controller/bank_cntrl.v | 25,516 | module MODULE1 #
(
parameter VAR131 = 100,
parameter VAR32 = "VAR33",
parameter VAR99 = 3,
parameter VAR62 = 2,
parameter VAR59 = "8",
parameter VAR90 = 12,
parameter VAR47 = 5,
parameter VAR15 = 8,
parameter VAR142 = "VAR137",
parameter VAR132 = "VAR41",
parameter VAR128 = 4,
parameter VAR18 = 4,
parameter VAR139 = 2,... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/probe_p/sky130_fd_sc_hd__probe_p.behavioral.v | 1,360 | module MODULE1 (
VAR5,
VAR4
);
output VAR5;
input VAR4;
supply1 VAR6;
supply0 VAR7;
supply1 VAR3 ;
supply0 VAR9 ;
wire VAR2;
buf VAR8 (VAR2, VAR4 );
buf VAR1 (VAR5 , VAR2 );
endmodule | apache-2.0 |
disaderp/automatic-chainsaw | CPU/debugging/Buff.v | 1,795 | module MODULE2 #(parameter VAR5 = 16)(
input clk,
input [VAR5-1:0] in,
output reg [VAR5-1:0] out,
input read,
input VAR3,
output reg VAR4,
output VAR2);
reg [VAR5-1:0] VAR6 [20:0];
reg [6:0] VAR8;
reg [15:0] counter = 0;
reg VAR7 = 0;
reg [6:0] VAR10 = 0;
assign VAR2 = (VAR10 > 0);
always @(posedge clk) begin
if (count... | gpl-3.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/FifoBuffer.v | 2,283 | module MODULE1(
din,
VAR15,
VAR2,
rst,
VAR11,
VAR5,
dout,
VAR4,
VAR16);
input [31 : 0] din;
input VAR15;
input VAR2;
input rst;
input VAR11;
input VAR5;
output [31 : 0] dout;
output VAR4;
output VAR16;
wire VAR3, VAR14;
VAR10 VAR7 (.din(din), .VAR15(VAR15), .VAR2(VAR2), .rst(rst), .VAR11(VAR11), .VAR5(VAR5), .dout(dout... | gpl-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/fifo/fifo72_to_fifo36.v | 3,043 | module MODULE1
(input clk, input reset, input VAR21,
input [71:0] VAR8,
input VAR15,
output VAR2,
output [35:0] VAR4,
output VAR32,
input VAR6 );
wire [35:0] VAR16;
wire VAR14, VAR29;
wire [71:0] VAR28;
wire VAR25, VAR23;
VAR1 #(.VAR11(72)) VAR30
(.clk(clk),.reset(reset),.VAR21(VAR21),
.VAR18(VAR8), .VAR33(VAR15), .VAR... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/nand4/gf180mcu_fd_sc_mcu9t5v0__nand4_2.behavioral.v | 1,341 | module MODULE1( VAR2, VAR1, VAR7, VAR3, VAR4 );
input VAR4, VAR3, VAR7, VAR1;
output VAR2;
VAR5 VAR8(.VAR2(VAR2),.VAR1(VAR1),.VAR7(VAR7),.VAR3(VAR3),.VAR4(VAR4));
VAR5 VAR6(.VAR2(VAR2),.VAR1(VAR1),.VAR7(VAR7),.VAR3(VAR3),.VAR4(VAR4)); | apache-2.0 |
DSDL2016/project2 | source/synthesizer/wave_gen_string.v | 1,668 | module MODULE1(
input [5:0] VAR2,
output reg [15:0]VAR1
);
always@(VAR2[5:0])
begin
case(VAR2[5:0])
0 :VAR1=16'h0;
1 :VAR1=16'h0;
2 :VAR1=16'h0;
3 :VAR1=16'h0;
4 :VAR1=16'h0;
5 :VAR1=16'h0;
6 :VAR1=16'h246;
7 :VAR1=16'hC36;
8 :VAR1=16'hCFC;
9 :VAR1=16'hC17;
10 :VAR1=16'hAEE;
11 :VAR1=16'hAA0;
12 :VAR1=16'hBB8;
13 :VAR1... | mit |
monotone-RK/FACE | IEICE-Trans/8-way/src/riffa/tx_multiplexer_64.v | 18,582 | module MODULE1
parameter VAR59 = 128,
parameter VAR52 = 12,
parameter VAR111 = 5, parameter VAR30 = "VAR12"
)
(
input VAR55,
input VAR6,
input [VAR52-1:0] VAR48, input [(VAR52*VAR5)-1:0] VAR37, input [(VAR52*VAR7)-1:0] VAR75, input [(VAR52*VAR59)-1:0] VAR94, output [VAR52-1:0] VAR84, output [VAR52-1:0] VAR34,
input [VA... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/ccx/rtl/cpx_databuf_ca2.v | 1,883 | module MODULE1(
VAR1,
VAR2
);
output [144:0] VAR1;
input [144:0] VAR2;
assign VAR1 = VAR2;
endmodule | gpl-2.0 |
asicguy/gplgpu | hdl/altera_project/fifo_238x128/fifo_238x128_bb.v | 6,096 | module MODULE1 (
VAR1,
VAR2,
VAR4,
VAR5,
VAR9,
VAR6,
VAR7,
VAR10,
VAR3,
VAR8);
input [237:0] VAR1;
input VAR2;
input VAR4;
input VAR5;
input VAR9;
output [237:0] VAR6;
output VAR7;
output VAR10;
output VAR3;
output [6:0] VAR8;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a311oi/sky130_fd_sc_ms__a311oi.pp.blackbox.v | 1,429 | module MODULE1 (
VAR10 ,
VAR4 ,
VAR5 ,
VAR2 ,
VAR6 ,
VAR1 ,
VAR8,
VAR3,
VAR7 ,
VAR9
);
output VAR10 ;
input VAR4 ;
input VAR5 ;
input VAR2 ;
input VAR6 ;
input VAR1 ;
input VAR8;
input VAR3;
input VAR7 ;
input VAR9 ;
endmodule | apache-2.0 |
andrewandrepowell/axiplasma | hdl/projects/Nexys4/bd/mig_wrap/ip/mig_wrap_auto_cc_0/mig_wrap_auto_cc_0_stub.v | 5,776 | module MODULE1(VAR45, VAR64, VAR4,
VAR42, VAR77, VAR33, VAR28, VAR1, VAR11,
VAR79, VAR44, VAR60, VAR23, VAR61, VAR8,
VAR52, VAR39, VAR48, VAR56, VAR17, VAR41, VAR46,
VAR16, VAR70, VAR31, VAR76, VAR67, VAR57,
VAR53, VAR19, VAR78, VAR5, VAR50, VAR68,
VAR3, VAR38, VAR14, VAR25, VAR65, VAR55, VAR47,
VAR69, VAR82, VAR21, VA... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/xor3/gf180mcu_fd_sc_mcu7t5v0__xor3_4.behavioral.pp.v | 2,576 | module MODULE1( VAR4, VAR9, VAR5, VAR1, VAR2, VAR7 );
input VAR9, VAR4, VAR5;
inout VAR2, VAR7;
output VAR1;
VAR3 VAR6(.VAR4(VAR4),.VAR9(VAR9),.VAR5(VAR5),.VAR1(VAR1),.VAR2(VAR2),.VAR7(VAR7));
VAR3 VAR8(.VAR4(VAR4),.VAR9(VAR9),.VAR5(VAR5),.VAR1(VAR1),.VAR2(VAR2),.VAR7(VAR7)); | apache-2.0 |
tommythorn/yari | BeMicro/rtl/toplevel.v | 5,079 | module MODULE1(input clk, output reg [ 7:0] VAR50,
output VAR57,
output VAR61,
inout [15:0] VAR60,
output VAR33,
output VAR5,
output VAR58,
output VAR6,
output [17:0] VAR46,
input VAR38,
output VAR34
);
parameter VAR29 = 27'd50000000; parameter VAR7 = 230400;
wire VAR11 = 0 ;
reg [26:0] VAR53 = VAR29;
wire reset = ~VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o32ai/sky130_fd_sc_hdll__o32ai_1.v | 2,457 | module MODULE1 (
VAR12 ,
VAR3 ,
VAR1 ,
VAR10 ,
VAR9 ,
VAR5 ,
VAR11,
VAR8,
VAR6 ,
VAR7
);
output VAR12 ;
input VAR3 ;
input VAR1 ;
input VAR10 ;
input VAR9 ;
input VAR5 ;
input VAR11;
input VAR8;
input VAR6 ;
input VAR7 ;
VAR2 VAR4 (
.VAR12(VAR12),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR1... | apache-2.0 |
YurongYou/MIPS_CPU | BranchControl.v | 2,893 | module MODULE1 (
input rst,
input[VAR9-1:0] VAR16,
input[VAR24-1:0] VAR19,
input[1:0] VAR6,
input[1:0] VAR12,
input[VAR15-1:0] VAR13,
input[VAR15-1:0] VAR22,
input[VAR15-1:0] VAR26,
input[VAR15-1:0] VAR1,
input[VAR15-1:0] VAR8,
output reg[VAR9-1:0] VAR30,
output reg VAR17,
output reg VAR21
);
reg[VAR15-1:0] VAR23;
reg[... | mpl-2.0 |
eleqian/WiDSO | CPLD/DSO_LA/src/la_trig.v | 1,400 | module MODULE1(VAR12, clk, din, VAR11, VAR7, VAR9, VAR13, VAR8);
input VAR12;
input clk;
input [7:0] din;
input [7:0] VAR11;
input [7:0] VAR7;
input [2:0] VAR9;
input VAR13;
output VAR8;
reg VAR6;
wire VAR4;
wire VAR5;
wire VAR3;
wire [7:0] VAR1;
wire [7:0] VAR2;
wire VAR10;
assign VAR4 = din[VAR9];
always @(posedge cl... | mit |
alexforencich/hdg2000 | fpga/lib/axis/rtl/axis_async_fifo_64.v | 6,149 | module MODULE1 #
(
parameter VAR20 = 12,
parameter VAR11 = 64,
parameter VAR36 = (VAR11/8)
)
(
input wire VAR4,
input wire VAR34,
input wire [VAR11-1:0] VAR35,
input wire [VAR36-1:0] VAR28,
input wire VAR22,
output wire VAR29,
input wire VAR15,
input wire VAR21,
input wire VAR38,
input wire VAR10,
output wire [VAR11-1:... | mit |
freecores/eco32 | fpga/src/busctrl/busctrl.v | 5,873 | module MODULE1(VAR8, VAR45, VAR3, VAR38,
VAR41, VAR24, VAR32,
VAR27, VAR56, VAR34, VAR2,
VAR60, VAR61, VAR33,
VAR18, VAR29, VAR51, VAR40,
VAR55, VAR35,
VAR5, VAR21, VAR58,
VAR37, VAR13, VAR54,
VAR47, VAR28, VAR30,
VAR4, VAR9, VAR63,
VAR17, VAR50, VAR16,
VAR52, VAR23, VAR22,
VAR20, VAR19, VAR62,
VAR31, VAR48, VAR15,
VAR... | bsd-2-clause |
davidjabon/Verilog | Binary_to_BCD/binary_to_BCD_fourteen_bit.v | 2,314 | module MODULE1(
input [13:0] in,
output [3:0] VAR75,
output [3:0] VAR56,
output [3:0] VAR64,
output [3:0] VAR70
);
wire [3:0] VAR46,VAR77,VAR48,VAR1,VAR38,VAR62,VAR59,VAR4,VAR74,VAR63,VAR5,VAR29,VAR50,VAR24,VAR16,VAR68,VAR30,VAR14,VAR49,VAR31,VAR2,VAR69,VAR79,VAR6,VAR78;
wire [3:0] VAR8,VAR55,VAR42,VAR10,VAR37,VAR25,VA... | gpl-2.0 |
VCTLabs/DE1_SOC_Linux_FB | soc_system/submodules/altera_avalon_st_handshake_clock_crosser.v | 7,547 | module MODULE1
parameter VAR18 = 8,
VAR33 = 8,
VAR17 = 0,
VAR30 = 0,
VAR12 = 1,
VAR15 = 0,
VAR6 = 1,
VAR10 = 2,
VAR1 = 2,
VAR40 = 1,
VAR38 = VAR18 / VAR33,
VAR13 = VAR41(VAR38)
)
(
input VAR22,
input VAR5,
input VAR16,
input VAR29,
output VAR36,
input VAR43,
input [VAR18 - 1 : 0] VAR21,
input [VAR12 - 1 : 0] VAR8,
inpu... | epl-1.0 |
ultraembedded/riscv | core/riscv/riscv_core.v | 22,201 | module MODULE1
parameter VAR7 = 1
,parameter VAR107 = 0
,parameter VAR16 = 0
,parameter VAR354 = 1
,parameter VAR190 = 1
,parameter VAR193 = 0
,parameter VAR27 = 0
,parameter VAR41 = 32'h80000000
,parameter VAR92 = 32'h8fffffff
)
(
input VAR355
,input VAR54
,input [ 31:0] VAR344
,input VAR232
,input VAR311
,input VAR17... | bsd-3-clause |
shailcoolboy/Warp-Trinity | PlatformSupport/CustomPeripherals/pcores/eeprom_v1_07_a/hdl/verilog/user_logic.v | 11,291 | module MODULE1
(
VAR8,
VAR11,
VAR19,
VAR37,
VAR49,
VAR9,
VAR48,
VAR43,
VAR41,
VAR39,
VAR10,
VAR23,
VAR53,
VAR50,
VAR31,
VAR26,
VAR5,
VAR51,
VAR54,
VAR15,
VAR52,
VAR40,
VAR25,
VAR46,
VAR20, VAR34, VAR2, VAR60, VAR4, VAR3, VAR45, VAR17, VAR6, VAR21, VAR47 );
parameter VAR28 = 32;
parameter VAR36 = 32;
parameter VAR18 = 1... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o311a/sky130_fd_sc_lp__o311a_0.v | 2,422 | module MODULE1 (
VAR6 ,
VAR1 ,
VAR9 ,
VAR12 ,
VAR8 ,
VAR7 ,
VAR3,
VAR4,
VAR10 ,
VAR11
);
output VAR6 ;
input VAR1 ;
input VAR9 ;
input VAR12 ;
input VAR8 ;
input VAR7 ;
input VAR3;
input VAR4;
input VAR10 ;
input VAR11 ;
VAR2 VAR5 (
.VAR6(VAR6),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR12(VAR12),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR3(V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o2111ai/sky130_fd_sc_hd__o2111ai_1.v | 2,461 | module MODULE2 (
VAR9 ,
VAR3 ,
VAR4 ,
VAR5 ,
VAR11 ,
VAR1 ,
VAR6,
VAR7,
VAR10 ,
VAR8
);
output VAR9 ;
input VAR3 ;
input VAR4 ;
input VAR5 ;
input VAR11 ;
input VAR1 ;
input VAR6;
input VAR7;
input VAR10 ;
input VAR8 ;
VAR2 VAR12 (
.VAR9(VAR9),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR11(VAR11),
.VAR1(VAR1),
.VAR6(VA... | apache-2.0 |
alexforencich/verilog-flowgen | rtl/fg_burst_gen.v | 9,974 | module MODULE1 #(
parameter VAR25 = 5,
parameter VAR7 = 8,
parameter VAR26 = 8
)
(
input wire clk,
input wire rst,
input wire VAR17,
output wire VAR23,
input wire [VAR7-1:0] VAR37,
input wire [15:0] VAR28,
input wire [15:0] VAR12,
input wire [31:0] VAR41,
input wire [31:0] VAR24,
output wire VAR39,
input wire VAR9,
out... | mit |
alexforencich/verilog-ethernet | example/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v | 21,727 | module MODULE1 (
input wire VAR22,
input wire VAR302,
output wire [1:0] VAR110,
output wire VAR311,
output wire [1:0] VAR6,
input wire [1:0] VAR104,
output wire VAR253,
output wire VAR191,
input wire VAR102,
input wire VAR77,
output wire VAR119,
output wire VAR51,
input wire VAR242,
input wire VAR168,
output wire VAR12... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/einvn/sky130_fd_sc_lp__einvn.behavioral.v | 1,314 | module MODULE1 (
VAR6 ,
VAR7 ,
VAR4
);
output VAR6 ;
input VAR7 ;
input VAR4;
supply1 VAR3;
supply0 VAR8;
supply1 VAR1 ;
supply0 VAR5 ;
notif0 VAR2 (VAR6 , VAR7, VAR4 );
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/sdffsnq/gf180mcu_fd_sc_mcu9t5v0__sdffsnq_4.behavioral.v | 18,884 | module MODULE1( VAR239, VAR182, VAR96, VAR55, VAR295, VAR179 );
input VAR55, VAR96, VAR239, VAR295, VAR182;
output VAR179;
reg VAR303;
VAR189 VAR92(.VAR239(VAR239),.VAR182(VAR182),.VAR96(VAR96),.VAR55(VAR55),.VAR295(VAR295),.VAR179(VAR179),.VAR303(VAR303));
VAR189 VAR177(.VAR239(VAR239),.VAR182(VAR182),.VAR96(VAR96),.V... | apache-2.0 |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/axi_data_fifo_v2_1/hdl/verilog/axi_data_fifo_v2_1_fifo_gen.v | 15,071 | module MODULE1 #(
parameter VAR178 = "VAR319",
parameter integer VAR58 = 1,
parameter integer VAR361 = 3,
parameter integer VAR11 = 5,
parameter integer VAR75 = 64,
parameter VAR213 = "lut"
)(
clk,
rst,
VAR378,
VAR414,
VAR335,
VAR146,
VAR72,
VAR172,
VAR226,
VAR76);
input clk;
input VAR378;
input VAR72;
input rst;
input... | bsd-2-clause |
elegabriel/myzju | junior1/CA/mips_pipeline2/code/cpu_ctl.v | 2,622 | module MODULE1(VAR31,VAR37,VAR39,VAR35,VAR36,VAR6,VAR2,VAR8,VAR9,VAR23,VAR24,VAR13,VAR16,VAR32,VAR12
);
input wire [5:0] VAR31, VAR37;
input wire VAR39;
output wire VAR35,VAR36,VAR6,VAR2,VAR8,VAR9,VAR23,VAR24,VAR13,VAR16,VAR32;
output wire [4:0] VAR12;
wire VAR25, VAR10, VAR26, VAR30, VAR5; wire VAR15,VAR19,VAR22,VAR21... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sedfxbp/sky130_fd_sc_ls__sedfxbp_2.v | 2,564 | module MODULE1 (
VAR8 ,
VAR2 ,
VAR12 ,
VAR7 ,
VAR11 ,
VAR6 ,
VAR10 ,
VAR13,
VAR3,
VAR9 ,
VAR5
);
output VAR8 ;
output VAR2 ;
input VAR12 ;
input VAR7 ;
input VAR11 ;
input VAR6 ;
input VAR10 ;
input VAR13;
input VAR3;
input VAR9 ;
input VAR5 ;
VAR4 VAR1 (
.VAR8(VAR8),
.VAR2(VAR2),
.VAR12(VAR12),
.VAR7(VAR7),
.VAR11(VAR... | apache-2.0 |
alanachtenberg/CSCE-350 | Project 2/IdealMemory.v | 1,596 | module MODULE2 (VAR1, VAR6);
parameter VAR9 = 10;
parameter VAR8 = 1024, VAR2 = 32;
input [VAR2-1:0] VAR1;
output [VAR2-1:0] VAR6;
reg [VAR2-1:0] VAR6;
reg [VAR2-1:0] VAR12[0:VAR8-1];
always
endmodule
module MODULE1 (VAR1, VAR3, VAR5, VAR11, VAR4, VAR7);
parameter VAR9 = 10, VAR14 = 10;
parameter VAR8 = 1024, VAR2 = 32... | gpl-2.0 |
asicguy/gplgpu | hdl/mc_graph/mc_arb.v | 30,387 | module MODULE1
parameter VAR163 = 16
)
(
input VAR121,
input VAR39,
input [27:0] VAR118,
input [4:0] VAR56,
input VAR18,
input VAR2,
input [31:0] VAR87,
input [3:0] VAR125,
input [1:0] VAR72,
input VAR156,
input [31:0] VAR54,
input VAR96,
input [66:0] VAR127,
input VAR100,
input [6:0] VAR112,
input [4:0] VAR60,
input [... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/fill/sky130_fd_sc_ls__fill.functional.pp.v | 1,147 | module MODULE1 (
VAR2,
VAR4,
VAR3 ,
VAR1
);
input VAR2;
input VAR4;
input VAR3 ;
input VAR1 ;
endmodule | apache-2.0 |
ShepardSiegel/ocpi | rtl/mkBiasWorker32B.v | 58,918 | module MODULE1(VAR69,
VAR31,
VAR123,
VAR73,
VAR145,
VAR47,
VAR137,
VAR222,
VAR285,
VAR327,
VAR244,
VAR107,
VAR276,
VAR18,
VAR79,
VAR149,
VAR39,
VAR122,
VAR6,
VAR336,
VAR14,
VAR19,
VAR208,
VAR98,
VAR306,
VAR29,
VAR339,
VAR236,
VAR8,
VAR22,
VAR193,
VAR116);
parameter [0 : 0] VAR232 = 1'b0;
input VAR69;
input VAR31;
input... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand2/sky130_fd_sc_ls__nand2_4.v | 2,097 | module MODULE2 (
VAR7 ,
VAR4 ,
VAR1 ,
VAR5,
VAR6,
VAR9 ,
VAR3
);
output VAR7 ;
input VAR4 ;
input VAR1 ;
input VAR5;
input VAR6;
input VAR9 ;
input VAR3 ;
VAR2 VAR8 (
.VAR7(VAR7),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR3(VAR3)
);
endmodule
module MODULE2 (
VAR7,
VAR4,
VAR1
);
output VAR7;
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/ebufn/sky130_fd_sc_hdll__ebufn_4.v | 2,164 | module MODULE2 (
VAR1 ,
VAR9 ,
VAR7,
VAR5,
VAR6,
VAR8 ,
VAR3
);
output VAR1 ;
input VAR9 ;
input VAR7;
input VAR5;
input VAR6;
input VAR8 ;
input VAR3 ;
VAR2 VAR4 (
.VAR1(VAR1),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR3(VAR3)
);
endmodule
module MODULE2 (
VAR1 ,
VAR9 ,
VAR7
);
output VAR1 ;... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/util_bsplit/util_bsplit.v | 3,929 | module MODULE1 (
VAR8,
VAR2,
VAR6,
VAR4,
VAR5,
VAR10,
VAR12,
VAR1,
VAR9);
parameter VAR11 = 1;
parameter VAR13 = 8;
localparam VAR3 = 9;
input [((VAR13*VAR11)-1):0] VAR8;
output [(VAR11-1):0] VAR2;
output [(VAR11-1):0] VAR6;
output [(VAR11-1):0] VAR4;
output [(VAR11-1):0] VAR5;
output [(VAR11-1):0] VAR10;
output [(VAR1... | gpl-3.0 |
GSejas/Karatsuba_FPU | Resultados/CORDIC/CORDIC_Arch3_Vivado/CORDIC_Arch3_Vivado.srcs/sources_1/imports/addsub/FSM_input_enable.v | 3,812 | module MODULE1(
input wire clk,
input wire rst,
input wire VAR10,
output reg VAR11,
output wire VAR6,
output reg VAR5
);
parameter [3:0] VAR2 = 3'd0,
VAR1 = 3'd1,
VAR14 = 3'd2,
VAR13 = 3'd3,
VAR12 = 3'd4,
VAR8= 3'd5,
VAR3 = 3'd6,
VAR9 = 3'd7;
reg [2:0] VAR4, VAR7;
always @(posedge clk, posedge rst)
if(rst)
VAR4 <= VAR2... | gpl-3.0 |
MarcoVogt/basil | firmware/modules/timestamp/timestamp.v | 1,846 | module MODULE1
parameter VAR20 = 16'h0000,
parameter VAR27 = 16'h0000,
parameter VAR5 = 16,
parameter VAR17 = 4'b0001
)(
input wire VAR15,
input wire [VAR5-1:0] VAR13,
inout wire [7:0] VAR11,
input wire VAR8,
input wire VAR24,
input wire VAR18,
input wire VAR29,
input wire VAR3,
input wire [63:0] VAR10,
output wire [63... | bsd-3-clause |
alexforencich/xfcp | lib/eth/lib/axis/rtl/arbiter.v | 4,984 | module MODULE1 #
(
parameter VAR21 = 4,
parameter VAR22 = 0,
parameter VAR28 = 0,
parameter VAR11 = 1,
parameter VAR2 = 0
)
(
input wire clk,
input wire rst,
input wire [VAR21-1:0] request,
input wire [VAR21-1:0] acknowledge,
output wire [VAR21-1:0] VAR30,
output wire VAR8,
output wire [VAR12(VAR21)-1:0] VAR15
);
reg [... | mit |
mithro/HDMI2USB | hdl/hdmi/hdmimatrix.v | 8,400 | module MODULE1 (
input wire VAR134, input wire [3:0] VAR52,
input wire [3:0] VAR94,
input wire [3:0] VAR89,
input wire [3:0] VAR28,
output wire [3:0] VAR36,
output wire [3:0] VAR147,
output wire [3:0] VAR153,
output wire [3:0] VAR78,
output wire VAR130, VAR42,
output wire VAR9, VAR41,
output wire VAR144, VAR63,
output ... | bsd-2-clause |
aj-michael/Digital-Systems | Pong/Phase1/pong.v | 1,162 | module MODULE1(
input VAR11,
input VAR6,
input VAR9,
output [2:0] VAR17,
output [2:0] VAR16,
output [1:0] VAR4,
output VAR3,
output VAR15
);
wire VAR13;
VAR14 VAR5(VAR11, VAR13);
reg VAR2;
always @(posedge VAR13) begin
VAR2 <= ~VAR2;
end
wire VAR7;
VAR8 VAR10(VAR7, VAR2);
wire [9:0] VAR12;
wire [9:0] VAR20;
VAR1 VAR21(... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/ebufn/sky130_fd_sc_hdll__ebufn_1.v | 2,164 | module MODULE2 (
VAR4 ,
VAR5 ,
VAR3,
VAR6,
VAR8,
VAR2 ,
VAR9
);
output VAR4 ;
input VAR5 ;
input VAR3;
input VAR6;
input VAR8;
input VAR2 ;
input VAR9 ;
VAR1 VAR7 (
.VAR4(VAR4),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR9(VAR9)
);
endmodule
module MODULE2 (
VAR4 ,
VAR5 ,
VAR3
);
output VAR4 ;... | apache-2.0 |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/or1200/or1200_dpram_32x32.v | 14,007 | module MODULE1(
VAR82, VAR166, VAR15, VAR10, VAR22, VAR59,
VAR117, VAR106, VAR119, VAR131, VAR124, VAR52
);
parameter VAR29 = 5;
parameter VAR65 = 32;
input VAR82; input VAR166; input VAR15; input VAR10; input [VAR29-1:0] VAR22; output [VAR65-1:0] VAR59; input VAR117; input VAR106; input VAR119; input VAR131; input [VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or4bb/sky130_fd_sc_ms__or4bb.functional.pp.v | 1,988 | module MODULE1 (
VAR16 ,
VAR10 ,
VAR14 ,
VAR17 ,
VAR3 ,
VAR7,
VAR15,
VAR5 ,
VAR4
);
output VAR16 ;
input VAR10 ;
input VAR14 ;
input VAR17 ;
input VAR3 ;
input VAR7;
input VAR15;
input VAR5 ;
input VAR4 ;
wire VAR8 ;
wire VAR11 ;
wire VAR2;
nand VAR9 (VAR8 , VAR3, VAR17 );
or VAR6 (VAR11 , VAR14, VAR10, VAR8 );
VAR1 VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfrtn/sky130_fd_sc_hd__dfrtn.pp.symbol.v | 1,436 | module MODULE1 (
input VAR6 ,
output VAR7 ,
input VAR2,
input VAR4 ,
input VAR1 ,
input VAR5 ,
input VAR8 ,
input VAR3
);
endmodule | apache-2.0 |
MIPSfpga/schoolMIPS | board/de0_cv/de0_cv.v | 2,331 | module MODULE1
(
input VAR53,
input VAR20,
inout VAR19,
input VAR30,
input VAR2,
input [ 3:0] VAR11,
input [ 9:0] VAR14,
output [ 9:0] VAR18,
output [ 6:0] VAR8,
output [ 6:0] VAR47,
output [ 6:0] VAR23,
output [ 6:0] VAR46,
output [ 6:0] VAR15,
output [ 6:0] VAR21,
output [12:0] VAR29,
output [ 1:0] VAR10,
output VAR2... | mit |
olgirard/openmsp430 | core/synthesis/actel/src/omsp_dbg_uart.v | 10,482 | module MODULE1 (
VAR32, VAR13, VAR7, VAR27, VAR26,
VAR5, VAR49, VAR33, VAR25, VAR44, VAR20, VAR23, VAR31, VAR8, VAR46 );
output [5:0] VAR32; output [15:0] VAR13; output VAR7; output VAR27; output VAR26;
input [15:0] VAR5; input VAR49; input VAR33; input VAR25; input VAR44; input VAR20; input VAR23; input VAR31; input V... | bsd-3-clause |
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