repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
ipburbank/Raster-Laser-Projector | src/Raster_Laser_Projector/synthesis/submodules/Raster_Laser_Projector_Video_In_video_scaler_0.v | 6,289 | module MODULE1 (
clk,
reset,
VAR34,
VAR27,
VAR19,
VAR1,
VAR13,
VAR29,
VAR28,
VAR17,
VAR5,
VAR10,
VAR3,
VAR35,
VAR30
);
parameter VAR9 = 0; parameter VAR31 = 7; parameter VAR26 = 0;
parameter VAR11 = 9; parameter VAR14 = 7; parameter VAR25 = 640;
parameter VAR7 = 4'b0000;
parameter VAR21 = 4'b0000;
parameter VAR23 = 9; ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o311a/sky130_fd_sc_lp__o311a.functional.v | 1,459 | module MODULE1 (
VAR4 ,
VAR8,
VAR11,
VAR6,
VAR7,
VAR1
);
output VAR4 ;
input VAR8;
input VAR11;
input VAR6;
input VAR7;
input VAR1;
wire VAR9 ;
wire VAR2;
or VAR3 (VAR9 , VAR11, VAR8, VAR6 );
and VAR5 (VAR2, VAR9, VAR7, VAR1);
buf VAR10 (VAR4 , VAR2 );
endmodule | apache-2.0 |
shailcoolboy/Warp-Trinity | edk_user_repository/WARP/pcores/radio_controller_v1_21_a/hdl/verilog/spi_shift.v | 5,928 | module MODULE1 (clk, rst, VAR12, VAR1, VAR14,
posedge, negedge, VAR15, VAR7,
VAR10, VAR3,
VAR18, VAR9, VAR2, VAR13);
parameter VAR6 = 1;
input clk; input rst; input [4:0] VAR12; input VAR1; input VAR14; input posedge; input negedge; input VAR15; input VAR7; output VAR10; output VAR3; input [17:0] VAR18; output [17:0] V... | bsd-2-clause |
sjohann81/hf-risc | devices/controllers/spi_sram_controller/23LC1024.v | 34,394 | module MODULE1 (VAR12, VAR25, VAR6, VAR32, VAR27, VAR21, VAR8);
inout VAR12; input VAR6;
input VAR32;
inout VAR27;
inout VAR21;
input VAR8;
inout VAR25;
reg [07:00] VAR15; reg [07:00] VAR7; reg [31:00] VAR2; reg [07:00] VAR1; reg [16:00] VAR23;
wire VAR17; wire VAR20; wire VAR22; wire VAR10; wire VAR29; wire VAR13; wir... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/nand4/gf180mcu_fd_sc_mcu9t5v0__nand4_1.functional.v | 1,390 | module MODULE1( VAR11, VAR7, VAR4, VAR13, VAR5 );
input VAR5, VAR13, VAR4, VAR11;
output VAR7;
wire VAR1;
not VAR14( VAR1, VAR5 );
wire VAR6;
not VAR8( VAR6, VAR13 );
wire VAR12;
not VAR2( VAR12, VAR4 );
wire VAR9;
not VAR3( VAR9, VAR11 );
or VAR10( VAR7, VAR1, VAR6, VAR12, VAR9 );
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_4.functional.pp.v | 1,611 | module MODULE1( VAR16, VAR15, VAR13, VAR14, VAR10, VAR4 );
input VAR15, VAR16, VAR13;
inout VAR10, VAR4;
output VAR14;
wire VAR17;
not VAR5( VAR17, VAR13 );
wire VAR6;
and VAR21( VAR6, VAR17, VAR15, VAR16 );
wire VAR1;
not VAR2( VAR1, VAR16 );
wire VAR7;
and VAR3( VAR7, VAR1, VAR15, VAR13 );
wire VAR11;
not VAR9( VAR11... | apache-2.0 |
olofk/oh | common/hdl/synchronizer.v | 1,583 | module MODULE1 (
out,
in, clk, reset
);
parameter VAR1 = 1;
input [VAR1-1:0] in;
input clk;
input reset;
output [VAR1-1:0] out;
reg [VAR1-1:0] VAR2;
reg [VAR1-1:0] out;
always @ (posedge clk or posedge reset)
if(reset)
begin
VAR2[VAR1-1:0] <= {(VAR1){1'b0}};
out[VAR1-1:0] <= {(VAR1){1'b0}};
end
else
begin
VAR2[VAR1-1:0... | gpl-3.0 |
aap/pdp6 | verilog/panel_6.v | 8,794 | module MODULE1(
input wire clk,
input wire reset,
input wire [5:0] VAR25,
input wire VAR27,
input wire VAR13,
input wire [31:0] VAR85,
output reg [31:0] VAR6,
output wire VAR22,
output reg VAR75,
output reg VAR19,
output reg VAR37,
output reg VAR17,
output reg VAR12,
output reg VAR50,
output reg VAR46,
output reg VAR67... | mit |
shailcoolboy/Warp-Trinity | PlatformSupport/CustomPeripherals/pcores/warp_v4_userio_v1_00_a/hdl/verilog/user_logic.v | 14,190 | module MODULE1
(
VAR41,
VAR21,
VAR37,
VAR14,
VAR8,
VAR25, VAR55, VAR6, VAR34, VAR10, VAR11, VAR59, VAR54, VAR57, VAR12 );
parameter VAR3 = 8'h40;
parameter VAR48 = 8'h50;
parameter VAR44 = 8'h40;
parameter VAR22 = 32;
parameter VAR39 = 5;
output [0:7] VAR41;
output VAR21;
output VAR37;
input [0:3] VAR14;
input [0:3] VA... | bsd-2-clause |
pavel-demin/red-pitaya-notes | cores/axis_variable_v1_0/axis_variable.v | 1,097 | module MODULE1 #
(
parameter integer VAR6 = 32
)
(
input wire VAR5,
input wire VAR1,
input wire [VAR6-1:0] VAR7,
input wire VAR9,
output wire [VAR6-1:0] VAR8,
output wire VAR10
);
reg [VAR6-1:0] VAR3;
reg VAR2, VAR4;
always @(posedge VAR5)
begin
if(~VAR1)
begin
VAR3 <= {(VAR6){1'b0}};
VAR2 <= 1'b0;
end
else
begin
VAR3 ... | mit |
borti4938/sd2snes | verilog/sd2snes_gsu/cheat.v | 12,310 | module MODULE1(
input clk,
input [7:0] VAR34,
input [23:0] VAR38,
input [7:0] VAR67,
input VAR56,
input VAR13,
input VAR52,
input VAR43,
input VAR48,
input VAR2,
input VAR37,
input VAR23,
input VAR20,
input VAR62,
input VAR45,
input VAR60,
input [2:0] VAR57,
input VAR64,
input [31:0] VAR27,
input VAR59,
output [7:0] VA... | gpl-2.0 |
vipinkmenon/fpgadriver | src/hw/fpga/source/memory_if/mig_7series_v1_8_ui_top.v | 14,966 | module MODULE1 #
(
parameter VAR79 = 100,
parameter VAR72 = 256,
parameter VAR84 = 32,
parameter VAR10 = 3,
parameter VAR13 = 12,
parameter VAR12 = 5,
parameter VAR66 = 5,
parameter VAR80 = "VAR51",
parameter VAR87 = "VAR51",
parameter VAR68 = "VAR36",
parameter VAR11 = 2,
parameter VAR24 = 4,
parameter VAR52 = "VAR42"... | mit |
ShepardSiegel/ocpi | libsrc/hdl/bsv/bram_patch/BRAM1_alt.v | 2,704 | module MODULE1(VAR4,
VAR12,
VAR6,
VAR11,
VAR10,
VAR2
);
parameter VAR13 = 0;
parameter VAR7 = 1;
parameter VAR9 = 1;
parameter VAR5 = 1;
input VAR4;
input VAR12;
input VAR6;
input [VAR7-1:0] VAR11;
input [VAR9-1:0] VAR10;
output [VAR9-1:0] VAR2;
reg [VAR9-1:0] VAR8[0:VAR5-1];
reg [VAR7-1:0] VAR1;
reg [VAR9-1:0] VAR14;
... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or2/sky130_fd_sc_ms__or2.behavioral.pp.v | 1,774 | module MODULE1 (
VAR2 ,
VAR12 ,
VAR6 ,
VAR1,
VAR4,
VAR11 ,
VAR3
);
output VAR2 ;
input VAR12 ;
input VAR6 ;
input VAR1;
input VAR4;
input VAR11 ;
input VAR3 ;
wire VAR10 ;
wire VAR7;
or VAR9 (VAR10 , VAR6, VAR12 );
VAR8 VAR5 (VAR7, VAR10, VAR1, VAR4);
buf VAR13 (VAR2 , VAR7 );
endmodule | apache-2.0 |
parallella/oh | common/hdl/oh_ram.v | 2,927 | module MODULE1 # (parameter VAR7 = 104, parameter VAR12 = 32, parameter VAR10 = 1, parameter VAR18= 1, parameter VAR22 = VAR9(VAR12) )
( input VAR4, input VAR29, input [VAR22-1:0] VAR32, output [VAR7-1:0] VAR3, input VAR27, input VAR6, input [VAR22-1:0] VAR21, input [VAR7-1:0] VAR15, input [VAR7-1:0] VAR24, input VAR30... | mit |
gigglesninja/digital-system-design | lab6_timer32/timer32.v | 2,051 | module MODULE1(clk, reset, din, dout, VAR3, VAR4, addr);
input clk, reset, VAR3, VAR4;
input [31:0] din;
output [31:0] dout;
input [1:0] addr;
reg [31:0] out, VAR6, VAR7, period;
reg [2:0] VAR10;
parameter VAR5 = 32'h0000000F; parameter VAR12 = 1'b0;
always @(posedge clk or posedge reset) begin
if(reset) begin
VAR7<= V... | gpl-2.0 |
tmatsuya/milkymist-ml401 | cores/lm32/rtl/JTAGB.v | 1,711 | module MODULE1 (
output VAR4,
output VAR1,
output VAR7,
output VAR8,
output VAR11,
output VAR9,
output VAR3,
output VAR2,
output VAR6,
input VAR10,
input VAR5
) ;
endmodule | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor4b/sky130_fd_sc_ls__nor4b.functional.pp.v | 1,988 | module MODULE1 (
VAR5 ,
VAR4 ,
VAR10 ,
VAR1 ,
VAR12 ,
VAR14,
VAR15,
VAR3 ,
VAR9
);
output VAR5 ;
input VAR4 ;
input VAR10 ;
input VAR1 ;
input VAR12 ;
input VAR14;
input VAR15;
input VAR3 ;
input VAR9 ;
wire VAR6 ;
wire VAR2 ;
wire VAR16;
not VAR7 (VAR6 , VAR12 );
nor VAR11 (VAR2 , VAR4, VAR10, VAR1, VAR6 );
VAR13 VAR1... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/buf/gf180mcu_fd_sc_mcu9t5v0__buf_12.behavioral.pp.v | 1,164 | module MODULE1( VAR3, VAR6, VAR5, VAR7 );
input VAR3;
inout VAR5, VAR7;
output VAR6;
VAR4 VAR2(.VAR3(VAR3),.VAR6(VAR6),.VAR5(VAR5),.VAR7(VAR7));
VAR4 VAR1(.VAR3(VAR3),.VAR6(VAR6),.VAR5(VAR5),.VAR7(VAR7)); | apache-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_k7_x8_250/source/pcie_7x_v1_3_qpll_drp.v | 15,782 | module MODULE1 #
(
parameter VAR47 = "VAR36", parameter VAR51 = 0, parameter VAR60 = 3'd4
)
(
input VAR35,
input VAR12,
input VAR56,
input VAR39,
input VAR53,
input [15:0] VAR22,
input VAR14,
output [ 7:0] VAR43,
output VAR34,
output [15:0] VAR41,
output VAR44,
output VAR1,
output [ 5:0] VAR58,
output [ 6:0] VAR52
);
r... | lgpl-3.0 |
d16-processor/d16 | verilog/src/mem.v | 2,629 | module MODULE1(
input clk,
input rst,
input en,
input VAR11,
input VAR8,
input VAR6,
input [15:0] addr,
input [15:0] VAR20,
output reg [15:0] VAR4,
output VAR2,
input VAR10,
input [15:0] VAR23,
input [15:0] VAR16,
output reg [15:0] VAR14
);
wire [15:0] VAR3; wire [15:0] VAR9; reg [15:0] VAR19;
reg [1:0] VAR13;
assign V... | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_hdmi_tx/axi_hdmi_tx_alt.v | 8,991 | module MODULE1 (
VAR34,
VAR60,
VAR69,
VAR6,
VAR15,
VAR20,
VAR26,
VAR56,
VAR58,
VAR18,
VAR53,
VAR28,
VAR52,
VAR70,
VAR37,
VAR63,
VAR49,
VAR1,
VAR68,
VAR51,
VAR38,
VAR50,
VAR21,
VAR72,
VAR55,
VAR13,
VAR33,
VAR45,
VAR30,
VAR19,
VAR36,
VAR54,
VAR29,
VAR74,
VAR48,
VAR67,
VAR8,
VAR41,
VAR47,
VAR46,
VAR5,
VAR22,
VAR14,
VAR2,
... | gpl-3.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_clk_gen/bsg_rp_clk_gen_coarse_delay_tuner.v | 2,344 | module MODULE1
(input VAR12
, input [1:0] VAR18
, input VAR24
, input VAR14
, output VAR29
, output VAR5
);
wire [1:0] VAR31;
wire [8:0] VAR6;
assign VAR6[0] = VAR12;
VAR34 VAR32 (.VAR16(VAR6[0]), .VAR17(VAR6[1]) );
VAR34 VAR37 (.VAR16(VAR6[1]), .VAR17(VAR6[2]) );
VAR39 VAR44 (.VAR16(VAR6[1]), .VAR17() );
VAR34 VAR43 (... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/ebufn/sky130_fd_sc_hdll__ebufn.symbol.v | 1,341 | module MODULE1 (
input VAR2 ,
output VAR6 ,
input VAR5
);
supply1 VAR1;
supply0 VAR4;
supply1 VAR7 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
takeshineshiro/fpga_linear_128 | ComWithCC3200.v | 1,598 | module MODULE1(
input VAR6,
input VAR1,
output reg VAR8,
input VAR2,
input VAR13,
output reg [7:0] VAR12, output reg VAR10,
output reg [1:0] VAR14,
output reg [5:0] VAR9,
input [7:0] VAR4,
output reg [8:0] VAR11
);
reg [15:0] VAR5;
reg [3:0] VAR7;
reg [7:0] VAR3;
always @(posedge VAR6 or negedge VAR1 ) begin
if(~VAR1) ... | mit |
kkalavantavanich/SD2017 | crcGenerator.v | 1,363 | /* VAR13 VAR3 VAR27 VAR11 VAR6 VAR9 VAR17.
* VAR22 VAR29 VAR10 use/VAR2/VAR5 in VAR16 VAR24 VAR4 this VAR8 VAR20 VAR7 VAR23 VAR1.
* VAR14: VAR18:VAR30 1ns / 1ps
module MODULE1
input VAR21,
input clk,
input VAR19,
input enable, input [VAR15:0] VAR28,
output reg [VAR15 - 1:0] VAR26
);
wire VAR12;
assign VAR12 = VAR21 ^ V... | mit |
alexforencich/xfcp | lib/i2c/rtl/i2c_slave_wbm.v | 16,847 | module MODULE1 #
(
parameter VAR29 = 4,
parameter VAR19 = 32, parameter VAR27 = 32, parameter VAR18 = (VAR19/8) )
(
input wire clk,
input wire rst,
input wire VAR20,
output wire VAR15,
output wire VAR16,
input wire VAR25,
output wire VAR30,
output wire VAR6,
output wire [VAR27-1:0] VAR14, input wire [VAR19-1:0] VAR5, o... | mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/ip/Gaussian_Filter/acl_fp_sitofp_double.v | 25,893 | module MODULE1
(
VAR5,
VAR9,
VAR14,
VAR13,
VAR17,
VAR7) ;
input VAR5;
input VAR9;
input VAR14;
input [31:0] VAR13;
input [4:0] VAR17;
output [31:0] VAR7;
tri0 VAR5;
tri1 VAR9;
tri0 VAR14;
reg [1:0] VAR15;
reg [31:0] VAR16;
reg [31:0] VAR3;
reg VAR12;
reg VAR6;
wire [5:0] VAR8;
wire VAR2;
wire [15:0] VAR1;
wire [191:0] ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand4b/sky130_fd_sc_lp__nand4b.pp.symbol.v | 1,330 | module MODULE1 (
input VAR9 ,
input VAR3 ,
input VAR4 ,
input VAR5 ,
output VAR6 ,
input VAR2 ,
input VAR7,
input VAR8,
input VAR1
);
endmodule | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/control_lib/dbsm.v | 5,068 | module MODULE1
(input clk,
input reset,
input VAR9,
output VAR26,
output VAR13,
input VAR19,
output VAR1,
output VAR20,
input VAR24,
output VAR23,
output VAR15,
input VAR7,
input VAR6
);
localparam VAR5 = 0;
localparam VAR17 = 1;
localparam VAR2 = 2;
localparam VAR18 = 3;
reg [1:0] VAR21, VAR22, VAR11;
localparam VAR12... | gpl-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_trn_v6_gtx_x4_250/source/pcie_reset_delay_v6.v | 3,948 | module MODULE1 # (
parameter VAR7 = "VAR2",
parameter VAR11 = 0
)
(
input wire VAR10,
input wire VAR5,
output VAR3
);
parameter VAR1 = 1;
localparam VAR6 = (VAR7 == "VAR2") ? ((VAR11 == 1) ? 20: (VAR11 == 0) ? 20 : 21) : 2;
reg [7:0] VAR12;
reg [7:0] VAR4;
reg [7:0] VAR9;
wire [23:0] VAR8;
assign VAR8 = {VAR9, VAR4, VA... | lgpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/jbi/jbi_min/rtl/jbi_min_rq_tag_slice.v | 4,255 | module MODULE1(
VAR17,
VAR6, VAR5, VAR8, VAR9, VAR12,
VAR14
);
input VAR6;
input VAR5;
input [VAR3-1:0] VAR8;
input VAR9;
input [VAR3-1:0] VAR12;
input VAR14;
output VAR17;
wire VAR17;
wire [VAR3-1:0] VAR15;
wire [VAR3-1:0] VAR1;
reg VAR18;
reg VAR19;
wire VAR16;
always @ ( VAR17 or VAR15 or VAR8) begin
if(VAR15 == VAR... | gpl-2.0 |
egyp7/mor1kx | bench/verilog/mor1kx_monitor.v | 24,926 | module MODULE1 #(parameter VAR11= "../out") ();
integer VAR1 = 0;
integer VAR10 = 0;
integer VAR4 = 0;
wire clk;
parameter VAR7 = 32;
reg VAR9;
VAR3 VAR9 = ("VAR6");
reg VAR2;
VAR3 VAR2 = ("VAR5");
assign clk = VAR12;
reg [63:0] VAR8 = 0 ;
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
be... | mpl-2.0 |
SeanZarzycki/openSPARC-FPU | project/src/fpu_mul_frac_dp.v | 15,083 | module MODULE1 (
VAR36,
VAR86,
VAR39,
VAR8,
VAR7,
VAR98,
VAR41,
VAR54,
VAR59,
VAR89,
VAR4,
VAR20,
VAR48,
VAR22,
VAR13,
VAR57,
VAR30,
VAR83,
VAR88,
VAR53,
VAR60,
VAR34,
VAR35,
VAR74,
VAR16,
VAR84,
VAR50,
VAR97,
VAR31,
VAR11,
VAR23,
VAR28,
VAR19,
VAR46,
VAR32,
VAR26,
VAR91,
VAR61,
VAR17,
VAR87,
VAR37,
VAR71,
VAR75,
VAR95... | gpl-3.0 |
fredmorcos/attic | projects/vo-tools/machines/sbn-machine/fast-mul/sbn.v | 3,406 | module MODULE1 (clk, state, VAR17, VAR9, VAR8);
parameter VAR7 = 8; parameter VAR26 = 32;
input clk;
output [2:0] state;
output [VAR7-1:0] VAR17;
output [VAR26-1:0] VAR9, VAR8;
parameter VAR29 = 4 * VAR7;
reg [VAR29-1:0] VAR4[0:((1<<VAR7)-1)];
reg [VAR26-1:0] VAR14[0:((1<<VAR7)-1)];
reg [VAR26-1:0] VAR6, VAR22;
reg [VA... | isc |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkdlyinv3sd3/sky130_fd_sc_ms__clkdlyinv3sd3.pp.symbol.v | 1,357 | module MODULE1 (
input VAR2 ,
output VAR3 ,
input VAR5 ,
input VAR6,
input VAR1,
input VAR4
);
endmodule | apache-2.0 |
ppnipuna/EDAC_ASIC_Design | rtl/encoder.v | 1,874 | module MODULE1 #(parameter VAR10 = 128, VAR11 = 9)
(VAR18, VAR2,VAR17, clk,
VAR4, VAR9);
parameter VAR3 = VAR10;
parameter VAR5 = VAR11;
input wire clk, VAR17, VAR2;
input wire [VAR3:1] VAR18;
output reg [VAR3:1] VAR4; output reg [VAR5:1] VAR9;
reg [VAR3:1] VAR1;
reg [VAR5:1] VAR6;
reg VAR13;
always @(posedge clk or ne... | mit |
The-OpenROAD-Project/asap7 | asap7sc6t_26/Verilog/asap7sc6t_AO_SRAM_FF_210930.v | 231,432 | module MODULE1 (VAR1, VAR4, VAR7, VAR10, VAR6);
output VAR1;
input VAR4, VAR7, VAR10, VAR6;
wire VAR5, VAR8, VAR11;
wire VAR9, VAR3, VAR2;
not (VAR9, VAR6);
not (VAR11, VAR10);
not (VAR8, VAR7);
and (VAR3, VAR8, VAR11);
not (VAR5, VAR4);
and (VAR2, VAR5, VAR11);
or (VAR1, VAR2, VAR3, VAR9); | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlrbn/sky130_fd_sc_hd__dlrbn.blackbox.v | 1,405 | module MODULE1 (
VAR5 ,
VAR2 ,
VAR9,
VAR1 ,
VAR7
);
output VAR5 ;
output VAR2 ;
input VAR9;
input VAR1 ;
input VAR7 ;
supply1 VAR4;
supply0 VAR3;
supply1 VAR8 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/srdlrtp/sky130_fd_sc_lp__srdlrtp.symbol.v | 1,440 | module MODULE1 (
input VAR1 ,
output VAR6 ,
input VAR10,
input VAR4 ,
input VAR5
);
supply1 VAR9;
supply1 VAR2 ;
supply0 VAR3 ;
supply1 VAR8 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/new/SHD.v | 25,957 | module MODULE1 #(parameter VAR9 = 200) (
VAR11,
VAR1,
VAR26
);
input [VAR9-1:0] VAR11, VAR1;
reg [(VAR9/2)-1:0] VAR19, VAR8, VAR15, VAR31, VAR10, VAR18, VAR12, VAR16, VAR28, VAR2, VAR4, VAR24;
output reg [7:0] VAR26;
reg [VAR9-1:0] VAR13, VAR30, VAR17, VAR3, VAR25, VAR29, VAR20, VAR14, VAR27, VAR5, VAR6;
integer VAR22,... | gpl-3.0 |
OpticalMeasurementsSystems/2DImageProcessing | 2d_image_processing.srcs/sources_1/bd/image_processing_2d_design/ipshared/xilinx.com/generic_baseblocks_v2_1/hdl/verilog/generic_baseblocks_v2_1_mux_enc.v | 9,821 | module MODULE1 #
(
parameter VAR23 = "VAR5",
parameter integer VAR33 = 4,
parameter integer VAR31 = 2,
parameter integer VAR27 = 1
)
(
input wire [VAR31-1:0] VAR15,
input wire [VAR33*VAR27-1:0] VAR8,
output wire [VAR27-1:0] VAR37,
input wire VAR36
);
wire [VAR27-1:0] VAR16;
genvar VAR24;
function [VAR27-1:0] VAR32
(
in... | gpl-2.0 |
CospanDesign/nysa-sata | rtl/generic/ppfifo.v | 18,948 | module MODULE1
VAR38 = 4
)(
input reset,
input VAR1,
output reg [1:0] VAR21,
input [1:0] VAR62,
output [23:0] VAR54,
input VAR45,
input [VAR25 - 1: 0] VAR13,
output VAR17,
input VAR10,
input VAR12,
output reg VAR60,
input VAR3,
output reg [23:0] VAR11,
output [VAR25 - 1: 0] VAR16,
output VAR32
);
localparam VAR28 = (1 ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o221a/sky130_fd_sc_hdll__o221a_1.v | 2,460 | module MODULE1 (
VAR3 ,
VAR11 ,
VAR1 ,
VAR10 ,
VAR5 ,
VAR7 ,
VAR9,
VAR12,
VAR8 ,
VAR6
);
output VAR3 ;
input VAR11 ;
input VAR1 ;
input VAR10 ;
input VAR5 ;
input VAR7 ;
input VAR9;
input VAR12;
input VAR8 ;
input VAR6 ;
VAR4 VAR2 (
.VAR3(VAR3),
.VAR11(VAR11),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR9... | apache-2.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_046.v | 1,515 | module MODULE1 (
VAR9,
VAR14
);
input [31:0] VAR9;
output [31:0]
VAR14;
wire [31:0]
VAR11,
VAR3,
VAR1,
VAR10,
VAR5,
VAR7,
VAR4,
VAR13,
VAR6;
assign VAR11 = VAR9;
assign VAR7 = VAR11 << 4;
assign VAR4 = VAR1 - VAR7;
assign VAR3 = VAR11 << 8;
assign VAR1 = VAR11 + VAR3;
assign VAR6 = VAR5 - VAR13;
assign VAR10 = VAR1 << ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o311ai/sky130_fd_sc_lp__o311ai_0.v | 2,435 | module MODULE1 (
VAR4 ,
VAR1 ,
VAR2 ,
VAR12 ,
VAR8 ,
VAR11 ,
VAR9,
VAR7,
VAR6 ,
VAR3
);
output VAR4 ;
input VAR1 ;
input VAR2 ;
input VAR12 ;
input VAR8 ;
input VAR11 ;
input VAR9;
input VAR7;
input VAR6 ;
input VAR3 ;
VAR10 VAR5 (
.VAR4(VAR4),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR12(VAR12),
.VAR8(VAR8),
.VAR11(VAR11),
.VAR9(... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dlyd/gf180mcu_fd_sc_mcu9t5v0__dlyd_4.behavioral.pp.v | 1,164 | module MODULE1( VAR6, VAR4, VAR1, VAR2 );
input VAR6;
inout VAR1, VAR2;
output VAR4;
VAR5 VAR3(.VAR6(VAR6),.VAR4(VAR4),.VAR1(VAR1),.VAR2(VAR2));
VAR5 VAR7(.VAR6(VAR6),.VAR4(VAR4),.VAR1(VAR1),.VAR2(VAR2)); | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/common/altera/DSP48E1.v | 5,529 | module MODULE1 (
VAR1,
VAR71,
VAR28,
VAR24,
VAR33,
VAR66,
VAR16,
VAR22,
VAR50,
VAR30,
VAR8,
VAR23,
VAR2,
VAR79,
VAR5,
VAR57,
VAR29,
VAR15,
VAR64,
VAR43,
VAR6,
VAR10,
VAR59,
VAR60,
VAR45,
VAR38,
VAR72,
VAR54,
VAR42,
VAR13,
VAR68,
VAR56,
VAR26,
VAR47,
VAR7,
VAR20,
VAR51,
VAR39,
VAR65,
VAR53,
VAR73,
VAR25,
VAR17,
VAR48,
V... | gpl-3.0 |
mosass/HexapodRobot | VIVADO/hexapod/hexapod.cache/ip/5445e913f36ad95e/design_1_axi_gpio_0_0_stub.v | 2,335 | module MODULE1(VAR19, VAR17, VAR5,
VAR12, VAR2, VAR8, VAR10, VAR4, VAR11,
VAR13, VAR18, VAR3, VAR1, VAR20, VAR6,
VAR9, VAR21, VAR16, VAR15, VAR7, VAR14)
;
input VAR19;
input VAR17;
input [8:0]VAR5;
input VAR12;
output VAR2;
input [31:0]VAR8;
input [3:0]VAR10;
input VAR4;
output VAR11;
output [1:0]VAR13;
output VAR18;
i... | mit |
Cognoscan/BoostLogic | verilog/src/buffers/Fifo.v | 1,977 | module MODULE1 #(
parameter VAR4 = 8, parameter VAR8 = 4 )
(
input clk, input rst, input write, input read, input [VAR4-1:0] VAR2, output wire [VAR4-1:0] VAR3, output reg VAR10, output wire VAR6, output wire VAR9 );
reg [VAR4-1:0] memory[2**VAR8-1:0];
reg [VAR8-1:0] VAR5;
wire VAR1;
integer VAR7; | apache-2.0 |
jefg89/proyecto_final_prototipado | ProyectoFinal/SOC/synthesis/submodules/SOC_timer_0.v | 6,661 | module MODULE1 (
address,
VAR19,
clk,
VAR24,
VAR9,
VAR21,
irq,
VAR14
)
;
output irq;
output [ 15: 0] VAR14;
input [ 2: 0] address;
input VAR19;
input clk;
input VAR24;
input VAR9;
input [ 15: 0] VAR21;
wire VAR22;
wire VAR27;
wire VAR1;
reg [ 3: 0] VAR4;
wire VAR28;
reg VAR10;
wire VAR25;
wire [ 31: 0] VAR12;
reg [ 31:... | gpl-2.0 |
sittner/lcnc-mdsio | vhdl/source/can/can_register_asyn_syn.v | 4,662 | module MODULE1
( VAR4,
VAR1,
VAR3,
clk,
rst,
VAR5
);
parameter VAR6 = 8; parameter VAR2 = 0;
input [VAR6-1:0] VAR4;
input VAR3;
input clk;
input rst;
input VAR5;
output [VAR6-1:0] VAR1;
reg [VAR6-1:0] VAR1;
always @ (posedge clk or posedge rst)
begin
if(rst)
VAR1<=VAR2;
end
else if (VAR5) VAR1<=VAR2;
else if (VAR3) VAR... | gpl-3.0 |
merckhung/zet | cores/sdspi/rtl/sdspi.v | 2,639 | module MODULE1 (
output reg VAR13,
input VAR1,
output reg VAR10,
output reg VAR8,
input VAR12,
input VAR18,
input [8:0] VAR6,
output reg [7:0] VAR19,
input VAR16,
input [1:0] VAR3,
input VAR20,
input VAR5,
output reg VAR14
);
wire VAR15;
wire VAR17;
wire VAR2;
reg [7:0] VAR9;
reg VAR4;
reg [7:0] VAR7;
reg [1:0] VAR11;
... | gpl-3.0 |
vad-rulezz/megabot | minsoc/rtl/verilog/or1200/rtl/verilog/or1200_pic.v | 7,273 | module MODULE1(
clk, rst, VAR11, VAR13, VAR15, VAR6, VAR5,
VAR17, VAR12,
VAR19
);
input clk; input rst; input VAR11; input VAR13; input [31:0] VAR15; input [31:0] VAR6; output [31:0] VAR5; output VAR17; output VAR12;
input [VAR3-1:0] VAR19;
reg [VAR3-1:2] VAR20; else
wire [VAR3-1:2] VAR20; VAR16
reg [VAR3-1:0] VAR4; el... | gpl-2.0 |
benjaminfjones/fpga-tunes | src/spi_slave.v | 1,596 | module MODULE1(
input clk,
input rst,
input VAR11,
input VAR1,
output VAR19,
input VAR9,
output VAR8,
input [7:0] din,
output [7:0] dout
);
reg VAR12, VAR4;
reg VAR10, VAR3;
reg VAR5, VAR6;
reg VAR21, VAR14;
reg [7:0] VAR2, VAR18;
reg VAR23, VAR13;
reg [2:0] VAR15, VAR16;
reg [7:0] VAR22, VAR20;
reg VAR17, VAR7;
assign... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/einvn/sky130_fd_sc_lp__einvn.pp.symbol.v | 1,329 | module MODULE1 (
input VAR5 ,
output VAR6 ,
input VAR7,
input VAR2 ,
input VAR3,
input VAR1,
input VAR4
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand4/sky130_fd_sc_hs__nand4.symbol.v | 1,258 | module MODULE1 (
input VAR1,
input VAR6,
input VAR5,
input VAR2,
output VAR7
);
supply1 VAR3;
supply0 VAR4;
endmodule | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync.v | 3,253 | module MODULE1 (
input clk,
input VAR4,
input VAR17,
output VAR3,
input VAR14,
input [7:0] VAR2,
input VAR13,
input VAR10,
input [31:0] VAR1,
output reg VAR5,
input VAR15,
output [23:0] VAR8,
output reg VAR18,
input VAR21,
output [31:0] VAR20,
output reg VAR16
);
reg [1:0] VAR11 = 'h00;
reg [31:0] VAR9 = 'h00;
reg [23:... | gpl-3.0 |
ak-fau/fpga-cyclone_iv | bemicro/zscale_wrapper.v | 4,354 | module MODULE1 (
input wire clk,
input wire reset,
output wire [7:0] VAR8
);
wire VAR38;
wire [63:0] VAR44;
wire [31:0] VAR9;
wire VAR7;
wire [2:0] VAR47;
wire [2:0] VAR25;
wire [3:0] VAR46;
wire [1:0] VAR17;
wire VAR22;
wire [31:0] VAR59;
wire [31:0] VAR42;
wire VAR18;
wire VAR55;
wire VAR33;
wire VAR39;
wire [31:0] V... | bsd-2-clause |
nliu96/openHMC_Altera | src/openhmc_ram.v | 4,109 | module MODULE1 #(
parameter VAR6 = 78, parameter VAR4 = 9, parameter VAR5 = 0
) (
input wire clk,
input wire VAR2,
input wire [VAR6-1:0] VAR1,
input wire [VAR4-1:0] VAR7,
input wire VAR13,
input wire [VAR4-1:0] VAR12,
output wire [VAR6-1:0] VAR3
);
wire [VAR6-1:0] VAR9;
generate
if (VAR5 == 0)
begin
assign VAR3 = VAR9;... | lgpl-3.0 |
sgq995/rc4-de0-nano-soc | fpga/hps/ghrd.v | 13,674 | module MODULE1(
output VAR103,
output VAR81,
output VAR89,
input VAR144,
inout [15:0] VAR36,
inout VAR74,
output VAR26,
inout VAR133,
input VAR56,
input VAR150,
input VAR39,
inout [35:0] VAR73,
inout [35:0] VAR105,
inout VAR32,
output [14:0] VAR125,
output [2:0] VAR86,
output VAR142,
output VAR5,
output VAR21,
output V... | mit |
hoangt/multiported-ram | mpram.v | 13,287 | module MODULE1
localparam VAR38 = VAR16(VAR19);
localparam VAR5 = VAR16(VAR12);
localparam VAR31 = VAR40*(VAR12-1);
localparam VAR11 = VAR5*(VAR12+VAR21-1);
localparam VAR13 = (VAR12-1)*(VAR21+1);
localparam VAR17 = ( (VAR13<=VAR31) && (VAR13<=VAR11) ) ? "VAR4" : ( (VAR11<=VAR31) ? "VAR26" : "VAR6" );
localparam VAR30 ... | bsd-3-clause |
cheehieu/qm-fir-digital-filter-core | ISAAC/qmfir_documentation/v/QM_FIR.v | 6,363 | module MODULE1(
VAR3, VAR19, VAR27, VAR2, VAR10, VAR26,
VAR15,
VAR30, VAR4, VAR34, VAR8, VAR36, VAR35, VAR32, VAR13,
VAR16, VAR40, VAR17, VAR38
);
parameter VAR6 = 16;
parameter VAR7 = 8;
parameter VAR11 = 32;
output signed [(VAR6-1):0] VAR3, VAR19, VAR27;
output signed [(VAR6-1):0] VAR2, VAR10, VAR26;
output VAR15;
in... | gpl-2.0 |
asicguy/gplgpu | hdl/altera_clk_synth/clk_gen_ipll_stim.v | 5,401 | module MODULE1;
reg VAR9;
reg VAR27;
reg VAR15;
reg [1:0] VAR1;
reg VAR13;
reg [1:0] VAR26;
reg VAR4;
reg [2:0] VAR24; reg VAR2;
reg [7:0] VAR8; reg [7:0] VAR7; reg [7:0] VAR16; reg [7:0] VAR5; reg [7:0] VAR11; reg [7:0] VAR20; reg [7:0] VAR22; reg [7:0] VAR12;
wire VAR23;
wire VAR25;
wire VAR21;
wire VAR17;
wire [2:0]... | gpl-3.0 |
walkthetalk/fsref | ip/s2mm_adv/src/s2mm_adv.v | 5,389 | module MODULE1 #
(
parameter integer VAR67 = 8,
parameter integer VAR46 = 12,
parameter integer VAR5 = 12,
parameter integer VAR63 = 12,
parameter integer VAR4 = 8,
parameter integer VAR35 = 1024,
parameter integer VAR49 = 16,
parameter integer VAR15 = 32,
parameter integer VAR40 = 32
)
(
input wire [VAR46-1:0] VAR16,
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/einvn/sky130_fd_sc_ms__einvn.functional.v | 1,218 | module MODULE1 (
VAR1 ,
VAR2 ,
VAR4
);
output VAR1 ;
input VAR2 ;
input VAR4;
notif0 VAR3 (VAR1 , VAR2, VAR4 );
endmodule | apache-2.0 |
htuNCSU/MmcCommunicationVerilog | DE2_115_MASTER/source_code/freedm_bus/fb_slave_counters.v | 4,646 | module MODULE1 (VAR35, VAR20, VAR38,
VAR16, VAR22, VAR25, VAR10, VAR29, VAR3,
VAR37, VAR8, VAR23, VAR4, VAR19, VAR18, VAR39, VAR11
);
input VAR35; input VAR20; input VAR16; input VAR22; input VAR25; input [1:0] VAR10; input VAR29; input VAR3;
input VAR38;
output [15:0] VAR37; output [15:0] VAR8;
output VAR23;
output VA... | gpl-3.0 |
545/Atari7800 | core/ag_6502/trunk/agat7/chip1.v | 1,700 | module MODULE1(
input clk,
input b1,
input VAR21,
input[3:0] VAR6,
input VAR29, VAR23, VAR27,
output[7:0] VAR11,
output VAR14,
output VAR13,
output VAR12,
output VAR10,
output VAR9,
output [3:0]VAR15,
input VAR1, output VAR18, output VAR19, output VAR2, output VAR30,
output VAR5,
output VAR31,
output VAR25,
output VAR2... | gpl-2.0 |
tmatsuya/milkymist-ml401 | cores/softusb/rtl/softusb_tx.v | 5,310 | module MODULE1(
input VAR28,
input VAR40,
input [7:0] VAR34,
input VAR41,
output reg VAR17,
output reg VAR6,
output reg VAR12,
output reg VAR10,
input VAR8,
input VAR16
);
reg VAR18;
reg VAR3;
reg VAR37;
always @(posedge VAR28) begin
VAR6 <= VAR18;
VAR12 <= VAR3;
VAR10 <= VAR37;
end
reg VAR19;
reg [4:0] VAR13;
always @... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand3/sky130_fd_sc_hs__nand3.blackbox.v | 1,224 | module MODULE1 (
VAR4,
VAR5,
VAR6,
VAR1
);
output VAR4;
input VAR5;
input VAR6;
input VAR1;
supply1 VAR2;
supply0 VAR3;
endmodule | apache-2.0 |
takeshineshiro/fpga_linear_128 | mult16_12_bb.v | 4,101 | module MODULE1 (
VAR1,
VAR2,
VAR3,
VAR4);
input VAR1;
input [15:0] VAR2;
input [15:0] VAR3;
output [31:0] VAR4;
endmodule | mit |
jotego/jt12 | hdl/jt12_eg_step.v | 3,296 | module MODULE1(
input VAR12,
input [ 4:0] VAR13,
input [ 4:0] VAR10,
input [14:0] VAR14,
input VAR9,
input [ 1:0] VAR11,
output VAR15,
output reg VAR7,
output reg [5:0] VAR3,
output reg VAR6
);
reg [6:0] VAR1;
always @
VAR3 = VAR1[6] ? 6'd63 : VAR1[5:0];
reg [2:0] VAR8;
reg [4:0] VAR4;
always @
case( VAR4 )
5'h0: VAR8 ... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_init.v | 123,052 | module MODULE1 #
(
parameter VAR152 = 100,
parameter VAR75 = 2, parameter VAR184 = 3333, parameter VAR36 = 2,
parameter VAR41 = 10,
parameter VAR212 = 1, parameter VAR209 = 64,
parameter VAR179 = 14,
parameter VAR110 = 1,
parameter VAR206 = 1, parameter VAR234 = "VAR57",
parameter VAR147 = "VAR128",
parameter VAR94 = 1... | lgpl-3.0 |
chris-wood/yield | sdsoc/hash/SDDebug/_sds/iprepo/repo/xilinx_com_hls_get_1_0/hdl/verilog/get.v | 18,460 | module MODULE1 (
VAR20,
VAR214,
VAR36,
VAR246,
VAR16,
VAR187,
VAR178,
VAR163,
VAR2,
VAR8,
VAR110,
VAR31,
VAR44,
VAR204,
VAR170,
VAR67,
VAR183,
VAR26,
VAR211,
VAR25,
VAR244,
VAR138,
VAR238,
VAR83,
VAR155,
VAR109,
VAR64,
VAR21,
VAR102,
VAR254,
VAR40,
VAR59,
VAR69,
VAR253,
VAR229,
VAR115,
VAR50,
VAR72,
VAR53,
VAR92,
VAR17... | mit |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_clk_gen/bsg_nonsynth_clk_watcher.v | 2,106 | module MODULE1 #(VAR6=0)
(input VAR18);
longint VAR17 = 0;
longint VAR15 = 0;
longint VAR8 = -1;
longint VAR9 = -1;
longint VAR20 = -1;
longint VAR16 = -1;
longint VAR4;
always @(posedge VAR18)
begin
VAR4 =
if ((VAR4-VAR15 > VAR8+VAR6)
|| (VAR4-VAR15 < VAR8-VAR6))
begin
if (VAR20 != -1)
("## VAR5 { VAR12 VAR3 (VAR14 %-... | bsd-3-clause |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ip/design_SWandHW_standalone_xbar_2/synth/design_SWandHW_standalone_xbar_2.v | 26,501 | module MODULE1 (
VAR30,
VAR16,
VAR87,
VAR36,
VAR10,
VAR34,
VAR89,
VAR75,
VAR84,
VAR41,
VAR47,
VAR131,
VAR70,
VAR28,
VAR50,
VAR20,
VAR2,
VAR8,
VAR103,
VAR46,
VAR31,
VAR99,
VAR17,
VAR120,
VAR94,
VAR21,
VAR77,
VAR25,
VAR74,
VAR122,
VAR80,
VAR67,
VAR53,
VAR125,
VAR39,
VAR63,
VAR101,
VAR57,
VAR40,
VAR64,
VAR95,
VAR45,
VAR6,... | gpl-3.0 |
tmolteno/TART | hardware/FPGA/fifo/fifo16.v | 3,929 | module MODULE1 (
VAR19,
VAR21,
VAR18,
VAR1, VAR9, VAR17,
VAR20,
VAR5,
VAR15,
VAR4
);
parameter VAR11 = 8'd16;
input VAR19;
input VAR21;
input VAR18;
input VAR1;
input VAR9;
input [VAR11 - 1:0] VAR17;
output [VAR11 - 1:0] VAR20;
output VAR5;
output VAR15;
output VAR4;
reg [3:0] VAR7 = 4'h0;
reg [3:0] VAR2 = 4'h0;
assign... | lgpl-3.0 |
antmicro/yosys-symbiflow-plugins | ql-qlf-plugin/qlf_k6n10/ffs_map.v | 3,707 | module \VAR2 (VAR18, VAR9, VAR13);
input VAR18;
input VAR9;
output VAR13;
parameter VAR23 = 1'VAR10;
VAR19 VAR28 (.VAR13(VAR13), .VAR18(VAR18), .VAR9(VAR9));
endmodule
module \VAR31 (VAR18, VAR9, VAR29, VAR13);
input VAR18;
input VAR9;
input VAR29;
output VAR13;
parameter VAR23 = 1'VAR10;
VAR7 VAR28 (.VAR13(VAR13), .VA... | isc |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src_previous/in_switch.v | 13,104 | module MODULE1(
input clk,
input reset,
output [239:0] VAR44,
input [63:0] VAR73,
input [15:0] VAR78,
input VAR48,
input VAR20,
output reg VAR70,
input [63:0] VAR32,
input [15:0] VAR34,
input VAR88,
input VAR52,
output reg VAR26,
input [63:0] VAR25,
input [15:0] VAR38,
input VAR30,
input VAR66,
output reg VAR1,
input [... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/or3/sky130_fd_sc_hvl__or3_1.v | 2,161 | module MODULE2 (
VAR10 ,
VAR5 ,
VAR4 ,
VAR6 ,
VAR2,
VAR1,
VAR9 ,
VAR3
);
output VAR10 ;
input VAR5 ;
input VAR4 ;
input VAR6 ;
input VAR2;
input VAR1;
input VAR9 ;
input VAR3 ;
VAR8 VAR7 (
.VAR10(VAR10),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR3(VAR3)
);
endmodule
module MODULE... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_hs__udp_dlatch_pr_pp_pg_n.symbol.v | 1,505 | module MODULE1 (
input VAR1 ,
output VAR5 ,
input VAR6 ,
input VAR3 ,
input VAR2,
input VAR7 ,
input VAR4
);
endmodule | apache-2.0 |
FAST-Switch/fast | projects/SDTS/example/hw-src/pkt_input_ctrl/pkt_input_ctrl.v | 3,173 | module MODULE1(
clk,
reset,
VAR25,
VAR13,
VAR17,
VAR22,
VAR23,
VAR26,
VAR1,
VAR4
);
input clk;
input reset;
input VAR22;
input [138:0] VAR23;
output [7:0] VAR26;
input VAR1;
input VAR4;
input VAR25;
output VAR13;
output [138:0] VAR17;
reg [138:0] VAR17;
reg VAR13;
reg [2:0] state;
parameter VAR5=3'b000,
VAR21=3'b001,
V... | apache-2.0 |
MegaShow/college-programming | Homework/Digital Circuits and Logical Design/StudentId/Print.v | 2,731 | module MODULE1(VAR9, VAR3, VAR6, VAR10, VAR12);
input VAR9, VAR3, VAR6;
output reg [3:0] VAR10; output reg [7:0] VAR12; reg [31:0] counter; reg [31:0] VAR2; parameter [31:0] VAR11 = 50000; parameter [31:0] VAR4 = 100000000; parameter [31:0] VAR7 = 32'VAR1; reg [15:0] VAR5; reg [4:0] VAR8; | mit |
mwswartwout/EECS318 | hw1/problem1/problem1.v | 1,239 | module MODULE1(out, VAR34, VAR9);
output [7:0] out;
input [3:0] VAR34, VAR9;
wire VAR29, VAR22, VAR11, VAR17, VAR57, VAR33, VAR49, VAR47, VAR24, VAR55, VAR38, VAR45, VAR2, VAR39, VAR18, VAR27, VAR64, VAR60, VAR37, VAR20;
wire VAR21, VAR28, VAR5, VAR1, VAR12, VAR41, VAR52, VAR3, VAR26, VAR42, VAR15, VAR53, VAR36, VAR59,... | mit |
cybero/Verilog | src/PicoBlaze (kcpsm6)/Utilities/KCPSM6_Release9_30Sept14/UART_and_PicoTerm/KC705_design/uart6_kc705.v | 15,219 | module MODULE1 ( input VAR3,
output VAR50,
input VAR37,
input VAR16);
wire VAR36;
wire clk;
wire [7:0] VAR46;
wire [11:0] address;
wire [17:0] VAR49;
wire VAR61;
reg [7:0] VAR66;
wire [7:0] VAR18;
wire [7:0] VAR23;
wire VAR27;
wire VAR59;
wire VAR45;
wire interrupt;
wire VAR34;
wire VAR41;
wire VAR57;
wire VAR32;
wire ... | mit |
Chapna/TTCache | src/cachek_t.v | 1,196 | module MODULE1;
reg [0:15] VAR5;
reg [0:4] VAR4;
reg enable;
reg write;
reg [0:1] word;
reg VAR7;
reg [0:3] VAR1;
reg VAR8;
reg rst;
wire [0:15] VAR6;
wire [0:4] VAR9;
wire VAR2;
wire VAR3;
wire valid;
wire ack; | gpl-2.0 |
google/bbcpu | pcounter.v | 1,123 | module MODULE1(
input rst,
input clk,
input enable,
input VAR2,
input VAR1,
input [VAR3-1 : 0] VAR5,
output [VAR3-1 : 0] VAR4);
parameter VAR3 = 4;
reg [VAR3-1 : 0] counter;
assign VAR4 = (VAR1) ? counter : 0;
always @(posedge clk) begin
if (rst) begin
counter <= 0;
end else begin
if (enable) begin
counter <= counter +... | apache-2.0 |
sigilance/tera-computer | src/control.v | 3,938 | module MODULE1 (VAR6, VAR15, VAR7, VAR16, VAR10, VAR13, VAR17, VAR8, VAR9, VAR2);
output VAR6, VAR15, VAR7, VAR16, VAR10, VAR13;
output [3:0] VAR17;
input VAR9, VAR2;
input [7:0] VAR8;
reg VAR14, VAR12, VAR3, VAR11, VAR5, VAR1;
reg [3:0] VAR4;
assign VAR6 = VAR14;
assign VAR15 = VAR12;
assign VAR7 = VAR3;
assign VAR16 ... | mit |
manili/Pipelined_6502 | DUT.v | 2,462 | module MODULE1;
wire VAR37;
wire [23:0] VAR14;
wire [15:0] VAR3;
wire [7:0] VAR1;
wire [7:0] VAR33;
wire VAR24;
wire [1:0] VAR17;
wire [1:0] VAR32;
wire [23:0] VAR13;
wire [15:0] VAR31;
wire [15:0] VAR26;
wire [15:0] VAR28;
wire [15:0] VAR23;
wire [15:0] VAR34;
wire [7:0] VAR4;
wire [7:0] VAR11;
wire [7:0] VAR30;
wire ... | gpl-3.0 |
aquaxis/FPGAMAG18 | fmrv32im-artya7.madd33/fmrv32im-artya7.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v | 3,812 | module MODULE1
(
output VAR3,
input VAR2
);
VAR1 VAR4
(
.VAR3(VAR3),
.VAR2(VAR2)
);
endmodule | mit |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_clk_wiz_0_0/OpenSSD2_clk_wiz_0_0.v | 3,976 | module MODULE1
(
input VAR1,
output VAR3,
input reset
);
VAR4 VAR2
(
.VAR1(VAR1),
.VAR3(VAR3),
.reset(reset)
);
endmodule | gpl-3.0 |
kevintownsend/inara-hdl-libraries | multistage_interconnect_network/omega_network_ff.v | 1,334 | module MODULE1(clk, VAR3, din, valid, dout, VAR15);
parameter VAR2 = 8;
parameter VAR12 = 8;
parameter VAR14 = VAR12;
parameter VAR11 = VAR6(VAR14-1);
input clk;
input [0:VAR12-1] VAR3;
input [VAR12*VAR2-1:0] din;
output [0:VAR14-1] valid;
output [VAR14*VAR2-1:0] dout;
input [VAR11-1:0] VAR15;
genvar VAR1, VAR10;
wire ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/xor2/sky130_fd_sc_hvl__xor2.blackbox.v | 1,268 | module MODULE1 (
VAR6,
VAR3,
VAR7
);
output VAR6;
input VAR3;
input VAR7;
supply1 VAR4;
supply0 VAR1;
supply1 VAR5 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
LSaldyt/qnp | output/vs/opt_difficult_multi.v | 48,178 | module MODULE1(VAR26, VAR20, VAR8, VAR17, VAR23, VAR13, VAR18, VAR12, VAR15, VAR19, VAR1, VAR11, VAR7, VAR5, VAR21, VAR24, VAR4, VAR3, VAR16, VAR14, VAR10, VAR9, VAR25, VAR22, VAR6, VAR2, valid);
wire 0000;
wire 0001;
wire 0002;
wire 0003;
wire 0004;
wire 0005;
wire 0006;
wire 0007;
wire 0008;
wire 0009;
wire 0010;
wir... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_8.behavioral.v | 1,116 | module MODULE1( VAR2, VAR3 );
input VAR2;
output VAR3;
VAR1 VAR5(.VAR2(VAR2),.VAR3(VAR3));
VAR1 VAR4(.VAR2(VAR2),.VAR3(VAR3)); | apache-2.0 |
liuyenting/CA-Project | src/L1_Cache_rework.v | 4,869 | module MODULE1
parameter VAR7 = 32,
parameter VAR39 = 32,
parameter VAR45 = 256
)
(
input clk,
input rst,
input [VAR7-1:0] VAR14,
input VAR36,
input VAR37,
output VAR13,
input [VAR39-1:0] VAR16,
output [VAR39-1:0] VAR18,
output [VAR7-1:0] VAR27,
output VAR60,
output VAR54,
input VAR35,
input [VAR45-1:0] VAR59,
output [... | gpl-3.0 |
lokisz/openzcore | pippo-riscv/rtl/verilog/reg_gpr.v | 3,987 | module MODULE1(
clk, rst,
VAR18, VAR27, VAR32, VAR37,
VAR20, VAR26, VAR10,
VAR4, VAR12, VAR36, VAR2, VAR38, VAR6
);
parameter VAR13 = VAR11;
parameter VAR23 = VAR25;
input clk;
input rst;
input VAR18;
input VAR27;
input [VAR23-1:0] VAR4;
input [VAR23-1:0] VAR12;
input VAR38;
input VAR6;
output [VAR13-1:0] VAR36;
output... | gpl-2.0 |
natsutan/NPU | fpga_implement/npu8/src/q_add8.v | 1,762 | module MODULE1
(
input VAR4,
input VAR8,
input VAR11,
input [7:0] VAR3,
input [7:0] VAR2,
output VAR25,
output [7:0] VAR17,
input [31:0] VAR18,
input [31:0] VAR7,
output reg [15:0] VAR12,
output reg [15:0] VAR15
);
wire [15:0] VAR19; reg [16:0] VAR26;
wire [24:0] VAR6;
reg [7:0] VAR21, VAR9, VAR1;
reg [VAR14-1:0] VAR23... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/fill/sky130_fd_sc_hvl__fill_1.v | 1,848 | module MODULE2 (
VAR2,
VAR3,
VAR4 ,
VAR6
);
input VAR2;
input VAR3;
input VAR4 ;
input VAR6 ;
VAR5 VAR1 (
.VAR2(VAR2),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR6(VAR6)
);
endmodule
module MODULE2 ();
supply1 VAR2;
supply0 VAR3;
supply1 VAR4 ;
supply0 VAR6 ;
VAR5 VAR1 ();
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/xor2/gf180mcu_fd_sc_mcu9t5v0__xor2_1.functional.pp.v | 1,168 | module MODULE1( VAR7, VAR6, VAR11, VAR9, VAR2 );
input VAR6, VAR7;
inout VAR9, VAR2;
output VAR11;
wire VAR12;
not VAR8( VAR12, VAR7 );
wire VAR4;
and VAR3( VAR4, VAR12, VAR6 );
wire VAR13;
not VAR14( VAR13, VAR6 );
wire VAR1;
and VAR5( VAR1, VAR13, VAR7 );
or VAR10( VAR11, VAR4, VAR1 );
endmodule | apache-2.0 |
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