repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor4b/sky130_fd_sc_lp__nor4b_1.v | 2,302 | module MODULE1 (
VAR10 ,
VAR4 ,
VAR8 ,
VAR9 ,
VAR1 ,
VAR2,
VAR5,
VAR7 ,
VAR11
);
output VAR10 ;
input VAR4 ;
input VAR8 ;
input VAR9 ;
input VAR1 ;
input VAR2;
input VAR5;
input VAR7 ;
input VAR11 ;
VAR6 VAR3 (
.VAR10(VAR10),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR7(VAR7),
.VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a21o/sky130_fd_sc_hd__a21o.behavioral.v | 1,502 | module MODULE1 (
VAR5 ,
VAR3,
VAR9,
VAR12
);
output VAR5 ;
input VAR3;
input VAR9;
input VAR12;
supply1 VAR1;
supply0 VAR13;
supply1 VAR11 ;
supply0 VAR8 ;
wire VAR4 ;
wire VAR10;
and VAR7 (VAR4 , VAR3, VAR9 );
or VAR2 (VAR10, VAR4, VAR12 );
buf VAR6 (VAR5 , VAR10 );
endmodule | apache-2.0 |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | bin_Dilation_Operation/ip/Dilation/acl_fp_custom_mul_op_s5.v | 13,483 | module MODULE1 (
VAR24, VAR27,
VAR47, VAR10, VAR20,
VAR30, VAR11, VAR65,
VAR38,
VAR2,
VAR31,
VAR41, VAR53, VAR26, VAR48,
enable);
parameter VAR33 = 1;
parameter VAR52 = 0;
parameter VAR62 = 1;
parameter VAR4 = 1;
parameter VAR54 = 1;
input VAR24, VAR27;
input [26:0] VAR47;
input [8:0] VAR10;
input VAR20;
input [26:0] V... | mit |
chenm001/connectal | verilog/FpgaReset.v | 2,339 | module MODULE1 (
VAR5,
VAR6
);
parameter VAR7 = 1 ;
input VAR5 ;
output VAR6 ;
reg [VAR7:0] VAR4 ;
wire [VAR7+1:0] VAR2 = {VAR4, ~ VAR1} ;
assign VAR6 = VAR4[VAR7] ;
always @( posedge VAR5 ) begin
VAR4 <= VAR3 VAR2[VAR7:0];
end
begin
VAR4 = {(VAR7 + 1) {VAR1 }} ;
end
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkdlybuf4s25/sky130_fd_sc_lp__clkdlybuf4s25.behavioral.v | 1,439 | module MODULE1 (
VAR5,
VAR9
);
output VAR5;
input VAR9;
supply1 VAR1;
supply0 VAR3;
supply1 VAR4 ;
supply0 VAR7 ;
wire VAR8;
buf VAR6 (VAR8, VAR9 );
buf VAR2 (VAR5 , VAR8 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a31oi/sky130_fd_sc_hdll__a31oi.pp.symbol.v | 1,382 | module MODULE1 (
input VAR3 ,
input VAR5 ,
input VAR1 ,
input VAR7 ,
output VAR9 ,
input VAR6 ,
input VAR4,
input VAR2,
input VAR8
);
endmodule | apache-2.0 |
jairov4/accel-oil | solution_virtex5/syn/verilog/nfa_get_initials.v | 10,533 | module MODULE1 (
VAR34,
VAR28,
VAR5,
VAR7,
VAR12,
VAR36,
VAR25,
VAR11,
VAR13,
VAR4,
VAR1,
VAR22,
VAR10,
VAR37,
VAR8,
VAR19,
VAR21,
VAR39
);
parameter VAR16 = 1'b1;
parameter VAR9 = 1'b0;
parameter VAR30 = 2'b10;
parameter VAR29 = 2'b00;
parameter VAR27 = 2'b1;
parameter VAR3 = 2'b11;
parameter VAR32 = 64'b1;
parameter ... | lgpl-3.0 |
jameshegarty/rigel | platform/camera/vsrc/CamReader.v | 4,311 | module MODULE1 (
input VAR22, input VAR1, input [7:0] din, input VAR24, input VAR26, output VAR33, output reg [7:0] VAR20,
input VAR32, input VAR11, output reg [31:0] VAR5,
output reg [31:0] VAR12
);
reg VAR7;
reg VAR29;
reg VAR28;
reg VAR13;
reg VAR9;
reg VAR10;
reg VAR2;
wire VAR4;
wire VAR3;
reg VAR8;
wire VAR31;
re... | mit |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | source/hardware/nfc-substrate/tiger4_nfc_substrate-1.0.0/d_BCH_CS_X.v | 6,327 | module MODULE1
(
parameter VAR5 = 2,
parameter VAR28 = 12
)
(
VAR26,
VAR11,
VAR34,
VAR4,
VAR8,
VAR33,
VAR38,
VAR9,
VAR24,
VAR40,
VAR32,
VAR19,
VAR29,
VAR7,
VAR3,
VAR13,
VAR1,
VAR36,
VAR35,
VAR30,
VAR14,
VAR31,
VAR39,
VAR37,
VAR16,
VAR25,
VAR20,
VAR6
);
input VAR26;
input VAR11;
input VAR34;
input [VAR5 - 1:0] VAR4;
inp... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/edfxtp/sky130_fd_sc_ls__edfxtp.functional.v | 1,753 | module MODULE1 (
VAR10 ,
VAR11,
VAR9 ,
VAR4
);
output VAR10 ;
input VAR11;
input VAR9 ;
input VAR4 ;
wire VAR7 ;
wire VAR2;
VAR8 VAR5 (VAR2, VAR7, VAR9, VAR4 );
VAR6 VAR12 VAR3 (VAR7 , VAR2, VAR11 );
buf VAR1 (VAR10 , VAR7 );
endmodule | apache-2.0 |
freecores/tiny_tate_bilinear_pairing | group_size_is_911_bits/rtl/fsm.v | 4,382 | module MODULE1(clk, reset, VAR10, VAR25, VAR13, VAR2, VAR17, VAR18, VAR8);
input clk;
input reset;
output reg [8:0] VAR10;
input [28:0] VAR25;
output reg [5:0] VAR13;
output reg [5:0] VAR2;
output VAR17;
output reg [10:0] VAR18;
output reg VAR8;
reg [5:0] state;
parameter VAR33=0, VAR23=1, VAR24=2, VAR26=4, VAR21=8, VA... | apache-2.0 |
asicguy/gplgpu | hdl/ramdac_sp/ram_blks.v | 5,762 | module MODULE1
(
input VAR42,
input VAR38,
input VAR35,
input VAR44,
input VAR27,
input [7:0] VAR20,
input [7:0] VAR52,
input [7:0] VAR13,
input [7:0] VAR25,
input VAR12,
input VAR48,
input [10:0] VAR16,
input [7:0] VAR17,
input VAR41,
input VAR31,
input [7:0] VAR15,
input [7:0] VAR55,
input [7:0] VAR51,
input [7:0] VA... | gpl-3.0 |
MeshSr/onetswitch30 | ons30-app52-ref_ofshw/vivado/onets_7030_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/header_parser.v | 21,127 | module MODULE1
parameter VAR9 = VAR69/8,
parameter VAR77 = 12,
parameter VAR6 = 16,
parameter VAR43 = 16'h0fff,
parameter VAR58 = 224,
parameter VAR24 = 8'h40,
parameter VAR12 = 16'hffff,
parameter VAR75 = 240,
parameter VAR27 = 64,
parameter VAR38 = 0
)
( input [VAR69-1:0] VAR28,
input [VAR9-1:0] VAR42,
input VAR49,
o... | lgpl-2.1 |
Chapna/TTCache | src/cache_t.v | 1,187 | module MODULE1;
reg [0:15] VAR3;
reg [0:4] VAR6;
reg enable;
reg write;
reg [0:1] word;
reg VAR1;
reg [0:3] VAR7;
reg VAR2;
reg rst;
wire [0:15] VAR4;
wire [0:4] VAR9;
wire VAR8;
wire VAR5;
wire valid;
wire ack; | gpl-2.0 |
lbl-cal/StanfordNoC | router/src/clib/c_decode.v | 221,608 | module MODULE1
(VAR6, VAR8);
parameter VAR3 = 8;
parameter VAR5 = 0;
parameter VAR4 = 0;
localparam VAR7 = VAR2(VAR3);
localparam [0:0] VAR1 = VAR4 ? 1'b1 : 1'b0;
input [0:VAR7-1] VAR6;
output [0:VAR3-1] VAR8;
reg [0:VAR3-1] VAR8;
generate
if(VAR3 < 2)
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
b... | bsd-2-clause |
cyrozap/mimas_v2_hex_display | display_hex_byte.v | 3,699 | module MODULE2(
input clk,
input [7:0] VAR4,
output wire [7:0] VAR10,
output wire [2:0] VAR14
);
parameter VAR7 = 1000; parameter VAR2 = 100000000;
localparam VAR5 = VAR2 / (VAR7 * 3);
reg [31:0] VAR9;
reg [7:0] VAR3;
reg [2:0] VAR13;
assign VAR10 = ~VAR3;
assign VAR14 = ~VAR13;
wire [7:0] VAR11;
wire [7:0] VAR12;
MODU... | apache-2.0 |
dawsonjon/fpu | double_to_long/double_to_long.v | 2,658 | module MODULE1(
VAR16,
VAR14,
VAR3,
clk,
rst,
VAR19,
VAR18,
VAR13);
input clk;
input rst;
input [63:0] VAR16;
input VAR14;
output VAR13;
output [63:0] VAR19;
output VAR18;
input VAR3;
reg VAR12;
reg [63:0] VAR17;
reg VAR8;
reg [2:0] state;
parameter VAR5 = 3'd0,
VAR9 = 3'd1,
VAR2 = 3'd2,
VAR1 = 3'd3,
VAR10 = 3'd4;
reg ... | mit |
ZipCPU/wbuart32 | rtl/ufifo.v | 12,382 | module MODULE1 #(
parameter VAR21=8, parameter [3:0] VAR32=4,
parameter [0:0] VAR23=1'b1,
localparam VAR19=(1<<VAR32)
) (
input wire VAR4, VAR15,
input wire VAR27,
input wire [(VAR21-1):0] VAR41,
output wire VAR12, input wire VAR29,
output wire [(VAR21-1):0] VAR18,
output wire [15:0] VAR10,
output wire VAR6
);
reg [(VA... | gpl-3.0 |
puroh/Procesador_monociclo | memoria_datos.v | 2,009 | module MODULE1(clk,VAR9,VAR3,VAR15,VAR13,VAR6);
input clk;
input VAR9; input [31:0] VAR3;
input [31:0] VAR15;
input VAR13; output reg [31:0] VAR6;
wire VAR17;
wire VAR8;
wire [2:0] VAR2;
wire [31:0] VAR10;
wire [31:0] VAR14;
wire [31:0] VAR5;
wire VAR7;
VAR12 VAR4(.clk(clk),
.VAR1(VAR17),
.VAR3(VAR3[7:0]),
.VAR15(VAR15... | gpl-3.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_clk_gen/bsg_dly_line.v | 6,370 | module MODULE1
import VAR20::VAR10;
(
input VAR10 VAR6
,input VAR10 VAR28
,input VAR5
,input VAR9
,output VAR22
);
wire VAR12;
wire VAR30 = ~VAR5;
VAR23 VAR13;
wire VAR1;
wire VAR16, VAR38;
VAR14
,.VAR26(1)
) VAR29
(.VAR6(VAR6)
,.VAR15(VAR13)
);
VAR14
,.VAR26(1)
) VAR19
(.VAR6(VAR28)
,.VAR15(VAR1)
);
wire VAR32, VAR25;... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlymetal6s6s/sky130_fd_sc_ls__dlymetal6s6s.behavioral.v | 1,441 | module MODULE1 (
VAR3,
VAR9
);
output VAR3;
input VAR9;
supply1 VAR8;
supply0 VAR7;
supply1 VAR2 ;
supply0 VAR1 ;
wire VAR4;
buf VAR5 (VAR4, VAR9 );
buf VAR6 (VAR3 , VAR4 );
endmodule | apache-2.0 |
tmatsuya/milkymist-ml401 | cores/tmu2/rtl/tmu2_qpram32.v | 1,613 | module MODULE1 #(
parameter VAR16 = 11
) (
input VAR9,
input [VAR16-1:0] VAR1,
output [31:0] VAR21,
input [VAR16-1:0] VAR3,
output [31:0] VAR8,
input [VAR16-1:0] VAR14,
output [31:0] VAR5,
input [VAR16-1:0] VAR18,
output [31:0] VAR17,
input VAR11,
input [VAR16-1-1:0] VAR19,
input [63:0] VAR13
);
VAR4 #(
.VAR16(VAR16),
... | lgpl-3.0 |
mgohde/MiniMicroII | old/intpipe.v | 2,793 | module MODULE1(
VAR34,
VAR28,
VAR6,
VAR23,
VAR16,
VAR20,
VAR8,
VAR21,
VAR3,
VAR25,
VAR18,
VAR15,
VAR4,
VAR5,
VAR13,
VAR22
);
input VAR34;
input VAR28;
input VAR6;
input [3:0] VAR23;
input [2:0] VAR16;
input [2:0] VAR20;
input [2:0] VAR8;
input [15:0] VAR21;
input [15:0] VAR3;
input [7:0] VAR25;
output [2:0] VAR18;
outp... | bsd-2-clause |
sam-falvo/remex | example/rtl/CSRs.v | 6,184 | module MODULE1(
input [11:0] VAR99,
output VAR62,
output [63:0] VAR32,
input [63:0] VAR91,
input VAR19,
input VAR61,
input VAR31,
input VAR28,
input VAR20,
input VAR21,
output [63:0] VAR98,
output [63:0] VAR50,
output [3:0] VAR88,
input [63:0] VAR65,
input [63:0] VAR17,
output VAR87,
output VAR89,
input VAR48,
input VA... | mpl-2.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_NVMeHostController_0_0/src/pcie_7x_0_core_top/source/pcie_7x_0_core_top_qpll_wrapper.v | 29,715 | module MODULE1 #
(
parameter VAR151 = "VAR50", parameter VAR119 = "VAR135", parameter VAR43 = "3.0", parameter VAR73 = "VAR29", parameter VAR80 = 0
)
(
input VAR124,
input VAR91,
input VAR104,
output VAR137,
output VAR103,
output VAR1,
input VAR45,
input VAR60,
input VAR146,
input [ 7:0] VAR125,
input VAR62,
input [15:... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/jbi/jbi_dbg/rtl/jbi_dbg_buf.v | 9,470 | module MODULE1(
VAR49, VAR28,
clk, VAR48, VAR20, VAR8, VAR54,
VAR4, VAR19, VAR7, VAR33,
VAR39, VAR50, VAR22, VAR35,
VAR37, VAR13
);
input clk;
input VAR48;
input VAR20;
input VAR8;
input [4:0] VAR54;
input [VAR10-1:0] VAR4;
input [VAR10-1:0] VAR19;
input [VAR10-1:0] VAR7;
input [VAR10-1:0] VAR33;
input VAR39;
input VAR... | gpl-2.0 |
ThomasLee969/verilog-homework | project/framing_encoding/fifo.v | 3,285 | module MODULE1(
output [7:0] dout,
output VAR17, input [7:0] din,
input VAR3,
input clk,
input VAR5
);
parameter VAR14 = 20,
VAR1 = 8,
VAR13 = VAR14 * 8 - 1;
localparam VAR16 = 0,
VAR7 = 1,
VAR9 = 2,
VAR11 = 3,
VAR2 = 4;
reg [2:0] state, VAR15;
reg [VAR13:0] VAR10, VAR12;
reg [VAR1 - 1:0] head, VAR4; reg [6:0] VAR8, VA... | mit |
olajep/oh | src/elink/hdl/etx_io.v | 6,531 | module MODULE1 (
VAR17, VAR16, VAR59, VAR33, VAR40,
VAR20, VAR42, VAR48,
VAR38, VAR22, VAR51, VAR30, VAR2,
VAR19, VAR28, VAR1, VAR14
);
parameter VAR54 = VAR13;
parameter VAR32 = "VAR75";
parameter VAR57 = 104;
parameter VAR63 = 0; input VAR38; input VAR22; input VAR51;
output VAR17, VAR16; output VAR59, VAR33; output ... | mit |
Elphel/x393_sata | x393/util_modules/axi_hp_clk.v | 3,217 | module MODULE1#(
parameter VAR9 = 20, parameter VAR27 = 18, parameter VAR29 = 6 )(
input rst,
input VAR17,
output VAR11,
output VAR26
);
wire VAR28, VAR19;
VAR13 VAR2 (.VAR23(VAR11), .VAR7(VAR19));
VAR25 #(
.VAR9(VAR9), .VAR10("VAR4"),
.VAR8(VAR27), .VAR14(VAR29), .VAR21(0.010),
.VAR18("VAR24")
) VAR20 (
.VAR17(VAR17),... | gpl-3.0 |
lerwys/bpm-sw-old-backup | hdl/ip_cores/pcie/7k325ffg900/ddr_core/user_design/rtl/phy/mig_7series_v1_8_ddr_byte_lane.v | 28,426 | module MODULE1 #(
parameter VAR34 = "VAR172", parameter VAR69 = "VAR269",
parameter VAR322 = 12'b111111111111,
parameter VAR320 = 12'b111111111111,
parameter VAR246 = 24'b001000100010001000100010,
parameter VAR109 = "VAR114",
parameter VAR298 = 4,
parameter VAR283 = "VAR269",
parameter VAR293 = 1,
parameter VAR270 = 1,... | lgpl-3.0 |
vad-rulezz/megabot | minsoc/rtl/verilog/ethmac/rtl/verilog/eth_top.v | 35,074 | module MODULE1
(
VAR16, VAR25, VAR56, VAR12,
VAR22, VAR23, VAR5, VAR59, VAR43, VAR46, VAR78,
VAR34, VAR53, VAR48,
VAR54, VAR76, VAR82,
VAR30, VAR15, VAR4,
VAR57, VAR13,
VAR47, VAR84, VAR7, VAR45,
VAR67, VAR83, VAR55, VAR77, VAR80, VAR36,
VAR81, VAR14, VAR6, VAR52,
VAR51
,
VAR50, VAR29, VAR72 VAR63
);
parameter VAR31 = ... | gpl-2.0 |
eda-globetrotter/PicenoDecoders | andy/design/pipe.v | 6,780 | module MODULE1 (in,out,VAR6,reset);
output out;
input in; input VAR6; input reset;
reg out;
reg o1; reg o2; reg o3; reg o4; reg o5; reg o6; reg o7; reg VAR5; reg VAR7; reg o10; reg o11; reg o12; reg o13; reg o14;
reg o15; reg o16; reg o17; reg VAR2; reg VAR1; reg o20; reg o21; reg o22; reg o23; reg o24; reg o25; reg o2... | mit |
ckdur/mriscv_vivado_arty | mriscv_vivado.srcs/sources_1/imports/impl_axi_fpga.v | 24,941 | module MODULE1(
input VAR6,
input VAR30,
input VAR33,
output VAR174,
output VAR91,
output VAR178,
output VAR185,
output VAR9,
output VAR140,
input VAR211,
input VAR101,
input VAR51,
output VAR107,
output VAR13,
input VAR198,
output VAR68,
output VAR165,
output VAR27,
output [12:0] VAR177,
output [2:0] VAR112,
output VA... | mit |
keith-epidev/VHDL-lib | top/lab_6/ip/dds/dds_stub.v | 1,373 | module MODULE1(VAR1, VAR3, VAR2, VAR4, VAR5)
;
input VAR1;
input VAR3;
input [23:0]VAR2;
output VAR4;
output [31:0]VAR5;
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand3b/sky130_fd_sc_hs__nand3b.behavioral.v | 1,892 | module MODULE1 (
VAR11 ,
VAR6 ,
VAR12 ,
VAR4 ,
VAR8,
VAR9
);
output VAR11 ;
input VAR6 ;
input VAR12 ;
input VAR4 ;
input VAR8;
input VAR9;
wire VAR13 ;
wire VAR1 ;
wire VAR7;
not VAR10 (VAR13 , VAR6 );
nand VAR2 (VAR1 , VAR12, VAR13, VAR4 );
VAR3 VAR5 (VAR7, VAR1, VAR8, VAR9);
buf VAR14 (VAR11 , VAR7 );
endmodule | apache-2.0 |
Pylonight/MIPS-CPU | cpu/Data_Memory.v | 1,079 | module MODULE1(
output [15 : 0] VAR1,
input write,
input [15 : 0] address,
input [15 : 0] VAR3,
output reg [15 : 0] VAR2
);
reg [15 : 0] memory [255 : 0];
assign VAR1 = memory[address];
always @(posedge write)
begin
if (address == 16'hBF00)
begin
VAR2 <= VAR3;
end
else
begin
memory[address] <= VAR3;
end
end
endmodule | gpl-2.0 |
The-OpenROAD-Project/asap7 | asap7sc6t_26/Verilog/asap7sc6t_CKINVDC_SLVT_TT_210930.v | 11,799 | module MODULE1 (VAR1, VAR2);
output VAR1;
input VAR2;
not (VAR1, VAR2); | bsd-3-clause |
HighlandersFRC/fpga | lights_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_processing_system7_1_0/hdl/processing_system7_bfm_v2_0_intr_wr_mem.v | 2,774 | module MODULE1(
VAR26,
VAR21,
VAR32,
VAR20,
VAR17,
VAR3,
VAR29,
VAR28,
VAR18,
VAR2,
VAR13
);
input VAR26, VAR21;
output VAR32;
input VAR17, VAR20;
output reg VAR13, VAR2;
output reg [VAR31-1:0] VAR29;
output reg [VAR5-1:0] VAR3;
output reg [VAR15:0] VAR28;
output reg [VAR10-1:0] VAR18;
reg [VAR7-1:0] VAR4 = 0, VAR16 = ... | mit |
PiJoules/Zybo-Vision-Processing | hdmi_passthrough_720p.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v | 2,200 | module MODULE1
(clk,
VAR16,
VAR10,
VAR27,
VAR5,
VAR31,
VAR28,
VAR25,
VAR4,
VAR9,
VAR21,
VAR8,
VAR17,
VAR2);
input clk;
inout VAR16;
inout VAR10;
input VAR27;
input VAR5;
input [2:0]VAR31;
input [2:0]VAR28;
output [0:0]VAR25;
output [0:0]VAR4;
output [4:0]VAR9;
output [5:0]VAR21;
output VAR8;
output [4:0]VAR17;
output V... | unlicense |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/tapmet1/sky130_fd_sc_ls__tapmet1.behavioral.v | 1,167 | module MODULE1 ();
supply1 VAR3;
supply0 VAR2;
supply1 VAR4 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/ifu/rtl/sparc_ifu_errdp.v | 26,401 | module MODULE1(
VAR183, VAR89, VAR50, VAR22,
VAR30, VAR24, VAR171,
VAR190, VAR140,
VAR18, VAR199, VAR29, VAR112, VAR9, VAR80,
VAR43, VAR37, VAR182,
VAR56, VAR184, VAR73,
VAR99, VAR131, VAR185,
VAR2, VAR26, VAR15,
VAR156, VAR153, VAR127,
VAR203, VAR200, VAR96,
VAR125, VAR186, VAR95,
VAR27, VAR85, VAR160,
VAR122, VAR74,
... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/nor3/gf180mcu_fd_sc_mcu9t5v0__nor3_2.behavioral.v | 1,262 | module MODULE1( VAR2, VAR4, VAR5, VAR3 );
input VAR3, VAR5, VAR4;
output VAR2;
VAR1 VAR6(.VAR2(VAR2),.VAR4(VAR4),.VAR5(VAR5),.VAR3(VAR3));
VAR1 VAR7(.VAR2(VAR2),.VAR4(VAR4),.VAR5(VAR5),.VAR3(VAR3)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/edfxbp/sky130_fd_sc_ms__edfxbp.functional.pp.v | 2,082 | module MODULE1 (
VAR10 ,
VAR2 ,
VAR13 ,
VAR18 ,
VAR8 ,
VAR11,
VAR7,
VAR3 ,
VAR1
);
output VAR10 ;
output VAR2 ;
input VAR13 ;
input VAR18 ;
input VAR8 ;
input VAR11;
input VAR7;
input VAR3 ;
input VAR1 ;
wire VAR12 ;
wire VAR15;
VAR9 VAR4 (VAR15, VAR12, VAR18, VAR8 );
VAR17 VAR16 VAR6 (VAR12 , VAR15, VAR13, , VAR11, VA... | apache-2.0 |
alexforencich/verilog-ethernet | example/ExaNIC_X10/fpga/rtl/eth_xcvr_phy_wrapper.v | 9,140 | module MODULE1 #
(
parameter VAR1 = 1,
parameter VAR40 = 64,
parameter VAR79 = (VAR40/8),
parameter VAR108 = 2,
parameter VAR58 = 0,
parameter VAR133 = 0,
parameter VAR125 = 0,
parameter VAR61 = 1,
parameter VAR73 = 8,
parameter VAR7 = 125000/6.4
)
(
input wire VAR129,
input wire VAR136,
output wire VAR51,
input wire V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o22a/sky130_fd_sc_hdll__o22a_2.v | 2,355 | module MODULE2 (
VAR11 ,
VAR7 ,
VAR10 ,
VAR1 ,
VAR6 ,
VAR2,
VAR8,
VAR9 ,
VAR5
);
output VAR11 ;
input VAR7 ;
input VAR10 ;
input VAR1 ;
input VAR6 ;
input VAR2;
input VAR8;
input VAR9 ;
input VAR5 ;
VAR3 VAR4 (
.VAR11(VAR11),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR9(VAR9),
.... | apache-2.0 |
alexforencich/xfcp | lib/eth/lib/axis/rtl/axis_frame_length_adjust_fifo.v | 7,109 | module MODULE1 #
(
parameter VAR2 = 8,
parameter VAR46 = (VAR2>8),
parameter VAR10 = (VAR2/8),
parameter VAR33 = 0,
parameter VAR16 = 8,
parameter VAR9 = 0,
parameter VAR13 = 8,
parameter VAR35 = 1,
parameter VAR28 = 1,
parameter VAR43 = 4096,
parameter VAR39 = 8
)
(
input wire clk,
input wire rst,
input wire [VAR2-1:0... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o21ba/sky130_fd_sc_ms__o21ba.functional.v | 1,467 | module MODULE1 (
VAR9 ,
VAR1 ,
VAR4 ,
VAR5
);
output VAR9 ;
input VAR1 ;
input VAR4 ;
input VAR5;
wire VAR3 ;
wire VAR6;
nor VAR7 (VAR3 , VAR1, VAR4 );
nor VAR8 (VAR6, VAR5, VAR3 );
buf VAR2 (VAR9 , VAR6 );
endmodule | apache-2.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/ipshared/ENCLab/Tiger4SharedKES_v1_0_0/8069a058/src/d_KES_CS_buffer.v | 14,090 | module MODULE1
parameter VAR20 = 2,
parameter VAR46 = 12,
parameter VAR60 = 9,
parameter VAR29 = 15
)
(
VAR25 ,
VAR5 ,
VAR16 ,
VAR15 ,
VAR12 ,
VAR30 ,
VAR6 ,
VAR2 ,
VAR13 ,
VAR38 ,
VAR7 ,
VAR58 ,
VAR28 ,
VAR41 ,
VAR10 ,
VAR40 ,
VAR21 ,
VAR51 ,
VAR11 ,
VAR35 ,
VAR45 ,
VAR39 ,
VAR8 ,
VAR18 ,
VAR31 ,
VAR34 ,
VAR59 ,
VAR37... | gpl-3.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/lib/verilog/core/utils/src/small_fifo_v3.v | 2,334 | module MODULE1
parameter VAR4 = 3,
parameter VAR6 = 2**VAR4 - 1
)
(
input [VAR12-1:0] din, input VAR2,
input VAR14,
output reg [VAR12-1:0] dout, output VAR8,
output VAR1,
output VAR11,
output VAR5,
input reset,
input clk
);
parameter VAR13 = 2 ** VAR4;
reg [VAR12-1:0] VAR10 [VAR13 - 1 : 0];
reg [VAR4 - 1 : 0] VAR9;
reg... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a21oi/sky130_fd_sc_ls__a21oi.behavioral.v | 1,516 | module MODULE1 (
VAR2 ,
VAR12,
VAR1,
VAR5
);
output VAR2 ;
input VAR12;
input VAR1;
input VAR5;
supply1 VAR6;
supply0 VAR10;
supply1 VAR7 ;
supply0 VAR4 ;
wire VAR8 ;
wire VAR11;
and VAR3 (VAR8 , VAR12, VAR1 );
nor VAR13 (VAR11, VAR5, VAR8 );
buf VAR9 (VAR2 , VAR11 );
endmodule | apache-2.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.0/IPRepo-1.0.0/Tiger4NSC/src/BCHEncoderDataChannel.v | 17,896 | module MODULE1
(
parameter VAR49 = 32 ,
parameter VAR66 = 16
)
(
VAR37 ,
VAR44 ,
VAR5 ,
VAR8 ,
VAR113 ,
VAR114 ,
VAR137 ,
VAR55 ,
VAR84 ,
VAR95 ,
VAR77 ,
VAR108 ,
VAR1 ,
VAR115
);
input VAR37 ;
input VAR44 ;
input [VAR66 - 1:0] VAR5 ;
input [1:0] VAR8 ;
input VAR113 ;
output VAR114 ;
output [VAR49 - 1:0] VAR137 ;
outpu... | gpl-3.0 |
DigitalLogicSummerTerm2015/mips-cpu-single-cycle | serial_transceiver.v | 1,969 | module MODULE1(
output dout,
output reg [7:0] VAR4,
output reg [7:0] VAR25,
output ready,
input din,
input [7:0] VAR16,
input VAR14,
input clk,
input VAR31
);
parameter VAR2 = 9600,
VAR26 = 16,
VAR24 = 100000000,
VAR15 = 1000;
localparam VAR23 = VAR24 / VAR2 / VAR26,
VAR5 = VAR23 * VAR26,
VAR8 = VAR24 / VAR15;
localpar... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dffnsnq/gf180mcu_fd_sc_mcu7t5v0__dffnsnq_4.behavioral.v | 3,781 | module MODULE1( VAR30, VAR27, VAR6, VAR31 );
input VAR30, VAR27, VAR6;
output VAR31;
reg VAR2;
VAR21 VAR26(.VAR30(VAR30),.VAR27(VAR27),.VAR6(VAR6),.VAR31(VAR31),.VAR2(VAR2));
VAR21 VAR17(.VAR30(VAR30),.VAR27(VAR27),.VAR6(VAR6),.VAR31(VAR31),.VAR2(VAR2));
not VAR10(VAR11,VAR27);
and VAR16(VAR32,VAR6,VAR11);
and VAR9(VAR... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/jbi/jbi_ncio/rtl/jbi_ncio_mto_ctl.v | 19,174 | module MODULE1(
VAR18,
clk, VAR20, VAR12, VAR6,
VAR27, VAR4, VAR9,
VAR43, VAR53
);
input clk;
input VAR20;
input [31:0] VAR12;
input VAR6;
output [31:0] VAR18;
input VAR27;
input VAR4;
input [VAR8-1:0] VAR9;
input VAR43;
input [VAR10:VAR51] VAR53;
wire [31:0] VAR18;
wire [31:0] VAR1;
wire [31:0] VAR28;
wire VAR31;
wire... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai33/gf180mcu_fd_sc_mcu9t5v0__oai33_2.functional.pp.v | 1,864 | module MODULE1( VAR7, VAR10, VAR4, VAR2, VAR18, VAR3, VAR6, VAR21, VAR24 );
input VAR6, VAR3, VAR18, VAR4, VAR10, VAR7;
inout VAR21, VAR24;
output VAR2;
wire VAR19;
not VAR26( VAR19, VAR6 );
wire VAR1;
not VAR5( VAR1, VAR3 );
wire VAR23;
not VAR12( VAR23, VAR18 );
wire VAR17;
and VAR9( VAR17, VAR19, VAR1, VAR23 );
wire... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_16.behavioral.pp.v | 1,172 | module MODULE1( VAR3, VAR7, VAR4, VAR6 );
input VAR3;
inout VAR4, VAR6;
output VAR7;
VAR2 VAR5(.VAR3(VAR3),.VAR7(VAR7),.VAR4(VAR4),.VAR6(VAR6));
VAR2 VAR1(.VAR3(VAR3),.VAR7(VAR7),.VAR4(VAR4),.VAR6(VAR6)); | apache-2.0 |
Jawanga/ece385lab9 | lab9_soc/synthesis/submodules/lab9_soc_nios2_qsys_0_jtag_debug_module_sysclk.v | 7,219 | module MODULE1 (
clk,
VAR5,
VAR28,
VAR6,
VAR13,
VAR30,
VAR29,
VAR32,
VAR1,
VAR17,
VAR24,
VAR18,
VAR12,
VAR3,
VAR23,
VAR33,
VAR8,
VAR14,
VAR26
)
;
output [ 37: 0] VAR30;
output VAR29;
output VAR32;
output VAR1;
output VAR17;
output VAR24;
output VAR18;
output VAR12;
output VAR3;
output VAR23;
output VAR33;
output VAR8;
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfstp/sky130_fd_sc_ls__dfstp.pp.blackbox.v | 1,335 | module MODULE1 (
VAR5 ,
VAR3 ,
VAR2 ,
VAR8,
VAR1 ,
VAR4 ,
VAR6 ,
VAR7
);
output VAR5 ;
input VAR3 ;
input VAR2 ;
input VAR8;
input VAR1 ;
input VAR4 ;
input VAR6 ;
input VAR7 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and2b/sky130_fd_sc_ls__and2b_4.v | 2,136 | module MODULE2 (
VAR1 ,
VAR7 ,
VAR4 ,
VAR6,
VAR5,
VAR3 ,
VAR2
);
output VAR1 ;
input VAR7 ;
input VAR4 ;
input VAR6;
input VAR5;
input VAR3 ;
input VAR2 ;
VAR9 VAR8 (
.VAR1(VAR1),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR1 ,
VAR7,
VAR4
);
output VAR1 ... | apache-2.0 |
AmeerAbdelhadi/Indirectly-Indexed-2D-Binary-Content-Addressable-Memory-BCAM | pe_bhv.v | 4,068 | module MODULE1
always @(*) begin
VAR1 = {VAR3(VAR4){1'b0}};
VAR2 = VAR5[VAR1] ;
while ((!VAR2) && (VAR1!=(VAR4-1))) begin
VAR1 = VAR1 + 1 ;
VAR2 = VAR5[VAR1];
end
end
endmodule | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkdlyinv3sd2/sky130_fd_sc_ls__clkdlyinv3sd2.pp.symbol.v | 1,357 | module MODULE1 (
input VAR5 ,
output VAR3 ,
input VAR4 ,
input VAR1,
input VAR6,
input VAR2
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/a22oi/sky130_fd_sc_hvl__a22oi.symbol.v | 1,375 | module MODULE1 (
input VAR5,
input VAR6,
input VAR4,
input VAR2,
output VAR9
);
supply1 VAR7;
supply0 VAR3;
supply1 VAR1 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/einvn/sky130_fd_sc_hs__einvn.behavioral.pp.v | 1,775 | module MODULE1 (
VAR11,
VAR10,
VAR5 ,
VAR7 ,
VAR6
);
input VAR11;
input VAR10;
output VAR5 ;
input VAR7 ;
input VAR6;
wire VAR9 ;
wire VAR3;
VAR4 VAR1 (VAR9 , VAR7, VAR11, VAR10 );
VAR4 VAR8 (VAR3, VAR6, VAR11, VAR10 );
notif0 VAR2 (VAR5 , VAR9, VAR3);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfxbp/sky130_fd_sc_hs__sdfxbp.pp.blackbox.v | 1,345 | module MODULE1 (
VAR3 ,
VAR6 ,
VAR5 ,
VAR4 ,
VAR2 ,
VAR8 ,
VAR7,
VAR1
);
input VAR3 ;
input VAR6 ;
output VAR5 ;
output VAR4 ;
input VAR2 ;
input VAR8 ;
input VAR7;
input VAR1;
endmodule | apache-2.0 |
peteasa/parallella-fpga | AdaptevaLib/src/eproto_tx/hdl/eproto_tx.v | 3,946 | module MODULE1 (
VAR10, VAR2, VAR9, VAR8, VAR16,
reset, VAR5, VAR1, VAR6, VAR14,
VAR13, VAR4, VAR11, VAR12, VAR3,
VAR7
);
input reset;
input VAR5;
input VAR1;
input [1:0] VAR6;
input [3:0] VAR14;
input [31:0] VAR13;
input [31:0] VAR4;
input [31:0] VAR11;
output VAR10;
output VAR2;
output VAR9;
input VAR12; output [7:0]... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfbbn/sky130_fd_sc_ms__sdfbbn.blackbox.v | 1,528 | module MODULE1 (
VAR8 ,
VAR1 ,
VAR6 ,
VAR3 ,
VAR7 ,
VAR10 ,
VAR5 ,
VAR9
);
output VAR8 ;
output VAR1 ;
input VAR6 ;
input VAR3 ;
input VAR7 ;
input VAR10 ;
input VAR5 ;
input VAR9;
supply1 VAR12;
supply0 VAR2;
supply1 VAR11 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
nikhilghanathe/HLS-for-EMTF | verilog/sp_mux_4to1_sel2_4_1.v | 1,201 | module MODULE1 #(
parameter
VAR12 = 0,
VAR9 = 1,
VAR10 = 32,
VAR4 = 32,
VAR8 = 32,
VAR11 = 32,
VAR13 = 32,
VAR16 = 32
)(
input [3 : 0] VAR7,
input [3 : 0] VAR5,
input [3 : 0] VAR1,
input [3 : 0] VAR3,
input [1 : 0] VAR14,
output [3 : 0] dout);
wire [1 : 0] sel;
wire [3 : 0] VAR15;
wire [3 : 0] VAR2;
wire [3 : 0] VAR6;
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nand2/sky130_fd_sc_hd__nand2.functional.pp.v | 1,792 | module MODULE1 (
VAR13 ,
VAR8 ,
VAR3 ,
VAR10,
VAR9,
VAR5 ,
VAR1
);
output VAR13 ;
input VAR8 ;
input VAR3 ;
input VAR10;
input VAR9;
input VAR5 ;
input VAR1 ;
wire VAR12 ;
wire VAR4;
nand VAR11 (VAR12 , VAR3, VAR8 );
VAR7 VAR2 (VAR4, VAR12, VAR10, VAR9);
buf VAR6 (VAR13 , VAR4 );
endmodule | apache-2.0 |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/v_axi4s_vid_out_v3_0/49ac95ae/hdl/verilog/v_axi4s_vid_out_v3_0_axi4s_vid_out_top.v | 8,046 | module MODULE1
parameter VAR13 = 8,
parameter VAR70 = 2,
parameter VAR2 = 24,
parameter VAR32 = 24,
parameter VAR30 = 10, parameter VAR6 = 12, parameter VAR16 = 3,
parameter VAR52 = 0 )
(
input wire VAR11, input wire rst, input wire VAR60, input wire VAR54, input wire [VAR32-1:0] VAR17 , input wire VAR57, output wire V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor2/sky130_fd_sc_hd__nor2.behavioral.pp.v | 1,783 | module MODULE1 (
VAR11 ,
VAR6 ,
VAR13 ,
VAR4,
VAR9,
VAR5 ,
VAR12
);
output VAR11 ;
input VAR6 ;
input VAR13 ;
input VAR4;
input VAR9;
input VAR5 ;
input VAR12 ;
wire VAR7 ;
wire VAR3;
nor VAR1 (VAR7 , VAR6, VAR13 );
VAR8 VAR2 (VAR3, VAR7, VAR4, VAR9);
buf VAR10 (VAR11 , VAR3 );
endmodule | apache-2.0 |
zeruniverse/pipelined_CPU | ISE project/pbdebounce.v | 1,058 | module MODULE2
(input wire clk,
input wire VAR1,
output reg VAR2);
reg [7:0] VAR5;
wire VAR6;
MODULE1 MODULE1(clk, VAR6);
always@(posedge VAR6) begin
VAR5=VAR5<<1; VAR5[0]=VAR1;
if (VAR5==0)
VAR2=0;
if (VAR5==8'hFF) VAR2=1;
end
endmodule
module MODULE1
(input wire clk,
output reg VAR6);
reg [15:0] VAR4; | gpl-3.0 |
seyedmaysamlavasani/GorillaPP | chisel/KmeansAndMesh/emulator/Offloaded-myharness.v | 2,334 | module MODULE1;
reg [0:0] VAR17;
reg [31:0] VAR16;
reg [0:0] VAR12;
reg [0:0] VAR2;
reg [0:0] VAR15;
reg [15:0] VAR13;
reg [7:0] VAR18;
reg [15:0] VAR14;
reg [3:0] VAR7;
wire [0:0] VAR4;
wire [0:0] VAR3;
wire [31:0] VAR1;
wire [0:0] VAR8;
wire [0:0] VAR9;
wire [15:0] VAR11;
wire [7:0] VAR10;
wire [15:0] VAR5;
wire [3:0... | bsd-3-clause |
kylemsguy/FPGA-Litecoin-Miner | ICARUS-LX150/pwm_fade.v | 1,637 | module MODULE1 (clk, VAR4, VAR6);
input VAR4;
input clk;
output VAR6;
parameter VAR7 = 8;
parameter VAR2 = 1;
reg [VAR7-1:0] VAR1 = 0;
always @(posedge clk) VAR1 = VAR1 + 1;
reg [VAR5-1:0] VAR8 = 0;
always @(posedge clk)
if (VAR4) VAR8 = 0 - 1;
else if (|VAR8) VAR8 = VAR8 - 1;
wire [VAR7-1:0] VAR3;
assign VAR3 = VAR8[V... | gpl-3.0 |
jeremysalwen/combinatorial_aes | rtl/aes_128.v | 2,492 | module MODULE1(state, VAR19, out);
input [127:0] state, VAR19;
output [127:0] out;
reg [127:0] VAR12, VAR37;
wire [127:0] VAR5, VAR30, VAR10, VAR21, VAR26, VAR32, VAR6, VAR24, VAR43,
VAR22, VAR35, VAR36, VAR11, VAR28, VAR20, VAR1, VAR4, VAR16,
VAR34, VAR15, VAR18, VAR13, VAR40, VAR25, VAR8, VAR2, VAR39, VAR42;
always @... | apache-2.0 |
GustavoOS/ARMAria | src/IOmodule/DeBounce.v | 2,626 | module MODULE1
(
input clk, VAR1, output VAR3 );
assign VAR3 = ~VAR6;
reg VAR6; parameter VAR10 = 11 ; reg [VAR10-1 : 0] VAR8; reg [VAR10-1 : 0] VAR7;
reg VAR2, VAR5; wire VAR11; wire VAR4, VAR9;
assign VAR9 =1'b1;
assign VAR4 = (VAR2 ^ VAR5); assign VAR11 = ~(VAR8[VAR10-1]);
always @ ( VAR4, VAR11, VAR8)
begin
case( {... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | models/udp_dff_nsr/sky130_fd_sc_hd__udp_dff_nsr.blackbox.v | 1,345 | module MODULE1 (
VAR5 ,
VAR3 ,
VAR2,
VAR1,
VAR4
);
output VAR5 ;
input VAR3 ;
input VAR2;
input VAR1;
input VAR4 ;
endmodule | apache-2.0 |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/pcie3_7x_0/pcie3_7x_0_stub.v | 7,541 | module MODULE1(VAR35, VAR14, VAR28, VAR76, VAR68, VAR45, VAR16, VAR64, VAR80, VAR70, VAR74, VAR20, VAR59, VAR49, VAR7, VAR36, VAR48, VAR81, VAR51, VAR73, VAR8, VAR47, VAR41, VAR63, VAR58, VAR22, VAR55, VAR61, VAR18, VAR15, VAR78, VAR50, VAR26, VAR54, VAR85, VAR33, VAR89, VAR19, VAR23, VAR21, VAR66, VAR75, VAR39, VAR86,... | gpl-3.0 |
ainterr/mips_processor | inst_decoder.v | 3,135 | module MODULE1(
input [15:0] VAR12,
output reg [3:0] VAR9, output reg [1:0] VAR7,
output reg [1:0] VAR3,
output reg [1:0] VAR5,
output reg [7:0] VAR2,
output reg VAR8,
output reg VAR10,
output reg VAR11,
output reg VAR13,
output reg [2:0] VAR1,
output reg VAR4,
output reg VAR6
);
always @(VAR12) begin
VAR9 = VAR12[15:1... | mit |
ThomasLee969/verilog-homework | big_homework/cpu/Control.v | 1,906 | module MODULE1(VAR11, VAR9,
VAR10, VAR6, VAR8, VAR1,
VAR12, VAR3, VAR4,
VAR2, VAR13, VAR5, VAR14, VAR7);
input [5:0] VAR11;
input [5:0] VAR9;
output [1:0] VAR10;
output VAR6;
output VAR8;
output [1:0] VAR1;
output VAR12;
output VAR3;
output [1:0] VAR4;
output VAR2;
output VAR13;
output VAR5;
output VAR14;
output [3:0] ... | mit |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/rd_fifo_256to64.v | 13,885 | module MODULE1(
rst,
VAR328,
VAR247,
din,
VAR333,
VAR342,
dout,
VAR201,
VAR222,
VAR175,
VAR12,
VAR204
);
input rst;
input VAR328;
input VAR247;
input [255 : 0] din;
input VAR333;
input VAR342;
output [63 : 0] dout;
output VAR201;
output VAR222;
output [11 : 0] VAR175;
output [9 : 0] VAR12;
output VAR204;
VAR217 #(
.VAR... | gpl-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_auto_pc_0/zqynq_lab_1_design_auto_pc_0_stub.v | 4,404 | module MODULE1(VAR31, VAR21, VAR16, VAR33,
VAR20, VAR45, VAR18, VAR46, VAR40, VAR8,
VAR39, VAR22, VAR34, VAR51, VAR14, VAR9,
VAR17, VAR28, VAR3, VAR24, VAR4, VAR48,
VAR43, VAR11, VAR7, VAR41, VAR42, VAR52,
VAR1, VAR35, VAR2, VAR10, VAR49, VAR47,
VAR50, VAR12, VAR36, VAR55, VAR5, VAR54,
VAR19, VAR32, VAR26, VAR27, VAR56... | mit |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/tx_port_channel_gate_64.v | 7,022 | module MODULE1 #(
parameter VAR21 = 9'd64,
parameter VAR6 = 8,
parameter VAR33 = VAR21+1
)
(
input VAR35,
input VAR36, output [VAR33-1:0] VAR25, output VAR5, input VAR9,
input VAR10, input VAR27, output VAR41, input VAR39, input [31:0] VAR29, input [30:0] VAR3, input [VAR21-1:0] VAR38, input VAR16, output VAR8 );
reg [... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/xnor3/sky130_fd_sc_ls__xnor3.functional.pp.v | 1,828 | module MODULE1 (
VAR11 ,
VAR4 ,
VAR10 ,
VAR14 ,
VAR2,
VAR13,
VAR9 ,
VAR7
);
output VAR11 ;
input VAR4 ;
input VAR10 ;
input VAR14 ;
input VAR2;
input VAR13;
input VAR9 ;
input VAR7 ;
wire VAR12 ;
wire VAR3;
xnor VAR8 (VAR12 , VAR4, VAR10, VAR14 );
VAR1 VAR5 (VAR3, VAR12, VAR2, VAR13);
buf VAR6 (VAR11 , VAR3 );
endmodul... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkdlyinv5sd3/sky130_fd_sc_hs__clkdlyinv5sd3.behavioral.pp.v | 1,768 | module MODULE1 (
VAR9 ,
VAR6 ,
VAR3,
VAR10
);
output VAR9 ;
input VAR6 ;
input VAR3;
input VAR10;
wire VAR5 ;
wire VAR8;
not VAR2 (VAR5 , VAR6 );
VAR7 VAR4 (VAR8, VAR5, VAR3, VAR10);
buf VAR1 (VAR9 , VAR8 );
endmodule | apache-2.0 |
intelligenttoasters/CPC2.0 | FPGA/Quartus/custom/usb/wrapper/usbHostSlaveCyc2Wrap.v | 6,057 | module MODULE1(
VAR30,
VAR40,
VAR20,
VAR2,
VAR18,
VAR39,
VAR19,
VAR23,
irq,
VAR37,
VAR10,
VAR38,
VAR3,
VAR15
);
input VAR30;
input VAR40;
input [7:0] VAR20;
input [7:0] VAR2;
output [7:0] VAR18;
input VAR39;
input VAR19;
output VAR23;
output irq;
input VAR37;
inout VAR10 ;
inout VAR38 ;
output VAR3 ;
output VAR15 ;
wir... | gpl-3.0 |
CprE488/Final | system/hdl/system_v_vid_in_axi4s_0_wrapper.v | 2,353 | module MODULE1
(
VAR28,
rst,
VAR1,
VAR32,
VAR18,
VAR30,
VAR31,
VAR9,
VAR6,
VAR12,
VAR16,
VAR10,
VAR3,
VAR24,
VAR22,
VAR17,
VAR26,
VAR15,
VAR21,
VAR23,
VAR11,
VAR29,
VAR8,
VAR7
);
input VAR28;
input rst;
input VAR1;
input VAR32;
input VAR18;
input VAR30;
input VAR31;
input [15:0] VAR9;
input VAR6;
input VAR12;
input VAR... | gpl-3.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_fpu/bsg_fpu_i2f.v | 3,260 | module MODULE1
, parameter VAR4(VAR38)
, localparam VAR31 = (VAR34+VAR38+1)
, localparam VAR42 = {1'b0, {(VAR34-1){1'b1}}}
)
(
input VAR36
, input VAR5
, input VAR3
, input VAR35
, input VAR30
, input [VAR31-1:0] VAR12
, output logic VAR16
, output logic VAR17
, output logic [VAR31-1:0] VAR2
, input VAR22
);
logic VAR1... | bsd-3-clause |
freecores/orsoc_graphics_accelerator | rtl/verilog/gfx/gfx_interp.v | 5,172 | module MODULE1(VAR38, VAR14,
VAR45, VAR49,
VAR35,
VAR30, VAR55, VAR62,
VAR9, VAR11, VAR29, VAR23,
VAR50, VAR61,
VAR33
);
parameter VAR52 = 16;
parameter VAR43 = 5;
parameter VAR59 = VAR52+1;
parameter VAR60 = 4;
input VAR38;
input VAR14;
input VAR45;
output reg VAR49;
input VAR35;
input [2*VAR52-1:0] VAR30;
input [2*VA... | gpl-3.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_076.v | 1,533 | module MODULE1 (
VAR11,
VAR9
);
input [31:0] VAR11;
output [31:0]
VAR9;
wire [31:0]
VAR14,
VAR5,
VAR12,
VAR3,
VAR2,
VAR1,
VAR6,
VAR8,
VAR7;
assign VAR14 = VAR11;
assign VAR3 = VAR14 << 7;
assign VAR8 = VAR2 << 1;
assign VAR7 = VAR6 + VAR8;
assign VAR1 = VAR14 << 5;
assign VAR12 = VAR5 - VAR14;
assign VAR5 = VAR14 << 13... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o31a/sky130_fd_sc_hs__o31a_4.v | 2,195 | module MODULE1 (
VAR7 ,
VAR6 ,
VAR3 ,
VAR8 ,
VAR5 ,
VAR2,
VAR9
);
output VAR7 ;
input VAR6 ;
input VAR3 ;
input VAR8 ;
input VAR5 ;
input VAR2;
input VAR9;
VAR4 VAR1 (
.VAR7(VAR7),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR9(VAR9)
);
endmodule
module MODULE1 (
VAR7 ,
VAR6,
VAR3,
VAR8,
VAR5
);... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/mux4/sky130_fd_sc_hd__mux4.pp.blackbox.v | 1,376 | module MODULE1 (
VAR6 ,
VAR1 ,
VAR8 ,
VAR3 ,
VAR2 ,
VAR5 ,
VAR9 ,
VAR11,
VAR7,
VAR10 ,
VAR4
);
output VAR6 ;
input VAR1 ;
input VAR8 ;
input VAR3 ;
input VAR2 ;
input VAR5 ;
input VAR9 ;
input VAR11;
input VAR7;
input VAR10 ;
input VAR4 ;
endmodule | apache-2.0 |
dm-urievich/afc-smm | software/third-patry/pipelined_fft_256/trunk/SRC/ram2x256.v | 5,661 | module MODULE1 ( VAR3 ,VAR2 ,VAR6 ,VAR23 ,VAR17 ,VAR34 ,VAR33 ,VAR18 ,VAR4 ,VAR24 );
output [VAR9-1:0] VAR4 ;
wire [VAR9-1:0] VAR4 ;
output [VAR9-1:0] VAR24 ;
wire [VAR9-1:0] VAR24 ;
input VAR3 ;
wire VAR3 ;
input VAR2 ;
wire VAR2 ;
input VAR6 ; wire VAR6 ;
input VAR23 ; wire VAR23 ;
input [7:0] VAR17 ;
wire [7:0] VAR1... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai31/gf180mcu_fd_sc_mcu9t5v0__oai31_4.functional.v | 1,436 | module MODULE1( VAR12, VAR6, VAR3, VAR7, VAR5 );
input VAR7, VAR3, VAR12, VAR5;
output VAR6;
wire VAR9;
not VAR11( VAR9, VAR7 );
wire VAR14;
not VAR1( VAR14, VAR3 );
wire VAR13;
not VAR10( VAR13, VAR12 );
wire VAR15;
and VAR2( VAR15, VAR9, VAR14, VAR13 );
wire VAR4;
not VAR16( VAR4, VAR5 );
or VAR8( VAR6, VAR15, VAR4 )... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor2/sky130_fd_sc_hd__nor2.blackbox.v | 1,233 | module MODULE1 (
VAR6,
VAR7,
VAR5
);
output VAR6;
input VAR7;
input VAR5;
supply1 VAR3;
supply0 VAR4;
supply1 VAR2 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
minosys-jp/FPGA | Zybo/vgagraph/vgagraph/HDL/vgagraph_ip_v1_0.v | 5,377 | module MODULE1 #
(
parameter VAR14 = 32'h40000000,
parameter integer VAR97 = 16,
parameter integer VAR53 = 1,
parameter integer VAR121 = 32,
parameter integer VAR23 = 32,
parameter integer VAR25 = 0,
parameter integer VAR13 = 0,
parameter integer VAR79 = 0,
parameter integer VAR10 = 0,
parameter integer VAR50 = 0
)
(
i... | bsd-2-clause |
pemsac/ANN_project | ANN_project.ip_user_repository/UC3M_MISEA_Thesis_feedforward_1_4/hdl/verilog/feedforward_mul_7ns_31ns_38_3.v | 1,407 | module MODULE1(clk, VAR15, VAR12, VAR13, VAR1);
input clk;
input VAR15;
input[7 - 1 : 0] VAR12; input[31 - 1 : 0] VAR13; output[38 - 1 : 0] VAR1;
reg [7 - 1 : 0] VAR2;
reg [31 - 1 : 0] VAR8;
wire [38 - 1 : 0] VAR16;
reg [38 - 1 : 0] VAR9;
assign VAR1 = VAR9;
assign VAR16 = VAR2 * VAR8;
always @ (posedge clk) begin
if (... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfsbp/sky130_fd_sc_ms__sdfsbp_2.v | 2,615 | module MODULE1 (
VAR5 ,
VAR4 ,
VAR11 ,
VAR10 ,
VAR13 ,
VAR9 ,
VAR3,
VAR1 ,
VAR7 ,
VAR2 ,
VAR8
);
output VAR5 ;
output VAR4 ;
input VAR11 ;
input VAR10 ;
input VAR13 ;
input VAR9 ;
input VAR3;
input VAR1 ;
input VAR7 ;
input VAR2 ;
input VAR8 ;
VAR6 VAR12 (
.VAR5(VAR5),
.VAR4(VAR4),
.VAR11(VAR11),
.VAR10(VAR10),
.VAR13(... | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_comm_link/master_calib_skip/bsg_source_sync_channel_control_master_master.v | 2,118 | module MODULE1
, parameter VAR16(VAR9 )
, parameter VAR16(VAR17 ) , parameter VAR16(VAR7 )) (input VAR13 , input VAR15
, input VAR8
, input [VAR9+1-1:0][VAR18-1:0] VAR11
, output [VAR12(VAR9+1)-1:0] VAR20
, output VAR10
, output VAR3 );
logic VAR14, VAR5;
logic [VAR12(VAR9+1)-1:0] VAR19, VAR2;
assign VAR20 = VAR2;
logi... | bsd-3-clause |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_dac_1c_2p_v1_00_a/hdl/verilog/cf_ddsv_vdma.v | 10,442 | module MODULE1 (
VAR21,
VAR48,
VAR40,
VAR43,
VAR1,
VAR6,
VAR28,
VAR44,
VAR12,
VAR45,
VAR32,
VAR31,
VAR4,
VAR14);
input VAR21;
input VAR48;
input [63:0] VAR40;
output VAR43;
output VAR1;
output VAR6;
input VAR28;
input VAR44;
input VAR12;
output [95:0] VAR45;
output [198:0] VAR32;
output [ 7:0] VAR31;
output [107:0] VAR... | mit |
ankitshah009/High-Radix-Adaptive-CORDIC | HCORDIC_Verilog/mult_k.v | 2,660 | module MODULE1(
input [31:0] VAR22,
input [31:0] VAR3,
input reset,
input VAR29,
output [31:0] VAR5
);
wire VAR8, VAR21, VAR6;
wire [32:0] VAR20,VAR23;
wire [32:0] VAR25,VAR13,VAR17;
wire [49:0] VAR34, VAR11;
wire [31:0] VAR16,VAR27,VAR2,VAR12;
VAR19 VAR14 (
.VAR9(VAR22),
.VAR24(VAR3),
.reset(reset),
.VAR29(VAR29),
.VA... | apache-2.0 |
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