repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
GSejas/Dise-o-ASIC-FPGA-FPU | Literature FPUs/hrfp_1.0/hrfp_backup_add.v | 1,804 | module MODULE1
(input wire clk,
input wire [VAR5:0] VAR12, VAR18,
input wire [30:0] VAR15, VAR19,
input wire VAR11,
output reg [VAR5:0] VAR14,
output reg [30:0] VAR4,
output reg [7:0] VAR9);
reg [VAR5:0] VAR17;
reg [30:0] VAR2;
reg [7:0] VAR7;
reg [30:0] VAR1;
always @* begin
if(VAR11) begin
VAR1 <= VAR19;
end else beg... | gpl-3.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/adder_trees/verilog/adder_tree_2L_004bits.v | 1,917 | module MODULE1 (
clk,
VAR3, VAR9, VAR10, VAR15, VAR4, VAR13, VAR6, VAR22,
sum,
);
input clk;
input [VAR11+0-1:0] VAR3, VAR9, VAR10, VAR15, VAR4, VAR13, VAR6, VAR22;
output [VAR11 :0] sum;
reg [VAR11 :0] sum;
wire [VAR11+3-1:0] VAR23;
wire [VAR11+2-1:0] VAR29, VAR18;
wire [VAR11+1-1:0] VAR14, VAR17, VAR7, VAR19;
reg [VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/maj3/sky130_fd_sc_lp__maj3.functional.v | 1,485 | module MODULE1 (
VAR9,
VAR2,
VAR7,
VAR5
);
output VAR9;
input VAR2;
input VAR7;
input VAR5;
wire VAR10 ;
wire VAR13 ;
wire VAR11 ;
wire VAR4;
or VAR1 (VAR10 , VAR7, VAR2 );
and VAR12 (VAR13 , VAR10, VAR5 );
and VAR3 (VAR11 , VAR2, VAR7 );
or VAR8 (VAR4, VAR11, VAR13);
buf VAR6 (VAR9 , VAR4 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor4b/sky130_fd_sc_hs__nor4b.behavioral.v | 1,882 | module MODULE1 (
VAR11 ,
VAR3 ,
VAR15 ,
VAR10 ,
VAR14 ,
VAR9,
VAR7
);
output VAR11 ;
input VAR3 ;
input VAR15 ;
input VAR10 ;
input VAR14 ;
input VAR9;
input VAR7;
wire VAR14 VAR1 ;
wire VAR4 ;
wire VAR5;
not VAR8 (VAR1 , VAR14 );
nor VAR2 (VAR4 , VAR3, VAR15, VAR10, VAR1 );
VAR6 VAR12 (VAR5, VAR4, VAR9, VAR7);
buf VAR... | apache-2.0 |
freecores/tiny_tate_bilinear_pairing | group_size_is_151_bits/rtl/pairing.v | 1,349 | module MODULE1(clk, reset, sel, addr, VAR3, VAR6, ready, VAR5, VAR8, VAR1);
input clk;
input reset; input sel;
input [5:0] addr;
input VAR3;
input VAR6; input ready; input VAR5;
output VAR8;
output VAR1;
reg [197:0] VAR7, VAR4;
wire [197:0] out;
assign VAR8 = VAR4[0];
VAR2
VAR9 (clk, reset, sel, addr, VAR3, VAR7, out, ... | apache-2.0 |
azonenberg/yosys | techlibs/intel/cycloneiv/cells_arith.v | 3,728 | module MODULE1(
module 80cycloneivalu (VAR17, VAR29, VAR18, VAR24, VAR23, VAR21, VAR3);
parameter VAR15 = 0;
parameter VAR9 = 0;
parameter VAR28 = 1;
parameter VAR16 = 1;
parameter VAR34 = 1;
input [VAR28-1:0] VAR17;
input [VAR16-1:0] VAR29;
output [VAR34-1:0] VAR23, VAR21;
input VAR18, VAR24;
output [VAR34:0] VAR3;
wi... | isc |
Valakor/EE201-Text-Editor | PS2_Controller.v | 7,825 | module MODULE1 #(parameter VAR11 = 0) (
VAR35,
reset,
VAR25,
VAR18,
VAR15, VAR2,
VAR5,
VAR32,
VAR22,
VAR14 );
input VAR35;
input reset;
input [7:0] VAR25;
input VAR18;
inout VAR15;
inout VAR2;
output VAR5;
output VAR32;
output [7:0] VAR22;
output VAR14;
wire [7:0] VAR6;
wire VAR4, VAR23, VAR26;
generate
if(VAR11) begin... | mit |
davidkoltak/tawas-core | ip/rcn/rtl/rcn_fifo_async.v | 2,380 | module MODULE1
(
input VAR16,
input VAR3,
input VAR20,
input [68:0] VAR2,
input VAR7,
output VAR4,
output [68:0] VAR8,
input VAR14,
output VAR19
);
parameter VAR11 = 16;
reg [1:0] VAR10;
reg [5:0] VAR18;
reg [5:0] VAR15;
reg [5:0] VAR17;
reg [1:0] VAR21;
reg [5:0] VAR13;
reg [5:0] VAR23;
reg [5:0] VAR9;
always @ (posed... | mit |
Triple-Z/COExperiment_Repo | Project_Assignment/datapath/dm.v | 1,410 | module MODULE1 (addr, din, VAR2, VAR3, clk, dout);
input [11:0] addr;
input [31:0] din;
input [1:0] VAR2;
input [1:0] VAR3;
input clk;
output reg [31:0] dout;
reg [31:0] VAR5 [1023:0];
wire [1:0] VAR1;
wire [9:0] VAR6;
reg [7:0] VAR4;
reg [31:0] VAR7;
assign VAR1 = addr[1:0] ^ 2'b11; assign VAR6 = addr[11:2];
always @ ... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/nand3/gf180mcu_fd_sc_mcu9t5v0__nand3_4.functional.v | 1,218 | module MODULE1( VAR2, VAR3, VAR6, VAR8 );
input VAR8, VAR2, VAR3;
output VAR6;
wire VAR11;
not VAR5( VAR11, VAR8 );
wire VAR10;
not VAR9( VAR10, VAR2 );
wire VAR7;
not VAR1( VAR7, VAR3 );
or VAR4( VAR6, VAR11, VAR10, VAR7 );
endmodule | apache-2.0 |
alexforencich/verilog-ethernet | rtl/eth_mac_1g_gmii_fifo.v | 10,843 | module MODULE1 #
(
parameter VAR66 = "VAR76",
parameter VAR86 = "VAR34",
parameter VAR102 = "VAR14",
parameter VAR112 = 8,
parameter VAR97 = (VAR112>8),
parameter VAR91 = (VAR112/8),
parameter VAR122 = 1,
parameter VAR10 = 64,
parameter VAR1 = 4096,
parameter VAR25 = 1,
parameter VAR41 = 1,
parameter VAR4 = VAR41,
para... | mit |
aap/pdp6 | verilog/ptp.v | 4,511 | module MODULE1(
input wire clk,
input wire reset,
input wire VAR5,
input wire VAR40,
input wire VAR18,
input wire VAR31,
input wire VAR24,
input wire VAR26,
input wire VAR28,
input wire VAR1,
input wire VAR36, input wire [3:9] VAR42,
input wire [0:35] VAR30,
output wire [1:7] VAR21,
output wire [0:35] VAR32,
output wir... | mit |
freecores/sha3 | high_throughput_core/rtl/rconst2in1.v | 1,738 | module MODULE1(VAR2, VAR3, VAR1);
input [11:0] VAR2;
output [63:0] VAR3, VAR1;
reg [63:0] VAR3, VAR1;
always @ (VAR2)
begin
VAR3 = 0;
VAR3[0] = VAR2[0] | VAR2[2] | VAR2[3] | VAR2[5] | VAR2[6] | VAR2[7] | VAR2[10] | VAR2[11];
VAR3[1] = VAR2[1] | VAR2[2] | VAR2[4] | VAR2[6] | VAR2[8] | VAR2[9];
VAR3[3] = VAR2[1] | VAR2[2... | apache-2.0 |
hakehuang/pycpld | ips/ip/spi_master_reduced/spi_ctrl_reduced.v | 1,347 | module MODULE1(
clk,VAR13,VAR1,VAR5,VAR19,VAR15,VAR11,VAR2,VAR14,VAR17
);
parameter VAR18 = 64;
input clk,VAR13,VAR19;
input VAR14;
output VAR1,VAR5,VAR15;
output VAR17;
input VAR11;
input VAR2;
wire VAR6;
wire VAR17;
reg VAR12;
reg[7:0] VAR10;
reg[7:0] VAR9;
reg VAR7;
assign VAR15 = 1'b0;
always @(posedge clk or neged... | mit |
varunnagpaal/Digital-Hardware-Modelling | xilinx-vivado/gcd_snickerdoodle/gcd_snickerdoodle.srcs/sources_1/bd/gcd_zynq_snick/ip/gcd_zynq_snick_auto_pc_0/gcd_zynq_snick_auto_pc_0_stub.v | 4,607 | module MODULE1(VAR38, VAR13, VAR26, VAR52,
VAR57, VAR35, VAR49, VAR39, VAR9, VAR46,
VAR16, VAR12, VAR17, VAR22, VAR37, VAR58, VAR21,
VAR31, VAR36, VAR27, VAR7, VAR44, VAR43, VAR30,
VAR4, VAR55, VAR54, VAR19, VAR10, VAR15,
VAR23, VAR5, VAR47, VAR14, VAR34, VAR8, VAR56,
VAR41, VAR29, VAR51, VAR11, VAR42, VAR24,
VAR6, VAR... | mit |
f3zz3h/Embedded-Co-Design | ts7300_top_restored/altera_dpram_16x32.v | 8,667 | module MODULE1 (
VAR50,
VAR41,
VAR4,
VAR24,
VAR12,
VAR43);
input VAR50;
input [31:0] VAR41;
input [3:0] VAR4;
input [3:0] VAR24;
input VAR12;
output [31:0] VAR43;
wire [31:0] VAR1;
wire [31:0] VAR43 = VAR1[31:0];
VAR17 VAR18 (
.VAR19 (VAR12),
.VAR35 (VAR50),
.VAR42 (VAR24),
.VAR31 (VAR4),
.VAR16 (VAR41),
.VAR8 (VAR1),
... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/fahcin/sky130_fd_sc_ls__fahcin.pp.blackbox.v | 1,342 | module MODULE1 (
VAR9,
VAR8 ,
VAR5 ,
VAR7 ,
VAR2 ,
VAR1,
VAR4,
VAR3 ,
VAR6
);
output VAR9;
output VAR8 ;
input VAR5 ;
input VAR7 ;
input VAR2 ;
input VAR1;
input VAR4;
input VAR3 ;
input VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or4bb/sky130_fd_sc_ls__or4bb.functional.pp.v | 1,988 | module MODULE1 (
VAR11 ,
VAR3 ,
VAR16 ,
VAR2 ,
VAR6 ,
VAR15,
VAR9,
VAR14 ,
VAR13
);
output VAR11 ;
input VAR3 ;
input VAR16 ;
input VAR2 ;
input VAR6 ;
input VAR15;
input VAR9;
input VAR14 ;
input VAR13 ;
wire VAR8 ;
wire VAR17 ;
wire VAR12;
nand VAR7 (VAR8 , VAR6, VAR2 );
or VAR4 (VAR17 , VAR16, VAR3, VAR8 );
VAR10 VA... | apache-2.0 |
jmacneal/Design-Project | Display/VGA_Controller/VGA_Controller.v | 4,313 | module MODULE1( VAR23,
VAR35,
VAR37,
VAR36,
VAR29,
VAR39,
VAR4,
VAR15,
VAR22,
VAR31,
VAR26,
VAR1,
VAR16,
VAR18,
VAR10,
VAR33,
VAR21,
VAR8,
VAR7,
VAR3,
VAR30,
VAR11 );
output reg [19:0] VAR31;
output reg [9:0] VAR26;
output reg [9:0] VAR1;
input [3:0] VAR23;
input [9:0] VAR35;
input [9:0] VAR37;
input [9:0] VAR36;
input... | gpl-3.0 |
olajep/oh | src/adi/hdl/library/common/ad_dds_cordic_pipe.v | 3,597 | module MODULE1#(
parameter VAR7 = 16,
parameter VAR10 = 16,
parameter VAR8 = 1,
parameter VAR2 = 0) (
input clk,
input VAR12,
input [ VAR10-1:0] VAR1,
input [ VAR10-1:0] VAR6,
input [ VAR7-1:0] VAR11,
input [ VAR7-1:0] VAR17,
output reg [ VAR10-1:0] VAR18,
output reg [ VAR10-1:0] VAR4,
output reg [ VAR7-1:0] VAR15,
inp... | mit |
asicguy/gplgpu | hdl/altera_ddr3/alt_ddrx_decoder_72.v | 29,831 | module MODULE1
(
VAR77,
VAR70,
VAR28,
VAR39,
VAR51,
VAR33) ;
input VAR77;
input [71:0] VAR70;
output VAR28;
output VAR39;
output VAR51;
output [63:0] VAR33;
tri0 VAR77;
reg [0:0] VAR22;
reg [0:0] VAR58;
reg [0:0] VAR27;
reg [63:0] VAR31;
wire [127:0] VAR19;
wire VAR98;
wire VAR41;
wire VAR52;
wire VAR23;
wire VAR60;
wi... | gpl-3.0 |
rkrajnc/minimig-mist | rtl/minimig/agnus_blitter.v | 27,504 | module MODULE1
(
input clk, input VAR8,
input reset, input VAR33, input VAR15, input VAR10, output VAR66, input VAR56, output VAR72, output reg VAR70, output reg VAR40, output VAR73, input [15:0] VAR61, output [15:0] VAR17, input [8:1] VAR91, output [20:1] VAR45, output reg [8:1] VAR39 );
parameter VAR106 = 9'h040;
par... | gpl-3.0 |
ncos/Xilinx-Verilog | GYRACC/src/ACC/format_data.v | 3,125 | module MODULE1(
VAR13,
VAR4,
VAR9,
VAR1,
VAR3
);
input VAR13;
input VAR4;
input VAR9;
input wire [9:0] VAR1;
output reg [15:0] VAR3;
wire [8:0] VAR8;
wire [15:0] VAR6;
reg [16:0] VAR2; reg [9:0] VAR10; always @(posedge VAR13) begin
VAR10 <= (VAR1[9] == 1'b1) ? ((~(VAR1)) + 1'b1) : VAR1;
VAR2 <= VAR10[8:0] * 8'd201;
end... | mit |
ptracton/UART_ECHO | tasks/uart_tasks.v | 2,733 | module MODULE1;
task VAR6;
begin
@(posedge VAR8);
@(posedge VAR8);
@(posedge VAR8);
@(posedge VAR8);
@(posedge VAR8);
@(posedge VAR8);
end
endtask
task VAR7;
input [7:0] VAR3;
begin
@(posedge VAR8);
end
endtask
task VAR9;
input [7:0] VAR2;
begin
begin
end
end
endtask
endmodule | mit |
ashwith/hdlroot | lib/modules/uart/design/uart_ctrl.v | 1,711 | module MODULE1(
input VAR10,
input VAR8,
input VAR34,
input [3:0] VAR19,
input VAR2,
input VAR29,
output VAR15,
input VAR4,
input VAR6,
input [7:0] VAR16,
output VAR5,
input VAR30,
output [7:0] VAR11,
output VAR13
);
wire VAR1;
wire VAR7;
wire [7:0] VAR35;
wire VAR36;
wire VAR26;
wire VAR20;
wire [7:0] VAR32;
wire VAR2... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/xor2/sky130_fd_sc_hs__xor2.pp.symbol.v | 1,261 | module MODULE1 (
input VAR3 ,
input VAR1 ,
output VAR2 ,
input VAR5,
input VAR4
);
endmodule | apache-2.0 |
rfotino/consolite-hardware | src/vga_display.v | 5,105 | module MODULE1
(
input clk,
input VAR10,
output VAR37,
output VAR13,
output reg [7:0] VAR8,
output VAR48,
output VAR3,
output [2:0] VAR53,
output [5:0] VAR33,
output [29:0] VAR4,
input VAR45,
input VAR15,
output VAR19,
output VAR42,
input [31:0] VAR22,
input VAR2,
input VAR32,
input [6:0] VAR29,
input VAR5,
input VAR24... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/einvn/sky130_fd_sc_hdll__einvn_2.v | 2,166 | module MODULE1 (
VAR7 ,
VAR3 ,
VAR5,
VAR1,
VAR6,
VAR4 ,
VAR8
);
output VAR7 ;
input VAR3 ;
input VAR5;
input VAR1;
input VAR6;
input VAR4 ;
input VAR8 ;
VAR9 VAR2 (
.VAR7(VAR7),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR8(VAR8)
);
endmodule
module MODULE1 (
VAR7 ,
VAR3 ,
VAR5
);
output VAR7 ;... | apache-2.0 |
zuloloxi/mecrisp-ice | hx8k/icestorm/j1a.v | 17,261 | module MODULE1(
output [1:0] VAR210,
input VAR16, VAR199, VAR47,
input [10:0] VAR24,
input VAR70, VAR113, VAR35,
input [10:0] VAR83,
input [1:0] VAR111, VAR182
);
parameter VAR206 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter VAR133 = 256'h0000000000000000000000000000000000000000000... | bsd-3-clause |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dffnrnq/gf180mcu_fd_sc_mcu7t5v0__dffnrnq_1.behavioral.pp.v | 3,755 | module MODULE1( VAR31, VAR9, VAR22, VAR3, VAR4, VAR24 );
input VAR31, VAR9, VAR22;
inout VAR4, VAR24;
output VAR3;
reg VAR2;
VAR1 VAR33(.VAR31(VAR31),.VAR9(VAR9),.VAR22(VAR22),.VAR3(VAR3),.VAR4(VAR4),.VAR24(VAR24),.VAR2(VAR2));
VAR1 VAR29(.VAR31(VAR31),.VAR9(VAR9),.VAR22(VAR22),.VAR3(VAR3),.VAR4(VAR4),.VAR24(VAR24),.VA... | apache-2.0 |
mcgodfrey/i2c-eeprom | read_i2c_eeprom.v | 4,483 | module MODULE1(
input clk,
input VAR52,
input VAR10,
output[7:0]VAR33,
output VAR29,
input VAR38,
input VAR45,
input VAR22,
output [3:0] VAR11,
input VAR49, output VAR54, input VAR9
);
wire reset = ~VAR52;
assign VAR29 = 1'VAR18;
assign VAR54 = 1'VAR18;
assign VAR11 = 4'VAR56;
assign VAR33[5:0] = 6'b000000;
assign VAR3... | mit |
praveendath92/securePUF | ipcore_dir/TemperatureMonitor.v | 6,533 | module MODULE1
(
VAR20, VAR19, VAR59, VAR41, VAR55, VAR35, VAR45, VAR23, VAR61);
input [6:0] VAR20;
input VAR19;
input VAR59;
input [15:0] VAR41;
input VAR55;
input VAR23;
input VAR61;
output [15:0] VAR35;
output VAR45;
wire VAR1;
wire VAR30;
wire VAR27;
wire VAR11;
wire [2:0] VAR7;
assign VAR11 = 0;
wire [15:0] VAR5;
... | gpl-2.0 |
AngelTerrones/MUSB | Hardware/uart/uart.v | 7,722 | module MODULE1(
input clk,
input rst,
input [2:0] VAR10, input [7:0] VAR50, input VAR41, input VAR26, output reg [7:0] VAR15, output reg VAR18, output VAR46, output VAR38, input VAR23, output VAR35 );
localparam VAR28 = 8; localparam VAR5 = 8;
localparam VAR39 = 0; localparam VAR21 = 1; localparam VAR47 = 2; localparam... | mit |
chris-wood/yield | sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ip/zc702_m00_regslice_0/synth/zc702_m00_regslice_0.v | 10,708 | module MODULE1 (
VAR35,
VAR108,
VAR39,
VAR56,
VAR64,
VAR109,
VAR60,
VAR84,
VAR68,
VAR5,
VAR51,
VAR20,
VAR6,
VAR79,
VAR88,
VAR93,
VAR31,
VAR104,
VAR45,
VAR98,
VAR73,
VAR54,
VAR40,
VAR23,
VAR26,
VAR21,
VAR38,
VAR47,
VAR65,
VAR18,
VAR66,
VAR59,
VAR10,
VAR97,
VAR27,
VAR69,
VAR55,
VAR82,
VAR107,
VAR50
);
input wire VAR35;
i... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/edfxtp/sky130_fd_sc_hd__edfxtp.blackbox.v | 1,345 | module MODULE1 (
VAR5 ,
VAR3,
VAR8 ,
VAR6
);
output VAR5 ;
input VAR3;
input VAR8 ;
input VAR6 ;
supply1 VAR2;
supply0 VAR4;
supply1 VAR7 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
hydai/Verilog-Practice | DigitalDesign/101062124_hw4/my_64x16_t.v | 1,688 | module MODULE1;
reg [9:0] VAR8 [VAR3-1:0];
parameter period = 20;
parameter delay = 2;
reg clk, VAR10, VAR4, VAR9;
reg [15:0] VAR7;
wire VAR12, VAR11, VAR1, VAR14, VAR5;
wire [15:0] VAR15;
integer VAR13;
VAR2 VAR6 (
clk,
VAR10,
VAR4,
VAR9,
VAR7,
VAR12,
VAR11,
VAR1,
VAR14,
VAR5,
VAR15
);
always #(period/2) clk = ~clk;
b... | mit |
e33b1711/rfnoc_pp_channelizer | sysgen_models/syntheses/checkpoint/sysgen/syntheses_entity_declarations.v | 22,088 | module MODULE2 (
output [(8 - 1):0] VAR3,
input clk,
input VAR1,
input VAR2);
assign VAR3 = 8'b00000001;
endmodule
module MODULE1 (
input [(1 - 1):0] VAR5,
output [(1 - 1):0] VAR3,
input clk,
input VAR1,
input VAR2);
wire VAR6;
reg VAR4[0:(1 - 1)];
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/mux2i/sky130_fd_sc_lp__mux2i.functional.pp.v | 1,934 | module MODULE1 (
VAR14 ,
VAR9 ,
VAR11 ,
VAR8 ,
VAR2,
VAR4,
VAR13 ,
VAR7
);
output VAR14 ;
input VAR9 ;
input VAR11 ;
input VAR8 ;
input VAR2;
input VAR4;
input VAR13 ;
input VAR7 ;
wire VAR10;
wire VAR3;
VAR5 VAR15 (VAR10, VAR9, VAR11, VAR8 );
VAR12 VAR6 (VAR3, VAR10, VAR2, VAR4);
buf VAR1 (VAR14 , VAR3 );
endmodule | apache-2.0 |
Triple-Z/COExperiment_Repo | Project_Assignment/mips.v | 3,196 | module MODULE1 (clk, rst);
input clk;
input rst;
wire [31:0] VAR10;
wire [31:0] VAR68;
wire [31:0] VAR51;
wire [31:0] VAR71;
wire [31:0] VAR32;
wire [31:0] VAR21;
wire [31:0] VAR60;
wire [31:0] VAR72;
wire [31:0] VAR41;
wire [31:0] VAR38;
wire [31:0] VAR37;
wire [31:0] VAR14;
wire [4:0] VAR57;
wire [31:0] VAR2;
wire [3... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or4/sky130_fd_sc_lp__or4.symbol.v | 1,282 | module MODULE1 (
input VAR1,
input VAR5,
input VAR2,
input VAR9,
output VAR3
);
supply1 VAR7;
supply0 VAR4;
supply1 VAR6 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
alexforencich/verilog-dsp | rtl/i2s_ctrl.v | 2,258 | module MODULE1 #
(
parameter VAR8 = 16
)
(
input wire clk,
input wire rst,
output wire VAR5,
output wire VAR2,
input wire [15:0] VAR7
);
reg [15:0] VAR3 = 0;
reg [VAR4(VAR8)-1:0] VAR1 = 0;
reg VAR6 = 0;
reg VAR9 = 0;
assign VAR5 = VAR6;
assign VAR2 = VAR9;
always @(posedge clk) begin
if (rst) begin
VAR3 <= 0;
VAR1 <= 0... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o311a/sky130_fd_sc_hs__o311a.behavioral.pp.v | 1,954 | module MODULE1 (
VAR13,
VAR14,
VAR2 ,
VAR7 ,
VAR3 ,
VAR4 ,
VAR8 ,
VAR1
);
input VAR13;
input VAR14;
output VAR2 ;
input VAR7 ;
input VAR3 ;
input VAR4 ;
input VAR8 ;
input VAR1 ;
wire VAR8 VAR6 ;
wire VAR16 ;
wire VAR15;
or VAR5 (VAR6 , VAR3, VAR7, VAR4 );
and VAR9 (VAR16 , VAR6, VAR8, VAR1 );
VAR10 VAR12 (VAR15, VAR16... | apache-2.0 |
jayant-sharma/ft2232h-fifo | hdl/sp_sync_fifo.v | 2,146 | module MODULE1 #(
parameter VAR7 = 8,
parameter VAR8 = 256,
parameter VAR3 = VAR6(VAR8)
)(
input rst,
input clk,
input wr,
input rd,
input [VAR7-1:0] din,
output [VAR7-1:0] dout,
output VAR9,
output VAR1
);
reg [VAR3:0] VAR10, VAR5;
wire [VAR7-1:0] VAR4;
wire [VAR3-1:0] VAR11;
reg VAR2; | unlicense |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a22oi/sky130_fd_sc_hs__a22oi.pp.symbol.v | 1,343 | module MODULE1 (
input VAR4 ,
input VAR1 ,
input VAR7 ,
input VAR5 ,
output VAR2 ,
input VAR3,
input VAR6
);
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig34/mig_v3_4/user_design/rtl/controller/bank_mach.v | 31,025 | module MODULE1 #
(
parameter VAR25 = 100,
parameter VAR153 = "VAR98",
parameter VAR62 = 3,
parameter VAR81 = 2,
parameter VAR167 = "8",
parameter VAR24 = 12,
parameter VAR111 = 4,
parameter VAR79 = 5,
parameter VAR118 = 8,
parameter VAR77 = "VAR136",
parameter VAR57 = "VAR33",
parameter VAR126 = "VAR33",
parameter VAR5... | lgpl-3.0 |
rbarzic/async_logic | async_lib/single_rail_2ph/fork_cond_r1_2ph/fork_cond_r1_2ph.v | 1,690 | module MODULE1 (
VAR13, VAR26, VAR22,
VAR18, VAR3, VAR20, VAR21, VAR11, VAR15
);
parameter VAR17 = 8;
input VAR18;
output VAR13;
output VAR26;
input VAR3;
input VAR20;
output VAR22;
input VAR21;
input VAR11;
input VAR15;
wire VAR19, VAR14;
wire VAR26,VAR22;
wire VAR13;
select VAR16(
.in(VAR18),
.sel(VAR20),
.false(VAR1... | gpl-2.0 |
eda-globetrotter/PicenoDecoders | coding_theory/pipelinedec.v | 1,289 | module MODULE1 (VAR2,VAR1,out);
output reg [14:0] out;
input [14:0] VAR2;
input [15:1] VAR1;
always @
begin
out[0]=in[2];
out[1]=in[4];
out[2]=in[5];
out[3]=in[6];
out[4]=in[8];
out[5]=in[9];
out[6]=in[10];
out[7]=in[11];
out[8]=in[12];
out[9]=in[13];
out[10]=in[14];
end
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or3b/sky130_fd_sc_hdll__or3b_1.v | 2,225 | module MODULE1 (
VAR4 ,
VAR2 ,
VAR3 ,
VAR9 ,
VAR7,
VAR6,
VAR5 ,
VAR8
);
output VAR4 ;
input VAR2 ;
input VAR3 ;
input VAR9 ;
input VAR7;
input VAR6;
input VAR5 ;
input VAR8 ;
VAR10 VAR1 (
.VAR4(VAR4),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR8(VAR8)
);
endmodule
module MODULE1 (... | apache-2.0 |
AngelTerrones/Antares | Hardware/verilog/antares_multiplier.v | 5,685 | module MODULE1(
input clk, input rst, input [31:0] VAR31, input [31:0] VAR7, input VAR21, input VAR1, input VAR25, input VAR16, output [63:0] VAR32, output VAR12, output VAR17 );
reg [32:0] VAR6;
reg [32:0] VAR29;
reg [31:0] VAR22;
reg [31:0] VAR19;
reg [31:0] VAR14;
reg [31:0] VAR3; reg [31:0] VAR8;
reg [31:0] VAR9; r... | mit |
vad-rulezz/megabot | minsoc/rtl/verilog/or1200/rtl/verilog/or1200_spram_512x20.v | 10,834 | module MODULE1(
VAR1, VAR53, VAR29,
clk, rst, VAR41, VAR32, VAR23, addr, VAR48, VAR22
);
parameter VAR42 = 9;
parameter VAR49 = 20;
input VAR1;
input [VAR25 - 1:0] VAR29;
output VAR53;
input clk; input rst; input VAR41; input VAR32; input VAR23; input [VAR42-1:0] addr; input [VAR49-1:0] VAR48; output [VAR49-1:0] VAR22;... | gpl-2.0 |
Tao-J/nexys3MIPSSoC | Top_Muliti_IOBUS.v | 13,880 | module MODULE1(
VAR67,
VAR135, VAR216,
VAR255,
VAR103,
VAR168,
VAR228,
VAR213,
VAR244,
VAR42,
VAR46,
VAR200,
VAR243,
VAR122,
VAR73,
VAR253,
VAR71,
VAR119, VAR112, VAR221,
VAR69,VAR126
);
parameter VAR205 = 16;
parameter VAR21 = 23;
parameter VAR146 = 4; parameter VAR25 = 4;
input VAR67;
input [4:0] VAR135;
input [7:0] ... | gpl-3.0 |
intelligenttoasters/CPC2.0 | FPGA/rtl/cache_byte.v | 18,013 | module MODULE1 (
input wire VAR28,
input wire VAR26,
output wire VAR58,
input wire VAR21,
input wire VAR18,
input wire VAR6,
output reg VAR3, input wire [23:0] VAR20, input wire [7:0] VAR7,
output reg [7:0] VAR23,
output reg VAR55,
input wire VAR12,
output reg VAR25,
output reg VAR1,
input wire VAR47, output reg [22:0]... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/tapvgnd2/sky130_fd_sc_hs__tapvgnd2_1.v | 1,825 | module MODULE2 (
VAR2,
VAR1
);
input VAR2;
input VAR1;
VAR4 VAR3 (
.VAR2(VAR2),
.VAR1(VAR1)
);
endmodule
module MODULE2 ();
supply1 VAR2;
supply0 VAR1;
VAR4 VAR3 ();
endmodule | apache-2.0 |
htogarcia/Microcontrolador-Calculadora | arm/Microcontroller.v | 2,289 | module MODULE1(
output [31:0] VAR45,
output [31:0] VAR51,
output [31:0] VAR52,
input [31:0] VAR29,
input VAR10,
input VAR46
);
wire [1:0] VAR43, VAR11, VAR50;
wire VAR35, VAR39, VAR6, VAR16, VAR28;
wire [31:0] VAR5;
wire [31:0] VAR38, VAR27, VAR15;
wire [3:0] VAR44;
wire [31:0] VAR32, VAR13, VAR49, VAR17, VAR37;
wire [... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/mux2/gf180mcu_fd_sc_mcu9t5v0__mux2_4.functional.v | 1,043 | module MODULE1( VAR3, VAR12, VAR6, VAR7 );
input VAR7, VAR12, VAR6;
output VAR3;
wire VAR10;
and VAR13( VAR10, VAR7, VAR12 );
wire VAR1;
not VAR2( VAR1, VAR6 );
wire VAR5;
and VAR9( VAR5, VAR1, VAR7 );
wire VAR8;
and VAR4( VAR8, VAR12, VAR6 );
or VAR11( VAR3, VAR10, VAR5, VAR8 );
endmodule | apache-2.0 |
vad-rulezz/megabot | fusesoc/orpsoc-cores/trunk/systems/mor1kx-generic/rtl/verilog/wb_intercon.v | 9,628 | module MODULE1
(input VAR134,
input VAR132,
input [31:0] VAR125,
input [31:0] VAR130,
input [3:0] VAR32,
input VAR56,
input VAR101,
input VAR124,
input [2:0] VAR98,
input [1:0] VAR17,
output [31:0] VAR72,
output VAR141,
output VAR78,
output VAR3,
input [31:0] VAR70,
input [31:0] VAR99,
input [3:0] VAR81,
input VAR24,
i... | gpl-2.0 |
unihd-cag/openhmc | rtl/hmc_controller/rx/rx_lane_logic.v | 5,536 | module MODULE1 #(
parameter VAR5 = 512,
parameter VAR22 = 8,
parameter VAR20 = (VAR5/VAR22),
parameter VAR21 = 1,
parameter VAR9= 1
) (
input wire clk,
input wire VAR23,
input wire [VAR20-1:0] VAR6,
input wire VAR10, input wire VAR17,
input wire VAR12,
output wire [VAR20-1:0] VAR1,
output wire VAR16,
input wire VAR19
)... | lgpl-3.0 |
nliu96/openHMC_Altera | src/tx_crc_combine.v | 15,823 | module MODULE1 #(
parameter VAR8 = 2,
parameter VAR52 = 4,
parameter VAR51 = 512
) (
input wire clk,
input wire VAR28,
input wire [VAR52-1:0] VAR35,
input wire [VAR52-1:0] VAR20,
input wire [VAR51-1:0] VAR46,
output wire [VAR51-1:0] VAR12
);
integer if; integer VAR37; integer VAR50;
genvar VAR10, VAR45;
wire [128-1:0] ... | lgpl-3.0 |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/acme/prj/solution1/syn/verilog/image_filter_AXIvideo2Mat.v | 29,950 | module MODULE1 (
VAR85,
VAR120,
VAR44,
VAR18,
VAR14,
VAR110,
VAR119,
VAR57,
VAR1,
VAR92,
VAR20,
VAR76,
VAR6,
VAR39,
VAR82,
VAR61,
VAR87,
VAR74,
VAR17,
VAR16,
VAR32,
VAR9,
VAR88,
VAR47,
VAR24,
VAR67,
VAR70
);
parameter VAR7 = 1'b1;
parameter VAR4 = 1'b0;
parameter VAR10 = 7'b1;
parameter VAR49 = 7'b10;
parameter VAR60 =... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/efc/rtl/efc_tck.v | 3,097 | module MODULE1 (
VAR3, VAR4,
VAR11, VAR2, VAR5, VAR9,
VAR7
);
output [31:0] VAR3; input [31:0] VAR11; input VAR2; output VAR4; input VAR5; input VAR9; input VAR7;
wire [31:0] VAR6;
wire [31:0] VAR3;
assign VAR6
= VAR9 ? VAR11
: VAR5 ? {VAR3[30:0], VAR2}
: VAR3;
VAR8 #(32) VAR10 (.din(VAR6 ),
.VAR1(VAR3 ), .clk(VAR7));
... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/bufinv/sky130_fd_sc_hs__bufinv.symbol.v | 1,236 | module MODULE1 (
input VAR2,
output VAR3
);
supply1 VAR1;
supply0 VAR4;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/bufbuf/sky130_fd_sc_ls__bufbuf_16.v | 2,036 | module MODULE1 (
VAR7 ,
VAR2 ,
VAR5,
VAR1,
VAR4 ,
VAR6
);
output VAR7 ;
input VAR2 ;
input VAR5;
input VAR1;
input VAR4 ;
input VAR6 ;
VAR8 VAR3 (
.VAR7(VAR7),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR7,
VAR2
);
output VAR7;
input VAR2;
supply1 VAR5;
supply0 VAR1;... | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig37/v6_mig37_bb.v | 13,663 | module MODULE1 #
(
parameter VAR110 = 200,
parameter VAR52 = "VAR34",
parameter VAR106 = 6, parameter VAR113 = 1,
parameter VAR3 = 3,
parameter VAR116 = 2,
parameter VAR71 = 2500,
parameter VAR48 = "VAR90",
parameter VAR53 = "VAR78",
parameter VAR72 = "VAR78",
parameter VAR6 = 1,
parameter VAR35 = 3,
parameter VAR97 = ... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/einvp/sky130_fd_sc_hdll__einvp.symbol.v | 1,337 | module MODULE1 (
input VAR3 ,
output VAR6 ,
input VAR4
);
supply1 VAR2;
supply0 VAR1;
supply1 VAR5 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or4bb/sky130_fd_sc_ms__or4bb.functional.v | 1,414 | module MODULE1 (
VAR9 ,
VAR3 ,
VAR10 ,
VAR6,
VAR2
);
output VAR9 ;
input VAR3 ;
input VAR10 ;
input VAR6;
input VAR2;
wire VAR8;
wire VAR1;
nand VAR7 (VAR8, VAR2, VAR6 );
or VAR4 (VAR1, VAR10, VAR3, VAR8);
buf VAR5 (VAR9 , VAR1 );
endmodule | apache-2.0 |
ultraembedded/riscv | top_tcm_wrapper/dport_axi.v | 10,438 | module MODULE1
(
input VAR48
,input VAR27
,input [ 31:0] VAR20
,input [ 31:0] VAR74
,input VAR11
,input [ 3:0] VAR5
,input VAR68
,input [ 10:0] VAR32
,input VAR52
,input VAR35
,input VAR63
,input VAR36
,input VAR70
,input VAR62
,input [ 1:0] VAR50
,input [ 3:0] VAR9
,input VAR2
,input VAR60
,input [ 31:0] VAR1
,input [... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a21o/sky130_fd_sc_ls__a21o.symbol.v | 1,341 | module MODULE1 (
input VAR6,
input VAR3,
input VAR2,
output VAR1
);
supply1 VAR5;
supply0 VAR4;
supply1 VAR8 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
takeshineshiro/fpga_linear_128 | coordinate_cordic.v | 9,310 | module MODULE1
(
VAR2,
VAR14,
clk,
VAR15,
VAR45,
VAR41,
VAR50
);
input signed [VAR61-1:0]VAR2,VAR14;
input clk;
output signed [VAR44-1:0]VAR15;
output signed [VAR74-1:0]VAR45;
input [9:0] VAR41;
output [9:0] VAR50;
assign VAR50 = {11{VAR41}};
parameter VAR61 = 18, VAR44 = 20, VAR43 = 21, VAR74 =15;
parameter VAR17 = 12... | mit |
Jside/pdp1 | pdp1_skp_decoder.v | 2,696 | module MODULE2(VAR6, VAR18);
input [0:2] VAR6;
output reg [0:5] VAR18;
always @(VAR6) begin
case(VAR6)
3'b000:
VAR18 <= 6'b000000;
3'b001:
VAR18 <= 6'b000001;
3'b010:
VAR18 <= 6'b000010;
3'b011:
VAR18 <= 6'b000100;
3'b100:
VAR18 <= 6'b001000;
3'b101:
VAR18 <= 6'b010000;
3'b110:
VAR18 <= 6'b100000;
3'b111:
VAR18 <= 6'b1... | gpl-3.0 |
Gum-Joe/Sora | FPGA/MIMO/rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/old/Sora_FRL_STATUS_OUT.v | 2,195 | module MODULE1(
input clk,
input rst,
output VAR5,
input VAR4,
input VAR1,
input VAR2,
input VAR3
);
endmodule | bsd-2-clause |
jhol/butterflylogic | rtl/sync.v | 5,263 | module MODULE1 #(
parameter VAR15 = 1,
parameter VAR29 = 1,
parameter VAR26 = 1,
parameter VAR2 = 32
)(
input wire VAR17,
input wire VAR27,
input wire VAR30,
input wire VAR24,
input wire VAR31,
input wire VAR33,
input wire VAR4,
input wire [VAR2-1:0] VAR20,
input wire [VAR2-1:0] VAR25,
output wire [VAR2-1:0] VAR1,
outp... | gpl-2.0 |
grvmind/amber-cycloneiii | trunk/hw/vlog/system/clocks_resets.v | 11,802 | module MODULE1 (
input VAR93,
input VAR25,
input VAR78,
input VAR28,
output VAR99,
output VAR27,
output VAR46
);
wire VAR45;
wire VAR101;
assign VAR99 = VAR101 || !VAR45;
localparam VAR60 = 25;
wire VAR80;
wire VAR20;
reg [VAR60-1:0] VAR6 ;
reg [VAR60-1:0] VAR24 ;
wire VAR50;
wire VAR64;
wire VAR81;
VAR47 # (
.VAR10 ( ... | gpl-2.0 |
hanw/Open-Source-FPGA-Bitcoin-Miner | projects/VC707_experimental/VC707_experimental.srcs/sources_1/ip/hashing_clock_multiplier/hashing_clock_multiplier_clk_wiz.v | 7,009 | module MODULE1
( input VAR19,
input VAR48,
output VAR83,
output VAR20
);
VAR21 VAR38
(.VAR34 (VAR2),
.VAR43 (VAR19),
.VAR74 (VAR48));
wire [15:0] VAR65;
wire VAR56;
wire VAR18;
wire VAR81;
wire VAR85;
wire VAR47;
wire VAR50;
wire VAR9;
wire VAR64;
wire VAR46;
wire VAR33;
wire VAR53;
wire VAR8;
wire VAR84;
wire VAR23;
w... | gpl-3.0 |
nyaxt/dmix | nkmd/cpu/cpu.v | 22,843 | module MODULE7(
input wire clk,
input wire rst,
input wire [31:0] VAR59,
output wire [31:0] VAR129,
input wire VAR30,
input wire [31:0] VAR20,
input wire VAR78,
output wire [31:0] VAR170);
assign VAR129 = VAR206;
assign VAR170 = VAR59;
reg [31:0] VAR206;
always @(posedge clk) begin
if (rst) begin
VAR206 <= 32'h0;
end e... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlygate4sd1/sky130_fd_sc_hd__dlygate4sd1.symbol.v | 1,322 | module MODULE1 (
input VAR1,
output VAR4
);
supply1 VAR3;
supply0 VAR6;
supply1 VAR2 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/icgtp/gf180mcu_fd_sc_mcu7t5v0__icgtp_1.behavioral.v | 2,716 | module MODULE1( VAR5, VAR19, VAR16, VAR11 );
input VAR16, VAR19, VAR5;
output VAR11;
reg VAR9;
VAR7 VAR18(.VAR5(VAR5),.VAR19(VAR19),.VAR16(VAR16),.VAR11(VAR11),.VAR9(VAR9));
VAR7 VAR15(.VAR5(VAR5),.VAR19(VAR19),.VAR16(VAR16),.VAR11(VAR11),.VAR9(VAR9));
not VAR21(VAR2,VAR19);
not VAR3(VAR14,VAR5);
and VAR17(VAR8,VAR14,V... | apache-2.0 |
aj-michael/Digital-Systems | Lab4-Part1-40x7bit-RAM/Lab4Part1TopLevel.v | 2,304 | module MODULE1(VAR24,VAR49,VAR4,VAR20,VAR13,VAR47,VAR33,VAR17,VAR34,VAR19,VAR11);
input [6:0] VAR24;
input VAR49, VAR4, VAR20, VAR13, VAR47, VAR33;
output [7:0] VAR17;
output [5:0] VAR34;
output [3:0] VAR19;
output VAR11;
wire VAR8;
wire VAR16;
wire VAR29;
wire [6:0] VAR2;
wire VAR25;
wire [6:0] VAR28;
wire VAR32;
wire... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/nor3/sky130_fd_sc_hvl__nor3.functional.pp.v | 1,853 | module MODULE1 (
VAR12 ,
VAR9 ,
VAR6 ,
VAR4 ,
VAR7,
VAR3,
VAR10 ,
VAR2
);
output VAR12 ;
input VAR9 ;
input VAR6 ;
input VAR4 ;
input VAR7;
input VAR3;
input VAR10 ;
input VAR2 ;
wire VAR5 ;
wire VAR13;
nor VAR11 (VAR5 , VAR4, VAR9, VAR6 );
VAR1 VAR8 (VAR13, VAR5, VAR7, VAR3);
buf VAR14 (VAR12 , VAR13 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand4/sky130_fd_sc_lp__nand4.pp.symbol.v | 1,303 | module MODULE1 (
input VAR4 ,
input VAR2 ,
input VAR5 ,
input VAR7 ,
output VAR6 ,
input VAR8 ,
input VAR3,
input VAR9,
input VAR1
);
endmodule | apache-2.0 |
Gilberto-Lopez/Arquitectura-Computadoras | Practica5/Memory.v | 1,284 | module MODULE1(
input wire [31:0] VAR2,
input wire clk,
input wire enable,
input wire VAR6,
input wire reset,
input wire [9:0] VAR5,
output reg [31:0] VAR1
);
reg [31:0] VAR4 [1023:0];
integer VAR3;
always @(posedge clk) begin
if (reset) begin
for(VAR3 = 0; VAR3 < 1024; VAR3 = VAR3 + 1) begin
VAR4[VAR3] = 32'h00000000;... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfrtn/sky130_fd_sc_lp__dfrtn.symbol.v | 1,431 | module MODULE1 (
input VAR3 ,
output VAR1 ,
input VAR2,
input VAR5
);
supply1 VAR8;
supply0 VAR6;
supply1 VAR7 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand4/sky130_fd_sc_lp__nand4.functional.pp.v | 1,846 | module MODULE1 (
VAR11 ,
VAR6 ,
VAR12 ,
VAR2 ,
VAR3 ,
VAR8,
VAR1,
VAR4 ,
VAR15
);
output VAR11 ;
input VAR6 ;
input VAR12 ;
input VAR2 ;
input VAR3 ;
input VAR8;
input VAR1;
input VAR4 ;
input VAR15 ;
wire VAR14 ;
wire VAR9;
nand VAR13 (VAR14 , VAR3, VAR2, VAR12, VAR6 );
VAR5 VAR10 (VAR9, VAR14, VAR8, VAR1);
buf VAR7 (... | apache-2.0 |
mammenx/pegasus | wxp/dgn/rtl/common/pkt_ff_async/pkt_ff_wptr.v | 3,989 | module MODULE1 #(VAR6 = 8)
(
clk,
VAR5,
valid,
VAR10,
VAR4,
VAR9.
VAR7
);
input clk;
input VAR5;
input valid;
input VAR10;
input VAR4;
input VAR9;
output [VAR6-1:0] VAR7;
reg [VAR6-1:0] VAR12;
reg VAR13;
reg VAR1;
always@(posedge clk, negedge VAR5)
begin
if(~VAR5)
begin
VAR12 <= 0;
end
else
begin
VAR12 <= (valid & VAR1... | gpl-3.0 |
rbarzic/async_logic | misc_lib/bytewrite_ram_32bits.v | 1,984 | module MODULE1 (clk, VAR7, addr, din, dout);
parameter VAR5 = 1024;
parameter VAR2 = 12;
parameter VAR12 = "VAR8.VAR10";
localparam VAR11 = 8;
localparam VAR1 = 4;
input clk;
input [VAR1-1:0] VAR7;
input [VAR2-1:0] addr;
input [VAR1*VAR11-1:0] din;
output [VAR1*VAR11-1:0] dout;
reg [VAR1*VAR11-1:0] VAR6 [VAR5-1:0];
int... | gpl-2.0 |
ShepardSiegel/ocpi | coregen/dram_k7_mig12/mig_7series_v1_2/user_design/rtl/clocking/iodelay_ctrl.v | 7,754 | module MODULE1 #
(
parameter VAR22 = 100, parameter VAR26 = "VAR8", parameter VAR5 = "VAR4", parameter VAR36 = 1, parameter VAR27 = "VAR32"
)
(
input VAR25,
input VAR12,
input VAR23,
input VAR40,
output VAR7,
output VAR37
);
localparam VAR39 = 15;
wire VAR38;
wire VAR2;
wire VAR17;
reg [VAR39-1:0] VAR10 ;
wire VAR18;
w... | lgpl-3.0 |
lerwys/bpm-sw-old-backup | hdl/ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pipe_rate.v | 46,222 | module MODULE1 #
(
parameter VAR135 = "VAR120", parameter VAR116 = "VAR25", parameter VAR75 = "3.0", parameter VAR74 = "VAR84", parameter VAR68 = "VAR79", parameter VAR95 = "VAR120", parameter VAR92 = "VAR120", parameter VAR123 = "VAR79", parameter VAR99 = 4'd15
)
(
input VAR103,
input VAR119,
input VAR24,
input VAR97,... | lgpl-3.0 |
alexforencich/xfcp | lib/eth/example/ATLYS/fpga/rtl/fpga.v | 4,446 | module MODULE1 (
input wire clk,
input wire VAR1,
input wire VAR23,
input wire VAR85,
input wire VAR77,
input wire VAR51,
input wire VAR53,
input wire [7:0] VAR18,
output wire [7:0] VAR59,
input wire VAR8,
input wire [7:0] VAR10,
input wire VAR15,
input wire VAR79,
output wire VAR39,
input wire VAR17,
output wire [7:0]... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/tapmet1/sky130_fd_sc_ls__tapmet1.functional.pp.v | 1,204 | module MODULE1 (
VAR3,
VAR4,
VAR2 ,
VAR1
);
input VAR3;
input VAR4;
input VAR2 ;
input VAR1 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/aoi21/gf180mcu_fd_sc_mcu9t5v0__aoi21_1.functional.pp.v | 1,386 | module MODULE1( VAR5, VAR7, VAR6, VAR15, VAR10, VAR13 );
input VAR6, VAR5, VAR15;
inout VAR10, VAR13;
output VAR7;
wire VAR8;
not VAR4( VAR8, VAR6 );
wire VAR11;
not VAR1( VAR11, VAR15 );
wire VAR17;
and VAR12( VAR17, VAR8, VAR11 );
wire VAR2;
not VAR16( VAR2, VAR5 );
wire VAR3;
and VAR9( VAR3, VAR2, VAR11 );
or VAR14(... | apache-2.0 |
ShirmanXia/EE469SPRING16 | lab4/nios_system/synthesis/submodules/nios_system_hex_0.v | 2,178 | module MODULE1 (
address,
VAR4,
clk,
VAR2,
VAR6,
VAR5,
VAR9,
VAR8
)
;
output [ 3: 0] VAR9;
output [ 31: 0] VAR8;
input [ 1: 0] address;
input VAR4;
input clk;
input VAR2;
input VAR6;
input [ 31: 0] VAR5;
wire VAR7;
reg [ 3: 0] VAR3;
wire [ 3: 0] VAR9;
wire [ 3: 0] VAR1;
wire [ 31: 0] VAR8;
assign VAR7 = 1;
assign VAR1 ... | gpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad9234/axi_ad9234_channel.v | 5,392 | module MODULE1 (
VAR46,
VAR31,
VAR24,
VAR56,
VAR48,
VAR17,
VAR5,
VAR26,
VAR23,
VAR41,
VAR18,
VAR16,
VAR35,
VAR8,
VAR36,
VAR14,
VAR20,
VAR52,
VAR29);
parameter VAR6 = 0;
parameter VAR19 = 0;
input VAR46;
input VAR31;
input [63:0] VAR24;
input VAR56;
output [63:0] VAR48;
output VAR17;
output VAR5;
output VAR26;
output VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o2bb2a/sky130_fd_sc_hs__o2bb2a.symbol.v | 1,350 | module MODULE1 (
input VAR1,
input VAR6,
input VAR5 ,
input VAR7 ,
output VAR4
);
supply1 VAR2;
supply0 VAR3;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/icgtn/gf180mcu_fd_sc_mcu9t5v0__icgtn_2.behavioral.v | 2,754 | module MODULE1( VAR1, VAR20, VAR4, VAR21 );
input VAR4, VAR20, VAR1;
output VAR21;
reg VAR17;
VAR6 VAR7(.VAR1(VAR1),.VAR20(VAR20),.VAR4(VAR4),.VAR21(VAR21),.VAR17(VAR17));
VAR6 VAR19(.VAR1(VAR1),.VAR20(VAR20),.VAR4(VAR4),.VAR21(VAR21),.VAR17(VAR17));
not VAR24(VAR13,VAR20);
not VAR9(VAR5,VAR1);
and VAR10(VAR14,VAR5,VAR... | apache-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_v6_gtx_x4_250/source/axi_basic_tx_pipeline.v | 22,520 | module MODULE1 #(
parameter VAR8 = 128, parameter VAR42 = "VAR17", parameter VAR51 = 1,
parameter VAR30 = (VAR8 == 128) ? 2 : 1, parameter VAR43 = VAR8 / 8 ) (
input [VAR8-1:0] VAR59, input VAR26, output VAR23, input [VAR43-1:0] VAR34, input VAR31, input [3:0] VAR5,
output [VAR8-1:0] VAR58, output VAR57, output VAR29, ... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkbuf/sky130_fd_sc_ls__clkbuf.functional.pp.v | 1,772 | module MODULE1 (
VAR8 ,
VAR2 ,
VAR4,
VAR1,
VAR5 ,
VAR9
);
output VAR8 ;
input VAR2 ;
input VAR4;
input VAR1;
input VAR5 ;
input VAR9 ;
wire VAR3 ;
wire VAR7;
buf VAR10 (VAR3 , VAR2 );
VAR12 VAR11 (VAR7, VAR3, VAR4, VAR1);
buf VAR6 (VAR8 , VAR7 );
endmodule | apache-2.0 |
ptracton/wb_dsp | rtl/adc_clk_gen.v | 1,043 | module MODULE1 (
VAR3,
VAR1, VAR2, VAR4
) ;
input VAR1;
input VAR2;
input [2:0] VAR4;
output reg VAR3;
reg [15:0] VAR5;
wire [7:0] VAR6 = (1 << VAR4)-1;
always @(posedge VAR1)
if (VAR2) begin
VAR3 <= 0;
VAR5 <= 0;
end else begin
VAR5 <= VAR5+1;
if (VAR5 >= VAR6) begin
VAR3 <= ~VAR3;
VAR5 <= 0;
end
end
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor3/sky130_fd_sc_lp__nor3.behavioral.v | 1,405 | module MODULE1 (
VAR9,
VAR10,
VAR6,
VAR11
);
output VAR9;
input VAR10;
input VAR6;
input VAR11;
supply1 VAR4;
supply0 VAR5;
supply1 VAR1 ;
supply0 VAR2 ;
wire VAR8;
nor VAR3 (VAR8, VAR11, VAR10, VAR6 );
buf VAR7 (VAR9 , VAR8 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o311a/sky130_fd_sc_hs__o311a.pp.blackbox.v | 1,353 | module MODULE1 (
VAR6 ,
VAR7 ,
VAR1 ,
VAR3 ,
VAR5 ,
VAR2 ,
VAR4,
VAR8
);
output VAR6 ;
input VAR7 ;
input VAR1 ;
input VAR3 ;
input VAR5 ;
input VAR2 ;
input VAR4;
input VAR8;
endmodule | apache-2.0 |
zYeoman/32BIT-MIPS-CPU | Single/ALU.v | 3,483 | module MODULE1 (
input [31:0] VAR11, VAR9,
input [5:0] VAR7,
input VAR6,
output reg [31:0] out
);
reg VAR5, VAR4;
wire VAR12;
reg [31:0] VAR10, VAR8, VAR1, VAR2;
reg VAR3;
assign VAR12 = VAR6&VAR3;
always @ (*) begin
case (VAR7[0])
1'b0: begin
VAR10 = VAR11 + VAR9;
VAR5 = (VAR10 == 1'b0)? 1'b1 : 1'b0;
VAR4 = (VAR6&(VAR... | gpl-2.0 |
alexforencich/xfcp | lib/eth/example/S10DX_DK/fpga_10g/rtl/xcvr_ctrl.v | 9,456 | module MODULE1 (
input wire VAR12,
input wire VAR36,
input wire VAR30,
output wire [18:0] VAR14,
output wire VAR40,
output wire VAR7,
input wire [7:0] VAR13,
output wire [7:0] VAR1,
input wire VAR4
);
localparam [3:0]
VAR16 = 4'd0,
VAR18 = 4'd1,
VAR39 = 4'd2,
VAR29 = 4'd3,
VAR11 = 4'd4,
VAR35 = 4'd5,
VAR6 = 4'd6,
VAR8 ... | mit |
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