repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or2b/sky130_fd_sc_hdll__or2b.functional.pp.v | 1,944 | module MODULE1 (
VAR13 ,
VAR6 ,
VAR7 ,
VAR9,
VAR5,
VAR2 ,
VAR11
);
output VAR13 ;
input VAR6 ;
input VAR7 ;
input VAR9;
input VAR5;
input VAR2 ;
input VAR11 ;
wire VAR12 ;
wire VAR14 ;
wire VAR1;
not VAR8 (VAR12 , VAR7 );
or VAR4 (VAR14 , VAR12, VAR6 );
VAR15 VAR3 (VAR1, VAR14, VAR9, VAR5);
buf VAR10 (VAR13 , VAR1 );
e... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a22oi/sky130_fd_sc_lp__a22oi.symbol.v | 1,371 | module MODULE1 (
input VAR9,
input VAR8,
input VAR1,
input VAR4,
output VAR2
);
supply1 VAR6;
supply0 VAR3;
supply1 VAR7 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
fallen/milkymist-mmu | cores/hpdmc_ddr32/rtl/spartan6/hpdmc_oddr4.v | 1,843 | module MODULE1 #(
parameter VAR1 = "VAR12",
parameter VAR9 = 1'b0,
parameter VAR4 = "VAR6"
) (
output [3:0] VAR17,
input VAR12,
input VAR11,
input VAR7,
input [3:0] VAR2,
input [3:0] VAR8,
input VAR14,
input VAR16
);
VAR15 #(
.VAR1(VAR1),
.VAR9(VAR9),
.VAR4(VAR4)
) VAR13 (
.VAR17(VAR17[0]),
.VAR12(VAR12),
.VAR11(VAR11)... | lgpl-3.0 |
alan4186/Hardware-CNN | DE2_115_CAMERA/DE2_115_CAMERA.v | 24,079 | module MODULE1(
VAR91,
VAR88,
VAR314,
VAR86,
VAR209,
VAR4,
VAR311,
VAR114,
VAR57,
VAR283,
VAR2,
VAR300,
VAR122,
VAR242,
VAR272,
VAR93,
VAR59,
VAR240,
VAR203,
VAR15,
VAR7,
VAR43,
VAR30,
VAR182,
VAR171,
VAR183,
VAR263,
VAR212,
VAR181,
VAR50,
VAR217,
VAR68,
VAR265,
VAR107,
VAR132,
VAR36,
VAR140,
VAR303,
VAR258,
VAR207,
VA... | mit |
olgirard/openmsp430 | fpga/altera_de0_nano_soc/rtl/verilog/mega/ram_16x512_dp.v | 11,714 | module MODULE1 (
VAR41,
VAR8,
VAR45,
VAR59,
VAR47,
VAR35,
VAR53,
VAR3,
VAR15,
VAR34,
VAR49,
VAR4,
VAR58,
VAR22);
input [8:0] VAR41;
input [8:0] VAR8;
input [1:0] VAR45;
input [1:0] VAR59;
input VAR47;
input VAR35;
input [15:0] VAR53;
input [15:0] VAR3;
input VAR15;
input VAR34;
input VAR49;
input VAR4;
output [15:0] VA... | bsd-3-clause |
alexforencich/verilog-wishbone | rtl/wb_reg.v | 4,976 | module MODULE1 #
(
parameter VAR22 = 32, parameter VAR16 = 32, parameter VAR14 = (VAR22/8) )
(
input wire clk,
input wire rst,
input wire [VAR16-1:0] VAR15, input wire [VAR22-1:0] VAR11, output wire [VAR22-1:0] VAR23, input wire VAR1, input wire [VAR14-1:0] VAR9, input wire VAR24, output wire VAR10, output wire VAR12, ... | mit |
ShepardSiegel/ocpi | coregen/dram_v6_mig39_2/mig_39_2/user_design/rtl/ecc/ecc_merge_enc.v | 5,628 | module MODULE1
parameter VAR15 = 100,
parameter VAR16 = 64,
parameter VAR25 = 72,
parameter VAR27 = 4,
parameter VAR18 = 1,
parameter VAR13 = 64,
parameter VAR23 = 72,
parameter VAR14 = 8
)
(
VAR5, VAR6,
clk, rst, VAR21, VAR26, VAR4, VAR20, VAR3
);
input clk;
input rst;
input [4*VAR16-1:0] VAR21;
input [4*VAR13/8-1:0] ... | lgpl-3.0 |
chris-wood/yield | sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/axi_data_fifo_v2_1/hdl/verilog/axi_data_fifo_v2_1_axic_fifo.v | 4,625 | module MODULE1 #
(
parameter VAR14 = "VAR10",
parameter integer VAR18 = 5, parameter integer VAR6 = 64, parameter VAR15 = "lut" )
(
input wire VAR19, input wire VAR22, input wire [VAR6-1:0] VAR7, input wire VAR4, output wire VAR8, output wire [VAR6-1:0] VAR23, output wire VAR11, input wire VAR3 );
VAR20 #(
.VAR14(VAR14... | mit |
ShirmanXia/EE469SPRING16 | lab4/nios_system/synthesis/submodules/nios_system_jtag_uart_0.v | 17,138 | module MODULE2 (
clk,
VAR56,
VAR23,
VAR13,
VAR6,
VAR49,
VAR2
)
;
output VAR13;
output [ 7: 0] VAR6;
output VAR49;
output [ 5: 0] VAR2;
input clk;
input [ 7: 0] VAR56;
input VAR23;
wire VAR13;
wire [ 7: 0] VAR6;
wire VAR49;
wire [ 5: 0] VAR2;
always @(posedge clk)
begin
if (VAR23)
("%VAR26", VAR56);
end
assign VAR2 = {6... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dfstp/sky130_fd_sc_hvl__dfstp.functional.v | 1,633 | module MODULE1 (
VAR8 ,
VAR5 ,
VAR11 ,
VAR3
);
output VAR8 ;
input VAR5 ;
input VAR11 ;
input VAR3;
wire VAR1;
wire VAR9 ;
not VAR4 (VAR9 , VAR3 );
VAR6 VAR7 VAR2 (VAR1 , VAR11, VAR5, VAR9 );
buf VAR10 (VAR8 , VAR1 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdlclkp/sky130_fd_sc_ls__sdlclkp.functional.v | 1,772 | module MODULE1 (
VAR2,
VAR3 ,
VAR1,
VAR12
);
output VAR2;
input VAR3 ;
input VAR1;
input VAR12 ;
wire VAR7 ;
wire VAR9 ;
wire VAR11 ;
wire VAR13;
not VAR14 (VAR9 , VAR7 );
not VAR6 (VAR11 , VAR12 );
nor VAR8 (VAR13, VAR1, VAR3 );
VAR5 VAR4 (VAR7 , VAR13, VAR11 );
and VAR10 (VAR2 , VAR9, VAR12 );
endmodule | apache-2.0 |
efabless/openlane | designs/151/src/FetchDecodeStage.v | 2,175 | module MODULE1 #(
parameter VAR9 = VAR17
)(
input wire clk,
input wire reset,
output wire [VAR9-1:0] VAR7,
output wire [VAR9-1:0] VAR1,
input wire [VAR9-1:0] VAR3,
input wire [VAR9-1:0] VAR4,
input wire [1:0] VAR20,
input wire [VAR10-1:0] VAR11,
output wire [4:0] VAR6,
output wire [4:0] VAR16,
output wire [4:0] VAR5,
o... | apache-2.0 |
johan92/altera_opencl_sandbox | vector_add/bin_vector_add/iface/ip/SGDMA_dispatcher/write_signal_breakout.v | 5,305 | module MODULE1 (
VAR11, VAR10,
VAR9,
VAR14,
VAR15,
VAR13,
VAR6,
VAR3,
VAR1,
VAR7, VAR2, VAR4,
VAR8,
VAR5
);
parameter VAR12 = 256;
input [VAR12-1:0] VAR11;
output wire [255:0] VAR10;
output wire [63:0] VAR9;
output wire [31:0] VAR14;
output wire VAR15;
output wire VAR13;
output wire VAR6;
output wire VAR3;
output wire ... | mit |
m-labs/milkymist | cores/norflash16/rtl/norflash16.v | 3,748 | module MODULE1 #(
parameter VAR18 = 22,
parameter VAR20 = 4'd12,
parameter VAR29 = 4'd6
) (
input VAR40,
input VAR37,
input [31:0] VAR36,
output reg [31:0] VAR6,
input [31:0] VAR25,
input [3:0] VAR4,
input VAR26,
input VAR13,
output reg VAR38,
input VAR16,
output [VAR18-1:0] VAR7,
inout [15:0] VAR5,
output reg VAR21,
o... | lgpl-3.0 |
briburrell/amica | device/scrypt_mono_pll/scrypt_mono_pll.srcs/sources_1/imports/scrypt_mono_pll/pbkdfengine.v | 20,412 | module MODULE1
(VAR21, VAR41, VAR63, VAR31, VAR87, VAR27, VAR77, VAR30, VAR88, VAR60, VAR42,
VAR12, VAR6, VAR108, VAR33, VAR20, VAR61, VAR14, VAR40);
input VAR21; input VAR41;
input [255:0] VAR63;
input [255:0] VAR31;
input [127:0] VAR87;
input [31:0] VAR27;
input [3:0] VAR77;
output reg [31:0] VAR30;
output reg [31:0]... | gpl-3.0 |
rkrajnc/minimig-mist | rtl/mist/user_io.v | 3,122 | module MODULE1(
input VAR24,
input VAR17,
output reg VAR6,
input VAR14,
input [7:0] VAR13,
output [7:0] VAR20,
output [7:0] VAR8,
output [2:0] VAR7,
output VAR15,
output VAR5,
output [1:0] VAR25,
output [7:0] VAR9,
output [1:0] VAR12,
output [1:0] VAR23,
output [3:0] VAR10
);
reg [6:0] VAR1;
reg [7:0] VAR16;
reg [5:0] ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor3/sky130_fd_sc_hs__nor3.pp.blackbox.v | 1,268 | module MODULE1 (
VAR4 ,
VAR2 ,
VAR6 ,
VAR5 ,
VAR1,
VAR3
);
output VAR4 ;
input VAR2 ;
input VAR6 ;
input VAR5 ;
input VAR1;
input VAR3;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_1.v | 2,477 | module MODULE2 (
VAR11 ,
VAR3,
VAR8,
VAR5 ,
VAR1 ,
VAR7,
VAR6,
VAR9 ,
VAR4
);
output VAR11 ;
input VAR3;
input VAR8;
input VAR5 ;
input VAR1 ;
input VAR7;
input VAR6;
input VAR9 ;
input VAR4 ;
VAR10 VAR2 (
.VAR11(VAR11),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR4(VA... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_2.functional.pp.v | 1,072 | module MODULE1( VAR1, VAR8, VAR5, VAR9, VAR2 );
input VAR1, VAR8;
inout VAR9, VAR2;
output VAR5;
wire VAR4;
not VAR7( VAR4, VAR1 );
wire VAR10;
not VAR6( VAR10, VAR8 );
or VAR3( VAR5, VAR4, VAR10 );
endmodule | apache-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/db/db_sao_cal_diff.v | 5,680 | module MODULE1(
VAR7 ,
VAR5 ,
VAR8 ,
VAR2 ,
VAR4
);
input [ 7:0 ] VAR7 ;
input [ 7:0 ] VAR5 ;
input VAR8 ;
output [287:0 ] VAR2 ;
output [ 31:0 ] VAR4 ;
wire signed [ 8:0 ] VAR1 ;
reg [287:0 ] VAR3 ;
reg [ 31:0] VAR6 ;
assign VAR1 = VAR5 - VAR7 ;
always @* begin
case(VAR7[7:3])
5'd0 : begin VAR3 = {279'b0,VAR1 }; VAR6 ... | gpl-3.0 |
MarcoVogt/basil | firmware/modules/timestamp/timestamp_core.v | 5,179 | module MODULE1
parameter VAR2 = 16,
parameter VAR9 = 4'b0001
)(
input wire VAR50,
input wire VAR73,
input wire VAR52,
input wire [63:0] VAR56,
output wire [63:0] VAR64,
input wire VAR32,
output wire VAR26,
output wire [31:0] VAR4,
input wire VAR60,
input wire [VAR2-1:0] VAR19,
input wire [7:0] VAR57,
output reg [7:0] V... | bsd-3-clause |
trivoldus28/pulsarch-verilog | design/sys/iop/srams/rtl/bw_r_icd.v | 34,208 | module MODULE1(VAR9, VAR111, VAR121,
VAR33, VAR23, VAR30, VAR45, VAR104, VAR39, VAR74, VAR18,
VAR88, VAR115, VAR68,
VAR60, VAR133, VAR122,
VAR14, VAR37, VAR118, VAR79,
VAR41, VAR69, VAR105,
VAR66, VAR36, VAR38,
VAR1);
input VAR30;
input VAR45;
input VAR104;
input VAR39;
input VAR74;
input [11:2] VAR18;
input [11:2] VAR... | gpl-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src_previous/tmp/spree/tmp/spree.v | 58,300 | module MODULE1 (
clk,
VAR415,
VAR15,
VAR164,
VAR174,
VAR7,
VAR435,
VAR240,
VAR252
);
parameter VAR273 = 6'b000000;
parameter VAR173 = 6'b000001;
parameter VAR462 = 6'b000010;
parameter VAR370 = 6'b000011;
parameter VAR190 = 6'b000100;
parameter VAR332 = 6'b000101;
parameter VAR289 = 6'b000110;
parameter VAR44 = 6'b0001... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o211ai/sky130_fd_sc_lp__o211ai.behavioral.v | 1,564 | module MODULE1 (
VAR11 ,
VAR6,
VAR10,
VAR1,
VAR14
);
output VAR11 ;
input VAR6;
input VAR10;
input VAR1;
input VAR14;
supply1 VAR9;
supply0 VAR4;
supply1 VAR5 ;
supply0 VAR12 ;
wire VAR3 ;
wire VAR8;
or VAR2 (VAR3 , VAR10, VAR6 );
nand VAR13 (VAR8, VAR14, VAR3, VAR1);
buf VAR7 (VAR11 , VAR8 );
endmodule | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_dataflow/bsg_fifo_tracker.v | 2,636 | module MODULE1 #(parameter VAR7(VAR28 )
, VAR26 = VAR11(VAR28)
)
(input VAR8
, input VAR29
, input VAR20
, input VAR3
, output [VAR26-1:0] VAR17
, output [VAR26-1:0] VAR4
, output [VAR26-1:0] VAR14
, output VAR6
, output VAR21
);
logic [VAR26-1:0] VAR22, VAR25, VAR18;
assign VAR17 = VAR18;
assign VAR4 = VAR22;
assign V... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o21a/sky130_fd_sc_ls__o21a.behavioral.pp.v | 1,998 | module MODULE1 (
VAR1 ,
VAR15 ,
VAR16 ,
VAR11 ,
VAR9,
VAR12,
VAR5 ,
VAR10
);
output VAR1 ;
input VAR15 ;
input VAR16 ;
input VAR11 ;
input VAR9;
input VAR12;
input VAR5 ;
input VAR10 ;
wire VAR6 ;
wire VAR8 ;
wire VAR2;
or VAR4 (VAR6 , VAR16, VAR15 );
and VAR14 (VAR8 , VAR6, VAR11 );
VAR7 VAR3 (VAR2, VAR8, VAR9, VAR12)... | apache-2.0 |
hydai/Verilog-Practice | HardwareLab/Lab8/MoleDecoder.v | 1,034 | module MODULE1(VAR2, VAR1);
input [4:0]VAR1;
output [15:0]VAR2;
reg [15:0]VAR2;
always @( * )begin
case(VAR1)
5'd0: VAR2 = 16'b0000000000000001;
5'd1: VAR2 = 16'b0000000000000010;
5'd2: VAR2 = 16'b0000000000000100;
5'd3: VAR2 = 16'b0000000000001000;
5'd4: VAR2 = 16'b0000000000010000;
5'd5: VAR2 = 16'b0000000000100000;
... | mit |
impedimentToProgress/ProbableCause | ddr2/cores/or1200/or1200_sprs.v | 19,228 | module MODULE1(
clk, rst,
VAR62, VAR49, flag, VAR75, VAR61, VAR69,
VAR29, VAR52, VAR78,
VAR27, VAR22, VAR26, VAR10, VAR105,
VAR97,
VAR102, VAR20, VAR2, VAR39,
VAR110, VAR46, VAR17, VAR11, VAR104, VAR48, VAR8, VAR95,
VAR24, VAR88, VAR103, VAR83,
VAR60,
VAR28,
VAR72, VAR33, VAR106,
VAR53, VAR99, VAR38,
VAR80, VAR35, VAR3... | mit |
MartinMosbeck/NoCMonitor | buildCONNECT4x4/module_outport_encoder.v | 2,656 | module MODULE1(VAR1,
VAR2);
input [4 : 0] VAR1;
output [3 : 0] VAR2;
wire [3 : 0] VAR2;
assign VAR2 =
{ VAR1[0] || VAR1[1] ||
VAR1[2] ||
VAR1[3] ||
VAR1[4],
VAR1[0] ?
3'd0 :
(VAR1[1] ?
3'd1 :
(VAR1[2] ?
3'd2 :
(VAR1[3] ? 3'd3 : 3'd4))) } ;
endmodule | gpl-2.0 |
rellermeyer/99tsp | verilog/sa/src/xorshift.v | 1,211 | module MODULE1(
input clk,
input rst,
input [127:0] VAR1,
output [31:0] out
);
reg [31:0] VAR5, VAR2, VAR7, VAR3, VAR8, VAR4, VAR6, VAR9;
assign out = VAR3;
always @(*) begin
VAR8 = VAR2;
VAR4 = VAR7;
VAR6 = VAR3;
VAR9 = VAR3 ^ (VAR3 >> 19) ^ (VAR5 ^ (VAR5 << 11)) ^ ((VAR5 ^ (VAR5 << 11)) >> 8);
end
always @(posedge cl... | bsd-3-clause |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/Approximate_Adders/integracion_fisica/front_end/db/ACA_I_N8_Q5_syn.v | 2,429 | module MODULE1 ( VAR81, VAR84, VAR82 );
input [7:0] VAR81;
input [7:0] VAR84;
output [8:0] VAR82;
wire VAR74, VAR23, VAR1, VAR78, VAR77, VAR71, VAR69,
VAR50, VAR13, VAR52, VAR45, VAR64, VAR29, VAR30, VAR7, VAR51, VAR70, VAR80, VAR36, VAR31, VAR9;
VAR28 VAR39 ( .VAR14(VAR84[1]), .VAR35(VAR81[1]), .VAR6(VAR74), .VAR46(
V... | gpl-3.0 |
tomhartley/EIEProj | dot_product/dot_product/dot_product.v7/cycle.v | 4,272 | module MODULE2 (
clk, en, VAR1, VAR4, VAR27, VAR22
);
input clk;
input en;
input VAR1;
input [7:0] VAR4;
input [7:0] VAR27;
output [7:0] VAR22;
reg [7:0] VAR22;
always @(*)
begin : VAR28
reg VAR20;
reg [7:0] VAR26;
reg [2:0] VAR3;
reg VAR16;
begin : VAR33
forever begin : VAR6
begin : VAR12
forever begin : VAR2
@(posedg... | mit |
eda-globetrotter/MarcheProcessor | processor/regfileww.v | 4,750 | module MODULE1(VAR3,VAR1,VAR8,VAR15,VAR13,VAR5,
VAR11,VAR12,VAR9,VAR4,clk);
output [127:0] VAR3,VAR1;
input [0:127] VAR8;
input clk;
input VAR9;
input VAR11, VAR12;
input [4:0] VAR5, VAR15, VAR13;
input [15:0] VAR4;
reg [127:0] VAR3,VAR1;
reg [127:0] VAR7 [31:0];
reg [127:0] VAR16; reg [127:0] VAR14; reg [7:0] VAR6;
al... | mit |
hanw/sonic-lite | hw/verilog/sonic_pma_v1_05.v | 7,350 | module MODULE1 (
input wire VAR44, input wire VAR27, input wire [8:0] VAR39, input wire VAR13, output wire [31:0] VAR34, output wire VAR67, input wire VAR54, input wire [31:0] VAR52, output wire [3:0] VAR53, output wire [3:0] VAR22, input wire [0:0] VAR25, output wire [3:0] VAR5, output wire [3:0] VAR7, input wire [3:0... | mit |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/or1200/or1200_immu_tlb.v | 10,887 | module MODULE1(
clk, rst,
VAR37, VAR32, VAR43, VAR14, VAR1, VAR25, VAR9,
VAR15, VAR22, VAR41,
VAR35, VAR36, VAR29, VAR44, VAR39
);
parameter VAR8 = VAR40;
parameter VAR13 = VAR40;
input clk;
input rst;
input VAR37;
input [VAR13-1:0] VAR32;
output VAR43;
output [31:VAR46] VAR14;
output VAR1;
output VAR25;
output VAR9;
i... | gpl-2.0 |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/or1200/or1200_reg2mem.v | 5,288 | module MODULE1(addr, VAR11, VAR13, VAR3);
parameter VAR4 = VAR1;
input [1:0] addr;
input [VAR2-1:0] VAR11;
input [VAR4-1:0] VAR13;
output [VAR4-1:0] VAR3;
reg [7:0] VAR10;
reg [7:0] VAR8;
reg [7:0] VAR7;
reg [7:0] VAR9;
assign VAR3 = {VAR10, VAR8, VAR7, VAR9};
always @(VAR11 or addr or VAR13) begin
casex({VAR11, addr[1... | gpl-3.0 |
joaocarlos/udlx-verilog | rtl/top/dlx_processor.v | 20,509 | module MODULE1
parameter VAR4 = 32,
parameter VAR83 = 20,
parameter VAR203 = 32
)
(
input clk,
input VAR107,
input enable,
output VAR189,
output [VAR83-1:0] VAR184,
input [VAR4-1:0] VAR90,
output VAR140,
output VAR57,
output [VAR203-1:0] VAR191,
input [VAR4-1:0] VAR85,
output [VAR4-1:0] VAR146,
input VAR72
);
localpara... | lgpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/ccx/rtl/cpx_fpbuf_p1.v | 13,011 | module MODULE1(
VAR3, VAR13,
VAR74, VAR46,
VAR31, VAR35,
VAR16, VAR41,
VAR47, VAR75,
VAR21, VAR70,
VAR73, VAR66,
VAR1, VAR57,
VAR64, VAR48,
VAR58, VAR67,
VAR4, VAR25,
VAR22, VAR79,
VAR81, VAR38,
VAR56, VAR26,
VAR2, VAR14,
VAR15, VAR71,
VAR55, VAR72,
VAR62, VAR33,
VAR45, VAR52,
VAR29, VAR9,
VAR27,
VAR59, VAR24,
VAR76, V... | gpl-2.0 |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | Dilation/ip/Dilation/acl_stall_monitor.v | 1,770 | module MODULE1 #(VAR6=32) (
input VAR5,
input VAR8,
input [VAR6-1:0] valid,
input [VAR6-1:0] VAR3,
input [VAR6-1:0] VAR7,
output [32*VAR6-1:0] VAR1
);
reg [31:0] VAR9[VAR6-1:0];
generate
genvar VAR2;
for (VAR2=0; VAR2<VAR6; VAR2=VAR2+1)
begin : VAR4
always @(posedge VAR5 or negedge VAR8)
begin
if (~(VAR8))
begin
VAR9[V... | mit |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_k7_x4_125/example_design/PIO_RX_ENGINE.v | 43,237 | module MODULE1 #(
parameter VAR35 = 1,
parameter VAR22 = 64,
parameter VAR54 = VAR22 / 8 ) (
input clk,
input VAR23,
input [VAR22-1:0] VAR31,
input [VAR54-1:0] VAR27,
input VAR6,
input VAR29,
output reg VAR24,
input [21:0] VAR1,
output reg VAR13,
output reg VAR19,
input VAR9,
output reg [2:0] VAR39, output reg VAR25, o... | lgpl-3.0 |
kernelpanics/Grad | CORDIC-Natural-Logarithm/Verilog/Natural-Logarithm/FSM_C_CORDIC.v | 7,344 | module MODULE1(
input wire VAR49, input wire VAR16, input wire VAR5, input wire VAR4, input wire VAR13, input wire VAR44, input wire [4:0] VAR41,
output reg VAR45, output reg VAR9, output reg VAR22, output reg VAR34, output reg VAR46, output reg VAR17, output reg VAR43, output reg VAR37, output reg VAR25, output reg VA... | gpl-3.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_NVMeHostController_0_0/src/pcie_7x_0_core_top/source/pcie_7x_0_core_top_qpll_drp.v | 20,806 | module MODULE1 #
(
parameter VAR22 = "VAR26", parameter VAR7 = "3.0", parameter VAR69 = "VAR28", parameter VAR55 = 0, parameter VAR80 = 2'd3, parameter VAR81 = 3'd6
)
(
input VAR37,
input VAR64,
input VAR9,
input VAR79,
input VAR65,
input VAR42,
input [15:0] VAR14,
input VAR34,
output [ 7:0] VAR12,
output VAR71,
output... | gpl-3.0 |
chrisfrederickson/verilog-stopwatch | stopwatch.v | 1,189 | module MODULE1(VAR24, VAR31, VAR22, VAR3, VAR1, VAR16, VAR18, VAR11, VAR5, VAR9);
input VAR24;
input [1:0] VAR31;
output [0:6] VAR22, VAR3, VAR1, VAR16, VAR18, VAR11, VAR5, VAR9;
wire VAR2;
wire VAR21, VAR27, VAR19;
wire [3:0] VAR12, VAR26, VAR14, VAR28;
VAR29 VAR8(VAR24, clk);
VAR10 VAR15(clk, VAR31[0], VAR2);
VAR32 V... | mit |
donnaware/ZBC---The-Zero-Board-Computer | rtl/ver1/rtl/csrbrg.v | 1,786 | module MODULE1(
input VAR15,
input VAR14,
input [ 3:1] VAR12, input [15:0] VAR17,
output reg [15:0] VAR11,
input VAR10,
input VAR8,
input VAR3,
output reg VAR5,
output reg [ 2:0] VAR2, output reg VAR1,
output reg [15:0] VAR6,
input [15:0] VAR13
);
always @(posedge VAR15) begin
VAR11 <= VAR13;
end
reg VAR16;
always @(po... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfbbp/sky130_fd_sc_hs__sdfbbp.symbol.v | 1,536 | module MODULE1 (
input VAR2 ,
output VAR8 ,
output VAR4 ,
input VAR3,
input VAR10 ,
input VAR9 ,
input VAR1 ,
input VAR7
);
supply1 VAR6;
supply0 VAR5;
endmodule | apache-2.0 |
nyaxt/dmix | csr.v | 2,649 | module MODULE1#(
parameter VAR2 = 8,
parameter VAR11 = 3,
parameter VAR24 = 5,
parameter VAR4 = VAR2*32,
parameter VAR12 = 16*8,
parameter VAR19 = VAR11*VAR24,
parameter VAR26 = VAR11*192,
parameter VAR17 = VAR26
)(
input wire clk,
input wire rst,
input wire [11:0] VAR16,
input wire VAR15,
input wire [7:0] VAR22,
outpu... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a221oi/sky130_fd_sc_hd__a221oi.pp.blackbox.v | 1,436 | module MODULE1 (
VAR7 ,
VAR2 ,
VAR1 ,
VAR10 ,
VAR5 ,
VAR6 ,
VAR8,
VAR9,
VAR4 ,
VAR3
);
output VAR7 ;
input VAR2 ;
input VAR1 ;
input VAR10 ;
input VAR5 ;
input VAR6 ;
input VAR8;
input VAR9;
input VAR4 ;
input VAR3 ;
endmodule | apache-2.0 |
plyr0/snake-alteraDE2 | snake.v | 6,668 | module MODULE2 (input [0:0] VAR57, input [1:0] VAR28, input [0:0] VAR29,
output reg [3:0] VAR15, VAR54, VAR47, output reg VAR52, VAR41, output [6:0] VAR26, VAR58, VAR14, VAR42
);
parameter VAR33 = 16;
parameter VAR23 = 96;
parameter VAR31 = 48;
parameter VAR43= 640;
parameter VAR50 = VAR33 + VAR23 + VAR31 + VAR43;
para... | gpl-3.0 |
ShepardSiegel/ocpi | libsrc/hdl/ocpi/fpgaTop_alder.v | 1,094 | module MODULE1(
input wire VAR15, input wire VAR9, input wire VAR20, input wire VAR17, input wire VAR2, output wire [7:0] VAR18, output wire [7:0] VAR3,
input wire [7:0] VAR16,
input wire [7:0] VAR5,
output wire [2:0] VAR4, input wire VAR19, output wire VAR12 );
VAR7 VAR1(
.VAR15 (VAR15),
.VAR9 (VAR9),
.VAR20 (VAR20),
... | lgpl-3.0 |
mrehkopf/sd2snes | verilog/sd2snes_sgb/sgb.v | 24,641 | module MODULE1(
input VAR150,
output VAR104,
input VAR50,
input VAR44,
input VAR121,
input VAR10,
input [23:0] VAR27,
input [7:0] VAR2,
output [7:0] VAR101,
input VAR152,
output VAR107,
output VAR78,
output VAR14,
output [23:0] VAR65,
input [7:0] VAR39,
output [7:0] VAR103,
output VAR60,
output [19:0] VAR16,
output VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o2111a/sky130_fd_sc_hs__o2111a.blackbox.v | 1,358 | module MODULE1 (
VAR4 ,
VAR6,
VAR3,
VAR7,
VAR8,
VAR1
);
output VAR4 ;
input VAR6;
input VAR3;
input VAR7;
input VAR8;
input VAR1;
supply1 VAR5;
supply0 VAR2;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a221o/sky130_fd_sc_ms__a221o_4.v | 2,444 | module MODULE1 (
VAR5 ,
VAR8 ,
VAR12 ,
VAR2 ,
VAR10 ,
VAR3 ,
VAR1,
VAR11,
VAR6 ,
VAR7
);
output VAR5 ;
input VAR8 ;
input VAR12 ;
input VAR2 ;
input VAR10 ;
input VAR3 ;
input VAR1;
input VAR11;
input VAR6 ;
input VAR7 ;
VAR9 VAR4 (
.VAR5(VAR5),
.VAR8(VAR8),
.VAR12(VAR12),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR1... | apache-2.0 |
olajep/oh | src/adi/hdl/library/axi_dmac/src_fifo_inf.v | 3,459 | module MODULE1 #(
parameter VAR1 = 3,
parameter VAR28 = 64,
parameter VAR21 = 4)(
input clk,
input VAR31,
input enable,
output VAR5,
input [VAR1-1:0] VAR24,
output [VAR1-1:0] VAR12,
input VAR16,
output VAR17,
input VAR2,
output [VAR21-1:0] VAR18,
input en,
input [VAR28-1:0] din,
output reg VAR11,
input sync,
output VAR... | mit |
osrf/wandrr | firmware/motor_controller/fpga/prom.v | 8,430 | module MODULE1
(input VAR16,
input [ 6:0] addr,
output reg [31:0] VAR11);
VAR3 VAR11 = 32'h0;
always @(posedge VAR16) begin
case (addr)
7'h00: VAR11 = { VAR1, 8'h00, 8'h00, 8'h00 };
7'h01: VAR11 = { VAR9 , 8'h00, 8'VAR6, 8'h00 };
7'h02: VAR11 = { VAR9 , 8'h01, 8'VAR6, 8'h01 };
7'h03: VAR11 = { VAR9 , 8'h02, 8'VAR6, 8'h... | apache-2.0 |
somethingnew2-0/CS552-CPU | RoadRunner/provided_modules/unified_mem.v | 3,750 | module MODULE1(clk,VAR5,addr,VAR4,VAR2,VAR14,VAR8,VAR6);
input clk,VAR5;
input VAR4,VAR2;
input [13:0] addr; input [63:0] VAR14;
output reg [63:0] VAR8;
output reg VAR6;
reg [15:0]VAR10[0:65535];
localparam VAR3 = 2'b00;
localparam VAR7 = 2'b01;
localparam VAR16 = 2'b10;
reg [13:0] VAR11; reg [1:0] state,VAR15; reg [1:... | mit |
r2apu/Labo_Digitales | L2/miniALU_L2/Collaterals.v | 4,127 | module MODULE2 # (parameter VAR20=16)
(
input wire VAR19, VAR37,
input wire [VAR20-1:0] VAR13,
input wire VAR8,
output reg [VAR20-1:0] VAR12
);
always @(posedge VAR19 )
begin
if (VAR37)
VAR12 = VAR13;
end
else
begin
if (VAR8)
VAR12 = VAR12 + 1;
end
end
endmodule
module MODULE3 (VAR17,VAR28,VAR11,VAR16, sel, out);
input... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/and3/sky130_fd_sc_hvl__and3_1.v | 2,172 | module MODULE2 (
VAR7 ,
VAR10 ,
VAR9 ,
VAR5 ,
VAR4,
VAR3,
VAR2 ,
VAR8
);
output VAR7 ;
input VAR10 ;
input VAR9 ;
input VAR5 ;
input VAR4;
input VAR3;
input VAR2 ;
input VAR8 ;
VAR1 VAR6 (
.VAR7(VAR7),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR8(VAR8)
);
endmodule
module MODULE... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand2/sky130_fd_sc_lp__nand2_lp2.v | 2,124 | module MODULE2 (
VAR8 ,
VAR3 ,
VAR9 ,
VAR5,
VAR4,
VAR6 ,
VAR2
);
output VAR8 ;
input VAR3 ;
input VAR9 ;
input VAR5;
input VAR4;
input VAR6 ;
input VAR2 ;
VAR1 VAR7 (
.VAR8(VAR8),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR8,
VAR3,
VAR9
);
output VAR8;
... | apache-2.0 |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_light/spw_light/synthesis/submodules/spw_light_ctrl_out.v | 1,868 | module MODULE1 (
address,
clk,
VAR2,
VAR5,
VAR1
)
;
output [ 31: 0] VAR1;
input [ 1: 0] address;
input clk;
input [ 1: 0] VAR2;
input VAR5;
wire VAR4;
wire [ 1: 0] VAR3;
wire [ 1: 0] VAR6;
reg [ 31: 0] VAR1;
assign VAR4 = 1;
assign VAR6 = {2 {(address == 0)}} & VAR3;
always @(posedge clk or negedge VAR5)
begin
if (VAR5... | gpl-3.0 |
alexforencich/hdg2000 | fpga/lib/axis/rtl/axis_mux_4.v | 10,142 | module MODULE1 #
(
parameter VAR50 = 8
)
(
input wire clk,
input wire rst,
input wire [VAR50-1:0] VAR21,
input wire VAR27,
output wire VAR53,
input wire VAR20,
input wire VAR52,
input wire [VAR50-1:0] VAR51,
input wire VAR29,
output wire VAR4,
input wire VAR45,
input wire VAR34,
input wire [VAR50-1:0] VAR28,
input wire... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_lsbuf_lh_hl_isowell_tap/sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap.behavioral.v | 1,540 | module MODULE1 (
VAR5,
VAR2
);
output VAR5;
input VAR2;
supply1 VAR3;
supply0 VAR4;
supply1 VAR1 ;
buf VAR6 (VAR5 , VAR2 );
endmodule | apache-2.0 |
CospanDesign/nysa-artemis-pcie-platform | artemis_pcie/host_interface/artemis_pcie_host_interface.v | 20,445 | module MODULE1 (
input clk,
input rst,
input VAR71,
input VAR27,
input VAR101,
input VAR187,
input VAR35,
output VAR155,
output VAR48,
input [31:0] VAR47,
input [31:0] VAR74,
input VAR139,
input VAR89,
input VAR121,
output VAR83,
output [31:0] VAR62,
output VAR193,
input VAR36,
output VAR168,
input [23:0] VAR21,
output... | mit |
VerticalResearchGroup/miaow | src/verilog/rtl/issue/issue_flow_control.v | 2,415 | module MODULE1
(
VAR9,
clk, rst, VAR16, VAR8,
VAR10, VAR1,
VAR17, VAR29, VAR11, VAR24,
VAR6, VAR4, VAR3
);
input clk,rst;
input VAR16;
input [VAR28-1:0] VAR8;
input [VAR28-1:0] VAR10;
input [VAR13-1:0] VAR1, VAR17,
VAR29;
input VAR11, VAR24,
VAR6,
VAR4, VAR3;
wire [VAR28-1:0] VAR25;
wire [VAR28-1:0] VAR15;
wire [VAR28-... | bsd-3-clause |
kwantam/multiexp-a5gx | verilog/mult_unit.v | 10,145 | module MODULE1 #( parameter VAR80 = 0
, parameter VAR23 = 4
, parameter VAR51 = 1024
, parameter VAR110 = VAR100(VAR23)
, parameter VAR92 = VAR100(VAR51)
)
( input clk
, input VAR56
, input [4:0] VAR36
, input [8:0] VAR33
, input [26:0] VAR40
, input VAR27
, input VAR106
, output [26:0] VAR47
, input [VAR110+VAR92-1:0]... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o32ai/sky130_fd_sc_lp__o32ai.functional.pp.v | 2,191 | module MODULE1 (
VAR17 ,
VAR18 ,
VAR14 ,
VAR8 ,
VAR2 ,
VAR5 ,
VAR15,
VAR7,
VAR1 ,
VAR19
);
output VAR17 ;
input VAR18 ;
input VAR14 ;
input VAR8 ;
input VAR2 ;
input VAR5 ;
input VAR15;
input VAR7;
input VAR1 ;
input VAR19 ;
wire VAR10 ;
wire VAR4 ;
wire VAR11 ;
wire VAR3;
nor VAR16 (VAR10 , VAR8, VAR18, VAR14 );
nor V... | apache-2.0 |
tmatsuya/milkymist-ml401 | cores/softusb/rtl/softusb_ram.v | 3,377 | module MODULE1(
input VAR33,
input VAR42,
input VAR38,
input VAR36,
input [31:0] VAR29,
output [31:0] VAR26,
input [31:0] VAR6,
input [3:0] VAR7,
input VAR15,
input VAR41,
output reg VAR8,
input VAR22,
input VAR9,
input [10:0] VAR40,
output [15:0] VAR10,
input VAR21,
input [12:0] VAR16,
input [7:0] VAR30,
output reg [7... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and3b/sky130_fd_sc_ls__and3b.behavioral.pp.v | 1,961 | module MODULE1 (
VAR9 ,
VAR3 ,
VAR6 ,
VAR12 ,
VAR11,
VAR15,
VAR13 ,
VAR16
);
output VAR9 ;
input VAR3 ;
input VAR6 ;
input VAR12 ;
input VAR11;
input VAR15;
input VAR13 ;
input VAR16 ;
wire VAR8 ;
wire VAR10 ;
wire VAR4;
not VAR14 (VAR8 , VAR3 );
and VAR2 (VAR10 , VAR12, VAR8, VAR6 );
VAR5 VAR7 (VAR4, VAR10, VAR11, VAR... | apache-2.0 |
zhaishaomin/ring_network-based-multicore- | communication_assist/d_m_areg.v | 1,290 | module MODULE1( clk,
rst,
VAR7,
VAR1,
VAR4,
VAR5,
VAR2,
VAR8
);
input clk;
input rst;
input [143:0] VAR7;
input VAR1;
input VAR4;
output [175:0] VAR5;
output VAR2;
output VAR8;
reg VAR6;
reg [175:0] VAR3;
assign VAR2=VAR6;
assign VAR8=VAR6;
always@(posedge clk)
begin
if(rst||VAR4)
VAR3<=175'h0000;
end
else if(VAR1)
VAR... | apache-2.0 |
OpticalMeasurementsSystems/2DImageProcessing | src/frequency_analyzer_manager.v | 9,575 | module MODULE1 #
(
parameter integer VAR7 = 32,
parameter integer VAR1 = 10,
parameter integer VAR42 = 63,
parameter integer VAR111 = 511,
parameter integer VAR46 = 1023,
parameter integer VAR8 = 5000,
parameter integer VAR29 = 10000,
parameter integer VAR84 = 15000,
parameter integer VAR107 = 20000,
parameter integer ... | gpl-2.0 |
aquaxis/FPGAMAG18 | fmrv32im-artya7.nonos/fmrv32im-artya7.srcs/sources_1/bd/fmrv32im_artya7/hdl/fmrv32im_artya7_wrapper.v | 1,111 | module MODULE1
(VAR2,
VAR7,
VAR1,
VAR6,
VAR4,
VAR8);
input VAR2;
output [31:0]VAR7;
input VAR1;
output VAR6;
input [31:0]VAR4;
output [31:0]VAR8;
wire VAR2;
wire [31:0]VAR7;
wire VAR1;
wire VAR6;
wire [31:0]VAR4;
wire [31:0]VAR8;
VAR9 VAR3
(.VAR2(VAR2),
.VAR10(VAR4),
.VAR5(VAR8),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR6(VAR6));... | mit |
red0bear/AES128 | rtl/aes_core.v | 5,640 | module MODULE1
(
output [31:0] VAR44,
output [31:0] VAR20,
output [31:0] VAR23,
output VAR9,
input [31:0] VAR51,
input [ 3:0] VAR26,
input [ 3:0] VAR16,
input [ 3:0] VAR5,
input [ 1:0] VAR13,
input [ 1:0] VAR8,
input [ 1:0] addr,
input [ 1:0] VAR52,
input [ 1:0] VAR43,
input VAR22,
input VAR21,
input VAR53,
input VAR41... | lgpl-3.0 |
scalable-networks/ext | uhd/fpga/usrp2/models/M24LC024B.v | 19,643 | module MODULE1 (VAR23, VAR15, VAR6, VAR13, VAR2, VAR26, VAR25);
input VAR23; input VAR15; input VAR6;
input VAR13;
inout VAR2; input VAR26;
input VAR25;
reg VAR1; reg VAR22;
wire VAR31; reg VAR24;
reg [03:00] VAR20;
reg VAR8; reg VAR32; reg VAR4; reg VAR19; reg VAR30;
reg VAR5; reg VAR21;
reg [07:00] VAR12;
reg [07:00]... | gpl-2.0 |
cafe-alpha/wasca | v12/fpga_firmware/wasca/synthesis/submodules/altera_reset_synchronizer.v | 3,479 | module MODULE1
parameter VAR3 = 1,
parameter VAR5 = 2
)
(
input VAR1 ,
input clk,
output VAR6
);
reg [VAR5-1:0] VAR4;
reg VAR2;
generate if (VAR3) begin
always @(posedge clk or posedge VAR1) begin
if (VAR1) begin
VAR4 <= {VAR5{1'b1}};
VAR2 <= 1'b1;
end
else begin
VAR4[VAR5-2:0] <= VAR4[VAR5-1:1];
VAR4[VAR5-1] <= 0;
VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | models/udp_dlatch_pr/sky130_fd_sc_lp__udp_dlatch_pr.symbol.v | 1,360 | module MODULE1 (
input VAR2 ,
output VAR3 ,
input VAR1,
input VAR4
);
endmodule | apache-2.0 |
peteasa/parallella-fpga | AdiHDLLib/library/common/ad_mem.v | 3,322 | module MODULE1 (
VAR7,
VAR9,
VAR12,
VAR10,
VAR11,
VAR8,
VAR1);
parameter VAR2 = 16;
parameter VAR6 = 5;
localparam VAR4 = VAR2 - 1;
localparam VAR5 = VAR6 - 1;
input VAR7;
input VAR9;
input [VAR5:0] VAR12;
input [VAR4:0] VAR10;
input VAR11;
input [VAR5:0] VAR8;
output [VAR4:0] VAR1;
reg [VAR4:0] VAR3[0:((2**VAR6)-1)];
... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a221o/sky130_fd_sc_hd__a221o.behavioral.v | 1,662 | module MODULE1 (
VAR8 ,
VAR2,
VAR10,
VAR12,
VAR14,
VAR7
);
output VAR8 ;
input VAR2;
input VAR10;
input VAR12;
input VAR14;
input VAR7;
supply1 VAR4;
supply0 VAR11;
supply1 VAR17 ;
supply0 VAR3 ;
wire VAR5 ;
wire VAR9 ;
wire VAR6;
and VAR15 (VAR5 , VAR12, VAR14 );
and VAR13 (VAR9 , VAR2, VAR10 );
or VAR1 (VAR6, VAR9, V... | apache-2.0 |
hakehuang/pycpld | ips/ip/i2c_slave_for_case/i2c_slave_op.v | 16,089 | module MODULE1(
VAR35,
VAR23,
VAR19,
VAR38,
VAR58,
VAR8,
);
input VAR23;
input VAR35;
input VAR38;
input VAR58;
output VAR8;
reg VAR8;
output VAR19;
reg VAR37;
reg VAR49;
reg VAR18;
reg VAR32;
reg VAR40;
reg VAR57;
reg VAR26;
reg VAR61;
reg [7:0] VAR28;
reg [7:0] VAR1;
reg [7:0] VAR46;
reg [7:0] VAR36;
reg [6:0] VAR20;... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/lsbuflv2hv_clkiso_hlkg/sky130_fd_sc_hvl__lsbuflv2hv_clkiso_hlkg.functional.v | 1,631 | module MODULE1 (
VAR5 ,
VAR2 ,
VAR4
);
output VAR5 ;
input VAR2 ;
input VAR4;
wire VAR7 ;
wire VAR1;
not VAR6 (VAR7 , VAR4 );
and VAR3 (VAR1, VAR4, VAR2 );
buf VAR8 (VAR5 , VAR1 );
endmodule | apache-2.0 |
windelbouwman/ppci-mirror | tools/fatfs/system.v | 4,697 | module MODULE1 (
input clk,
input VAR27,
output VAR33,
output VAR12,
output VAR17,
input VAR22,
output VAR21,
input VAR45,
output VAR10
);
parameter VAR14 = 32768;
integer VAR37;
wire VAR40;
wire VAR9;
reg VAR20;
reg VAR29;
wire [31:0] VAR5;
wire [31:0] VAR23;
wire [3:0] VAR49;
reg [31:0] VAR36;
wire [31:0] VAR1;
wire ... | bsd-2-clause |
aneez/nexys-fpga-exp | vSevenSegmentDisplay/vHex_to_ssg.v | 1,265 | module MODULE1(
input wire[3:0] VAR3,
output reg[7:0] VAR1, input VAR2
);
always @*
begin
case(VAR3)
4'h0: VAR1[6:0] = 7'b0000001;
4'h1: VAR1[6:0] = 7'b1001111;
4'h2: VAR1[6:0] = 7'b0010010;
4'h3: VAR1[6:0] = 7'b0000110;
4'h4: VAR1[6:0] = 7'b1001100;
4'h5: VAR1[6:0] = 7'b0100100;
4'h6: VAR1[6:0] = 7'b0100000;
4'h7: VAR... | gpl-2.0 |
peteasa/parallella-fpga | AdiHDLLib/library/axi_hdmi_tx/axi_hdmi_tx.v | 11,575 | module MODULE1 (
VAR44,
VAR171,
VAR7,
VAR8,
VAR54,
VAR163,
VAR111,
VAR53,
VAR49,
VAR13,
VAR21,
VAR103,
VAR87,
VAR88,
VAR110,
VAR41,
VAR11,
VAR150,
VAR10,
VAR66,
VAR133,
VAR117,
VAR172,
VAR105,
VAR166,
VAR141,
VAR27,
VAR129,
VAR20,
VAR145,
VAR106,
VAR15,
VAR146,
VAR83,
VAR169,
VAR56,
VAR50,
VAR74,
VAR173,
VAR2,
VAR73,
V... | lgpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21_2.functional.pp.v | 1,290 | module MODULE1( VAR12, VAR2, VAR9, VAR6, VAR4, VAR8 );
input VAR6, VAR9, VAR12;
inout VAR4, VAR8;
output VAR2;
wire VAR14;
not VAR15( VAR14, VAR6 );
wire VAR7;
not VAR1( VAR7, VAR9 );
wire VAR11;
and VAR3( VAR11, VAR14, VAR7 );
wire VAR5;
not VAR13( VAR5, VAR12 );
or VAR10( VAR2, VAR11, VAR5 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp.behavioral.v | 2,251 | module MODULE1 (
VAR17 ,
VAR15,
VAR11 ,
VAR20,
VAR18
);
output VAR17 ;
input VAR15;
input VAR11 ;
input VAR20;
input VAR18;
supply1 VAR9;
supply0 VAR10;
supply1 VAR8 ;
supply0 VAR23 ;
wire VAR6 ;
wire VAR16 ;
reg VAR22 ;
wire VAR21 ;
wire VAR5 ;
wire VAR2 ;
wire VAR7 ;
wire VAR24;
wire VAR1;
wire VAR14;
VAR3 VAR19 (VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfstp/sky130_fd_sc_lp__dfstp.functional.v | 1,624 | module MODULE1 (
VAR1 ,
VAR10 ,
VAR3 ,
VAR2
);
output VAR1 ;
input VAR10 ;
input VAR3 ;
input VAR2;
wire VAR5;
wire VAR7 ;
not VAR6 (VAR7 , VAR2 );
VAR11 VAR4 VAR9 (VAR5 , VAR3, VAR10, VAR7 );
buf VAR8 (VAR1 , VAR5 );
endmodule | apache-2.0 |
asicguy/gplgpu | hdl/math/flt_alu.v | 2,906 | module MODULE1
(
input clk,
input VAR15,
input [64:0] VAR8,
input [64:0] VAR9,
input [64:0] VAR10,
input [64:0] VAR13,
input [128:0] VAR17,
input [63:0] VAR7,
output [31:0] VAR5,
output [31:0] VAR26,
output [31:0] VAR20,
output [31:0] VAR16,
output [31:0] VAR22,
output [31:0] VAR4,
output [31:0] VAR3,
output [31:0] VAR... | gpl-3.0 |
mballance/wb_dma | rtl/wb_dma_wb_slv.v | 5,975 | module MODULE1(clk, rst,
VAR11, VAR5, VAR7, VAR19, VAR13, VAR15,
VAR4, VAR1, VAR21, VAR22,
VAR20, VAR8, VAR9, VAR17, VAR10,
VAR18, VAR6, VAR3
);
parameter VAR12 = 0;
input clk, rst;
input [31:0] VAR11;
output [31:0] VAR5;
input [31:0] VAR7;
input [3:0] VAR19;
input VAR13;
input VAR15;
input VAR4;
output VAR1;
output VA... | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/ug871-design-files/Interface_Synthesis/lab2/adders_io_prj/solution1/syn/verilog/adders_io.v | 7,266 | module MODULE1 (
VAR3,
VAR9,
VAR13,
VAR30,
VAR4,
VAR17,
VAR21,
VAR15,
VAR33,
VAR29,
VAR2,
VAR31,
VAR14,
VAR12,
VAR16,
VAR26
);
parameter VAR27 = 2'd1;
parameter VAR22 = 2'd2;
input VAR3;
input VAR9;
input VAR13;
output VAR30;
output VAR4;
output VAR17;
input [31:0] VAR21;
input VAR15;
input [31:0] VAR33;
output VAR29;
... | mit |
Fabeltranm/FPGA-Game-D1 | HW/RTL/06PCM-AUDIO-MICROFONO/Version_01/02 verilog/Otros/Audio-SB/03FIFO/fifo.v | 3,331 | module MODULE1
parameter VAR8 = 5,
parameter VAR18 = 8
)
(
input clk, reset,
input VAR20, VAR1,
input [VAR18-1:0] VAR10,
output [VAR18-1:0] VAR11,
output VAR12,
output VAR16
);
reg wr, rd;
parameter VAR2 = (1 << VAR8);
reg [VAR18-1:0] VAR17 [VAR2-1:0];
reg [VAR8-1:0] VAR7, VAR14;
reg [VAR8-1:0] VAR21, VAR5;
reg VAR3, V... | gpl-3.0 |
deepakcu/maestro | fpga/DE4_Ethernet_0/src/oq_regs_generic_reg_grp.v | 23,691 | module MODULE1
parameter VAR50 = VAR47,
parameter VAR55 = 8,
parameter VAR11 = VAR82(VAR55),
parameter VAR51 = 16,
parameter VAR62 = 0, parameter VAR95 = 0 )
(
input VAR6,
input [VAR11-1:0] VAR45,
output [VAR50-1:0] VAR57,
input VAR19,
input [VAR11-1:0] VAR80,
input [VAR51-1:0] VAR24,
output reg [VAR50-1:0] VAR12,
outp... | apache-2.0 |
markusC64/1541ultimate2 | fpga/nios_dut/nios_dut/synthesis/submodules/nios_dut_nios2_gen2_0_cpu_debug_slave_tck.v | 8,288 | module MODULE1 (
VAR16,
VAR25,
VAR20,
VAR13,
VAR22,
VAR2,
VAR1,
VAR21,
VAR3,
VAR23,
VAR36,
VAR31,
VAR37,
VAR4,
VAR15,
VAR39,
VAR33,
VAR17,
VAR14,
VAR24,
VAR5,
VAR38,
VAR40,
VAR26,
VAR9,
VAR35,
VAR34,
VAR18,
VAR19,
VAR7,
VAR27
)
;
output [ 1: 0] VAR34;
output VAR18;
output [ 37: 0] VAR19;
output VAR7;
output VAR27;
inpu... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a21o/sky130_fd_sc_ms__a21o_2.v | 2,248 | module MODULE1 (
VAR3 ,
VAR2 ,
VAR1 ,
VAR5 ,
VAR4,
VAR6,
VAR8 ,
VAR7
);
output VAR3 ;
input VAR2 ;
input VAR1 ;
input VAR5 ;
input VAR4;
input VAR6;
input VAR8 ;
input VAR7 ;
VAR10 VAR9 (
.VAR3(VAR3),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR7(VAR7)
);
endmodule
module MODULE1 (... | apache-2.0 |
cpulabs/mist1032sa | src/core/scheduler2/reservation_alu2_entry.v | 8,402 | module MODULE1(
input wire VAR57,
input wire VAR13,
input wire VAR15,
input wire VAR35,
output wire VAR21,
input wire VAR70,
input wire VAR60,
input wire [4:0] VAR64,
input wire [3:0] VAR40,
input wire VAR12,
input wire VAR2,
input wire VAR48,
input wire VAR9,
input wire VAR7,
input wire [3:0] VAR56,
input wire VAR47,
... | bsd-2-clause |
vipinkmenon/scas | hw/fpga/ipcore_dir/system_mon.v | 7,745 | module MODULE1
(
VAR3, VAR7, VAR1, VAR11, VAR10, VAR12, VAR9,
VAR6, VAR5,
VAR14, VAR8, VAR13, VAR2, VAR4);
input [6:0] VAR3;
input VAR7;
input VAR1;
input [15:0] VAR11;
input VAR10;
input VAR12;
input VAR9;
input VAR6;
input VAR5;
input VAR2;
input VAR4;
output reg [15:0] VAR14;
output reg VAR8;
output VAR13;
always @(... | mit |
Jside/nova1 | nova_io_cpu.v | 2,671 | module MODULE1(VAR10, VAR2,
VAR13, VAR8, VAR16, VAR6, VAR12, VAR7,
VAR9, VAR14, VAR11
);
input VAR10;
input VAR2;
output VAR13;
input VAR8;
input VAR16;
input [0:7] VAR6;
input [0:15] VAR12;
output reg [0:15] VAR7;
output reg VAR9;
output reg VAR14;
input VAR11;
parameter VAR5 = 6'o77;
reg VAR4;
reg [0:15] VAR1;
reg VA... | gpl-3.0 |
jouyang3/FMCW | DSP/Radar_DSP/FPGA/Individual Modules/PLL_ADF4158/PLL_ADF4158/PLL_ADF4158.v | 2,424 | module MODULE1(
input clk,
input VAR6,
output reg VAR13,
output reg VAR16,
output VAR8
);
localparam VAR3 = 2'b00;
localparam VAR5 = 2'b01;
localparam VAR9 = 2'b10;
localparam VAR10 = 2'b11;
localparam VAR7 = 8;
reg [31:0] VAR12 [VAR7 - 1:0];
reg [31:0] VAR2;
reg [1:0] VAR4, state;
reg [4:0] VAR15;
reg [2:0] VAR1;
reg ... | gpl-3.0 |
Monash-2015-Ultrasonic/Logs | Final System Code/SYSTEMV3/Source/SPI_Master_ADC.v | 2,439 | module MODULE1 # (parameter VAR11 = 16)(
input VAR15,
input VAR7,
input [15:0] VAR17,
input VAR9,
output VAR10,
output reg VAR16,
output VAR1,
output reg VAR3,
output [15:0] VAR4
);
reg [(VAR11-1):0] VAR8 = 0; reg [(VAR11-1):0] VAR6 = 0; reg [(VAR11-1):0] VAR2 = 0; reg [5 :0] VAR13 = 0; reg [5 :0] VAR12 = 0;
reg [1:0] ... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dlya/gf180mcu_fd_sc_mcu7t5v0__dlya_1.behavioral.v | 1,098 | module MODULE1( VAR3, VAR4 );
input VAR3;
output VAR4;
VAR1 VAR2(.VAR3(VAR3),.VAR4(VAR4));
VAR1 VAR5(.VAR3(VAR3),.VAR4(VAR4)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o41ai/sky130_fd_sc_hd__o41ai_1.v | 2,424 | module MODULE1 (
VAR6 ,
VAR4 ,
VAR7 ,
VAR10 ,
VAR11 ,
VAR1 ,
VAR12,
VAR5,
VAR3 ,
VAR2
);
output VAR6 ;
input VAR4 ;
input VAR7 ;
input VAR10 ;
input VAR11 ;
input VAR1 ;
input VAR12;
input VAR5;
input VAR3 ;
input VAR2 ;
VAR8 VAR9 (
.VAR6(VAR6),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR11(VAR11),
.VAR1(VAR1),
.VAR1... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/mux2i/sky130_fd_sc_hs__mux2i.blackbox.v | 1,255 | module MODULE1 (
VAR1 ,
VAR4,
VAR2,
VAR5
);
output VAR1 ;
input VAR4;
input VAR2;
input VAR5 ;
supply1 VAR3;
supply0 VAR6;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlybuf4s50kapwr/sky130_fd_sc_lp__dlybuf4s50kapwr.pp.blackbox.v | 1,414 | module MODULE1 (
VAR6 ,
VAR4 ,
VAR1 ,
VAR2 ,
VAR5,
VAR3 ,
VAR7
);
output VAR6 ;
input VAR4 ;
input VAR1 ;
input VAR2 ;
input VAR5;
input VAR3 ;
input VAR7 ;
endmodule | apache-2.0 |
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